Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128470

1

T2

6

T4

14

T5

12

auto[1]

129428

1

T2

4

T4

10

T5

4

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	98009	1			T5	8		T6	2		T26	6
len_1026_2046	5644	1			T4	3		T6	1		T7	5
len_514_1022	3446	1			T7	8		T8	3		T10	10
len_2_510	3973	1			T4	2		T7	3		T9	1
len_2056	154	1			T4	4		T7	3		T8	2
len_2048	321	1			T7	2		T25	1		T13	1
len_2040	173	1			T7	5		T17	2		T149	8
len_1032	131	1			T7	7		T8	6		T150	3
len_1024	1962	1			T2	1		T7	7		T8	4
len_1016	165	1			T8	2		T135	2		T149	4
len_520	143	1			T2	3		T8	4		T150	3
len_512	686	1			T4	2		T7	4		T8	2
len_504	376	1			T2	1		T8	2		T41	2
len_8	945	1			T137	2		T17	1		T151	1
len_0	12821	1			T4	1		T7	1		T9	6

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

98

1

T11

2

T25

2

T19

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	51228	1			T5	6		T6	2		T26	4
auto[0]	len_1026_2046	2866	1			T7	3		T8	1		T10	18
auto[0]	len_514_1022	1798	1			T7	4		T8	1		T10	9
auto[0]	len_2_510	2245	1			T4	2		T8	2		T10	7
auto[0]	len_2056	77	1			T4	3		T7	2		T17	2
auto[0]	len_2048	178	1			T7	2		T13	1		T150	1
auto[0]	len_2040	93	1			T7	4		T17	1		T149	5
auto[0]	len_1032	75	1			T7	3		T8	4		T150	3
auto[0]	len_1024	364	1			T7	4		T8	1		T11	1
auto[0]	len_1016	97	1			T149	1		T152	3		T153	1
auto[0]	len_520	92	1			T2	3		T8	2		T150	1
auto[0]	len_512	208	1			T4	2		T7	2		T8	1
auto[0]	len_504	106	1			T41	2		T154	1		T16	2
auto[0]	len_8	17	1			T151	1		T155	1		T156	2
auto[0]	len_0	4791	1			T7	1		T9	5		T8	1
auto[1]	len_2050_plus	46781	1			T5	2		T26	2		T10	263
auto[1]	len_1026_2046	2778	1			T4	3		T6	1		T7	2
auto[1]	len_514_1022	1648	1			T7	4		T8	2		T10	1
auto[1]	len_2_510	1728	1			T7	3		T9	1		T12	1
auto[1]	len_2056	77	1			T4	1		T7	1		T8	2
auto[1]	len_2048	143	1			T25	1		T17	2		T35	3
auto[1]	len_2040	80	1			T7	1		T17	1		T149	3
auto[1]	len_1032	56	1			T7	4		T8	2		T149	1
auto[1]	len_1024	1598	1			T2	1		T7	3		T8	3
auto[1]	len_1016	68	1			T8	2		T135	2		T149	3
auto[1]	len_520	51	1			T8	2		T150	2		T41	1
auto[1]	len_512	478	1			T7	2		T8	1		T13	1
auto[1]	len_504	270	1			T2	1		T8	2		T135	1
auto[1]	len_8	928	1			T137	2		T17	1		T157	6
auto[1]	len_0	8030	1			T4	1		T9	1		T8	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

60

1

T11

2

T25

2

T158

2

auto[1]

len_upper

38

1

T19

2

T54

2

T14

1