Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4475392

1

T2

78

T4

146

T5

4

auto[1]

2773501

1

T2

95

T4

226

T5

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2782728

1

T2

41

T4

250

T5

3

auto[1]

4466165

1

T2

132

T4

122

T5

3

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3262703

1

T2

129

T4

229

T5

4

auto[1]

3986190

1

T2

44

T4

143

T5

2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4455153

1

T2

120

T4

125

T5

6

auto[1]

2793740

1

T2

53

T4

247

T6

940

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6591475	1			T2	135		T4	371		T5	3
fifo_depth[1]	111320	1			T2	5		T4	1		T5	1
fifo_depth[2]	81068	1			T2	5		T6	20		T7	12
fifo_depth[3]	63549	1			T2	5		T6	8		T7	4
fifo_depth[4]	58024	1			T2	7		T6	1		T7	1
fifo_depth[5]	46265	1			T8	1		T10	35		T11	1
fifo_depth[6]	37525	1			T2	6		T5	1		T10	90
fifo_depth[7]	24985	1			T2	4		T10	46		T12	87

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657418

1

T2

38

T4

1

T5

3

auto[1]

6591475

1

T2

135

T4

371

T5

3

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7239294

1

T2

173

T4

372

T5

6

auto[1]

9599

1

T10

59

T12

18

T25

260

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

28981

1

T7

1

T8

1

T25

209

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

33501

1

T10

189

T25

234

T136

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

27997

1

T7

5

T10

183

T12

660

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

33357

1

T25

1509

T27

58

T136

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

122815

1

T2

6

T5

1

T6

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

29325

1

T6

27

T7

2

T9

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

26921

1

T2

14

T5

1

T7

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30248

1

T4

1

T10

174

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45943

1

T5

1

T6

20

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

38870

1

T8

2

T10

1311

T25

893

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41038

1

T8

5

T12

10

T25

253

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

44579

1

T2

9

T6

2

T7

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42183

1

T160

162

T52

86

T13

569

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38000

1

T7

4

T8

5

T17

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

38547

1

T7

4

T8

4

T12

2046

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35113

1

T2

9

T7

7

T11

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

150238

1

T2

13

T5

1

T7

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

168521

1

T4

51

T6

283

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

169011

1

T4

61

T7

123

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

169410

1

T2

9

T4

49

T9

420

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1776250

1

T2

58

T5

1

T6

299

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

157603

1

T6

587

T7

189

T9

408

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

159592

1

T2

29

T4

3

T7

106

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

178933

1

T4

64

T7

25

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

423193

1

T6

344

T7

237

T8

47

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

492737

1

T4

41

T7

46

T9

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

434968

1

T4

48

T5

1

T8

34

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

480384

1

T2

10

T6

41

T7

17

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

488978

1

T4

13

T7

71

T8

37

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

438254

1

T2

1

T4

41

T7

121

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

478498

1

T7

37

T8

177

T10

144

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

424905

1

T2

15

T7

91

T8

35

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

178504

1

T2

13

T5

1

T7

11

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

200701

1

T4

51

T6

283

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

196579

1

T4

61

T7

128

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

202098

1

T2

9

T4

49

T9

420

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1898386

1

T2

64

T5

2

T6

313

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

186102

1

T6

614

T7

191

T9

417

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

186119

1

T2

43

T4

3

T5

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

208331

1

T4

65

T7

25

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

468667

1

T5

1

T6

364

T7

238

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

531181

1

T4

41

T7

46

T9

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

475188

1

T4

48

T5

1

T8

39

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

524258

1

T2

19

T6

43

T7

18

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

530793

1

T4

13

T7

71

T8

37

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

476083

1

T2

1

T4

41

T7

125

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

516965

1

T7

41

T8

181

T10

144

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

459339

1

T2

24

T7

98

T8

35

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

715

1

T25

3

T13

14

T134

82

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1321

1

T13

24

T128

8

T161

99

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

429

1

T13

3

T134

26

T162

46

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

669

1

T25

88

T134

4

T96

15

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

679

1

T25

16

T13

40

T93

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

826

1

T10

1

T25

43

T134

44

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

394

1

T10

1

T25

37

T13

54

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

850

1

T13

41

T134

1

T162

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

469

1

T12

4

T13

43

T162

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

426

1

T10

57

T25

3

T162

150

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

818

1

T25

13

T13

12

T163

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

705

1

T25

57

T162

2

T96

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

368

1

T13

9

T162

40

T164

22

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

171

1

T96

79

T164

50

T165

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

80

1

T12

14

T164

9

T166

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

679

1

T163

4

T161

1

T104

511

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

150238

1

T2

13

T5

1

T7

10

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

168521

1

T4

51

T6

283

T9

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

169011

1

T4

61

T7

123

T9

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

169410

1

T2

9

T4

49

T9

420

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1776250

1

T2

58

T5

1

T6

299

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

157603

1

T6

587

T7

189

T9

408

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

159592

1

T2

29

T4

3

T7

106

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

178933

1

T4

64

T7

25

T9

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

423193

1

T6

344

T7

237

T8

47

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

492737

1

T4

41

T7

46

T9

2

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

434968

1

T4

48

T5

1

T8

34

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

480384

1

T2

10

T6

41

T7

17

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

488978

1

T4

13

T7

71

T8

37

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

438254

1

T2

1

T4

41

T7

121

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

478498

1

T7

37

T8

177

T10

144

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

424905

1

T2

15

T7

91

T8

35

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3146

1

T13

3

T37

6

T54

6

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3418

1

T10

2

T25

14

T136

5

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3547

1

T7

1

T10

11

T12

16

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3474

1

T25

32

T27

5

T136

2

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

36310

1

T6

10

T25

30

T27

4

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3418

1

T6

15

T7

1

T9

7

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3095

1

T2

3

T7

2

T10

2

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3755

1

T4

1

T10

4

T12

15

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6279

1

T5

1

T6

8

T27

14

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5427

1

T8

1

T25

1

T35

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5946

1

T8

1

T13

3

T53

15

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

7340

1

T6

1

T25

15

T28

4

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7781

1

T160

129

T52

14

T53

9

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6292

1

T7

2

T8

1

T17

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6092

1

T7

3

T8

2

T52

18

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6000

1

T2

2

T7

4

T27

13

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2770

1

T7

1

T13

6

T19

1

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[1]

2637

1

T10

2

T25

9

T136

1

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[0]

2837

1

T7

3

T10

8

T12

2

fifo_depth[2]

auto[0]

auto[0]

auto[1]

auto[1]

2688

1

T25

21

T27

12

T136

1

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[0]

20515

1

T2

2

T6

2

T7

1

fifo_depth[2]

auto[0]

auto[1]

auto[0]

auto[1]

2768

1

T6

8

T7

1

T9

1

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[0]

2586

1

T2

2

T7

1

T10

2

fifo_depth[2]

auto[0]

auto[1]

auto[1]

auto[1]

3003

1

T10

4

T12

15

T25

1

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[0]

5157

1

T6

9

T27

13

T136

3

fifo_depth[2]

auto[1]

auto[0]

auto[0]

auto[1]

4149

1

T8

1

T10

2

T25

2

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[0]

4869

1

T8

2

T13

4

T53

5

fifo_depth[2]

auto[1]

auto[0]

auto[1]

auto[1]

6114

1

T2

1

T6

1

T25

1

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[0]

5991

1

T160

30

T52

14

T53

4

fifo_depth[2]

auto[1]

auto[1]

auto[0]

auto[1]

5208

1

T7

2

T8

1

T14

1

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[0]

4972

1

T7

1

T8

1

T52

29

fifo_depth[2]

auto[1]

auto[1]

auto[1]

auto[1]

4804

1

T7

2

T27

19

T28

8

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[0]

2030

1

T8

1

T25

2

T13

5

fifo_depth[3]

auto[0]

auto[0]

auto[0]

auto[1]

2034

1

T10

2

T25

14

T35

1

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[0]

2316

1

T7

1

T10

9

T12

17

fifo_depth[3]

auto[0]

auto[0]

auto[1]

auto[1]

2216

1

T25

32

T27

7

T13

6

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[0]

14182

1

T6

2

T7

1

T25

31

fifo_depth[3]

auto[0]

auto[1]

auto[0]

auto[1]

2100

1

T6

4

T9

1

T8

1

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[0]

2057

1

T2

4

T10

4

T12

2

fifo_depth[3]

auto[0]

auto[1]

auto[1]

auto[1]

2409

1

T10

4

T12

14

T25

1

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[0]

4177

1

T6

2

T7

1

T27

13

fifo_depth[3]

auto[1]

auto[0]

auto[0]

auto[1]

3220

1

T10

1

T25

5

T36

10

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[0]

4157

1

T8

2

T13

15

T35

2

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[1]

5176

1

T2

1

T25

15

T28

1

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[0]

4740

1

T160

3

T52

18

T53

1

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

4562

1

T8

1

T57

5

T167

5

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[0]

4251

1

T12

65

T52

22

T13

2

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

3922

1

T7

1

T27

15

T52

2

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

2170

1

T25

2

T13

4

T35

1

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

2192

1

T10

2

T25

13

T35

6

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

2133

1

T10

11

T52

16

T13

16

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

2259

1

T25

51

T27

4

T13

20

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

10279

1

T2

2

T26

1

T25

44

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

1994

1

T10

62

T25

8

T13

13

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[0]

2083

1

T2

3

T10

4

T12

15

fifo_depth[4]

auto[0]

auto[1]

auto[1]

auto[1]

2515

1

T10

4

T12

16

T25

2

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

3989

1

T6

1

T12

9

T27

13

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

3095

1

T36

6

T54

11

T162

3

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

3830

1

T12

1

T25

8

T13

10

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

4970

1

T2

2

T7

1

T25

1

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

4366

1

T52

16

T53

1

T60

1

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

4294

1

T8

1

T167

1

T168

6

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4124

1

T8

1

T12

33

T52

26

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

3731

1

T25

3

T27

19

T28

1

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1623

1

T25

1

T13

2

T54

13

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

1614

1

T10

2

T25

11

T13

2

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1752

1

T10

7

T12

17

T52

17

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1692

1

T25

29

T27

9

T13

8

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[0]

7224

1

T25

27

T27

5

T52

38

fifo_depth[5]

auto[0]

auto[1]

auto[0]

auto[1]

1540

1

T10

20

T25

24

T13

12

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[0]

1549

1

T10

2

T12

1

T25

5

fifo_depth[5]

auto[0]

auto[1]

auto[1]

auto[1]

1898

1

T10

4

T12

15

T25

1

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[0]

3389

1

T12

3

T27

11

T52

13

fifo_depth[5]

auto[1]

auto[0]

auto[0]

auto[1]

2597

1

T19

1

T35

3

T36

6

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[0]

3267

1

T12

2

T25

1

T13

17

fifo_depth[5]

auto[1]

auto[0]

auto[1]

auto[1]

4154

1

T25

14

T52

11

T13

2

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[0]

3654

1

T52

10

T74

171

T19

1

fifo_depth[5]

auto[1]

auto[1]

auto[0]

auto[1]

3661

1

T8

1

T167

1

T151

11

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[0]

3420

1

T12

66

T52

23

T13

2

fifo_depth[5]

auto[1]

auto[1]

auto[1]

auto[1]

3231

1

T11

1

T27

6

T52

1

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[0]

1489

1

T13

4

T54

9

T134

76

fifo_depth[6]

auto[0]

auto[0]

auto[0]

auto[1]

1546

1

T10

3

T25

15

T35

4

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

1468

1

T10

9

T52

12

T13

79

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1394

1

T25

47

T27

8

T13

22

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

5501

1

T2

2

T5

1

T25

76

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1227

1

T10

64

T25

4

T13

14

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[0]

1336

1

T2

1

T10

6

T12

13

fifo_depth[6]

auto[0]

auto[1]

auto[1]

auto[1]

1471

1

T10

4

T11

1

T12

14

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

2831

1

T27

14

T52

11

T13

236

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2057

1

T10

4

T25

14

T36

3

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[0]

2587

1

T25

1

T13

7

T35

2

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

3436

1

T2

1

T52

9

T13

1

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

3034

1

T52

6

T74

146

T34

34

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

2860

1

T35

2

T168

1

T151

7

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

2746

1

T12

11

T52

23

T13

2

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[1]

2542

1

T2

2

T27

5

T35

2

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

881

1

T25

6

T13

2

T54

5

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

1034

1

T25

14

T128

5

T54

8

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[0]

965

1

T10

11

T12

15

T52

5

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

942

1

T25

23

T27

10

T13

7

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[0]

3239

1

T25

29

T27

3

T52

14

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[1]

772

1

T10

29

T25

26

T13

13

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

881

1

T2

1

T10

1

T12

5

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

1071

1

T10

4

T12

2

T25

1

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

1985

1

T27

6

T52

10

T13

203

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1368

1

T10

1

T25

12

T36

4

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

1836

1

T13

26

T35

2

T36

8

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

2238

1

T2

2

T25

14

T52

6

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

2129

1

T52

8

T13

15

T74

136

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

1970

1

T151

5

T162

3

T169

1

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

1882

1

T12

65

T52

10

T13

2

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

1792

1

T2

1

T25

1

T27

5