Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17676519	1			T2	335		T4	737		T5	2070
all_pins[1]	17676519	1			T2	335		T4	737		T5	2070
all_pins[2]	17676519	1			T2	335		T4	737		T5	2070

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45223819	1			T2	972		T4	1828		T5	4957
values[0x1]	7805738	1			T2	33		T4	383		T5	1253
transitions[0x0=>0x1]	7805599	1			T2	33		T4	383		T5	1253
transitions[0x1=>0x0]	7805613	1			T2	33		T4	383		T5	1253

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17656664	1			T2	328		T4	728		T5	2064
all_pins[0]	values[0x1]	19855	1			T2	7		T4	9		T5	6
all_pins[0]	transitions[0x0=>0x1]	19799	1			T2	7		T4	9		T5	6
all_pins[0]	transitions[0x1=>0x0]	7785491	1			T2	26		T4	374		T5	1247
all_pins[1]	values[0x0]	17676169	1			T2	335		T4	737		T5	2070
all_pins[1]	values[0x1]	350	1			T10	1		T25	4		T13	2
all_pins[1]	transitions[0x0=>0x1]	314	1			T10	1		T25	4		T13	2
all_pins[1]	transitions[0x1=>0x0]	19819	1			T2	7		T4	9		T5	6
all_pins[2]	values[0x0]	9890986	1			T2	309		T4	363		T5	823
all_pins[2]	values[0x1]	7785533	1			T2	26		T4	374		T5	1247
all_pins[2]	transitions[0x0=>0x1]	7785486	1			T2	26		T4	374		T5	1247
all_pins[2]	transitions[0x1=>0x0]	303	1			T10	1		T25	4		T13	2