Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 845 1 T15 10 T66 21 T67 7
all_values[1] 845 1 T15 10 T66 21 T67 7
all_values[2] 845 1 T15 10 T66 21 T67 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1335 1 T15 19 T66 34 T67 9
auto[1] 1200 1 T15 11 T66 29 T67 12


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 904 1 T15 10 T66 26 T67 3
auto[1] 1631 1 T15 20 T66 37 T67 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1474 1 T15 16 T66 36 T67 8
auto[1] 1061 1 T15 14 T66 27 T67 13


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 178 1 T15 2 T66 8 T67 1
all_values[0] auto[0] auto[0] auto[1] 79 1 T15 2 T66 1 T67 1
all_values[0] auto[0] auto[1] auto[0] 149 1 T15 1 T66 3 T67 1
all_values[0] auto[0] auto[1] auto[1] 85 1 T68 1 T138 1 T76 2
all_values[0] auto[1] auto[0] auto[1] 194 1 T15 3 T66 9 T67 3
all_values[0] auto[1] auto[1] auto[1] 160 1 T15 2 T67 1 T139 1
all_values[1] auto[0] auto[0] auto[0] 145 1 T15 2 T66 1 T139 1
all_values[1] auto[0] auto[0] auto[1] 115 1 T15 1 T66 3 T139 1
all_values[1] auto[0] auto[1] auto[0] 118 1 T15 2 T66 5 T139 1
all_values[1] auto[0] auto[1] auto[1] 109 1 T15 1 T66 3 T67 2
all_values[1] auto[1] auto[0] auto[1] 183 1 T15 3 T66 3 T67 2
all_values[1] auto[1] auto[1] auto[1] 175 1 T15 1 T66 6 T67 3
all_values[2] auto[0] auto[0] auto[0] 178 1 T66 3 T76 4 T104 2
all_values[2] auto[0] auto[0] auto[1] 90 1 T15 2 T66 2 T139 1
all_values[2] auto[0] auto[1] auto[0] 136 1 T15 3 T66 6 T67 1
all_values[2] auto[0] auto[1] auto[1] 92 1 T66 1 T67 2 T68 3
all_values[2] auto[1] auto[0] auto[1] 173 1 T15 4 T66 4 T67 2
all_values[2] auto[1] auto[1] auto[1] 176 1 T15 1 T66 5 T67 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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