Summary for Variable digest_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for digest_size
Bins
| | | | | | | | | | | | |
sha2_invalid |
4055 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T5 |
1 |
sha2_none |
4026 |
1 |
|
|
T2 |
1 |
|
T4 |
5 |
|
T5 |
1 |
sha2_512 |
7333 |
1 |
|
|
T2 |
3 |
|
T4 |
6 |
|
T5 |
1 |
sha2_384 |
7246 |
1 |
|
|
T2 |
2 |
|
T4 |
3 |
|
T5 |
2 |
sha2_256 |
6041 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable digest_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for digest_swap
Bins
| | | | | | | | | | | | |
auto[0] |
18163 |
1 |
|
|
T2 |
4 |
|
T4 |
7 |
|
T5 |
4 |
auto[1] |
10869 |
1 |
|
|
T2 |
4 |
|
T4 |
10 |
|
T5 |
2 |
Summary for Variable endian_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for endian_swap
Bins
| | | | | | | | | | | | |
auto[0] |
10598 |
1 |
|
|
T2 |
3 |
|
T4 |
10 |
|
T5 |
3 |
auto[1] |
18434 |
1 |
|
|
T2 |
5 |
|
T4 |
7 |
|
T5 |
3 |
Summary for Variable hmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for hmac_en
Bins
| | | | | | | | | | | | |
enabled |
14926 |
1 |
|
|
T2 |
3 |
|
T4 |
8 |
|
T5 |
2 |
disabled |
14106 |
1 |
|
|
T2 |
5 |
|
T4 |
9 |
|
T5 |
4 |
Summary for Variable key_length
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
7 |
0 |
7 |
100.00 |
User Defined Bins for key_length
Bins
| | | | | | | | | | | | |
key_invalid |
4470 |
1 |
|
|
T2 |
2 |
|
T4 |
4 |
|
T5 |
2 |
key_none |
7685 |
1 |
|
|
T4 |
3 |
|
T7 |
6 |
|
T8 |
7 |
key_1024 |
4163 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T7 |
8 |
key_512 |
3585 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T6 |
1 |
key_384 |
3256 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
2 |
key_256 |
2973 |
1 |
|
|
T4 |
3 |
|
T5 |
2 |
|
T7 |
6 |
key_128 |
2829 |
1 |
|
|
T2 |
3 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable key_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for key_swap
Bins
| | | | | | | | | | | | |
auto[0] |
18326 |
1 |
|
|
T2 |
4 |
|
T4 |
8 |
|
T5 |
6 |
auto[1] |
10706 |
1 |
|
|
T2 |
4 |
|
T4 |
9 |
|
T6 |
4 |
Summary for Variable sha_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for sha_en
Bins
| | | | | | | | | | | | |
enabled |
28835 |
1 |
|
|
T2 |
8 |
|
T4 |
17 |
|
T5 |
6 |
disabled |
197 |
1 |
|
|
T57 |
2 |
|
T58 |
2 |
|
T59 |
2 |
Summary for Cross cfg_cross
Samples crossed: hmac_en endian_swap digest_swap key_swap
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cfg_cross
Bins
| | | | | | | | | | | | | | | |
enabled |
auto[0] |
auto[0] |
auto[0] |
1495 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
9 |
enabled |
auto[0] |
auto[0] |
auto[1] |
1527 |
1 |
|
|
T4 |
3 |
|
T7 |
1 |
|
T9 |
2 |
enabled |
auto[0] |
auto[1] |
auto[0] |
1491 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T8 |
5 |
enabled |
auto[0] |
auto[1] |
auto[1] |
1570 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
enabled |
auto[1] |
auto[0] |
auto[0] |
4260 |
1 |
|
|
T4 |
2 |
|
T7 |
2 |
|
T8 |
2 |
enabled |
auto[1] |
auto[0] |
auto[1] |
1498 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T7 |
5 |
enabled |
auto[1] |
auto[1] |
auto[0] |
1641 |
1 |
|
|
T7 |
1 |
|
T8 |
6 |
|
T10 |
1 |
enabled |
auto[1] |
auto[1] |
auto[1] |
1444 |
1 |
|
|
T2 |
1 |
|
T7 |
4 |
|
T8 |
2 |
disabled |
auto[0] |
auto[0] |
auto[0] |
1086 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T7 |
1 |
disabled |
auto[0] |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T4 |
1 |
|
T6 |
1 |
|
T9 |
1 |
disabled |
auto[0] |
auto[1] |
auto[0] |
1134 |
1 |
|
|
T4 |
3 |
|
T7 |
5 |
|
T9 |
1 |
disabled |
auto[0] |
auto[1] |
auto[1] |
1167 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T9 |
1 |
disabled |
auto[1] |
auto[0] |
auto[0] |
6009 |
1 |
|
|
T2 |
2 |
|
T5 |
2 |
|
T6 |
1 |
disabled |
auto[1] |
auto[0] |
auto[1] |
1160 |
1 |
|
|
T6 |
2 |
|
T7 |
6 |
|
T9 |
3 |
disabled |
auto[1] |
auto[1] |
auto[0] |
1210 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T5 |
1 |
disabled |
auto[1] |
auto[1] |
auto[1] |
1212 |
1 |
|
|
T4 |
3 |
|
T7 |
2 |
|
T8 |
4 |
Summary for Cross hmac_dis_x_sha_en
Samples crossed: hmac_en sha_en
| | | | | |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
3 |
0 |
3 |
100.00 |
|
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for hmac_dis_x_sha_en
Bins
| | | | | | | | | | | | | |
enabled |
enabled |
14857 |
1 |
|
|
T2 |
3 |
|
T4 |
8 |
|
T5 |
2 |
enabled |
disabled |
69 |
1 |
|
|
T58 |
1 |
|
T147 |
1 |
|
T148 |
1 |
disabled |
disabled |
128 |
1 |
|
|
T57 |
2 |
|
T58 |
1 |
|
T59 |
2 |
User Defined Cross Bins for hmac_dis_x_sha_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
b0 |
13978 |
1 |
|
|
T2 |
5 |
|
T4 |
9 |
|
T5 |
4 |
Summary for Cross key_x_digest_mismatch
Samples crossed: key_length digest_size
| | | | | |
TOTAL |
35 |
0 |
35 |
100.00 |
|
Automatically Generated Cross Bins |
34 |
0 |
34 |
100.00 |
|
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
Automatically Generated Cross Bins for key_x_digest_mismatch
Bins
| | | | | | | | | | | | | |
key_invalid |
sha2_invalid |
1075 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
3 |
key_invalid |
sha2_none |
878 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T8 |
1 |
key_invalid |
sha2_512 |
785 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T7 |
3 |
key_invalid |
sha2_384 |
826 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
key_invalid |
sha2_256 |
808 |
1 |
|
|
T9 |
1 |
|
T8 |
1 |
|
T11 |
1 |
key_none |
sha2_invalid |
493 |
1 |
|
|
T4 |
1 |
|
T8 |
1 |
|
T26 |
1 |
key_none |
sha2_none |
511 |
1 |
|
|
T8 |
2 |
|
T11 |
1 |
|
T27 |
1 |
key_none |
sha2_512 |
2520 |
1 |
|
|
T4 |
1 |
|
T7 |
5 |
|
T26 |
1 |
key_none |
sha2_384 |
2529 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
4 |
key_none |
sha2_256 |
1599 |
1 |
|
|
T10 |
1 |
|
T11 |
1 |
|
T12 |
1 |
key_1024 |
sha2_invalid |
497 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
1 |
key_1024 |
sha2_none |
529 |
1 |
|
|
T8 |
1 |
|
T11 |
1 |
|
T27 |
2 |
key_1024 |
sha2_512 |
1702 |
1 |
|
|
T2 |
1 |
|
T7 |
2 |
|
T10 |
1 |
key_1024 |
sha2_384 |
866 |
1 |
|
|
T4 |
1 |
|
T7 |
2 |
|
T8 |
1 |
key_512 |
sha2_invalid |
483 |
1 |
|
|
T9 |
1 |
|
T26 |
1 |
|
T10 |
2 |
key_512 |
sha2_none |
495 |
1 |
|
|
T4 |
3 |
|
T7 |
3 |
|
T8 |
1 |
key_512 |
sha2_512 |
575 |
1 |
|
|
T7 |
1 |
|
T12 |
1 |
|
T25 |
1 |
key_512 |
sha2_384 |
1170 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
key_512 |
sha2_256 |
823 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T8 |
1 |
key_384 |
sha2_invalid |
503 |
1 |
|
|
T8 |
1 |
|
T10 |
2 |
|
T27 |
2 |
key_384 |
sha2_none |
514 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T7 |
1 |
key_384 |
sha2_512 |
573 |
1 |
|
|
T5 |
1 |
|
T7 |
2 |
|
T8 |
4 |
key_384 |
sha2_384 |
606 |
1 |
|
|
T6 |
1 |
|
T7 |
4 |
|
T8 |
2 |
key_384 |
sha2_256 |
1022 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
1 |
key_256 |
sha2_invalid |
495 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
key_256 |
sha2_none |
516 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
3 |
key_256 |
sha2_512 |
618 |
1 |
|
|
T4 |
1 |
|
T7 |
3 |
|
T8 |
3 |
key_256 |
sha2_384 |
608 |
1 |
|
|
T5 |
1 |
|
T12 |
3 |
|
T25 |
2 |
key_256 |
sha2_256 |
699 |
1 |
|
|
T7 |
2 |
|
T9 |
1 |
|
T8 |
3 |
key_128 |
sha2_invalid |
495 |
1 |
|
|
T11 |
1 |
|
T25 |
1 |
|
T28 |
1 |
key_128 |
sha2_none |
568 |
1 |
|
|
T7 |
1 |
|
T8 |
3 |
|
T25 |
1 |
key_128 |
sha2_512 |
549 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T8 |
2 |
key_128 |
sha2_384 |
629 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T25 |
2 |
key_128 |
sha2_256 |
547 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
2 |
User Defined Cross Bins for key_x_digest_mismatch
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
b0 |
527 |
1 |
|
|
T7 |
3 |
|
T8 |
2 |
|
T10 |
1 |
Summary for Cross key_length_x_digest_size
Samples crossed: key_length digest_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
0 |
35 |
100.00 |
|
Automatically Generated Cross Bins for key_length_x_digest_size
Bins
| | | | | | | | | | | | | |
key_invalid |
sha2_invalid |
1075 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
3 |
key_invalid |
sha2_none |
878 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T8 |
1 |
key_invalid |
sha2_512 |
785 |
1 |
|
|
T2 |
1 |
|
T4 |
3 |
|
T7 |
3 |
key_invalid |
sha2_384 |
826 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
key_invalid |
sha2_256 |
808 |
1 |
|
|
T9 |
1 |
|
T8 |
1 |
|
T11 |
1 |
key_none |
sha2_invalid |
493 |
1 |
|
|
T4 |
1 |
|
T8 |
1 |
|
T26 |
1 |
key_none |
sha2_none |
511 |
1 |
|
|
T8 |
2 |
|
T11 |
1 |
|
T27 |
1 |
key_none |
sha2_512 |
2520 |
1 |
|
|
T4 |
1 |
|
T7 |
5 |
|
T26 |
1 |
key_none |
sha2_384 |
2529 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
4 |
key_none |
sha2_256 |
1599 |
1 |
|
|
T10 |
1 |
|
T11 |
1 |
|
T12 |
1 |
key_1024 |
sha2_invalid |
497 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
1 |
key_1024 |
sha2_none |
529 |
1 |
|
|
T8 |
1 |
|
T11 |
1 |
|
T27 |
2 |
key_1024 |
sha2_512 |
1702 |
1 |
|
|
T2 |
1 |
|
T7 |
2 |
|
T10 |
1 |
key_1024 |
sha2_384 |
866 |
1 |
|
|
T4 |
1 |
|
T7 |
2 |
|
T8 |
1 |
key_1024 |
sha2_256 |
527 |
1 |
|
|
T7 |
3 |
|
T8 |
2 |
|
T10 |
1 |
key_512 |
sha2_invalid |
483 |
1 |
|
|
T9 |
1 |
|
T26 |
1 |
|
T10 |
2 |
key_512 |
sha2_none |
495 |
1 |
|
|
T4 |
3 |
|
T7 |
3 |
|
T8 |
1 |
key_512 |
sha2_512 |
575 |
1 |
|
|
T7 |
1 |
|
T12 |
1 |
|
T25 |
1 |
key_512 |
sha2_384 |
1170 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
1 |
key_512 |
sha2_256 |
823 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T8 |
1 |
key_384 |
sha2_invalid |
503 |
1 |
|
|
T8 |
1 |
|
T10 |
2 |
|
T27 |
2 |
key_384 |
sha2_none |
514 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T7 |
1 |
key_384 |
sha2_512 |
573 |
1 |
|
|
T5 |
1 |
|
T7 |
2 |
|
T8 |
4 |
key_384 |
sha2_384 |
606 |
1 |
|
|
T6 |
1 |
|
T7 |
4 |
|
T8 |
2 |
key_384 |
sha2_256 |
1022 |
1 |
|
|
T5 |
1 |
|
T6 |
1 |
|
T7 |
1 |
key_256 |
sha2_invalid |
495 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T11 |
1 |
key_256 |
sha2_none |
516 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T8 |
3 |
key_256 |
sha2_512 |
618 |
1 |
|
|
T4 |
1 |
|
T7 |
3 |
|
T8 |
3 |
key_256 |
sha2_384 |
608 |
1 |
|
|
T5 |
1 |
|
T12 |
3 |
|
T25 |
2 |
key_256 |
sha2_256 |
699 |
1 |
|
|
T7 |
2 |
|
T9 |
1 |
|
T8 |
3 |
key_128 |
sha2_invalid |
495 |
1 |
|
|
T11 |
1 |
|
T25 |
1 |
|
T28 |
1 |
key_128 |
sha2_none |
568 |
1 |
|
|
T7 |
1 |
|
T8 |
3 |
|
T25 |
1 |
key_128 |
sha2_512 |
549 |
1 |
|
|
T2 |
1 |
|
T7 |
1 |
|
T8 |
2 |
key_128 |
sha2_384 |
629 |
1 |
|
|
T2 |
1 |
|
T11 |
1 |
|
T25 |
2 |
key_128 |
sha2_256 |
547 |
1 |
|
|
T2 |
1 |
|
T6 |
1 |
|
T7 |
2 |