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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.61 95.37 97.17 100.00 94.12 98.25 98.52 99.85


Total test records in report: 654
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T121 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.1630197460 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:24 PM UTC 24 14003105 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3310725746 Sep 24 07:13:10 PM UTC 24 Sep 24 07:13:13 PM UTC 24 33595446 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.773521852 Sep 24 07:13:09 PM UTC 24 Sep 24 07:13:13 PM UTC 24 179582136 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4131733302 Sep 24 07:13:10 PM UTC 24 Sep 24 07:13:13 PM UTC 24 75053064 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1025266897 Sep 24 07:13:11 PM UTC 24 Sep 24 07:13:13 PM UTC 24 13282509 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3175532472 Sep 24 07:13:11 PM UTC 24 Sep 24 07:13:13 PM UTC 24 76787252 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.3284933820 Sep 24 07:13:11 PM UTC 24 Sep 24 07:13:13 PM UTC 24 48827838 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.703111782 Sep 24 07:13:12 PM UTC 24 Sep 24 07:13:15 PM UTC 24 227113729 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.2566525784 Sep 24 07:13:14 PM UTC 24 Sep 24 07:13:15 PM UTC 24 40743031 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1468026418 Sep 24 07:13:11 PM UTC 24 Sep 24 07:13:15 PM UTC 24 64370933 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.2661979773 Sep 24 07:13:13 PM UTC 24 Sep 24 07:13:15 PM UTC 24 101112168 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.2185802146 Sep 24 07:13:14 PM UTC 24 Sep 24 07:13:15 PM UTC 24 20185696 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2100473557 Sep 24 07:13:14 PM UTC 24 Sep 24 07:13:16 PM UTC 24 49010044 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1295001138 Sep 24 07:13:12 PM UTC 24 Sep 24 07:13:16 PM UTC 24 226315549 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.2264553478 Sep 24 07:13:11 PM UTC 24 Sep 24 07:13:16 PM UTC 24 492288531 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1201710233 Sep 24 07:13:14 PM UTC 24 Sep 24 07:13:16 PM UTC 24 286353595 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3159537758 Sep 24 07:13:12 PM UTC 24 Sep 24 07:13:17 PM UTC 24 161230425 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.1630407195 Sep 24 07:13:10 PM UTC 24 Sep 24 07:13:17 PM UTC 24 1433120308 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.833959682 Sep 24 07:13:12 PM UTC 24 Sep 24 07:13:17 PM UTC 24 154185919 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.2806657625 Sep 24 07:13:07 PM UTC 24 Sep 24 07:13:17 PM UTC 24 1804301794 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2976631733 Sep 24 07:13:11 PM UTC 24 Sep 24 07:13:17 PM UTC 24 415449662 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.107235712 Sep 24 07:13:14 PM UTC 24 Sep 24 07:13:17 PM UTC 24 132493682 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3944791819 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:18 PM UTC 24 41808637 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.4034783159 Sep 24 07:13:15 PM UTC 24 Sep 24 07:13:18 PM UTC 24 94331097 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.746079232 Sep 24 07:13:14 PM UTC 24 Sep 24 07:13:18 PM UTC 24 111168180 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.835266756 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:18 PM UTC 24 22915560 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.3070342763 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:18 PM UTC 24 124142651 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.73475257 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:18 PM UTC 24 35092785 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2271475612 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:18 PM UTC 24 21395983 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.122702475 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:19 PM UTC 24 46006222 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.3085113323 Sep 24 07:13:10 PM UTC 24 Sep 24 07:13:19 PM UTC 24 602214835 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.1581529401 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:24 PM UTC 24 15665822 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1563506767 Sep 24 07:13:17 PM UTC 24 Sep 24 07:13:19 PM UTC 24 219939500 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1390117374 Sep 24 07:13:15 PM UTC 24 Sep 24 07:13:20 PM UTC 24 166206752 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.802518448 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:20 PM UTC 24 46776666 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3428760441 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:20 PM UTC 24 18895305 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3520922278 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:20 PM UTC 24 65068093 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.560890085 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:20 PM UTC 24 231913752 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.659223104 Sep 24 07:13:17 PM UTC 24 Sep 24 07:13:20 PM UTC 24 38509045 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.769162133 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:21 PM UTC 24 214823326 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2095680375 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:21 PM UTC 24 305158707 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.2927902104 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:21 PM UTC 24 310601593 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3755229294 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:21 PM UTC 24 94772271 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1586181638 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:21 PM UTC 24 14203493 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3799797461 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:21 PM UTC 24 48457114 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1102418800 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:22 PM UTC 24 122097740 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.2365943741 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:22 PM UTC 24 38237451 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1467263133 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:22 PM UTC 24 455131410 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.382903516 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:22 PM UTC 24 43163724 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.3688562611 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:24 PM UTC 24 16933295 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3124181308 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:22 PM UTC 24 46921271 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.891273800 Sep 24 07:13:20 PM UTC 24 Sep 24 07:13:22 PM UTC 24 45242209 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.792133628 Sep 24 07:13:18 PM UTC 24 Sep 24 07:13:22 PM UTC 24 398037069 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3924744287 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:22 PM UTC 24 100918193 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.767279670 Sep 24 07:13:20 PM UTC 24 Sep 24 07:13:22 PM UTC 24 15893476 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.231552752 Sep 24 07:13:21 PM UTC 24 Sep 24 07:13:23 PM UTC 24 14929689 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.2071660469 Sep 24 07:13:21 PM UTC 24 Sep 24 07:13:23 PM UTC 24 104199563 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3856745096 Sep 24 07:13:21 PM UTC 24 Sep 24 07:13:23 PM UTC 24 32555434 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3589611984 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:23 PM UTC 24 136139587 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.4118359952 Sep 24 07:13:20 PM UTC 24 Sep 24 07:13:23 PM UTC 24 387992381 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3046660632 Sep 24 07:13:21 PM UTC 24 Sep 24 07:13:24 PM UTC 24 95313796 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3626641851 Sep 24 07:13:21 PM UTC 24 Sep 24 07:13:24 PM UTC 24 336633488 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2704130239 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:24 PM UTC 24 674919136 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3941841249 Sep 24 07:13:19 PM UTC 24 Sep 24 07:13:24 PM UTC 24 188314687 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2783369878 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:24 PM UTC 24 24660364 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2273825957 Sep 24 07:13:20 PM UTC 24 Sep 24 07:13:24 PM UTC 24 42341255 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3051322963 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:25 PM UTC 24 374060127 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2671364726 Sep 24 07:13:20 PM UTC 24 Sep 24 07:13:25 PM UTC 24 159618496 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.519542996 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:25 PM UTC 24 693192318 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2992805416 Sep 24 07:13:21 PM UTC 24 Sep 24 07:13:25 PM UTC 24 553039683 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1004201645 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:25 PM UTC 24 53486346 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.530854599 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:26 PM UTC 24 41055233 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.710288943 Sep 24 07:13:14 PM UTC 24 Sep 24 07:13:26 PM UTC 24 1014979193 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.1724096213 Sep 24 07:13:23 PM UTC 24 Sep 24 07:13:26 PM UTC 24 62215049 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3692320049 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:26 PM UTC 24 492556039 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1175283051 Sep 24 07:13:23 PM UTC 24 Sep 24 07:13:26 PM UTC 24 13136142 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.4116676998 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:26 PM UTC 24 309403987 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.3222936438 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:26 PM UTC 24 234905855 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2317581766 Sep 24 07:13:23 PM UTC 24 Sep 24 07:13:26 PM UTC 24 54589797 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4268849650 Sep 24 07:13:16 PM UTC 24 Sep 24 07:13:27 PM UTC 24 1224439156 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.395362358 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:27 PM UTC 24 13553240 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.531874124 Sep 24 07:13:22 PM UTC 24 Sep 24 07:13:27 PM UTC 24 1246364971 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.257722016 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:27 PM UTC 24 15008995 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.392966091 Sep 24 07:13:23 PM UTC 24 Sep 24 07:13:27 PM UTC 24 119872700 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1770961664 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:27 PM UTC 24 41257257 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4157226517 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:27 PM UTC 24 270743469 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2589323887 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:28 PM UTC 24 508414727 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3618286452 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:28 PM UTC 24 280957401 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.580048931 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:28 PM UTC 24 15380482 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2546710676 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:28 PM UTC 24 13206894 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.868489545 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:28 PM UTC 24 291558430 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.396362525 Sep 24 07:13:24 PM UTC 24 Sep 24 07:13:28 PM UTC 24 86623548 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.257804741 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:28 PM UTC 24 48106505 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2841556130 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:28 PM UTC 24 23788535 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.100434605 Sep 24 07:13:23 PM UTC 24 Sep 24 07:13:28 PM UTC 24 368040336 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4153089075 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:29 PM UTC 24 32353390 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3381508061 Sep 24 07:13:23 PM UTC 24 Sep 24 07:13:29 PM UTC 24 385247099 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.367661361 Sep 24 07:13:26 PM UTC 24 Sep 24 07:13:29 PM UTC 24 75745413 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.703779743 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:29 PM UTC 24 70167818 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.3246460621 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 33742234 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3331741722 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 57320108 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.387161949 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 35778727 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.4071658171 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 16196808 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.451463874 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:30 PM UTC 24 361212087 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1785771578 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 18085742 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.1808931880 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:30 PM UTC 24 214562085 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.179489615 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:30 PM UTC 24 71636183 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3379652563 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 23636952 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.3412103110 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 72208971 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.4053375989 Sep 24 07:13:26 PM UTC 24 Sep 24 07:13:30 PM UTC 24 503254047 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2031543120 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 34780773 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1535735614 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:30 PM UTC 24 672179025 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1463265382 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:30 PM UTC 24 17526828 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3675792446 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:30 PM UTC 24 462368383 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1974069822 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:30 PM UTC 24 48678714 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.2351061234 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:31 PM UTC 24 723833397 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1207756327 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:31 PM UTC 24 184758707 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1298609428 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:31 PM UTC 24 47737247 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2518192582 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:31 PM UTC 24 213244215 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.45511494 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:31 PM UTC 24 11950732 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.450036390 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:31 PM UTC 24 115683977 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1668117775 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:31 PM UTC 24 55698426 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4053050535 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:31 PM UTC 24 93104284 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3246370541 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:31 PM UTC 24 66035304 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.710629373 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:31 PM UTC 24 101262551 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.1490777399 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:31 PM UTC 24 13279477 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2024569365 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:31 PM UTC 24 531153286 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2616511888 Sep 24 07:13:28 PM UTC 24 Sep 24 07:13:31 PM UTC 24 43832951 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3163482713 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:31 PM UTC 24 455494511 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.951393402 Sep 24 07:13:26 PM UTC 24 Sep 24 07:13:31 PM UTC 24 622111918 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3256362423 Sep 24 07:13:27 PM UTC 24 Sep 24 07:13:31 PM UTC 24 115459212 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3606578680 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:32 PM UTC 24 232584803 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.97603896 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 46722288 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.241592704 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 21081487 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1882255008 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 50865837 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.3351302761 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 31054895 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1293081777 Sep 24 07:13:25 PM UTC 24 Sep 24 07:13:32 PM UTC 24 571178960 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2582653472 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 14269849 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.934559598 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 25773889 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3270083347 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 31628847 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.848262972 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 29024607 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2057304151 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 85654807 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.2544855888 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 24054697 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3308367574 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 41536646 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.2998078032 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 24332095 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.772125895 Sep 24 07:13:30 PM UTC 24 Sep 24 07:13:32 PM UTC 24 11843259 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.700486349 Sep 24 07:13:31 PM UTC 24 Sep 24 07:13:33 PM UTC 24 42882886 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1927613999 Sep 24 07:13:31 PM UTC 24 Sep 24 07:13:33 PM UTC 24 13724431 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2726256779 Sep 24 07:13:31 PM UTC 24 Sep 24 07:13:36 PM UTC 24 44064804 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3284569708 Sep 24 07:13:31 PM UTC 24 Sep 24 07:13:36 PM UTC 24 16442958 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2948082031 Sep 24 07:13:31 PM UTC 24 Sep 24 07:13:36 PM UTC 24 50943039 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.900092526 Sep 24 07:13:09 PM UTC 24 Sep 24 07:29:12 PM UTC 24 82657782164 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2924258332 Sep 24 07:13:26 PM UTC 24 Sep 24 07:32:48 PM UTC 24 64400676369 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3823623292 Sep 24 07:13:19 PM UTC 24 Sep 24 07:37:34 PM UTC 24 507168471518 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.2894991171
Short name T5
Test name
Test status
Simulation time 236671596 ps
CPU time 15.84 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:52 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894991171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2894991171
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.3711295962
Short name T25
Test name
Test status
Simulation time 4490160883 ps
CPU time 49.33 seconds
Started Sep 24 07:13:34 PM UTC 24
Finished Sep 24 07:14:25 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711295962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3711295962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_stress_all_with_rand_reset.578489335
Short name T15
Test name
Test status
Simulation time 22415528620 ps
CPU time 146.75 seconds
Started Sep 24 07:14:27 PM UTC 24
Finished Sep 24 07:16:56 PM UTC 24
Peak memory 219108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57848933
5 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.578489335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.3981243101
Short name T13
Test name
Test status
Simulation time 9124095849 ps
CPU time 62.66 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:14:39 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981243101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3981243101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_stress_all_with_rand_reset.3336440037
Short name T16
Test name
Test status
Simulation time 101890436066 ps
CPU time 346.89 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:19:32 PM UTC 24
Peak memory 431568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33364400
37 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3336440037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.2264553478
Short name T140
Test name
Test status
Simulation time 492288531 ps
CPU time 4.13 seconds
Started Sep 24 07:13:11 PM UTC 24
Finished Sep 24 07:13:16 PM UTC 24
Peak memory 206788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264553478 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2264553478
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_smoke.2641813796
Short name T8
Test name
Test status
Simulation time 3683231842 ps
CPU time 16.72 seconds
Started Sep 24 07:13:43 PM UTC 24
Finished Sep 24 07:14:02 PM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641813796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2641813796
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.3730704408
Short name T3
Test name
Test status
Simulation time 61159325 ps
CPU time 0.88 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:13:41 PM UTC 24
Peak memory 238204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730704408 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3730704408
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.3636699180
Short name T29
Test name
Test status
Simulation time 1500296486 ps
CPU time 103.92 seconds
Started Sep 24 07:33:20 PM UTC 24
Finished Sep 24 07:35:06 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636699180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3636699180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_error.733369677
Short name T58
Test name
Test status
Simulation time 1953952365 ps
CPU time 76.07 seconds
Started Sep 24 07:15:24 PM UTC 24
Finished Sep 24 07:16:42 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733369677 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.733369677
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.409083467
Short name T107
Test name
Test status
Simulation time 15339203 ps
CPU time 0.83 seconds
Started Sep 24 07:13:06 PM UTC 24
Finished Sep 24 07:13:08 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409083467 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.409083467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_long_msg.2529766601
Short name T52
Test name
Test status
Simulation time 1926708858 ps
CPU time 60.78 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:14:37 PM UTC 24
Peak memory 210012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529766601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2529766601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_stress_all.1784783553
Short name T66
Test name
Test status
Simulation time 7086092518 ps
CPU time 462.42 seconds
Started Sep 24 07:13:37 PM UTC 24
Finished Sep 24 07:21:30 PM UTC 24
Peak memory 406776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784783553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1784783553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_long_msg.4223209470
Short name T54
Test name
Test status
Simulation time 17167714404 ps
CPU time 190.83 seconds
Started Sep 24 07:14:34 PM UTC 24
Finished Sep 24 07:17:48 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223209470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4223209470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_alert_test.1583410962
Short name T1
Test name
Test status
Simulation time 15659569 ps
CPU time 0.67 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:13:37 PM UTC 24
Peak memory 207412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583410962 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1583410962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.1945964885
Short name T63
Test name
Test status
Simulation time 314813171 ps
CPU time 1.89 seconds
Started Sep 24 07:13:04 PM UTC 24
Finished Sep 24 07:13:07 PM UTC 24
Peak memory 205852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945964885 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1945964885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.460961224
Short name T164
Test name
Test status
Simulation time 2733070341 ps
CPU time 70.87 seconds
Started Sep 24 07:26:01 PM UTC 24
Finished Sep 24 07:27:14 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460961224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.460961224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_stress_all.2488973405
Short name T443
Test name
Test status
Simulation time 11543018978 ps
CPU time 1198.05 seconds
Started Sep 24 07:26:47 PM UTC 24
Finished Sep 24 07:47:00 PM UTC 24
Peak memory 744760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488973405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2488973405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2283618563
Short name T151
Test name
Test status
Simulation time 1742861832 ps
CPU time 99.38 seconds
Started Sep 24 07:15:55 PM UTC 24
Finished Sep 24 07:17:36 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283618563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2283618563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.4116676998
Short name T145
Test name
Test status
Simulation time 309403987 ps
CPU time 2.99 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 206768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116676998 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.4116676998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.2806657625
Short name T111
Test name
Test status
Simulation time 1804301794 ps
CPU time 8.19 seconds
Started Sep 24 07:13:07 PM UTC 24
Finished Sep 24 07:13:17 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806657625 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2806657625
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.1679491104
Short name T117
Test name
Test status
Simulation time 453191900 ps
CPU time 4.74 seconds
Started Sep 24 07:13:06 PM UTC 24
Finished Sep 24 07:13:12 PM UTC 24
Peak memory 206832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679491104 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1679491104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.4139233912
Short name T527
Test name
Test status
Simulation time 20815228 ps
CPU time 0.99 seconds
Started Sep 24 07:13:06 PM UTC 24
Finished Sep 24 07:13:08 PM UTC 24
Peak memory 206400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139233912 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4139233912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.900092526
Short name T652
Test name
Test status
Simulation time 82657782164 ps
CPU time 951.32 seconds
Started Sep 24 07:13:09 PM UTC 24
Finished Sep 24 07:29:12 PM UTC 24
Peak memory 219332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=900092526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_re
set.900092526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.1983832504
Short name T526
Test name
Test status
Simulation time 82486041 ps
CPU time 0.63 seconds
Started Sep 24 07:13:05 PM UTC 24
Finished Sep 24 07:13:07 PM UTC 24
Peak memory 203976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983832504 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1983832504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3750198791
Short name T120
Test name
Test status
Simulation time 388006486 ps
CPU time 1.48 seconds
Started Sep 24 07:13:07 PM UTC 24
Finished Sep 24 07:13:10 PM UTC 24
Peak memory 205936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750198791 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.3750198791
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.212035574
Short name T69
Test name
Test status
Simulation time 147219718 ps
CPU time 3.81 seconds
Started Sep 24 07:13:04 PM UTC 24
Finished Sep 24 07:13:09 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212035574 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.212035574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.3085113323
Short name T113
Test name
Test status
Simulation time 602214835 ps
CPU time 7.49 seconds
Started Sep 24 07:13:10 PM UTC 24
Finished Sep 24 07:13:19 PM UTC 24
Peak memory 206932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085113323 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3085113323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.1630407195
Short name T534
Test name
Test status
Simulation time 1433120308 ps
CPU time 5.66 seconds
Started Sep 24 07:13:10 PM UTC 24
Finished Sep 24 07:13:17 PM UTC 24
Peak memory 206780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630407195 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1630407195
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.1097321487
Short name T108
Test name
Test status
Simulation time 37276544 ps
CPU time 0.96 seconds
Started Sep 24 07:13:10 PM UTC 24
Finished Sep 24 07:13:12 PM UTC 24
Peak memory 206044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097321487 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1097321487
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4131733302
Short name T71
Test name
Test status
Simulation time 75053064 ps
CPU time 1.8 seconds
Started Sep 24 07:13:10 PM UTC 24
Finished Sep 24 07:13:13 PM UTC 24
Peak memory 206132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4131733302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.4131733302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1301495104
Short name T529
Test name
Test status
Simulation time 95392354 ps
CPU time 0.8 seconds
Started Sep 24 07:13:10 PM UTC 24
Finished Sep 24 07:13:12 PM UTC 24
Peak memory 206400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301495104 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1301495104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.2584206966
Short name T528
Test name
Test status
Simulation time 44479102 ps
CPU time 0.54 seconds
Started Sep 24 07:13:09 PM UTC 24
Finished Sep 24 07:13:10 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584206966 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2584206966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3310725746
Short name T122
Test name
Test status
Simulation time 33595446 ps
CPU time 1.58 seconds
Started Sep 24 07:13:10 PM UTC 24
Finished Sep 24 07:13:13 PM UTC 24
Peak memory 206060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310725746 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.3310725746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.2958964761
Short name T70
Test name
Test status
Simulation time 332587033 ps
CPU time 1.9 seconds
Started Sep 24 07:13:09 PM UTC 24
Finished Sep 24 07:13:12 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958964761 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2958964761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.773521852
Short name T64
Test name
Test status
Simulation time 179582136 ps
CPU time 2.94 seconds
Started Sep 24 07:13:09 PM UTC 24
Finished Sep 24 07:13:13 PM UTC 24
Peak memory 206932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773521852 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.773521852
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.530854599
Short name T574
Test name
Test status
Simulation time 41055233 ps
CPU time 2.63 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 215040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=530854599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_r
eset.530854599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.2071660469
Short name T560
Test name
Test status
Simulation time 104199563 ps
CPU time 1.01 seconds
Started Sep 24 07:13:21 PM UTC 24
Finished Sep 24 07:13:23 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071660469 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2071660469
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.231552752
Short name T559
Test name
Test status
Simulation time 14929689 ps
CPU time 0.71 seconds
Started Sep 24 07:13:21 PM UTC 24
Finished Sep 24 07:13:23 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231552752 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.231552752
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3051322963
Short name T569
Test name
Test status
Simulation time 374060127 ps
CPU time 1.71 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:25 PM UTC 24
Peak memory 205952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051322963 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.3051322963
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2992805416
Short name T572
Test name
Test status
Simulation time 553039683 ps
CPU time 3.23 seconds
Started Sep 24 07:13:21 PM UTC 24
Finished Sep 24 07:13:25 PM UTC 24
Peak memory 206860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992805416 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2992805416
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.3626641851
Short name T565
Test name
Test status
Simulation time 336633488 ps
CPU time 2.01 seconds
Started Sep 24 07:13:21 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626641851 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3626641851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.519542996
Short name T571
Test name
Test status
Simulation time 693192318 ps
CPU time 1.78 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:25 PM UTC 24
Peak memory 206112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=519542996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_r
eset.519542996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.1630197460
Short name T121
Test name
Test status
Simulation time 14003105 ps
CPU time 0.86 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 205404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630197460 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1630197460
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.1581529401
Short name T542
Test name
Test status
Simulation time 15665822 ps
CPU time 0.88 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581529401 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1581529401
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2783369878
Short name T567
Test name
Test status
Simulation time 24660364 ps
CPU time 1.22 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 206016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783369878 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.2783369878
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.531874124
Short name T583
Test name
Test status
Simulation time 1246364971 ps
CPU time 3.79 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:27 PM UTC 24
Peak memory 206792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531874124 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.531874124
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2317581766
Short name T580
Test name
Test status
Simulation time 54589797 ps
CPU time 1.59 seconds
Started Sep 24 07:13:23 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 221696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2317581766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.2317581766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.1724096213
Short name T576
Test name
Test status
Simulation time 62215049 ps
CPU time 1.05 seconds
Started Sep 24 07:13:23 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 206044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724096213 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1724096213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.3688562611
Short name T554
Test name
Test status
Simulation time 16933295 ps
CPU time 0.68 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688562611 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3688562611
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.392966091
Short name T585
Test name
Test status
Simulation time 119872700 ps
CPU time 1.77 seconds
Started Sep 24 07:13:23 PM UTC 24
Finished Sep 24 07:13:27 PM UTC 24
Peak memory 205992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392966091 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.392966091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3692320049
Short name T577
Test name
Test status
Simulation time 492556039 ps
CPU time 2.7 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 206916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692320049 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3692320049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.1004201645
Short name T573
Test name
Test status
Simulation time 53486346 ps
CPU time 1.99 seconds
Started Sep 24 07:13:22 PM UTC 24
Finished Sep 24 07:13:25 PM UTC 24
Peak memory 205876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004201645 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1004201645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4157226517
Short name T587
Test name
Test status
Simulation time 270743469 ps
CPU time 1.91 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:27 PM UTC 24
Peak memory 205952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4157226517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.4157226517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.3222936438
Short name T579
Test name
Test status
Simulation time 234905855 ps
CPU time 0.75 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 206580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222936438 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3222936438
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1175283051
Short name T578
Test name
Test status
Simulation time 13136142 ps
CPU time 0.63 seconds
Started Sep 24 07:13:23 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175283051 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1175283051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2589323887
Short name T588
Test name
Test status
Simulation time 508414727 ps
CPU time 2.3 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 206924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589323887 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.2589323887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.3381508061
Short name T597
Test name
Test status
Simulation time 385247099 ps
CPU time 3.89 seconds
Started Sep 24 07:13:23 PM UTC 24
Finished Sep 24 07:13:29 PM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381508061 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3381508061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.100434605
Short name T595
Test name
Test status
Simulation time 368040336 ps
CPU time 3.15 seconds
Started Sep 24 07:13:23 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 207124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100434605 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.100434605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3618286452
Short name T589
Test name
Test status
Simulation time 280957401 ps
CPU time 1.77 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 206008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3618286452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.3618286452
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.257722016
Short name T584
Test name
Test status
Simulation time 15008995 ps
CPU time 0.78 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:27 PM UTC 24
Peak memory 206040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257722016 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.257722016
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.395362358
Short name T582
Test name
Test status
Simulation time 13553240 ps
CPU time 0.73 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:27 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395362358 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.395362358
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.868489545
Short name T592
Test name
Test status
Simulation time 291558430 ps
CPU time 2.13 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868489545 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.868489545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1770961664
Short name T586
Test name
Test status
Simulation time 41257257 ps
CPU time 1.2 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:27 PM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770961664 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1770961664
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.396362525
Short name T146
Test name
Test status
Simulation time 86623548 ps
CPU time 2.81 seconds
Started Sep 24 07:13:24 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 206860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396362525 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.396362525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.179489615
Short name T607
Test name
Test status
Simulation time 71636183 ps
CPU time 2.32 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 206832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=179489615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_r
eset.179489615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.257804741
Short name T593
Test name
Test status
Simulation time 48106505 ps
CPU time 0.81 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 205804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257804741 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.257804741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.580048931
Short name T590
Test name
Test status
Simulation time 15380482 ps
CPU time 0.65 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 202228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580048931 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.580048931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3675792446
Short name T614
Test name
Test status
Simulation time 462368383 ps
CPU time 2.4 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 206800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675792446 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.3675792446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.2518192582
Short name T619
Test name
Test status
Simulation time 213244215 ps
CPU time 2.98 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 206452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518192582 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2518192582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3606578680
Short name T632
Test name
Test status
Simulation time 232584803 ps
CPU time 4.16 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 206400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606578680 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3606578680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.451463874
Short name T604
Test name
Test status
Simulation time 361212087 ps
CPU time 2.23 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 217160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=451463874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_r
eset.451463874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.4153089075
Short name T596
Test name
Test status
Simulation time 32353390 ps
CPU time 1.04 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:29 PM UTC 24
Peak memory 205792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153089075 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4153089075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2841556130
Short name T594
Test name
Test status
Simulation time 23788535 ps
CPU time 0.73 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841556130 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2841556130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1535735614
Short name T612
Test name
Test status
Simulation time 672179025 ps
CPU time 2.38 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 206860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535735614 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.1535735614
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.1808931880
Short name T606
Test name
Test status
Simulation time 214562085 ps
CPU time 2.23 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808931880 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1808931880
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1293081777
Short name T637
Test name
Test status
Simulation time 571178960 ps
CPU time 4.36 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 206856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293081777 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1293081777
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2924258332
Short name T653
Test name
Test status
Simulation time 64400676369 ps
CPU time 1145.75 seconds
Started Sep 24 07:13:26 PM UTC 24
Finished Sep 24 07:32:48 PM UTC 24
Peak memory 231632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2924258332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.2924258332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.703779743
Short name T599
Test name
Test status
Simulation time 70167818 ps
CPU time 1.04 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:29 PM UTC 24
Peak memory 206040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703779743 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.703779743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.2546710676
Short name T591
Test name
Test status
Simulation time 13206894 ps
CPU time 0.6 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:28 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546710676 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2546710676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.367661361
Short name T598
Test name
Test status
Simulation time 75745413 ps
CPU time 1.02 seconds
Started Sep 24 07:13:26 PM UTC 24
Finished Sep 24 07:13:29 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367661361 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.367661361
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.2351061234
Short name T616
Test name
Test status
Simulation time 723833397 ps
CPU time 3.05 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 206840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351061234 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2351061234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2024569365
Short name T627
Test name
Test status
Simulation time 531153286 ps
CPU time 3.13 seconds
Started Sep 24 07:13:25 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024569365 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2024569365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2031543120
Short name T611
Test name
Test status
Simulation time 34780773 ps
CPU time 1.04 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 205816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2031543120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.2031543120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.1463265382
Short name T613
Test name
Test status
Simulation time 17526828 ps
CPU time 1.06 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 205920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463265382 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1463265382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3331741722
Short name T601
Test name
Test status
Simulation time 57320108 ps
CPU time 0.76 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331741722 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3331741722
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4053050535
Short name T623
Test name
Test status
Simulation time 93104284 ps
CPU time 1.73 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 205964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053050535 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.4053050535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.951393402
Short name T630
Test name
Test status
Simulation time 622111918 ps
CPU time 3.2 seconds
Started Sep 24 07:13:26 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 206852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951393402 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.951393402
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.4053375989
Short name T610
Test name
Test status
Simulation time 503254047 ps
CPU time 1.79 seconds
Started Sep 24 07:13:26 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 205876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053375989 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.4053375989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3246370541
Short name T624
Test name
Test status
Simulation time 66035304 ps
CPU time 1.71 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 222388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3246370541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.3246370541
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.3412103110
Short name T609
Test name
Test status
Simulation time 72208971 ps
CPU time 0.84 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412103110 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3412103110
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.3246460621
Short name T600
Test name
Test status
Simulation time 33742234 ps
CPU time 0.67 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246460621 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3246460621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3256362423
Short name T631
Test name
Test status
Simulation time 115459212 ps
CPU time 2.34 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 207108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256362423 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.3256362423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3163482713
Short name T629
Test name
Test status
Simulation time 455494511 ps
CPU time 2.26 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 206836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163482713 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3163482713
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1207756327
Short name T617
Test name
Test status
Simulation time 184758707 ps
CPU time 1.72 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 205876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207756327 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1207756327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3159537758
Short name T533
Test name
Test status
Simulation time 161230425 ps
CPU time 3.13 seconds
Started Sep 24 07:13:12 PM UTC 24
Finished Sep 24 07:13:17 PM UTC 24
Peak memory 207112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159537758 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3159537758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.2976631733
Short name T536
Test name
Test status
Simulation time 415449662 ps
CPU time 4.86 seconds
Started Sep 24 07:13:11 PM UTC 24
Finished Sep 24 07:13:17 PM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976631733 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2976631733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3175532472
Short name T531
Test name
Test status
Simulation time 76787252 ps
CPU time 0.75 seconds
Started Sep 24 07:13:11 PM UTC 24
Finished Sep 24 07:13:13 PM UTC 24
Peak memory 205020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175532472 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3175532472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.703111782
Short name T72
Test name
Test status
Simulation time 227113729 ps
CPU time 1.16 seconds
Started Sep 24 07:13:12 PM UTC 24
Finished Sep 24 07:13:15 PM UTC 24
Peak memory 206044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=703111782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_re
set.703111782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.3284933820
Short name T109
Test name
Test status
Simulation time 48827838 ps
CPU time 0.83 seconds
Started Sep 24 07:13:11 PM UTC 24
Finished Sep 24 07:13:13 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284933820 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3284933820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.1025266897
Short name T530
Test name
Test status
Simulation time 13282509 ps
CPU time 0.69 seconds
Started Sep 24 07:13:11 PM UTC 24
Finished Sep 24 07:13:13 PM UTC 24
Peak memory 202988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025266897 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1025266897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1295001138
Short name T124
Test name
Test status
Simulation time 226315549 ps
CPU time 2.29 seconds
Started Sep 24 07:13:12 PM UTC 24
Finished Sep 24 07:13:16 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295001138 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.1295001138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1468026418
Short name T92
Test name
Test status
Simulation time 64370933 ps
CPU time 3.13 seconds
Started Sep 24 07:13:11 PM UTC 24
Finished Sep 24 07:13:15 PM UTC 24
Peak memory 206976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468026418 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1468026418
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.4071658171
Short name T603
Test name
Test status
Simulation time 16196808 ps
CPU time 0.67 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071658171 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4071658171
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1785771578
Short name T605
Test name
Test status
Simulation time 18085742 ps
CPU time 0.63 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785771578 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1785771578
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.3379652563
Short name T608
Test name
Test status
Simulation time 23636952 ps
CPU time 0.75 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379652563 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3379652563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.387161949
Short name T602
Test name
Test status
Simulation time 35778727 ps
CPU time 0.56 seconds
Started Sep 24 07:13:27 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387161949 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.387161949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.1298609428
Short name T618
Test name
Test status
Simulation time 47737247 ps
CPU time 0.57 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298609428 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1298609428
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.1974069822
Short name T615
Test name
Test status
Simulation time 48678714 ps
CPU time 0.6 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:30 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974069822 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1974069822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.1668117775
Short name T622
Test name
Test status
Simulation time 55698426 ps
CPU time 0.64 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668117775 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1668117775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.45511494
Short name T620
Test name
Test status
Simulation time 11950732 ps
CPU time 0.59 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 202860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45511494 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.45511494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.450036390
Short name T621
Test name
Test status
Simulation time 115683977 ps
CPU time 0.62 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450036390 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.450036390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2616511888
Short name T628
Test name
Test status
Simulation time 43832951 ps
CPU time 0.62 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616511888 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2616511888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.746079232
Short name T539
Test name
Test status
Simulation time 111168180 ps
CPU time 3.23 seconds
Started Sep 24 07:13:14 PM UTC 24
Finished Sep 24 07:13:18 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746079232 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.746079232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.710288943
Short name T575
Test name
Test status
Simulation time 1014979193 ps
CPU time 10.92 seconds
Started Sep 24 07:13:14 PM UTC 24
Finished Sep 24 07:13:26 PM UTC 24
Peak memory 207128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710288943 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.710288943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.2100473557
Short name T110
Test name
Test status
Simulation time 49010044 ps
CPU time 0.93 seconds
Started Sep 24 07:13:14 PM UTC 24
Finished Sep 24 07:13:16 PM UTC 24
Peak memory 205648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100473557 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2100473557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.107235712
Short name T537
Test name
Test status
Simulation time 132493682 ps
CPU time 2.38 seconds
Started Sep 24 07:13:14 PM UTC 24
Finished Sep 24 07:13:17 PM UTC 24
Peak memory 206908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=107235712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_re
set.107235712
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.2185802146
Short name T123
Test name
Test status
Simulation time 20185696 ps
CPU time 0.74 seconds
Started Sep 24 07:13:14 PM UTC 24
Finished Sep 24 07:13:15 PM UTC 24
Peak memory 204988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185802146 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2185802146
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.2566525784
Short name T532
Test name
Test status
Simulation time 40743031 ps
CPU time 0.67 seconds
Started Sep 24 07:13:14 PM UTC 24
Finished Sep 24 07:13:15 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566525784 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2566525784
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1201710233
Short name T125
Test name
Test status
Simulation time 286353595 ps
CPU time 1.64 seconds
Started Sep 24 07:13:14 PM UTC 24
Finished Sep 24 07:13:16 PM UTC 24
Peak memory 205932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201710233 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.1201710233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.833959682
Short name T535
Test name
Test status
Simulation time 154185919 ps
CPU time 3.13 seconds
Started Sep 24 07:13:12 PM UTC 24
Finished Sep 24 07:13:17 PM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833959682 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.833959682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.2661979773
Short name T65
Test name
Test status
Simulation time 101112168 ps
CPU time 1.75 seconds
Started Sep 24 07:13:13 PM UTC 24
Finished Sep 24 07:13:15 PM UTC 24
Peak memory 205940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661979773 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2661979773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.710629373
Short name T625
Test name
Test status
Simulation time 101262551 ps
CPU time 0.58 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710629373 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.710629373
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.1490777399
Short name T626
Test name
Test status
Simulation time 13279477 ps
CPU time 0.61 seconds
Started Sep 24 07:13:28 PM UTC 24
Finished Sep 24 07:13:31 PM UTC 24
Peak memory 202928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490777399 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1490777399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.241592704
Short name T634
Test name
Test status
Simulation time 21081487 ps
CPU time 0.71 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241592704 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.241592704
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.934559598
Short name T639
Test name
Test status
Simulation time 25773889 ps
CPU time 0.8 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934559598 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.934559598
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.1882255008
Short name T635
Test name
Test status
Simulation time 50865837 ps
CPU time 0.64 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882255008 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1882255008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.97603896
Short name T633
Test name
Test status
Simulation time 46722288 ps
CPU time 0.61 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97603896 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.97603896
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.2582653472
Short name T638
Test name
Test status
Simulation time 14269849 ps
CPU time 0.73 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582653472 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2582653472
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.3351302761
Short name T636
Test name
Test status
Simulation time 31054895 ps
CPU time 0.59 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351302761 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3351302761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.848262972
Short name T641
Test name
Test status
Simulation time 29024607 ps
CPU time 0.67 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848262972 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.848262972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.2544855888
Short name T643
Test name
Test status
Simulation time 24054697 ps
CPU time 0.64 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544855888 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2544855888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.2095680375
Short name T115
Test name
Test status
Simulation time 305158707 ps
CPU time 3.41 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:21 PM UTC 24
Peak memory 206784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095680375 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2095680375
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4268849650
Short name T581
Test name
Test status
Simulation time 1224439156 ps
CPU time 9.4 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:27 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268849650 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4268849650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.73475257
Short name T112
Test name
Test status
Simulation time 35092785 ps
CPU time 1.09 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:18 PM UTC 24
Peak memory 206148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73475257 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.73475257
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2271475612
Short name T541
Test name
Test status
Simulation time 21395983 ps
CPU time 1.23 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:18 PM UTC 24
Peak memory 206028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2271475612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.2271475612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.3070342763
Short name T126
Test name
Test status
Simulation time 124142651 ps
CPU time 1.01 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:18 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070342763 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3070342763
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.3944791819
Short name T538
Test name
Test status
Simulation time 41808637 ps
CPU time 0.7 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:18 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944791819 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3944791819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.122702475
Short name T127
Test name
Test status
Simulation time 46006222 ps
CPU time 1.22 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:19 PM UTC 24
Peak memory 206228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122702475 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.122702475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1390117374
Short name T543
Test name
Test status
Simulation time 166206752 ps
CPU time 3.67 seconds
Started Sep 24 07:13:15 PM UTC 24
Finished Sep 24 07:13:20 PM UTC 24
Peak memory 206996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390117374 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1390117374
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.4034783159
Short name T141
Test name
Test status
Simulation time 94331097 ps
CPU time 1.82 seconds
Started Sep 24 07:13:15 PM UTC 24
Finished Sep 24 07:13:18 PM UTC 24
Peak memory 205940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034783159 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4034783159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3270083347
Short name T640
Test name
Test status
Simulation time 31628847 ps
CPU time 0.59 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270083347 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3270083347
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2057304151
Short name T642
Test name
Test status
Simulation time 85654807 ps
CPU time 0.65 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057304151 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2057304151
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.3308367574
Short name T644
Test name
Test status
Simulation time 41536646 ps
CPU time 0.64 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308367574 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3308367574
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.772125895
Short name T646
Test name
Test status
Simulation time 11843259 ps
CPU time 0.56 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772125895 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.772125895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.2998078032
Short name T645
Test name
Test status
Simulation time 24332095 ps
CPU time 0.57 seconds
Started Sep 24 07:13:30 PM UTC 24
Finished Sep 24 07:13:32 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998078032 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2998078032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1927613999
Short name T648
Test name
Test status
Simulation time 13724431 ps
CPU time 0.62 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:33 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927613999 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1927613999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2726256779
Short name T649
Test name
Test status
Simulation time 44064804 ps
CPU time 0.55 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726256779 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2726256779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.3284569708
Short name T650
Test name
Test status
Simulation time 16442958 ps
CPU time 0.62 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284569708 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3284569708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2948082031
Short name T651
Test name
Test status
Simulation time 50943039 ps
CPU time 0.6 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:36 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948082031 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2948082031
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.700486349
Short name T647
Test name
Test status
Simulation time 42882886 ps
CPU time 0.61 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:33 PM UTC 24
Peak memory 202864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700486349 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.700486349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3520922278
Short name T546
Test name
Test status
Simulation time 65068093 ps
CPU time 1.59 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:20 PM UTC 24
Peak memory 206120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3520922278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.3520922278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.1563506767
Short name T114
Test name
Test status
Simulation time 219939500 ps
CPU time 0.85 seconds
Started Sep 24 07:13:17 PM UTC 24
Finished Sep 24 07:13:19 PM UTC 24
Peak memory 206104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563506767 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1563506767
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.835266756
Short name T540
Test name
Test status
Simulation time 22915560 ps
CPU time 0.68 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:18 PM UTC 24
Peak memory 202860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835266756 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.835266756
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.659223104
Short name T548
Test name
Test status
Simulation time 38509045 ps
CPU time 1.74 seconds
Started Sep 24 07:13:17 PM UTC 24
Finished Sep 24 07:13:20 PM UTC 24
Peak memory 206000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659223104 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.659223104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.560890085
Short name T547
Test name
Test status
Simulation time 231913752 ps
CPU time 2.92 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:20 PM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560890085 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.560890085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.1467263133
Short name T142
Test name
Test status
Simulation time 455131410 ps
CPU time 4.27 seconds
Started Sep 24 07:13:16 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 206848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467263133 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1467263133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3124181308
Short name T555
Test name
Test status
Simulation time 46921271 ps
CPU time 3.02 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3124181308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.3124181308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3428760441
Short name T545
Test name
Test status
Simulation time 18895305 ps
CPU time 0.89 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:20 PM UTC 24
Peak memory 205752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428760441 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3428760441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.802518448
Short name T544
Test name
Test status
Simulation time 46776666 ps
CPU time 0.76 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:20 PM UTC 24
Peak memory 202860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802518448 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.802518448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.769162133
Short name T549
Test name
Test status
Simulation time 214823326 ps
CPU time 1.71 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:21 PM UTC 24
Peak memory 205996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769162133 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.769162133
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3755229294
Short name T550
Test name
Test status
Simulation time 94772271 ps
CPU time 2.02 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:21 PM UTC 24
Peak memory 206912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755229294 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3755229294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.2927902104
Short name T144
Test name
Test status
Simulation time 310601593 ps
CPU time 1.71 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:21 PM UTC 24
Peak memory 205728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927902104 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2927902104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3823623292
Short name T654
Test name
Test status
Simulation time 507168471518 ps
CPU time 1438.07 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:37:34 PM UTC 24
Peak memory 237824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3823623292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_r
eset.3823623292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.3799797461
Short name T116
Test name
Test status
Simulation time 48457114 ps
CPU time 0.98 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:21 PM UTC 24
Peak memory 205988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799797461 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3799797461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1586181638
Short name T551
Test name
Test status
Simulation time 14203493 ps
CPU time 0.69 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:21 PM UTC 24
Peak memory 202988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586181638 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1586181638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3589611984
Short name T562
Test name
Test status
Simulation time 136139587 ps
CPU time 2.43 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:23 PM UTC 24
Peak memory 206776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589611984 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.3589611984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.792133628
Short name T557
Test name
Test status
Simulation time 398037069 ps
CPU time 3.24 seconds
Started Sep 24 07:13:18 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 206840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792133628 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.792133628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3924744287
Short name T558
Test name
Test status
Simulation time 100918193 ps
CPU time 2 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 205888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924744287 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3924744287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2273825957
Short name T568
Test name
Test status
Simulation time 42341255 ps
CPU time 2.83 seconds
Started Sep 24 07:13:20 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 206876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2273825957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.2273825957
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.2365943741
Short name T118
Test name
Test status
Simulation time 38237451 ps
CPU time 0.88 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 206104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365943741 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2365943741
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1102418800
Short name T552
Test name
Test status
Simulation time 122097740 ps
CPU time 0.73 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 203048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102418800 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1102418800
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.382903516
Short name T553
Test name
Test status
Simulation time 43163724 ps
CPU time 1.18 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 205996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382903516 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.382903516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2704130239
Short name T566
Test name
Test status
Simulation time 674919136 ps
CPU time 3.55 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 206924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704130239 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2704130239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.3941841249
Short name T143
Test name
Test status
Simulation time 188314687 ps
CPU time 3.42 seconds
Started Sep 24 07:13:19 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 206804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941841249 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3941841249
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3856745096
Short name T561
Test name
Test status
Simulation time 32555434 ps
CPU time 1.22 seconds
Started Sep 24 07:13:21 PM UTC 24
Finished Sep 24 07:13:23 PM UTC 24
Peak memory 206048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3856745096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3856745096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.767279670
Short name T119
Test name
Test status
Simulation time 15893476 ps
CPU time 0.82 seconds
Started Sep 24 07:13:20 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 206336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767279670 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.767279670
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.891273800
Short name T556
Test name
Test status
Simulation time 45242209 ps
CPU time 0.71 seconds
Started Sep 24 07:13:20 PM UTC 24
Finished Sep 24 07:13:22 PM UTC 24
Peak memory 202860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891273800 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.891273800
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3046660632
Short name T564
Test name
Test status
Simulation time 95313796 ps
CPU time 1.84 seconds
Started Sep 24 07:13:21 PM UTC 24
Finished Sep 24 07:13:24 PM UTC 24
Peak memory 205876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046660632 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.3046660632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.2671364726
Short name T570
Test name
Test status
Simulation time 159618496 ps
CPU time 3.42 seconds
Started Sep 24 07:13:20 PM UTC 24
Finished Sep 24 07:13:25 PM UTC 24
Peak memory 206708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671364726 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2671364726
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.4118359952
Short name T563
Test name
Test status
Simulation time 387992381 ps
CPU time 1.99 seconds
Started Sep 24 07:13:20 PM UTC 24
Finished Sep 24 07:13:23 PM UTC 24
Peak memory 205888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118359952 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4118359952
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.1839732717
Short name T340
Test name
Test status
Simulation time 6271591952 ps
CPU time 1262.56 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:34:51 PM UTC 24
Peak memory 742824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839732717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1839732717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_error.476919534
Short name T9
Test name
Test status
Simulation time 6930034826 ps
CPU time 26.02 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:14:02 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476919534 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.476919534
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_smoke.3174837319
Short name T2
Test name
Test status
Simulation time 69302350 ps
CPU time 2.83 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:38 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174837319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3174837319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_stress_all.617547352
Short name T391
Test name
Test status
Simulation time 96451719302 ps
CPU time 1639.12 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:41:18 PM UTC 24
Peak memory 742656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617547352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.617547352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.859063721
Short name T56
Test name
Test status
Simulation time 9524572860 ps
CPU time 84.9 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:15:02 PM UTC 24
Peak memory 210688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859063721 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.859063721
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.940997049
Short name T34
Test name
Test status
Simulation time 9298135176 ps
CPU time 105.06 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:15:29 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940997049 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.940997049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.1311919365
Short name T172
Test name
Test status
Simulation time 8016941416 ps
CPU time 100.1 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:15:17 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311919365 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1311919365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.3288687291
Short name T275
Test name
Test status
Simulation time 59101235878 ps
CPU time 893.97 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:28:41 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288687291 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3288687291
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.187408642
Short name T488
Test name
Test status
Simulation time 76228820069 ps
CPU time 2444.75 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:54:49 PM UTC 24
Peak memory 226156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187408642 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.187408642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.1368778351
Short name T497
Test name
Test status
Simulation time 270742774921 ps
CPU time 2795.02 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 08:00:43 PM UTC 24
Peak memory 218984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368778351 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1368778351
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.4111547251
Short name T6
Test name
Test status
Simulation time 5826723428 ps
CPU time 23.21 seconds
Started Sep 24 07:13:31 PM UTC 24
Finished Sep 24 07:13:59 PM UTC 24
Peak memory 210824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111547251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4111547251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_alert_test.2920448649
Short name T22
Test name
Test status
Simulation time 44016176 ps
CPU time 0.64 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:13:42 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920448649 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2920448649
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.1409725657
Short name T11
Test name
Test status
Simulation time 2887328485 ps
CPU time 47.87 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:14:24 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409725657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1409725657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.304685668
Short name T12
Test name
Test status
Simulation time 778503306 ps
CPU time 43.28 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:14:25 PM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304685668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.304685668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.24564931
Short name T343
Test name
Test status
Simulation time 11223390214 ps
CPU time 1269.49 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:35:05 PM UTC 24
Peak memory 722164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24564931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.24564931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_error.873494974
Short name T147
Test name
Test status
Simulation time 67037097551 ps
CPU time 191.26 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:16:55 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873494974 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.873494974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_long_msg.2412277385
Short name T167
Test name
Test status
Simulation time 7925325323 ps
CPU time 147.82 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:16:13 PM UTC 24
Peak memory 219236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412277385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2412277385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.1049112986
Short name T23
Test name
Test status
Simulation time 275497261 ps
CPU time 1.39 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:13:43 PM UTC 24
Peak memory 238200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049112986 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1049112986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_smoke.29256082
Short name T7
Test name
Test status
Simulation time 4426910740 ps
CPU time 23.75 seconds
Started Sep 24 07:13:32 PM UTC 24
Finished Sep 24 07:14:00 PM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29256082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.hmac_smoke.29256082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_stress_all.3365253166
Short name T104
Test name
Test status
Simulation time 20886463639 ps
CPU time 1156.21 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:33:11 PM UTC 24
Peak memory 221024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365253166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3365253166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.1163870998
Short name T160
Test name
Test status
Simulation time 7617442698 ps
CPU time 54.38 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:14:36 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163870998 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1163870998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.2643071987
Short name T39
Test name
Test status
Simulation time 2284947827 ps
CPU time 113.93 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:15:37 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643071987 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2643071987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.1254968829
Short name T74
Test name
Test status
Simulation time 9335784977 ps
CPU time 97.7 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:15:20 PM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254968829 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1254968829
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.1606863466
Short name T155
Test name
Test status
Simulation time 10253261252 ps
CPU time 630.41 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:24:19 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606863466 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1606863466
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.2523660551
Short name T501
Test name
Test status
Simulation time 289423600590 ps
CPU time 2911.19 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 08:02:49 PM UTC 24
Peak memory 226844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523660551 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2523660551
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.1904197079
Short name T500
Test name
Test status
Simulation time 184612206908 ps
CPU time 2868.62 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 08:02:06 PM UTC 24
Peak memory 218984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904197079 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1904197079
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.2902253608
Short name T28
Test name
Test status
Simulation time 4436056598 ps
CPU time 49.02 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:14:31 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902253608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2902253608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_alert_test.2876924417
Short name T193
Test name
Test status
Simulation time 14051092 ps
CPU time 0.99 seconds
Started Sep 24 07:17:51 PM UTC 24
Finished Sep 24 07:17:53 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876924417 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2876924417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.786453885
Short name T190
Test name
Test status
Simulation time 258917194 ps
CPU time 19.11 seconds
Started Sep 24 07:17:23 PM UTC 24
Finished Sep 24 07:17:43 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786453885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.786453885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.283569585
Short name T195
Test name
Test status
Simulation time 1693627208 ps
CPU time 48.46 seconds
Started Sep 24 07:17:34 PM UTC 24
Finished Sep 24 07:18:24 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283569585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.283569585
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.935738647
Short name T301
Test name
Test status
Simulation time 18983370094 ps
CPU time 821.29 seconds
Started Sep 24 07:17:32 PM UTC 24
Finished Sep 24 07:31:22 PM UTC 24
Peak memory 751104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935738647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.935738647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_error.2329052836
Short name T209
Test name
Test status
Simulation time 8990059932 ps
CPU time 178.49 seconds
Started Sep 24 07:17:38 PM UTC 24
Finished Sep 24 07:20:40 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329052836 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2329052836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_long_msg.4100518543
Short name T206
Test name
Test status
Simulation time 9244286105 ps
CPU time 176.97 seconds
Started Sep 24 07:17:23 PM UTC 24
Finished Sep 24 07:20:23 PM UTC 24
Peak memory 219028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100518543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4100518543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_smoke.728713013
Short name T189
Test name
Test status
Simulation time 568975773 ps
CPU time 4.35 seconds
Started Sep 24 07:17:16 PM UTC 24
Finished Sep 24 07:17:22 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728713013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.728713013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_stress_all.4039478048
Short name T490
Test name
Test status
Simulation time 21691356726 ps
CPU time 2212.63 seconds
Started Sep 24 07:17:44 PM UTC 24
Finished Sep 24 07:55:02 PM UTC 24
Peak memory 761348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039478048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.4039478048
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.1276923730
Short name T86
Test name
Test status
Simulation time 6081448544 ps
CPU time 120.51 seconds
Started Sep 24 07:17:43 PM UTC 24
Finished Sep 24 07:19:46 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276923730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1276923730
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_alert_test.1288151756
Short name T196
Test name
Test status
Simulation time 11579910 ps
CPU time 1.01 seconds
Started Sep 24 07:18:39 PM UTC 24
Finished Sep 24 07:18:42 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288151756 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1288151756
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.2145330860
Short name T194
Test name
Test status
Simulation time 838898161 ps
CPU time 26.37 seconds
Started Sep 24 07:17:56 PM UTC 24
Finished Sep 24 07:18:24 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145330860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2145330860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.441477775
Short name T200
Test name
Test status
Simulation time 20672725406 ps
CPU time 98.08 seconds
Started Sep 24 07:18:25 PM UTC 24
Finished Sep 24 07:20:05 PM UTC 24
Peak memory 226884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441477775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.441477775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.922073360
Short name T238
Test name
Test status
Simulation time 5188790438 ps
CPU time 432.46 seconds
Started Sep 24 07:18:12 PM UTC 24
Finished Sep 24 07:25:30 PM UTC 24
Peak memory 480604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922073360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.922073360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_error.646056727
Short name T89
Test name
Test status
Simulation time 15723951995 ps
CPU time 88.14 seconds
Started Sep 24 07:18:27 PM UTC 24
Finished Sep 24 07:19:57 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646056727 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.646056727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_long_msg.1351582630
Short name T199
Test name
Test status
Simulation time 6377804233 ps
CPU time 86.5 seconds
Started Sep 24 07:17:54 PM UTC 24
Finished Sep 24 07:19:22 PM UTC 24
Peak memory 219044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351582630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1351582630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_smoke.418676900
Short name T169
Test name
Test status
Simulation time 273909806 ps
CPU time 18.64 seconds
Started Sep 24 07:17:51 PM UTC 24
Finished Sep 24 07:18:11 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418676900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.418676900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_stress_all.221011534
Short name T348
Test name
Test status
Simulation time 24160948404 ps
CPU time 1051.41 seconds
Started Sep 24 07:18:28 PM UTC 24
Finished Sep 24 07:36:14 PM UTC 24
Peak memory 716104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221011534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.221011534
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.1359873126
Short name T91
Test name
Test status
Simulation time 2715508281 ps
CPU time 94.42 seconds
Started Sep 24 07:18:27 PM UTC 24
Finished Sep 24 07:20:04 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359873126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1359873126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_alert_test.3578490371
Short name T85
Test name
Test status
Simulation time 51275630 ps
CPU time 0.93 seconds
Started Sep 24 07:19:42 PM UTC 24
Finished Sep 24 07:19:44 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578490371 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3578490371
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.3509723900
Short name T83
Test name
Test status
Simulation time 1670975394 ps
CPU time 35.83 seconds
Started Sep 24 07:18:56 PM UTC 24
Finished Sep 24 07:19:34 PM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509723900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3509723900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.3919291618
Short name T87
Test name
Test status
Simulation time 6160956321 ps
CPU time 41.5 seconds
Started Sep 24 07:19:09 PM UTC 24
Finished Sep 24 07:19:53 PM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919291618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3919291618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.458940766
Short name T222
Test name
Test status
Simulation time 2021136109 ps
CPU time 269.18 seconds
Started Sep 24 07:18:58 PM UTC 24
Finished Sep 24 07:23:32 PM UTC 24
Peak memory 486612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458940766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.458940766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_error.129346944
Short name T213
Test name
Test status
Simulation time 1607628694 ps
CPU time 107.58 seconds
Started Sep 24 07:19:25 PM UTC 24
Finished Sep 24 07:21:15 PM UTC 24
Peak memory 210356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129346944 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.129346944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_long_msg.2726959286
Short name T214
Test name
Test status
Simulation time 9701556922 ps
CPU time 161.95 seconds
Started Sep 24 07:18:42 PM UTC 24
Finished Sep 24 07:21:27 PM UTC 24
Peak memory 221144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726959286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2726959286
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_smoke.2784347575
Short name T154
Test name
Test status
Simulation time 2226160415 ps
CPU time 14.63 seconds
Started Sep 24 07:18:41 PM UTC 24
Finished Sep 24 07:18:57 PM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784347575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2784347575
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_stress_all.3831730727
Short name T138
Test name
Test status
Simulation time 144308481562 ps
CPU time 699.04 seconds
Started Sep 24 07:19:35 PM UTC 24
Finished Sep 24 07:31:23 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831730727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3831730727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.3360110464
Short name T88
Test name
Test status
Simulation time 5820897794 ps
CPU time 20.22 seconds
Started Sep 24 07:19:35 PM UTC 24
Finished Sep 24 07:19:57 PM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360110464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3360110464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_alert_test.2420107765
Short name T203
Test name
Test status
Simulation time 160294094 ps
CPU time 0.91 seconds
Started Sep 24 07:20:11 PM UTC 24
Finished Sep 24 07:20:13 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420107765 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2420107765
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.739953813
Short name T210
Test name
Test status
Simulation time 596779147 ps
CPU time 48.04 seconds
Started Sep 24 07:19:53 PM UTC 24
Finished Sep 24 07:20:43 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739953813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.739953813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.3934451344
Short name T208
Test name
Test status
Simulation time 1561461589 ps
CPU time 37.94 seconds
Started Sep 24 07:20:00 PM UTC 24
Finished Sep 24 07:20:40 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934451344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3934451344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.2277808846
Short name T357
Test name
Test status
Simulation time 8403876905 ps
CPU time 1015.36 seconds
Started Sep 24 07:19:58 PM UTC 24
Finished Sep 24 07:37:08 PM UTC 24
Peak memory 738820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277808846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2277808846
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_error.2944121228
Short name T225
Test name
Test status
Simulation time 47311253223 ps
CPU time 213.54 seconds
Started Sep 24 07:20:05 PM UTC 24
Finished Sep 24 07:23:42 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944121228 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2944121228
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_long_msg.1209083613
Short name T205
Test name
Test status
Simulation time 1882845863 ps
CPU time 30.31 seconds
Started Sep 24 07:19:49 PM UTC 24
Finished Sep 24 07:20:21 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209083613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1209083613
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_smoke.3126972296
Short name T201
Test name
Test status
Simulation time 3245345658 ps
CPU time 20.89 seconds
Started Sep 24 07:19:46 PM UTC 24
Finished Sep 24 07:20:09 PM UTC 24
Peak memory 219048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126972296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3126972296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_stress_all.1752416597
Short name T511
Test name
Test status
Simulation time 201586625580 ps
CPU time 2934.4 seconds
Started Sep 24 07:20:07 PM UTC 24
Finished Sep 24 08:09:35 PM UTC 24
Peak memory 816496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752416597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1752416597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.3917709919
Short name T133
Test name
Test status
Simulation time 685113533 ps
CPU time 36.46 seconds
Started Sep 24 07:20:05 PM UTC 24
Finished Sep 24 07:20:43 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917709919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3917709919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_alert_test.4029461315
Short name T211
Test name
Test status
Simulation time 14633292 ps
CPU time 0.94 seconds
Started Sep 24 07:20:45 PM UTC 24
Finished Sep 24 07:20:47 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029461315 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4029461315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.2182975370
Short name T207
Test name
Test status
Simulation time 32098837 ps
CPU time 2.74 seconds
Started Sep 24 07:20:22 PM UTC 24
Finished Sep 24 07:20:26 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182975370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2182975370
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.3046463558
Short name T96
Test name
Test status
Simulation time 2266393584 ps
CPU time 86.28 seconds
Started Sep 24 07:20:25 PM UTC 24
Finished Sep 24 07:21:54 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046463558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3046463558
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.3643068610
Short name T252
Test name
Test status
Simulation time 1925089194 ps
CPU time 377.56 seconds
Started Sep 24 07:20:22 PM UTC 24
Finished Sep 24 07:26:45 PM UTC 24
Peak memory 709780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643068610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3643068610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_error.2241316916
Short name T220
Test name
Test status
Simulation time 87969490466 ps
CPU time 176.63 seconds
Started Sep 24 07:20:27 PM UTC 24
Finished Sep 24 07:23:27 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241316916 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2241316916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_long_msg.39639047
Short name T223
Test name
Test status
Simulation time 20299037270 ps
CPU time 196.05 seconds
Started Sep 24 07:20:14 PM UTC 24
Finished Sep 24 07:23:33 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39639047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.39639047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_smoke.335931069
Short name T204
Test name
Test status
Simulation time 121299568 ps
CPU time 5.22 seconds
Started Sep 24 07:20:14 PM UTC 24
Finished Sep 24 07:20:20 PM UTC 24
Peak memory 210640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335931069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.335931069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_stress_all.4097851849
Short name T67
Test name
Test status
Simulation time 84709637538 ps
CPU time 349.65 seconds
Started Sep 24 07:20:42 PM UTC 24
Finished Sep 24 07:26:38 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097851849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.4097851849
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.1616640318
Short name T219
Test name
Test status
Simulation time 2510017837 ps
CPU time 159.95 seconds
Started Sep 24 07:20:42 PM UTC 24
Finished Sep 24 07:23:25 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616640318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1616640318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_alert_test.2771008811
Short name T94
Test name
Test status
Simulation time 23852492 ps
CPU time 0.91 seconds
Started Sep 24 07:21:44 PM UTC 24
Finished Sep 24 07:21:46 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771008811 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2771008811
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.3600882023
Short name T100
Test name
Test status
Simulation time 6341118392 ps
CPU time 108.04 seconds
Started Sep 24 07:20:49 PM UTC 24
Finished Sep 24 07:22:40 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600882023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3600882023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.4258457080
Short name T93
Test name
Test status
Simulation time 2034075787 ps
CPU time 24.15 seconds
Started Sep 24 07:21:17 PM UTC 24
Finished Sep 24 07:21:42 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258457080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4258457080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.1774419790
Short name T334
Test name
Test status
Simulation time 3513947912 ps
CPU time 782.05 seconds
Started Sep 24 07:21:08 PM UTC 24
Finished Sep 24 07:34:20 PM UTC 24
Peak memory 740600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774419790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1774419790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_error.2603735314
Short name T227
Test name
Test status
Simulation time 2421224352 ps
CPU time 145.4 seconds
Started Sep 24 07:21:18 PM UTC 24
Finished Sep 24 07:23:46 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603735314 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2603735314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_long_msg.493312457
Short name T216
Test name
Test status
Simulation time 29007366598 ps
CPU time 138.28 seconds
Started Sep 24 07:20:49 PM UTC 24
Finished Sep 24 07:23:10 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493312457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.493312457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_smoke.1005761618
Short name T212
Test name
Test status
Simulation time 129633128 ps
CPU time 2.72 seconds
Started Sep 24 07:20:45 PM UTC 24
Finished Sep 24 07:20:49 PM UTC 24
Peak memory 210116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005761618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1005761618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_stress_all.2481521370
Short name T161
Test name
Test status
Simulation time 13184978639 ps
CPU time 211.4 seconds
Started Sep 24 07:21:34 PM UTC 24
Finished Sep 24 07:25:09 PM UTC 24
Peak memory 221116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481521370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2481521370
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.3094472346
Short name T218
Test name
Test status
Simulation time 5825994575 ps
CPU time 110.74 seconds
Started Sep 24 07:21:29 PM UTC 24
Finished Sep 24 07:23:23 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094472346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3094472346
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_alert_test.93411707
Short name T215
Test name
Test status
Simulation time 12162327 ps
CPU time 0.93 seconds
Started Sep 24 07:22:57 PM UTC 24
Finished Sep 24 07:22:59 PM UTC 24
Peak memory 207392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93411707 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.93411707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.1065953117
Short name T99
Test name
Test status
Simulation time 903302281 ps
CPU time 36.54 seconds
Started Sep 24 07:21:55 PM UTC 24
Finished Sep 24 07:22:33 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065953117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1065953117
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.786762183
Short name T221
Test name
Test status
Simulation time 2403814326 ps
CPU time 67.08 seconds
Started Sep 24 07:22:20 PM UTC 24
Finished Sep 24 07:23:29 PM UTC 24
Peak memory 210540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786762183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.786762183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.2878513249
Short name T387
Test name
Test status
Simulation time 31861831702 ps
CPU time 1116.49 seconds
Started Sep 24 07:21:55 PM UTC 24
Finished Sep 24 07:40:45 PM UTC 24
Peak memory 752960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878513249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2878513249
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_error.751607747
Short name T244
Test name
Test status
Simulation time 59474195175 ps
CPU time 215.31 seconds
Started Sep 24 07:22:36 PM UTC 24
Finished Sep 24 07:26:14 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751607747 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.751607747
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_long_msg.2360722778
Short name T97
Test name
Test status
Simulation time 89003890 ps
CPU time 1.07 seconds
Started Sep 24 07:21:52 PM UTC 24
Finished Sep 24 07:21:54 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360722778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2360722778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_smoke.1426065302
Short name T95
Test name
Test status
Simulation time 63479616 ps
CPU time 2.73 seconds
Started Sep 24 07:21:47 PM UTC 24
Finished Sep 24 07:21:50 PM UTC 24
Peak memory 210676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426065302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1426065302
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_stress_all.1010114327
Short name T105
Test name
Test status
Simulation time 80253149695 ps
CPU time 710.08 seconds
Started Sep 24 07:22:42 PM UTC 24
Finished Sep 24 07:34:41 PM UTC 24
Peak memory 636260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010114327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1010114327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.3941774545
Short name T101
Test name
Test status
Simulation time 628039520 ps
CPU time 19.18 seconds
Started Sep 24 07:22:36 PM UTC 24
Finished Sep 24 07:22:56 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941774545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3941774545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_alert_test.4277700991
Short name T224
Test name
Test status
Simulation time 26362607 ps
CPU time 0.99 seconds
Started Sep 24 07:23:35 PM UTC 24
Finished Sep 24 07:23:37 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277700991 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.4277700991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.4282755790
Short name T20
Test name
Test status
Simulation time 3735592306 ps
CPU time 103.33 seconds
Started Sep 24 07:23:18 PM UTC 24
Finished Sep 24 07:25:04 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282755790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4282755790
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.2023812907
Short name T163
Test name
Test status
Simulation time 1009396350 ps
CPU time 36.48 seconds
Started Sep 24 07:23:27 PM UTC 24
Finished Sep 24 07:24:05 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023812907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2023812907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.2023984948
Short name T400
Test name
Test status
Simulation time 5527957022 ps
CPU time 1122.29 seconds
Started Sep 24 07:23:24 PM UTC 24
Finished Sep 24 07:42:19 PM UTC 24
Peak memory 724220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023984948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2023984948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_error.3767008945
Short name T247
Test name
Test status
Simulation time 24378196826 ps
CPU time 169.16 seconds
Started Sep 24 07:23:29 PM UTC 24
Finished Sep 24 07:26:21 PM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767008945 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3767008945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_long_msg.1664400172
Short name T235
Test name
Test status
Simulation time 8764050761 ps
CPU time 122.02 seconds
Started Sep 24 07:23:12 PM UTC 24
Finished Sep 24 07:25:16 PM UTC 24
Peak memory 219024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664400172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1664400172
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_smoke.4025081131
Short name T217
Test name
Test status
Simulation time 1736861019 ps
CPU time 16.38 seconds
Started Sep 24 07:23:00 PM UTC 24
Finished Sep 24 07:23:18 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025081131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.4025081131
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_stress_all.3128541057
Short name T80
Test name
Test status
Simulation time 188226061658 ps
CPU time 1765.32 seconds
Started Sep 24 07:23:33 PM UTC 24
Finished Sep 24 07:53:18 PM UTC 24
Peak memory 757080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128541057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3128541057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.2634328478
Short name T102
Test name
Test status
Simulation time 3196990974 ps
CPU time 74.84 seconds
Started Sep 24 07:23:30 PM UTC 24
Finished Sep 24 07:24:47 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634328478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2634328478
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_alert_test.1936767001
Short name T232
Test name
Test status
Simulation time 12647834 ps
CPU time 0.96 seconds
Started Sep 24 07:24:06 PM UTC 24
Finished Sep 24 07:24:08 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936767001 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1936767001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.732964450
Short name T228
Test name
Test status
Simulation time 40971308 ps
CPU time 2.39 seconds
Started Sep 24 07:23:46 PM UTC 24
Finished Sep 24 07:23:50 PM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732964450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.732964450
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.2133868648
Short name T231
Test name
Test status
Simulation time 236308167 ps
CPU time 8.12 seconds
Started Sep 24 07:23:50 PM UTC 24
Finished Sep 24 07:24:00 PM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133868648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2133868648
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.2899437744
Short name T253
Test name
Test status
Simulation time 1295692986 ps
CPU time 182.22 seconds
Started Sep 24 07:23:48 PM UTC 24
Finished Sep 24 07:26:54 PM UTC 24
Peak memory 427256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899437744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2899437744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_error.97916713
Short name T234
Test name
Test status
Simulation time 908090261 ps
CPU time 51.86 seconds
Started Sep 24 07:23:59 PM UTC 24
Finished Sep 24 07:24:52 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97916713 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.97916713
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_long_msg.2446443287
Short name T255
Test name
Test status
Simulation time 10304276216 ps
CPU time 202.65 seconds
Started Sep 24 07:23:44 PM UTC 24
Finished Sep 24 07:27:11 PM UTC 24
Peak memory 221048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446443287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2446443287
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_smoke.457479371
Short name T230
Test name
Test status
Simulation time 3783525130 ps
CPU time 18.38 seconds
Started Sep 24 07:23:38 PM UTC 24
Finished Sep 24 07:23:58 PM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457479371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.457479371
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_stress_all.2532351177
Short name T139
Test name
Test status
Simulation time 2621717887 ps
CPU time 179.94 seconds
Started Sep 24 07:24:01 PM UTC 24
Finished Sep 24 07:27:04 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532351177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2532351177
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.953360213
Short name T248
Test name
Test status
Simulation time 3006195927 ps
CPU time 139.57 seconds
Started Sep 24 07:24:00 PM UTC 24
Finished Sep 24 07:26:22 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953360213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.953360213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_alert_test.2751294023
Short name T237
Test name
Test status
Simulation time 78913020 ps
CPU time 0.79 seconds
Started Sep 24 07:25:22 PM UTC 24
Finished Sep 24 07:25:24 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751294023 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2751294023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.171312310
Short name T98
Test name
Test status
Simulation time 1680204608 ps
CPU time 119.76 seconds
Started Sep 24 07:24:36 PM UTC 24
Finished Sep 24 07:26:38 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171312310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.171312310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.1592376531
Short name T243
Test name
Test status
Simulation time 3617770082 ps
CPU time 75.31 seconds
Started Sep 24 07:24:53 PM UTC 24
Finished Sep 24 07:26:11 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592376531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1592376531
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.3835877319
Short name T312
Test name
Test status
Simulation time 4828036572 ps
CPU time 449.48 seconds
Started Sep 24 07:24:48 PM UTC 24
Finished Sep 24 07:32:23 PM UTC 24
Peak memory 658976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835877319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3835877319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_error.1046523939
Short name T277
Test name
Test status
Simulation time 60732794740 ps
CPU time 221.88 seconds
Started Sep 24 07:25:06 PM UTC 24
Finished Sep 24 07:28:51 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046523939 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1046523939
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_long_msg.3474631278
Short name T241
Test name
Test status
Simulation time 6140546963 ps
CPU time 94.36 seconds
Started Sep 24 07:24:23 PM UTC 24
Finished Sep 24 07:26:00 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474631278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3474631278
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_smoke.662510493
Short name T233
Test name
Test status
Simulation time 365225467 ps
CPU time 24.52 seconds
Started Sep 24 07:24:09 PM UTC 24
Finished Sep 24 07:24:35 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662510493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.662510493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_stress_all.416810051
Short name T256
Test name
Test status
Simulation time 6577842819 ps
CPU time 109.42 seconds
Started Sep 24 07:25:22 PM UTC 24
Finished Sep 24 07:27:13 PM UTC 24
Peak memory 226896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416810051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.416810051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1953383352
Short name T240
Test name
Test status
Simulation time 5051430334 ps
CPU time 38.57 seconds
Started Sep 24 07:25:10 PM UTC 24
Finished Sep 24 07:25:50 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953383352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1953383352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_alert_test.651915295
Short name T24
Test name
Test status
Simulation time 38495928 ps
CPU time 0.94 seconds
Started Sep 24 07:13:42 PM UTC 24
Finished Sep 24 07:13:44 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651915295 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.651915295
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.2952653161
Short name T19
Test name
Test status
Simulation time 8362640244 ps
CPU time 108.14 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:15:25 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952653161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2952653161
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.3483833106
Short name T157
Test name
Test status
Simulation time 5978062361 ps
CPU time 294.65 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:18:40 PM UTC 24
Peak memory 716080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483833106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3483833106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_error.3937784505
Short name T57
Test name
Test status
Simulation time 26577537224 ps
CPU time 135.49 seconds
Started Sep 24 07:13:34 PM UTC 24
Finished Sep 24 07:15:53 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937784505 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3937784505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_long_msg.3884044251
Short name T53
Test name
Test status
Simulation time 3907713677 ps
CPU time 59.19 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:14:42 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884044251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3884044251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.879249050
Short name T18
Test name
Test status
Simulation time 111587446 ps
CPU time 0.85 seconds
Started Sep 24 07:13:39 PM UTC 24
Finished Sep 24 07:13:42 PM UTC 24
Peak memory 238208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879249050 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.879249050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_smoke.1351973643
Short name T4
Test name
Test status
Simulation time 314157231 ps
CPU time 8.74 seconds
Started Sep 24 07:13:33 PM UTC 24
Finished Sep 24 07:13:50 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351973643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1351973643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.152466318
Short name T17
Test name
Test status
Simulation time 16148813991 ps
CPU time 96.69 seconds
Started Sep 24 07:13:38 PM UTC 24
Finished Sep 24 07:15:20 PM UTC 24
Peak memory 348964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15246631
8 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.152466318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.3651524403
Short name T55
Test name
Test status
Simulation time 4437762676 ps
CPU time 81.05 seconds
Started Sep 24 07:13:35 PM UTC 24
Finished Sep 24 07:14:58 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651524403 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3651524403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.3085266205
Short name T60
Test name
Test status
Simulation time 25257789030 ps
CPU time 84.2 seconds
Started Sep 24 07:13:37 PM UTC 24
Finished Sep 24 07:15:06 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085266205 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3085266205
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.2288037210
Short name T176
Test name
Test status
Simulation time 15631290510 ps
CPU time 139.21 seconds
Started Sep 24 07:13:37 PM UTC 24
Finished Sep 24 07:16:02 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288037210 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2288037210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.935295994
Short name T156
Test name
Test status
Simulation time 55619433101 ps
CPU time 823.82 seconds
Started Sep 24 07:13:34 PM UTC 24
Finished Sep 24 07:27:29 PM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935295994 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.935295994
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.1522584054
Short name T516
Test name
Test status
Simulation time 836232269617 ps
CPU time 3469.7 seconds
Started Sep 24 07:13:34 PM UTC 24
Finished Sep 24 08:12:10 PM UTC 24
Peak memory 228756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522584054 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1522584054
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.629932455
Short name T504
Test name
Test status
Simulation time 551821850324 ps
CPU time 2988.05 seconds
Started Sep 24 07:13:35 PM UTC 24
Finished Sep 24 08:04:01 PM UTC 24
Peak memory 223088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629932455 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.629932455
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.1749988535
Short name T27
Test name
Test status
Simulation time 986197302 ps
CPU time 52.26 seconds
Started Sep 24 07:13:34 PM UTC 24
Finished Sep 24 07:14:29 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749988535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1749988535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_alert_test.3251242040
Short name T246
Test name
Test status
Simulation time 10814461 ps
CPU time 0.89 seconds
Started Sep 24 07:26:19 PM UTC 24
Finished Sep 24 07:26:21 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251242040 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3251242040
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.1621748879
Short name T245
Test name
Test status
Simulation time 1293637481 ps
CPU time 40.2 seconds
Started Sep 24 07:25:36 PM UTC 24
Finished Sep 24 07:26:18 PM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621748879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1621748879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.1446950212
Short name T242
Test name
Test status
Simulation time 532418523 ps
CPU time 14.37 seconds
Started Sep 24 07:25:51 PM UTC 24
Finished Sep 24 07:26:07 PM UTC 24
Peak memory 212488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446950212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1446950212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_error.361450442
Short name T272
Test name
Test status
Simulation time 2209169693 ps
CPU time 138.94 seconds
Started Sep 24 07:26:08 PM UTC 24
Finished Sep 24 07:28:30 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361450442 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.361450442
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_long_msg.3712916374
Short name T281
Test name
Test status
Simulation time 27010093088 ps
CPU time 226.17 seconds
Started Sep 24 07:25:32 PM UTC 24
Finished Sep 24 07:29:22 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712916374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3712916374
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_smoke.1439736417
Short name T239
Test name
Test status
Simulation time 2809905900 ps
CPU time 9.5 seconds
Started Sep 24 07:25:25 PM UTC 24
Finished Sep 24 07:25:36 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439736417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1439736417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_stress_all.1096648979
Short name T295
Test name
Test status
Simulation time 4355897439 ps
CPU time 279.82 seconds
Started Sep 24 07:26:16 PM UTC 24
Finished Sep 24 07:31:00 PM UTC 24
Peak memory 484660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096648979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1096648979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.3375180725
Short name T269
Test name
Test status
Simulation time 6185092995 ps
CPU time 118.91 seconds
Started Sep 24 07:26:11 PM UTC 24
Finished Sep 24 07:28:13 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375180725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3375180725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_alert_test.3425980354
Short name T254
Test name
Test status
Simulation time 60694400 ps
CPU time 0.87 seconds
Started Sep 24 07:26:55 PM UTC 24
Finished Sep 24 07:26:57 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425980354 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3425980354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.487285608
Short name T257
Test name
Test status
Simulation time 1045615041 ps
CPU time 64.06 seconds
Started Sep 24 07:26:23 PM UTC 24
Finished Sep 24 07:27:29 PM UTC 24
Peak memory 210452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487285608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.487285608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.4189832363
Short name T263
Test name
Test status
Simulation time 5980216740 ps
CPU time 64.17 seconds
Started Sep 24 07:26:38 PM UTC 24
Finished Sep 24 07:27:44 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189832363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4189832363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.3388724663
Short name T428
Test name
Test status
Simulation time 9950856065 ps
CPU time 1135.81 seconds
Started Sep 24 07:26:35 PM UTC 24
Finished Sep 24 07:45:44 PM UTC 24
Peak memory 779568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388724663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3388724663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_error.2351965545
Short name T276
Test name
Test status
Simulation time 8259029689 ps
CPU time 121.3 seconds
Started Sep 24 07:26:41 PM UTC 24
Finished Sep 24 07:28:45 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351965545 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2351965545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_long_msg.268927645
Short name T250
Test name
Test status
Simulation time 570908246 ps
CPU time 11.89 seconds
Started Sep 24 07:26:23 PM UTC 24
Finished Sep 24 07:26:36 PM UTC 24
Peak memory 210416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268927645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.268927645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_smoke.1944080217
Short name T249
Test name
Test status
Simulation time 2015248735 ps
CPU time 10.25 seconds
Started Sep 24 07:26:23 PM UTC 24
Finished Sep 24 07:26:35 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944080217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1944080217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.342830965
Short name T103
Test name
Test status
Simulation time 1153872653 ps
CPU time 32.37 seconds
Started Sep 24 07:26:41 PM UTC 24
Finished Sep 24 07:27:15 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342830965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.342830965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_alert_test.73245066
Short name T260
Test name
Test status
Simulation time 18192301 ps
CPU time 0.89 seconds
Started Sep 24 07:27:35 PM UTC 24
Finished Sep 24 07:27:37 PM UTC 24
Peak memory 207396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73245066 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.73245066
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.2744282166
Short name T258
Test name
Test status
Simulation time 3131097926 ps
CPU time 22.02 seconds
Started Sep 24 07:27:06 PM UTC 24
Finished Sep 24 07:27:29 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744282166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2744282166
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.2519247667
Short name T266
Test name
Test status
Simulation time 669419912 ps
CPU time 49.71 seconds
Started Sep 24 07:27:14 PM UTC 24
Finished Sep 24 07:28:06 PM UTC 24
Peak memory 220876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519247667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2519247667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.4130011978
Short name T489
Test name
Test status
Simulation time 44314956627 ps
CPU time 1637.79 seconds
Started Sep 24 07:27:13 PM UTC 24
Finished Sep 24 07:54:50 PM UTC 24
Peak memory 808540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130011978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.4130011978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_error.4232352986
Short name T320
Test name
Test status
Simulation time 16548240921 ps
CPU time 338.48 seconds
Started Sep 24 07:27:14 PM UTC 24
Finished Sep 24 07:32:58 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232352986 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4232352986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_long_msg.4281136630
Short name T271
Test name
Test status
Simulation time 4685472975 ps
CPU time 77.48 seconds
Started Sep 24 07:27:06 PM UTC 24
Finished Sep 24 07:28:25 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281136630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4281136630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_smoke.1129846751
Short name T251
Test name
Test status
Simulation time 600582164 ps
CPU time 5.41 seconds
Started Sep 24 07:26:58 PM UTC 24
Finished Sep 24 07:27:04 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129846751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1129846751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_stress_all.1028748813
Short name T336
Test name
Test status
Simulation time 46013702465 ps
CPU time 410.72 seconds
Started Sep 24 07:27:35 PM UTC 24
Finished Sep 24 07:34:31 PM UTC 24
Peak memory 226868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028748813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1028748813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.1015666431
Short name T261
Test name
Test status
Simulation time 366770863 ps
CPU time 25.68 seconds
Started Sep 24 07:27:16 PM UTC 24
Finished Sep 24 07:27:43 PM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015666431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1015666431
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_alert_test.2676335044
Short name T267
Test name
Test status
Simulation time 12806411 ps
CPU time 0.9 seconds
Started Sep 24 07:28:06 PM UTC 24
Finished Sep 24 07:28:08 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676335044 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2676335044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.2933976870
Short name T287
Test name
Test status
Simulation time 12440949172 ps
CPU time 126.26 seconds
Started Sep 24 07:27:38 PM UTC 24
Finished Sep 24 07:29:47 PM UTC 24
Peak memory 219060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933976870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2933976870
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.3457554308
Short name T265
Test name
Test status
Simulation time 541023560 ps
CPU time 13.88 seconds
Started Sep 24 07:27:44 PM UTC 24
Finished Sep 24 07:27:59 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457554308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3457554308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.1437657535
Short name T427
Test name
Test status
Simulation time 4912988707 ps
CPU time 1062.46 seconds
Started Sep 24 07:27:44 PM UTC 24
Finished Sep 24 07:45:39 PM UTC 24
Peak memory 703736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437657535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1437657535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_error.3078688525
Short name T283
Test name
Test status
Simulation time 19091096061 ps
CPU time 106.04 seconds
Started Sep 24 07:27:45 PM UTC 24
Finished Sep 24 07:29:34 PM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078688525 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3078688525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_long_msg.2850543896
Short name T262
Test name
Test status
Simulation time 478189389 ps
CPU time 6.99 seconds
Started Sep 24 07:27:35 PM UTC 24
Finished Sep 24 07:27:43 PM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850543896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2850543896
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_smoke.277733617
Short name T264
Test name
Test status
Simulation time 3097994835 ps
CPU time 19.47 seconds
Started Sep 24 07:27:35 PM UTC 24
Finished Sep 24 07:27:55 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277733617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.277733617
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_stress_all.1440732710
Short name T75
Test name
Test status
Simulation time 337489686 ps
CPU time 7.31 seconds
Started Sep 24 07:28:00 PM UTC 24
Finished Sep 24 07:28:09 PM UTC 24
Peak memory 210176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440732710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1440732710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.2558672058
Short name T292
Test name
Test status
Simulation time 4860979768 ps
CPU time 134.98 seconds
Started Sep 24 07:27:56 PM UTC 24
Finished Sep 24 07:30:14 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558672058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2558672058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_alert_test.4117786978
Short name T274
Test name
Test status
Simulation time 68895234 ps
CPU time 0.93 seconds
Started Sep 24 07:28:34 PM UTC 24
Finished Sep 24 07:28:36 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117786978 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4117786978
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.1576247971
Short name T21
Test name
Test status
Simulation time 1054924288 ps
CPU time 19.35 seconds
Started Sep 24 07:28:14 PM UTC 24
Finished Sep 24 07:28:35 PM UTC 24
Peak memory 210336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576247971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1576247971
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.1338311262
Short name T279
Test name
Test status
Simulation time 1845990040 ps
CPU time 52.62 seconds
Started Sep 24 07:28:22 PM UTC 24
Finished Sep 24 07:29:16 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338311262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1338311262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.2136167508
Short name T393
Test name
Test status
Simulation time 16687441253 ps
CPU time 808.51 seconds
Started Sep 24 07:28:16 PM UTC 24
Finished Sep 24 07:41:54 PM UTC 24
Peak memory 695640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136167508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2136167508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_error.4105565563
Short name T305
Test name
Test status
Simulation time 3095310249 ps
CPU time 195.88 seconds
Started Sep 24 07:28:23 PM UTC 24
Finished Sep 24 07:31:42 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105565563 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4105565563
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_long_msg.1197177813
Short name T270
Test name
Test status
Simulation time 2225019263 ps
CPU time 8.76 seconds
Started Sep 24 07:28:10 PM UTC 24
Finished Sep 24 07:28:20 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197177813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1197177813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_smoke.2976920120
Short name T273
Test name
Test status
Simulation time 1240443577 ps
CPU time 22.92 seconds
Started Sep 24 07:28:10 PM UTC 24
Finished Sep 24 07:28:34 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976920120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2976920120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_stress_all.2054809274
Short name T289
Test name
Test status
Simulation time 1176544013 ps
CPU time 80.21 seconds
Started Sep 24 07:28:32 PM UTC 24
Finished Sep 24 07:29:55 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054809274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2054809274
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.3027864583
Short name T285
Test name
Test status
Simulation time 7430270416 ps
CPU time 68.23 seconds
Started Sep 24 07:28:26 PM UTC 24
Finished Sep 24 07:29:37 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027864583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3027864583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_alert_test.2780385596
Short name T282
Test name
Test status
Simulation time 12872282 ps
CPU time 0.92 seconds
Started Sep 24 07:29:24 PM UTC 24
Finished Sep 24 07:29:26 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780385596 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2780385596
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.709340993
Short name T288
Test name
Test status
Simulation time 1424722242 ps
CPU time 64.83 seconds
Started Sep 24 07:28:45 PM UTC 24
Finished Sep 24 07:29:52 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709340993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.709340993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.3949841498
Short name T284
Test name
Test status
Simulation time 8117501038 ps
CPU time 41.69 seconds
Started Sep 24 07:28:53 PM UTC 24
Finished Sep 24 07:29:36 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949841498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3949841498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2674284134
Short name T374
Test name
Test status
Simulation time 3091907905 ps
CPU time 599.3 seconds
Started Sep 24 07:28:47 PM UTC 24
Finished Sep 24 07:38:54 PM UTC 24
Peak memory 693764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674284134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2674284134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_error.2786951277
Short name T280
Test name
Test status
Simulation time 5505144439 ps
CPU time 23.66 seconds
Started Sep 24 07:28:56 PM UTC 24
Finished Sep 24 07:29:21 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786951277 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2786951277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_long_msg.827748235
Short name T294
Test name
Test status
Simulation time 6709405184 ps
CPU time 106.05 seconds
Started Sep 24 07:28:38 PM UTC 24
Finished Sep 24 07:30:26 PM UTC 24
Peak memory 210564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827748235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.827748235
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_smoke.3405591249
Short name T278
Test name
Test status
Simulation time 1486506835 ps
CPU time 18.29 seconds
Started Sep 24 07:28:36 PM UTC 24
Finished Sep 24 07:28:55 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405591249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3405591249
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_stress_all.2207319240
Short name T524
Test name
Test status
Simulation time 104532167140 ps
CPU time 6067.94 seconds
Started Sep 24 07:29:17 PM UTC 24
Finished Sep 24 09:11:31 PM UTC 24
Peak memory 896232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207319240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2207319240
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.1869678240
Short name T291
Test name
Test status
Simulation time 24659722005 ps
CPU time 57.19 seconds
Started Sep 24 07:29:13 PM UTC 24
Finished Sep 24 07:30:12 PM UTC 24
Peak memory 210492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869678240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1869678240
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_alert_test.885709612
Short name T290
Test name
Test status
Simulation time 41330153 ps
CPU time 0.88 seconds
Started Sep 24 07:29:56 PM UTC 24
Finished Sep 24 07:29:58 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885709612 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.885709612
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.2714921385
Short name T297
Test name
Test status
Simulation time 4990102859 ps
CPU time 89.65 seconds
Started Sep 24 07:29:35 PM UTC 24
Finished Sep 24 07:31:07 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714921385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2714921385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.2374719159
Short name T165
Test name
Test status
Simulation time 2850966353 ps
CPU time 81.69 seconds
Started Sep 24 07:29:38 PM UTC 24
Finished Sep 24 07:31:02 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374719159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2374719159
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.3355182586
Short name T353
Test name
Test status
Simulation time 9046973191 ps
CPU time 426.53 seconds
Started Sep 24 07:29:38 PM UTC 24
Finished Sep 24 07:36:51 PM UTC 24
Peak memory 480860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355182586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3355182586
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_error.1447573409
Short name T333
Test name
Test status
Simulation time 12282227295 ps
CPU time 273.01 seconds
Started Sep 24 07:29:38 PM UTC 24
Finished Sep 24 07:34:15 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447573409 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1447573409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_long_msg.364619943
Short name T313
Test name
Test status
Simulation time 8180022240 ps
CPU time 178.66 seconds
Started Sep 24 07:29:27 PM UTC 24
Finished Sep 24 07:32:29 PM UTC 24
Peak memory 218972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364619943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.364619943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_smoke.1338323335
Short name T286
Test name
Test status
Simulation time 875195837 ps
CPU time 12.09 seconds
Started Sep 24 07:29:24 PM UTC 24
Finished Sep 24 07:29:37 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338323335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1338323335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_stress_all.4009683366
Short name T81
Test name
Test status
Simulation time 73900596598 ps
CPU time 1403.03 seconds
Started Sep 24 07:29:53 PM UTC 24
Finished Sep 24 07:53:33 PM UTC 24
Peak memory 730424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009683366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4009683366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.2857905833
Short name T302
Test name
Test status
Simulation time 7562413498 ps
CPU time 99.68 seconds
Started Sep 24 07:29:49 PM UTC 24
Finished Sep 24 07:31:31 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857905833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2857905833
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_alert_test.3355297874
Short name T298
Test name
Test status
Simulation time 11987141 ps
CPU time 0.86 seconds
Started Sep 24 07:31:07 PM UTC 24
Finished Sep 24 07:31:09 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355297874 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3355297874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.1355673904
Short name T307
Test name
Test status
Simulation time 4843281410 ps
CPU time 88.63 seconds
Started Sep 24 07:30:16 PM UTC 24
Finished Sep 24 07:31:47 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355673904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1355673904
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.574384795
Short name T296
Test name
Test status
Simulation time 549009063 ps
CPU time 36.76 seconds
Started Sep 24 07:30:28 PM UTC 24
Finished Sep 24 07:31:06 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574384795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.574384795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.253629686
Short name T381
Test name
Test status
Simulation time 7252469360 ps
CPU time 564.93 seconds
Started Sep 24 07:30:22 PM UTC 24
Finished Sep 24 07:39:54 PM UTC 24
Peak memory 714068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253629686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.253629686
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_error.2661530733
Short name T310
Test name
Test status
Simulation time 45723852579 ps
CPU time 83.33 seconds
Started Sep 24 07:30:54 PM UTC 24
Finished Sep 24 07:32:20 PM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661530733 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2661530733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_long_msg.934559649
Short name T327
Test name
Test status
Simulation time 24337273607 ps
CPU time 194.96 seconds
Started Sep 24 07:30:13 PM UTC 24
Finished Sep 24 07:33:32 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934559649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.934559649
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_smoke.178823890
Short name T293
Test name
Test status
Simulation time 1199617235 ps
CPU time 20.9 seconds
Started Sep 24 07:29:59 PM UTC 24
Finished Sep 24 07:30:21 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178823890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.178823890
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_stress_all.3302794015
Short name T477
Test name
Test status
Simulation time 41469356490 ps
CPU time 1166.85 seconds
Started Sep 24 07:31:02 PM UTC 24
Finished Sep 24 07:50:44 PM UTC 24
Peak memory 718440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302794015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3302794015
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.1725650910
Short name T299
Test name
Test status
Simulation time 550700342 ps
CPU time 7.03 seconds
Started Sep 24 07:31:02 PM UTC 24
Finished Sep 24 07:31:10 PM UTC 24
Peak memory 210300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725650910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1725650910
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_alert_test.1221452916
Short name T306
Test name
Test status
Simulation time 14713657 ps
CPU time 0.87 seconds
Started Sep 24 07:31:44 PM UTC 24
Finished Sep 24 07:31:46 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221452916 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1221452916
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.1883675689
Short name T303
Test name
Test status
Simulation time 1210035836 ps
CPU time 20.29 seconds
Started Sep 24 07:31:11 PM UTC 24
Finished Sep 24 07:31:33 PM UTC 24
Peak memory 210380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883675689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1883675689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.259506610
Short name T304
Test name
Test status
Simulation time 831501678 ps
CPU time 10.98 seconds
Started Sep 24 07:31:29 PM UTC 24
Finished Sep 24 07:31:42 PM UTC 24
Peak memory 210304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259506610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.259506610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.4236759376
Short name T492
Test name
Test status
Simulation time 26785589592 ps
CPU time 1501.91 seconds
Started Sep 24 07:31:22 PM UTC 24
Finished Sep 24 07:56:40 PM UTC 24
Peak memory 797956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236759376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4236759376
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_error.1916708687
Short name T317
Test name
Test status
Simulation time 10968669974 ps
CPU time 75.33 seconds
Started Sep 24 07:31:29 PM UTC 24
Finished Sep 24 07:32:47 PM UTC 24
Peak memory 210788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916708687 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1916708687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_long_msg.2241034085
Short name T330
Test name
Test status
Simulation time 6264563680 ps
CPU time 148.97 seconds
Started Sep 24 07:31:10 PM UTC 24
Finished Sep 24 07:33:42 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241034085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2241034085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_smoke.283570709
Short name T300
Test name
Test status
Simulation time 484251163 ps
CPU time 10.66 seconds
Started Sep 24 07:31:09 PM UTC 24
Finished Sep 24 07:31:21 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283570709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.283570709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_stress_all.3943877343
Short name T502
Test name
Test status
Simulation time 64707650527 ps
CPU time 1871.73 seconds
Started Sep 24 07:31:34 PM UTC 24
Finished Sep 24 08:03:09 PM UTC 24
Peak memory 730340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943877343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3943877343
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.442064341
Short name T311
Test name
Test status
Simulation time 2307207182 ps
CPU time 47.61 seconds
Started Sep 24 07:31:32 PM UTC 24
Finished Sep 24 07:32:21 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442064341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.442064341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_alert_test.1753693183
Short name T314
Test name
Test status
Simulation time 45287193 ps
CPU time 0.72 seconds
Started Sep 24 07:32:30 PM UTC 24
Finished Sep 24 07:32:32 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753693183 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1753693183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.2698277184
Short name T316
Test name
Test status
Simulation time 690286687 ps
CPU time 47.61 seconds
Started Sep 24 07:31:48 PM UTC 24
Finished Sep 24 07:32:37 PM UTC 24
Peak memory 210580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698277184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2698277184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.869904479
Short name T315
Test name
Test status
Simulation time 2122932720 ps
CPU time 12.27 seconds
Started Sep 24 07:32:20 PM UTC 24
Finished Sep 24 07:32:34 PM UTC 24
Peak memory 210344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869904479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.869904479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.780966433
Short name T356
Test name
Test status
Simulation time 7572688168 ps
CPU time 297.07 seconds
Started Sep 24 07:31:56 PM UTC 24
Finished Sep 24 07:36:57 PM UTC 24
Peak memory 677244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780966433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.780966433
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_error.2593648279
Short name T365
Test name
Test status
Simulation time 21211419911 ps
CPU time 330.78 seconds
Started Sep 24 07:32:22 PM UTC 24
Finished Sep 24 07:37:58 PM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593648279 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2593648279
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_long_msg.985190896
Short name T309
Test name
Test status
Simulation time 16019312669 ps
CPU time 30.27 seconds
Started Sep 24 07:31:48 PM UTC 24
Finished Sep 24 07:32:19 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985190896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.985190896
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_smoke.125699275
Short name T308
Test name
Test status
Simulation time 1881991135 ps
CPU time 9.94 seconds
Started Sep 24 07:31:44 PM UTC 24
Finished Sep 24 07:31:55 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125699275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.125699275
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_stress_all.1010415372
Short name T521
Test name
Test status
Simulation time 417866323845 ps
CPU time 3312.67 seconds
Started Sep 24 07:32:25 PM UTC 24
Finished Sep 24 08:28:16 PM UTC 24
Peak memory 701712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010415372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1010415372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.4159442094
Short name T321
Test name
Test status
Simulation time 4471170336 ps
CPU time 38.78 seconds
Started Sep 24 07:32:22 PM UTC 24
Finished Sep 24 07:33:02 PM UTC 24
Peak memory 210432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159442094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4159442094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_alert_test.3633392560
Short name T170
Test name
Test status
Simulation time 34654484 ps
CPU time 0.94 seconds
Started Sep 24 07:14:32 PM UTC 24
Finished Sep 24 07:14:34 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633392560 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3633392560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.4006050897
Short name T26
Test name
Test status
Simulation time 600048192 ps
CPU time 19.69 seconds
Started Sep 24 07:13:44 PM UTC 24
Finished Sep 24 07:14:07 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006050897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4006050897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.2857349787
Short name T10
Test name
Test status
Simulation time 1493446310 ps
CPU time 28.35 seconds
Started Sep 24 07:13:51 PM UTC 24
Finished Sep 24 07:14:21 PM UTC 24
Peak memory 210548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857349787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2857349787
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.2512161333
Short name T229
Test name
Test status
Simulation time 28229229043 ps
CPU time 603.11 seconds
Started Sep 24 07:13:45 PM UTC 24
Finished Sep 24 07:23:56 PM UTC 24
Peak memory 728308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512161333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2512161333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_error.2028197810
Short name T191
Test name
Test status
Simulation time 6999614352 ps
CPU time 231 seconds
Started Sep 24 07:13:53 PM UTC 24
Finished Sep 24 07:17:48 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028197810 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2028197810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_long_msg.2919747866
Short name T136
Test name
Test status
Simulation time 2471491413 ps
CPU time 43.94 seconds
Started Sep 24 07:13:43 PM UTC 24
Finished Sep 24 07:14:32 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919747866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2919747866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.2813402342
Short name T61
Test name
Test status
Simulation time 38545823 ps
CPU time 1.39 seconds
Started Sep 24 07:14:30 PM UTC 24
Finished Sep 24 07:14:33 PM UTC 24
Peak memory 238204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813402342 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2813402342
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_stress_all.1196018945
Short name T482
Test name
Test status
Simulation time 19146750092 ps
CPU time 2221.85 seconds
Started Sep 24 07:14:25 PM UTC 24
Finished Sep 24 07:51:50 PM UTC 24
Peak memory 787764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196018945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1196018945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3740702962
Short name T171
Test name
Test status
Simulation time 3160573443 ps
CPU time 61.58 seconds
Started Sep 24 07:14:08 PM UTC 24
Finished Sep 24 07:15:11 PM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740702962 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3740702962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.4026054337
Short name T178
Test name
Test status
Simulation time 9036054485 ps
CPU time 108.42 seconds
Started Sep 24 07:14:22 PM UTC 24
Finished Sep 24 07:16:13 PM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026054337 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.4026054337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.4115338463
Short name T175
Test name
Test status
Simulation time 2109087201 ps
CPU time 91.47 seconds
Started Sep 24 07:14:25 PM UTC 24
Finished Sep 24 07:15:59 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115338463 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.4115338463
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.2375799009
Short name T268
Test name
Test status
Simulation time 678618843949 ps
CPU time 838.17 seconds
Started Sep 24 07:14:01 PM UTC 24
Finished Sep 24 07:28:11 PM UTC 24
Peak memory 210460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375799009 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2375799009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.460090658
Short name T508
Test name
Test status
Simulation time 210745909064 ps
CPU time 3004.2 seconds
Started Sep 24 07:14:03 PM UTC 24
Finished Sep 24 08:04:44 PM UTC 24
Peak memory 227112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460090658 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.460090658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.1757924168
Short name T509
Test name
Test status
Simulation time 85878484780 ps
CPU time 3033.82 seconds
Started Sep 24 07:14:03 PM UTC 24
Finished Sep 24 08:05:15 PM UTC 24
Peak memory 218980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757924168 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1757924168
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.504845213
Short name T36
Test name
Test status
Simulation time 3177295563 ps
CPU time 91.65 seconds
Started Sep 24 07:14:00 PM UTC 24
Finished Sep 24 07:15:34 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504845213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.504845213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_alert_test.1174042125
Short name T322
Test name
Test status
Simulation time 13927339 ps
CPU time 0.87 seconds
Started Sep 24 07:33:00 PM UTC 24
Finished Sep 24 07:33:02 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174042125 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1174042125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.1040578325
Short name T326
Test name
Test status
Simulation time 833394575 ps
CPU time 49.46 seconds
Started Sep 24 07:32:38 PM UTC 24
Finished Sep 24 07:33:29 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040578325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1040578325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.737278268
Short name T325
Test name
Test status
Simulation time 2693488816 ps
CPU time 31.21 seconds
Started Sep 24 07:32:49 PM UTC 24
Finished Sep 24 07:33:22 PM UTC 24
Peak memory 210156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737278268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.737278268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.450128573
Short name T479
Test name
Test status
Simulation time 8681169139 ps
CPU time 1081.32 seconds
Started Sep 24 07:32:48 PM UTC 24
Finished Sep 24 07:51:03 PM UTC 24
Peak memory 689404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450128573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.450128573
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_error.1493173298
Short name T319
Test name
Test status
Simulation time 218771029 ps
CPU time 1.96 seconds
Started Sep 24 07:32:49 PM UTC 24
Finished Sep 24 07:32:52 PM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493173298 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1493173298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_long_msg.4290778183
Short name T351
Test name
Test status
Simulation time 42935635799 ps
CPU time 230.63 seconds
Started Sep 24 07:32:35 PM UTC 24
Finished Sep 24 07:36:30 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290778183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.4290778183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_smoke.2749184935
Short name T318
Test name
Test status
Simulation time 818556563 ps
CPU time 13.39 seconds
Started Sep 24 07:32:33 PM UTC 24
Finished Sep 24 07:32:48 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749184935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2749184935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_stress_all.1054403309
Short name T496
Test name
Test status
Simulation time 34401369111 ps
CPU time 1582.69 seconds
Started Sep 24 07:32:57 PM UTC 24
Finished Sep 24 07:59:39 PM UTC 24
Peak memory 765180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054403309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1054403309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.754822979
Short name T335
Test name
Test status
Simulation time 5406067005 ps
CPU time 83.14 seconds
Started Sep 24 07:32:56 PM UTC 24
Finished Sep 24 07:34:21 PM UTC 24
Peak memory 210568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754822979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.754822979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_alert_test.1055894340
Short name T329
Test name
Test status
Simulation time 36804994 ps
CPU time 0.83 seconds
Started Sep 24 07:33:39 PM UTC 24
Finished Sep 24 07:33:41 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055894340 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1055894340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.1634970756
Short name T328
Test name
Test status
Simulation time 290219484 ps
CPU time 15.71 seconds
Started Sep 24 07:33:21 PM UTC 24
Finished Sep 24 07:33:38 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634970756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1634970756
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.1229240263
Short name T449
Test name
Test status
Simulation time 18661739848 ps
CPU time 834.15 seconds
Started Sep 24 07:33:20 PM UTC 24
Finished Sep 24 07:47:23 PM UTC 24
Peak memory 724196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229240263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1229240263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_error.142673446
Short name T337
Test name
Test status
Simulation time 1186900748 ps
CPU time 74.94 seconds
Started Sep 24 07:33:23 PM UTC 24
Finished Sep 24 07:34:39 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142673446 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.142673446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_long_msg.3591541030
Short name T331
Test name
Test status
Simulation time 2107840903 ps
CPU time 48.92 seconds
Started Sep 24 07:33:03 PM UTC 24
Finished Sep 24 07:33:53 PM UTC 24
Peak memory 210216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591541030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3591541030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_smoke.3136171507
Short name T323
Test name
Test status
Simulation time 408541978 ps
CPU time 9.24 seconds
Started Sep 24 07:33:03 PM UTC 24
Finished Sep 24 07:33:13 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136171507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3136171507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_stress_all.3132774152
Short name T487
Test name
Test status
Simulation time 29739400906 ps
CPU time 1234.93 seconds
Started Sep 24 07:33:33 PM UTC 24
Finished Sep 24 07:54:23 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132774152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3132774152
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.1097066268
Short name T48
Test name
Test status
Simulation time 22119549354 ps
CPU time 114.35 seconds
Started Sep 24 07:33:31 PM UTC 24
Finished Sep 24 07:35:28 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097066268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1097066268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_alert_test.1151512436
Short name T338
Test name
Test status
Simulation time 22322558 ps
CPU time 0.84 seconds
Started Sep 24 07:34:40 PM UTC 24
Finished Sep 24 07:34:42 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151512436 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1151512436
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.3965232734
Short name T30
Test name
Test status
Simulation time 1417668760 ps
CPU time 89.6 seconds
Started Sep 24 07:33:55 PM UTC 24
Finished Sep 24 07:35:26 PM UTC 24
Peak memory 220996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965232734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3965232734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.3254067085
Short name T44
Test name
Test status
Simulation time 919497108 ps
CPU time 57.56 seconds
Started Sep 24 07:34:17 PM UTC 24
Finished Sep 24 07:35:16 PM UTC 24
Peak memory 218896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254067085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3254067085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.4167698182
Short name T426
Test name
Test status
Simulation time 7198196988 ps
CPU time 689.56 seconds
Started Sep 24 07:33:56 PM UTC 24
Finished Sep 24 07:45:33 PM UTC 24
Peak memory 748840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167698182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4167698182
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_error.289658126
Short name T360
Test name
Test status
Simulation time 2528229287 ps
CPU time 167.18 seconds
Started Sep 24 07:34:23 PM UTC 24
Finished Sep 24 07:37:14 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289658126 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.289658126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_long_msg.4114186751
Short name T339
Test name
Test status
Simulation time 6137362327 ps
CPU time 59.25 seconds
Started Sep 24 07:33:44 PM UTC 24
Finished Sep 24 07:34:45 PM UTC 24
Peak memory 219032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114186751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.4114186751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_smoke.2097553075
Short name T332
Test name
Test status
Simulation time 305606328 ps
CPU time 10.83 seconds
Started Sep 24 07:33:42 PM UTC 24
Finished Sep 24 07:33:54 PM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097553075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2097553075
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_stress_all.2291096691
Short name T519
Test name
Test status
Simulation time 63735524049 ps
CPU time 2725.52 seconds
Started Sep 24 07:34:35 PM UTC 24
Finished Sep 24 08:20:31 PM UTC 24
Peak memory 785736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291096691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2291096691
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.3657537019
Short name T50
Test name
Test status
Simulation time 3196788468 ps
CPU time 79.67 seconds
Started Sep 24 07:34:23 PM UTC 24
Finished Sep 24 07:35:45 PM UTC 24
Peak memory 210592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657537019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3657537019
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_alert_test.822357701
Short name T45
Test name
Test status
Simulation time 30497118 ps
CPU time 0.95 seconds
Started Sep 24 07:35:17 PM UTC 24
Finished Sep 24 07:35:19 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822357701 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.822357701
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.1793500058
Short name T352
Test name
Test status
Simulation time 3026045152 ps
CPU time 108.57 seconds
Started Sep 24 07:34:46 PM UTC 24
Finished Sep 24 07:36:37 PM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793500058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1793500058
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.4034995068
Short name T349
Test name
Test status
Simulation time 986006645 ps
CPU time 76.48 seconds
Started Sep 24 07:34:57 PM UTC 24
Finished Sep 24 07:36:15 PM UTC 24
Peak memory 210352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034995068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4034995068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.1347865803
Short name T347
Test name
Test status
Simulation time 3180874890 ps
CPU time 71.98 seconds
Started Sep 24 07:34:55 PM UTC 24
Finished Sep 24 07:36:09 PM UTC 24
Peak memory 379280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347865803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1347865803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_error.2456267993
Short name T370
Test name
Test status
Simulation time 11923240148 ps
CPU time 206.55 seconds
Started Sep 24 07:34:59 PM UTC 24
Finished Sep 24 07:38:29 PM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456267993 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2456267993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_long_msg.2653224088
Short name T341
Test name
Test status
Simulation time 136313410 ps
CPU time 11.07 seconds
Started Sep 24 07:34:44 PM UTC 24
Finished Sep 24 07:34:56 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653224088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2653224088
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_smoke.2148598383
Short name T342
Test name
Test status
Simulation time 1258971849 ps
CPU time 13.08 seconds
Started Sep 24 07:34:44 PM UTC 24
Finished Sep 24 07:34:58 PM UTC 24
Peak memory 210584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148598383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2148598383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_stress_all.4243724999
Short name T505
Test name
Test status
Simulation time 138667977600 ps
CPU time 1717.06 seconds
Started Sep 24 07:35:09 PM UTC 24
Finished Sep 24 08:04:05 PM UTC 24
Peak memory 783720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243724999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4243724999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.2623522624
Short name T46
Test name
Test status
Simulation time 1793376734 ps
CPU time 12.63 seconds
Started Sep 24 07:35:08 PM UTC 24
Finished Sep 24 07:35:21 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623522624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2623522624
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_alert_test.1435666583
Short name T346
Test name
Test status
Simulation time 45695600 ps
CPU time 0.98 seconds
Started Sep 24 07:36:02 PM UTC 24
Finished Sep 24 07:36:04 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435666583 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1435666583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.208344655
Short name T345
Test name
Test status
Simulation time 906202055 ps
CPU time 38.55 seconds
Started Sep 24 07:35:24 PM UTC 24
Finished Sep 24 07:36:04 PM UTC 24
Peak memory 210644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208344655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.208344655
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.2078749399
Short name T49
Test name
Test status
Simulation time 232585061 ps
CPU time 4.64 seconds
Started Sep 24 07:35:29 PM UTC 24
Finished Sep 24 07:35:35 PM UTC 24
Peak memory 210296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078749399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2078749399
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.3077647234
Short name T491
Test name
Test status
Simulation time 33034665596 ps
CPU time 1179.9 seconds
Started Sep 24 07:35:28 PM UTC 24
Finished Sep 24 07:55:20 PM UTC 24
Peak memory 786004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077647234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3077647234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_error.1757850974
Short name T344
Test name
Test status
Simulation time 716853209 ps
CPU time 22.6 seconds
Started Sep 24 07:35:37 PM UTC 24
Finished Sep 24 07:36:00 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757850974 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1757850974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_long_msg.4200426517
Short name T51
Test name
Test status
Simulation time 1747067161 ps
CPU time 25.68 seconds
Started Sep 24 07:35:23 PM UTC 24
Finished Sep 24 07:35:50 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200426517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4200426517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_smoke.431406186
Short name T47
Test name
Test status
Simulation time 82446256 ps
CPU time 1.72 seconds
Started Sep 24 07:35:20 PM UTC 24
Finished Sep 24 07:35:23 PM UTC 24
Peak memory 209404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431406186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.431406186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_stress_all.2417352914
Short name T446
Test name
Test status
Simulation time 41941809690 ps
CPU time 675.8 seconds
Started Sep 24 07:35:50 PM UTC 24
Finished Sep 24 07:47:16 PM UTC 24
Peak memory 226884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417352914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2417352914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.3160760885
Short name T106
Test name
Test status
Simulation time 5138379606 ps
CPU time 165.44 seconds
Started Sep 24 07:35:46 PM UTC 24
Finished Sep 24 07:38:35 PM UTC 24
Peak memory 210516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160760885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3160760885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_alert_test.4277638276
Short name T355
Test name
Test status
Simulation time 70562787 ps
CPU time 0.83 seconds
Started Sep 24 07:36:53 PM UTC 24
Finished Sep 24 07:36:55 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277638276 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4277638276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.3258732013
Short name T369
Test name
Test status
Simulation time 1676423457 ps
CPU time 124.09 seconds
Started Sep 24 07:36:09 PM UTC 24
Finished Sep 24 07:38:16 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258732013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3258732013
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.3226446441
Short name T362
Test name
Test status
Simulation time 1005314568 ps
CPU time 72.18 seconds
Started Sep 24 07:36:18 PM UTC 24
Finished Sep 24 07:37:33 PM UTC 24
Peak memory 219156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226446441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3226446441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.2338520902
Short name T457
Test name
Test status
Simulation time 3558105530 ps
CPU time 689.56 seconds
Started Sep 24 07:36:17 PM UTC 24
Finished Sep 24 07:47:55 PM UTC 24
Peak memory 728312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338520902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2338520902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_error.3865065234
Short name T383
Test name
Test status
Simulation time 64039821177 ps
CPU time 230.73 seconds
Started Sep 24 07:36:21 PM UTC 24
Finished Sep 24 07:40:16 PM UTC 24
Peak memory 210488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865065234 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3865065234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_long_msg.1176830786
Short name T354
Test name
Test status
Simulation time 5485302003 ps
CPU time 45.69 seconds
Started Sep 24 07:36:05 PM UTC 24
Finished Sep 24 07:36:52 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176830786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1176830786
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_smoke.786957386
Short name T350
Test name
Test status
Simulation time 892935729 ps
CPU time 14.24 seconds
Started Sep 24 07:36:05 PM UTC 24
Finished Sep 24 07:36:20 PM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786957386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.786957386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_stress_all.3518352667
Short name T78
Test name
Test status
Simulation time 116549007745 ps
CPU time 769.41 seconds
Started Sep 24 07:36:39 PM UTC 24
Finished Sep 24 07:49:37 PM UTC 24
Peak memory 695556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518352667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3518352667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.4237642820
Short name T367
Test name
Test status
Simulation time 1653918871 ps
CPU time 93.3 seconds
Started Sep 24 07:36:32 PM UTC 24
Finished Sep 24 07:38:07 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237642820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4237642820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_alert_test.1855402188
Short name T363
Test name
Test status
Simulation time 23172732 ps
CPU time 0.93 seconds
Started Sep 24 07:37:33 PM UTC 24
Finished Sep 24 07:37:35 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855402188 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1855402188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.1590804365
Short name T358
Test name
Test status
Simulation time 150148776 ps
CPU time 12.45 seconds
Started Sep 24 07:36:59 PM UTC 24
Finished Sep 24 07:37:12 PM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590804365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1590804365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.4278898049
Short name T361
Test name
Test status
Simulation time 475164535 ps
CPU time 4.05 seconds
Started Sep 24 07:37:14 PM UTC 24
Finished Sep 24 07:37:19 PM UTC 24
Peak memory 209996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278898049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.4278898049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.305286888
Short name T481
Test name
Test status
Simulation time 15002853834 ps
CPU time 838.39 seconds
Started Sep 24 07:37:11 PM UTC 24
Finished Sep 24 07:51:20 PM UTC 24
Peak memory 494900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305286888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.305286888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_error.1655937493
Short name T398
Test name
Test status
Simulation time 18713908897 ps
CPU time 295.22 seconds
Started Sep 24 07:37:14 PM UTC 24
Finished Sep 24 07:42:14 PM UTC 24
Peak memory 210752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655937493 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1655937493
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_long_msg.1576625596
Short name T366
Test name
Test status
Simulation time 875918720 ps
CPU time 60.85 seconds
Started Sep 24 07:36:56 PM UTC 24
Finished Sep 24 07:37:59 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576625596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1576625596
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_smoke.2725625363
Short name T359
Test name
Test status
Simulation time 6018918596 ps
CPU time 18.84 seconds
Started Sep 24 07:36:53 PM UTC 24
Finished Sep 24 07:37:13 PM UTC 24
Peak memory 210504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725625363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2725625363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_stress_all.3458490259
Short name T513
Test name
Test status
Simulation time 453796489318 ps
CPU time 1954.43 seconds
Started Sep 24 07:37:20 PM UTC 24
Finished Sep 24 08:10:18 PM UTC 24
Peak memory 710204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458490259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3458490259
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.662896656
Short name T368
Test name
Test status
Simulation time 12256308275 ps
CPU time 50.81 seconds
Started Sep 24 07:37:16 PM UTC 24
Finished Sep 24 07:38:08 PM UTC 24
Peak memory 210772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662896656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.662896656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_alert_test.1355928928
Short name T371
Test name
Test status
Simulation time 13040531 ps
CPU time 0.92 seconds
Started Sep 24 07:38:31 PM UTC 24
Finished Sep 24 07:38:33 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355928928 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1355928928
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.3647894920
Short name T377
Test name
Test status
Simulation time 5472726705 ps
CPU time 88.68 seconds
Started Sep 24 07:37:41 PM UTC 24
Finished Sep 24 07:39:12 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647894920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3647894920
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2930476146
Short name T373
Test name
Test status
Simulation time 2146718844 ps
CPU time 44.9 seconds
Started Sep 24 07:38:00 PM UTC 24
Finished Sep 24 07:38:47 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930476146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2930476146
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.3520193125
Short name T515
Test name
Test status
Simulation time 33141664795 ps
CPU time 2024.89 seconds
Started Sep 24 07:38:00 PM UTC 24
Finished Sep 24 08:12:09 PM UTC 24
Peak memory 795900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520193125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3520193125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_error.1701047875
Short name T380
Test name
Test status
Simulation time 3475229730 ps
CPU time 72.57 seconds
Started Sep 24 07:38:09 PM UTC 24
Finished Sep 24 07:39:24 PM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701047875 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1701047875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_long_msg.2323566273
Short name T376
Test name
Test status
Simulation time 1413031331 ps
CPU time 86.6 seconds
Started Sep 24 07:37:36 PM UTC 24
Finished Sep 24 07:39:05 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323566273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2323566273
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_smoke.3284957955
Short name T364
Test name
Test status
Simulation time 2091966014 ps
CPU time 4.24 seconds
Started Sep 24 07:37:35 PM UTC 24
Finished Sep 24 07:37:41 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284957955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3284957955
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_stress_all.1639719109
Short name T520
Test name
Test status
Simulation time 320172710316 ps
CPU time 2785.78 seconds
Started Sep 24 07:38:18 PM UTC 24
Finished Sep 24 08:25:18 PM UTC 24
Peak memory 751020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639719109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1639719109
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2132016643
Short name T384
Test name
Test status
Simulation time 16450188647 ps
CPU time 132.11 seconds
Started Sep 24 07:38:09 PM UTC 24
Finished Sep 24 07:40:24 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132016643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2132016643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_alert_test.4204467553
Short name T378
Test name
Test status
Simulation time 12443017 ps
CPU time 0.9 seconds
Started Sep 24 07:39:14 PM UTC 24
Finished Sep 24 07:39:16 PM UTC 24
Peak memory 205360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204467553 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4204467553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.2622623799
Short name T31
Test name
Test status
Simulation time 1555463268 ps
CPU time 48.25 seconds
Started Sep 24 07:38:41 PM UTC 24
Finished Sep 24 07:39:31 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622623799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2622623799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.2530584331
Short name T375
Test name
Test status
Simulation time 402230916 ps
CPU time 9.36 seconds
Started Sep 24 07:38:52 PM UTC 24
Finished Sep 24 07:39:03 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530584331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2530584331
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.446968157
Short name T483
Test name
Test status
Simulation time 5023218270 ps
CPU time 784.5 seconds
Started Sep 24 07:38:51 PM UTC 24
Finished Sep 24 07:52:05 PM UTC 24
Peak memory 746856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446968157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.446968157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_error.3970815605
Short name T401
Test name
Test status
Simulation time 3601332561 ps
CPU time 207.17 seconds
Started Sep 24 07:38:55 PM UTC 24
Finished Sep 24 07:42:26 PM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970815605 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3970815605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_long_msg.3137248489
Short name T382
Test name
Test status
Simulation time 6320239813 ps
CPU time 95.96 seconds
Started Sep 24 07:38:36 PM UTC 24
Finished Sep 24 07:40:14 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137248489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3137248489
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_smoke.4013329722
Short name T372
Test name
Test status
Simulation time 273807307 ps
CPU time 5.41 seconds
Started Sep 24 07:38:34 PM UTC 24
Finished Sep 24 07:38:41 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013329722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.4013329722
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_stress_all.3249158792
Short name T82
Test name
Test status
Simulation time 87808801333 ps
CPU time 2937.5 seconds
Started Sep 24 07:39:06 PM UTC 24
Finished Sep 24 08:28:39 PM UTC 24
Peak memory 804128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249158792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3249158792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.2918746018
Short name T392
Test name
Test status
Simulation time 2561105064 ps
CPU time 145.75 seconds
Started Sep 24 07:39:04 PM UTC 24
Finished Sep 24 07:41:32 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918746018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2918746018
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_alert_test.1183502144
Short name T386
Test name
Test status
Simulation time 20369444 ps
CPU time 0.98 seconds
Started Sep 24 07:40:32 PM UTC 24
Finished Sep 24 07:40:34 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183502144 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1183502144
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.1694438337
Short name T385
Test name
Test status
Simulation time 1885848829 ps
CPU time 63.26 seconds
Started Sep 24 07:39:25 PM UTC 24
Finished Sep 24 07:40:30 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694438337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1694438337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.2407832007
Short name T390
Test name
Test status
Simulation time 6833226843 ps
CPU time 61.29 seconds
Started Sep 24 07:39:56 PM UTC 24
Finished Sep 24 07:40:59 PM UTC 24
Peak memory 210548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407832007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2407832007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.1021527236
Short name T499
Test name
Test status
Simulation time 6161970872 ps
CPU time 1329.34 seconds
Started Sep 24 07:39:33 PM UTC 24
Finished Sep 24 08:01:58 PM UTC 24
Peak memory 798040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021527236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1021527236
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_error.823026672
Short name T407
Test name
Test status
Simulation time 38373495965 ps
CPU time 159.54 seconds
Started Sep 24 07:40:15 PM UTC 24
Finished Sep 24 07:42:58 PM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823026672 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.823026672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_long_msg.686766773
Short name T388
Test name
Test status
Simulation time 1287376916 ps
CPU time 85.9 seconds
Started Sep 24 07:39:20 PM UTC 24
Finished Sep 24 07:40:48 PM UTC 24
Peak memory 210408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686766773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.686766773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_smoke.2371150830
Short name T379
Test name
Test status
Simulation time 34138937 ps
CPU time 1.61 seconds
Started Sep 24 07:39:17 PM UTC 24
Finished Sep 24 07:39:20 PM UTC 24
Peak memory 210544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371150830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2371150830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_stress_all.90512879
Short name T512
Test name
Test status
Simulation time 73188697620 ps
CPU time 1769.71 seconds
Started Sep 24 07:40:26 PM UTC 24
Finished Sep 24 08:10:17 PM UTC 24
Peak memory 511292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90512879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.90512879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.452766757
Short name T403
Test name
Test status
Simulation time 43363121521 ps
CPU time 137.05 seconds
Started Sep 24 07:40:17 PM UTC 24
Finished Sep 24 07:42:37 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452766757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.452766757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_alert_test.441928798
Short name T73
Test name
Test status
Simulation time 12520392 ps
CPU time 0.94 seconds
Started Sep 24 07:15:18 PM UTC 24
Finished Sep 24 07:15:20 PM UTC 24
Peak memory 205352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441928798 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.441928798
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.2228187028
Short name T14
Test name
Test status
Simulation time 4867757819 ps
CPU time 69.82 seconds
Started Sep 24 07:14:35 PM UTC 24
Finished Sep 24 07:15:47 PM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228187028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2228187028
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.2362394021
Short name T35
Test name
Test status
Simulation time 10294004093 ps
CPU time 52.01 seconds
Started Sep 24 07:14:39 PM UTC 24
Finished Sep 24 07:15:32 PM UTC 24
Peak memory 210436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362394021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2362394021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.2305245098
Short name T137
Test name
Test status
Simulation time 667638562 ps
CPU time 36.86 seconds
Started Sep 24 07:14:37 PM UTC 24
Finished Sep 24 07:15:16 PM UTC 24
Peak memory 242856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305245098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2305245098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_error.1406560215
Short name T148
Test name
Test status
Simulation time 35517405994 ps
CPU time 169.71 seconds
Started Sep 24 07:14:40 PM UTC 24
Finished Sep 24 07:17:32 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406560215 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1406560215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.49359610
Short name T62
Test name
Test status
Simulation time 332987691 ps
CPU time 1.41 seconds
Started Sep 24 07:15:17 PM UTC 24
Finished Sep 24 07:15:19 PM UTC 24
Peak memory 238208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49359610 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.49359610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_smoke.1464943391
Short name T150
Test name
Test status
Simulation time 5817777304 ps
CPU time 10.56 seconds
Started Sep 24 07:14:34 PM UTC 24
Finished Sep 24 07:14:45 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464943391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1464943391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_stress_all.1389206997
Short name T166
Test name
Test status
Simulation time 153055276367 ps
CPU time 924.75 seconds
Started Sep 24 07:15:12 PM UTC 24
Finished Sep 24 07:30:48 PM UTC 24
Peak memory 673088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389206997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1389206997
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.3313228363
Short name T174
Test name
Test status
Simulation time 1223882731 ps
CPU time 50.16 seconds
Started Sep 24 07:15:03 PM UTC 24
Finished Sep 24 07:15:55 PM UTC 24
Peak memory 210576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313228363 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.3313228363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.3785088879
Short name T177
Test name
Test status
Simulation time 1605809529 ps
CPU time 61.68 seconds
Started Sep 24 07:15:03 PM UTC 24
Finished Sep 24 07:16:07 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785088879 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3785088879
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.2575777020
Short name T182
Test name
Test status
Simulation time 19475762525 ps
CPU time 81.11 seconds
Started Sep 24 07:15:08 PM UTC 24
Finished Sep 24 07:16:31 PM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575777020 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2575777020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.2740152709
Short name T236
Test name
Test status
Simulation time 21988251880 ps
CPU time 626.5 seconds
Started Sep 24 07:14:43 PM UTC 24
Finished Sep 24 07:25:18 PM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740152709 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2740152709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.1577394726
Short name T506
Test name
Test status
Simulation time 924663297229 ps
CPU time 2957.17 seconds
Started Sep 24 07:14:46 PM UTC 24
Finished Sep 24 08:04:38 PM UTC 24
Peak memory 226808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577394726 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1577394726
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.2290170190
Short name T498
Test name
Test status
Simulation time 360407285553 ps
CPU time 2744.42 seconds
Started Sep 24 07:14:59 PM UTC 24
Finished Sep 24 08:01:16 PM UTC 24
Peak memory 218884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290170190 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2290170190
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.2315709535
Short name T37
Test name
Test status
Simulation time 2285201069 ps
CPU time 48.82 seconds
Started Sep 24 07:14:43 PM UTC 24
Finished Sep 24 07:15:34 PM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315709535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2315709535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_alert_test.1120910304
Short name T395
Test name
Test status
Simulation time 31763920 ps
CPU time 0.94 seconds
Started Sep 24 07:41:57 PM UTC 24
Finished Sep 24 07:41:59 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120910304 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1120910304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.4071052731
Short name T394
Test name
Test status
Simulation time 844875807 ps
CPU time 66.87 seconds
Started Sep 24 07:40:49 PM UTC 24
Finished Sep 24 07:41:58 PM UTC 24
Peak memory 210480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071052731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4071052731
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.193325736
Short name T397
Test name
Test status
Simulation time 13425546399 ps
CPU time 70.23 seconds
Started Sep 24 07:41:00 PM UTC 24
Finished Sep 24 07:42:12 PM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193325736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.193325736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.1937879817
Short name T485
Test name
Test status
Simulation time 7340507528 ps
CPU time 681.41 seconds
Started Sep 24 07:40:51 PM UTC 24
Finished Sep 24 07:52:21 PM UTC 24
Peak memory 505208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937879817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1937879817
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_error.421933076
Short name T409
Test name
Test status
Simulation time 1984040212 ps
CPU time 124.68 seconds
Started Sep 24 07:41:24 PM UTC 24
Finished Sep 24 07:43:31 PM UTC 24
Peak memory 210304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421933076 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.421933076
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_long_msg.1663742599
Short name T413
Test name
Test status
Simulation time 2071041650 ps
CPU time 175.36 seconds
Started Sep 24 07:40:49 PM UTC 24
Finished Sep 24 07:43:48 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663742599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1663742599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_smoke.1218993561
Short name T389
Test name
Test status
Simulation time 214274456 ps
CPU time 14.09 seconds
Started Sep 24 07:40:35 PM UTC 24
Finished Sep 24 07:40:50 PM UTC 24
Peak memory 210644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218993561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1218993561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_stress_all.4229148277
Short name T32
Test name
Test status
Simulation time 118247982313 ps
CPU time 1352.99 seconds
Started Sep 24 07:41:44 PM UTC 24
Finished Sep 24 08:04:35 PM UTC 24
Peak memory 713984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229148277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4229148277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.2962871356
Short name T402
Test name
Test status
Simulation time 3542637384 ps
CPU time 59.57 seconds
Started Sep 24 07:41:34 PM UTC 24
Finished Sep 24 07:42:35 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962871356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2962871356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_alert_test.2396522289
Short name T404
Test name
Test status
Simulation time 25120781 ps
CPU time 0.93 seconds
Started Sep 24 07:42:36 PM UTC 24
Finished Sep 24 07:42:38 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396522289 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2396522289
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.2798573029
Short name T399
Test name
Test status
Simulation time 45815904 ps
CPU time 4.27 seconds
Started Sep 24 07:42:11 PM UTC 24
Finished Sep 24 07:42:16 PM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798573029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2798573029
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.4175935366
Short name T408
Test name
Test status
Simulation time 667448406 ps
CPU time 47.43 seconds
Started Sep 24 07:42:15 PM UTC 24
Finished Sep 24 07:43:04 PM UTC 24
Peak memory 210628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175935366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.4175935366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.1626046007
Short name T486
Test name
Test status
Simulation time 6402799750 ps
CPU time 662.19 seconds
Started Sep 24 07:42:13 PM UTC 24
Finished Sep 24 07:53:23 PM UTC 24
Peak memory 734584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626046007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1626046007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_error.3001725374
Short name T423
Test name
Test status
Simulation time 2677428477 ps
CPU time 166.43 seconds
Started Sep 24 07:42:17 PM UTC 24
Finished Sep 24 07:45:07 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001725374 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3001725374
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_long_msg.965196319
Short name T421
Test name
Test status
Simulation time 5707925249 ps
CPU time 175.48 seconds
Started Sep 24 07:42:00 PM UTC 24
Finished Sep 24 07:44:58 PM UTC 24
Peak memory 218976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965196319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.965196319
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_smoke.3649451078
Short name T396
Test name
Test status
Simulation time 301654321 ps
CPU time 10.16 seconds
Started Sep 24 07:41:59 PM UTC 24
Finished Sep 24 07:42:10 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649451078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3649451078
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_stress_all.673448822
Short name T441
Test name
Test status
Simulation time 31707386071 ps
CPU time 261.7 seconds
Started Sep 24 07:42:28 PM UTC 24
Finished Sep 24 07:46:54 PM UTC 24
Peak memory 677108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673448822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.673448822
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.1511498710
Short name T414
Test name
Test status
Simulation time 9241360731 ps
CPU time 91.34 seconds
Started Sep 24 07:42:22 PM UTC 24
Finished Sep 24 07:43:55 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511498710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1511498710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_alert_test.3436675982
Short name T412
Test name
Test status
Simulation time 14376760 ps
CPU time 0.97 seconds
Started Sep 24 07:43:45 PM UTC 24
Finished Sep 24 07:43:47 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436675982 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3436675982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.4164087553
Short name T43
Test name
Test status
Simulation time 5738542128 ps
CPU time 43.19 seconds
Started Sep 24 07:42:42 PM UTC 24
Finished Sep 24 07:43:27 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164087553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.4164087553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.288307645
Short name T415
Test name
Test status
Simulation time 8353442636 ps
CPU time 65.57 seconds
Started Sep 24 07:43:00 PM UTC 24
Finished Sep 24 07:44:07 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288307645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.288307645
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.3175209766
Short name T410
Test name
Test status
Simulation time 277577296 ps
CPU time 51.8 seconds
Started Sep 24 07:42:51 PM UTC 24
Finished Sep 24 07:43:45 PM UTC 24
Peak memory 344400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175209766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3175209766
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_error.2409514608
Short name T431
Test name
Test status
Simulation time 7124736759 ps
CPU time 169.04 seconds
Started Sep 24 07:43:05 PM UTC 24
Finished Sep 24 07:45:57 PM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409514608 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2409514608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_long_msg.941073057
Short name T418
Test name
Test status
Simulation time 23566480742 ps
CPU time 113.82 seconds
Started Sep 24 07:42:42 PM UTC 24
Finished Sep 24 07:44:38 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941073057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.941073057
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_smoke.4069477745
Short name T406
Test name
Test status
Simulation time 1323472232 ps
CPU time 7.45 seconds
Started Sep 24 07:42:42 PM UTC 24
Finished Sep 24 07:42:50 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069477745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4069477745
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_stress_all.745683071
Short name T518
Test name
Test status
Simulation time 220957202769 ps
CPU time 1741.13 seconds
Started Sep 24 07:43:32 PM UTC 24
Finished Sep 24 08:12:55 PM UTC 24
Peak memory 498996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745683071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.745683071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.470269682
Short name T425
Test name
Test status
Simulation time 5266871981 ps
CPU time 106.53 seconds
Started Sep 24 07:43:28 PM UTC 24
Finished Sep 24 07:45:16 PM UTC 24
Peak memory 210740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470269682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.470269682
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_alert_test.1217324195
Short name T420
Test name
Test status
Simulation time 11682148 ps
CPU time 0.87 seconds
Started Sep 24 07:44:52 PM UTC 24
Finished Sep 24 07:44:54 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217324195 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1217324195
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.2484943412
Short name T417
Test name
Test status
Simulation time 1468999750 ps
CPU time 28.09 seconds
Started Sep 24 07:43:54 PM UTC 24
Finished Sep 24 07:44:23 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484943412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2484943412
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.1232948526
Short name T419
Test name
Test status
Simulation time 1922831042 ps
CPU time 42.38 seconds
Started Sep 24 07:44:08 PM UTC 24
Finished Sep 24 07:44:52 PM UTC 24
Peak memory 210308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232948526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1232948526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.2764051424
Short name T503
Test name
Test status
Simulation time 22394733443 ps
CPU time 1182.23 seconds
Started Sep 24 07:43:57 PM UTC 24
Finished Sep 24 08:03:53 PM UTC 24
Peak memory 742704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764051424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2764051424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_error.3331043736
Short name T444
Test name
Test status
Simulation time 10610991240 ps
CPU time 170.11 seconds
Started Sep 24 07:44:21 PM UTC 24
Finished Sep 24 07:47:14 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331043736 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3331043736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_long_msg.1477744770
Short name T437
Test name
Test status
Simulation time 11476796239 ps
CPU time 158.98 seconds
Started Sep 24 07:43:54 PM UTC 24
Finished Sep 24 07:46:36 PM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477744770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1477744770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_smoke.2770738241
Short name T416
Test name
Test status
Simulation time 3235722445 ps
CPU time 26.32 seconds
Started Sep 24 07:43:52 PM UTC 24
Finished Sep 24 07:44:20 PM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770738241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2770738241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_stress_all.1136051116
Short name T522
Test name
Test status
Simulation time 238489159056 ps
CPU time 2956.65 seconds
Started Sep 24 07:44:39 PM UTC 24
Finished Sep 24 08:34:32 PM UTC 24
Peak memory 759132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136051116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1136051116
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.2653353656
Short name T434
Test name
Test status
Simulation time 29022136139 ps
CPU time 109.65 seconds
Started Sep 24 07:44:24 PM UTC 24
Finished Sep 24 07:46:17 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653353656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2653353656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_alert_test.3897320144
Short name T430
Test name
Test status
Simulation time 47011008 ps
CPU time 0.9 seconds
Started Sep 24 07:45:47 PM UTC 24
Finished Sep 24 07:45:49 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897320144 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3897320144
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.3750521851
Short name T436
Test name
Test status
Simulation time 1226688592 ps
CPU time 76.79 seconds
Started Sep 24 07:45:03 PM UTC 24
Finished Sep 24 07:46:21 PM UTC 24
Peak memory 210304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750521851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3750521851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.3652139199
Short name T433
Test name
Test status
Simulation time 4792766937 ps
CPU time 63.83 seconds
Started Sep 24 07:45:10 PM UTC 24
Finished Sep 24 07:46:16 PM UTC 24
Peak memory 210468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652139199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3652139199
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.2091636391
Short name T510
Test name
Test status
Simulation time 12576111159 ps
CPU time 1298.11 seconds
Started Sep 24 07:45:09 PM UTC 24
Finished Sep 24 08:07:02 PM UTC 24
Peak memory 771372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091636391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2091636391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_error.254246397
Short name T429
Test name
Test status
Simulation time 393964688 ps
CPU time 25.9 seconds
Started Sep 24 07:45:18 PM UTC 24
Finished Sep 24 07:45:45 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254246397 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.254246397
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_long_msg.3402885258
Short name T424
Test name
Test status
Simulation time 649652696 ps
CPU time 6.84 seconds
Started Sep 24 07:45:01 PM UTC 24
Finished Sep 24 07:45:09 PM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402885258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3402885258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_smoke.3685405113
Short name T422
Test name
Test status
Simulation time 323742334 ps
CPU time 5.76 seconds
Started Sep 24 07:44:55 PM UTC 24
Finished Sep 24 07:45:02 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685405113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3685405113
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_stress_all.3530145163
Short name T484
Test name
Test status
Simulation time 63903728611 ps
CPU time 383.31 seconds
Started Sep 24 07:45:42 PM UTC 24
Finished Sep 24 07:52:11 PM UTC 24
Peak memory 271680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530145163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3530145163
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.2448718140
Short name T439
Test name
Test status
Simulation time 19852576706 ps
CPU time 69.61 seconds
Started Sep 24 07:45:35 PM UTC 24
Finished Sep 24 07:46:47 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448718140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2448718140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_alert_test.1610243762
Short name T438
Test name
Test status
Simulation time 39744700 ps
CPU time 0.86 seconds
Started Sep 24 07:46:38 PM UTC 24
Finished Sep 24 07:46:40 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610243762 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1610243762
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.375331417
Short name T453
Test name
Test status
Simulation time 1468676600 ps
CPU time 100.79 seconds
Started Sep 24 07:45:58 PM UTC 24
Finished Sep 24 07:47:41 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375331417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.375331417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.207673886
Short name T435
Test name
Test status
Simulation time 67756641 ps
CPU time 2.8 seconds
Started Sep 24 07:46:17 PM UTC 24
Finished Sep 24 07:46:20 PM UTC 24
Peak memory 210224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207673886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.207673886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.2610580134
Short name T507
Test name
Test status
Simulation time 86661181175 ps
CPU time 1106.57 seconds
Started Sep 24 07:46:01 PM UTC 24
Finished Sep 24 08:04:42 PM UTC 24
Peak memory 755100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610580134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2610580134
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_error.2556997269
Short name T472
Test name
Test status
Simulation time 2787559614 ps
CPU time 216.38 seconds
Started Sep 24 07:46:18 PM UTC 24
Finished Sep 24 07:49:59 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556997269 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2556997269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_long_msg.1370149845
Short name T445
Test name
Test status
Simulation time 1103875439 ps
CPU time 82.21 seconds
Started Sep 24 07:45:51 PM UTC 24
Finished Sep 24 07:47:15 PM UTC 24
Peak memory 210320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370149845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1370149845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_smoke.3533273553
Short name T432
Test name
Test status
Simulation time 756170226 ps
CPU time 11.95 seconds
Started Sep 24 07:45:47 PM UTC 24
Finished Sep 24 07:46:01 PM UTC 24
Peak memory 210388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533273553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3533273553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_stress_all.1412444412
Short name T33
Test name
Test status
Simulation time 53631189047 ps
CPU time 2784.6 seconds
Started Sep 24 07:46:23 PM UTC 24
Finished Sep 24 08:33:22 PM UTC 24
Peak memory 791804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412444412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1412444412
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.1363002485
Short name T442
Test name
Test status
Simulation time 1931468882 ps
CPU time 31.73 seconds
Started Sep 24 07:46:21 PM UTC 24
Finished Sep 24 07:46:54 PM UTC 24
Peak memory 210364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363002485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1363002485
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_alert_test.714035265
Short name T447
Test name
Test status
Simulation time 49118276 ps
CPU time 0.87 seconds
Started Sep 24 07:47:16 PM UTC 24
Finished Sep 24 07:47:18 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714035265 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.714035265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.3146902151
Short name T448
Test name
Test status
Simulation time 4545384998 ps
CPU time 27.88 seconds
Started Sep 24 07:46:52 PM UTC 24
Finished Sep 24 07:47:22 PM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146902151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3146902151
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.2587426601
Short name T450
Test name
Test status
Simulation time 5949650006 ps
CPU time 32.07 seconds
Started Sep 24 07:46:55 PM UTC 24
Finished Sep 24 07:47:29 PM UTC 24
Peak memory 219000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587426601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2587426601
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.1096042597
Short name T495
Test name
Test status
Simulation time 15579649298 ps
CPU time 748.02 seconds
Started Sep 24 07:46:55 PM UTC 24
Finished Sep 24 07:59:32 PM UTC 24
Peak memory 652520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096042597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1096042597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_error.3469763964
Short name T454
Test name
Test status
Simulation time 573586387 ps
CPU time 35.6 seconds
Started Sep 24 07:47:05 PM UTC 24
Finished Sep 24 07:47:42 PM UTC 24
Peak memory 210240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469763964 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3469763964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_long_msg.1999010023
Short name T474
Test name
Test status
Simulation time 9688116117 ps
CPU time 194.81 seconds
Started Sep 24 07:46:48 PM UTC 24
Finished Sep 24 07:50:07 PM UTC 24
Peak memory 221072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999010023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1999010023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_smoke.410886609
Short name T440
Test name
Test status
Simulation time 2065850749 ps
CPU time 9.47 seconds
Started Sep 24 07:46:41 PM UTC 24
Finished Sep 24 07:46:51 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410886609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.410886609
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_stress_all.2659551488
Short name T523
Test name
Test status
Simulation time 289894211941 ps
CPU time 4403.41 seconds
Started Sep 24 07:47:06 PM UTC 24
Finished Sep 24 09:01:20 PM UTC 24
Peak memory 851192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659551488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2659551488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.37171484
Short name T465
Test name
Test status
Simulation time 3787196478 ps
CPU time 88.03 seconds
Started Sep 24 07:47:05 PM UTC 24
Finished Sep 24 07:48:35 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37171484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.37171484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1578759358
Short name T455
Test name
Test status
Simulation time 11312542 ps
CPU time 0.91 seconds
Started Sep 24 07:47:44 PM UTC 24
Finished Sep 24 07:47:46 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578759358 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1578759358
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.1967229728
Short name T451
Test name
Test status
Simulation time 124195200 ps
CPU time 7.72 seconds
Started Sep 24 07:47:21 PM UTC 24
Finished Sep 24 07:47:30 PM UTC 24
Peak memory 210316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967229728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1967229728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.1848063364
Short name T464
Test name
Test status
Simulation time 2289318987 ps
CPU time 66.07 seconds
Started Sep 24 07:47:26 PM UTC 24
Finished Sep 24 07:48:34 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848063364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1848063364
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.3332932909
Short name T514
Test name
Test status
Simulation time 24875640152 ps
CPU time 1411.16 seconds
Started Sep 24 07:47:23 PM UTC 24
Finished Sep 24 08:11:11 PM UTC 24
Peak memory 779508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332932909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3332932909
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_error.1750093193
Short name T456
Test name
Test status
Simulation time 7017504847 ps
CPU time 19.7 seconds
Started Sep 24 07:47:30 PM UTC 24
Finished Sep 24 07:47:51 PM UTC 24
Peak memory 210428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750093193 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1750093193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_long_msg.1700138442
Short name T469
Test name
Test status
Simulation time 7701605314 ps
CPU time 137.94 seconds
Started Sep 24 07:47:21 PM UTC 24
Finished Sep 24 07:49:41 PM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700138442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1700138442
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_smoke.3369062809
Short name T452
Test name
Test status
Simulation time 270522795 ps
CPU time 13.51 seconds
Started Sep 24 07:47:16 PM UTC 24
Finished Sep 24 07:47:31 PM UTC 24
Peak memory 210404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369062809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3369062809
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2237951956
Short name T458
Test name
Test status
Simulation time 1689117078 ps
CPU time 27.27 seconds
Started Sep 24 07:47:31 PM UTC 24
Finished Sep 24 07:48:00 PM UTC 24
Peak memory 210412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237951956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2237951956
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.3097553213
Short name T460
Test name
Test status
Simulation time 11849289190 ps
CPU time 43.25 seconds
Started Sep 24 07:47:30 PM UTC 24
Finished Sep 24 07:48:15 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097553213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3097553213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_alert_test.2091479129
Short name T463
Test name
Test status
Simulation time 17098299 ps
CPU time 0.95 seconds
Started Sep 24 07:48:31 PM UTC 24
Finished Sep 24 07:48:33 PM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091479129 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2091479129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.2425413219
Short name T462
Test name
Test status
Simulation time 572826251 ps
CPU time 36.07 seconds
Started Sep 24 07:47:52 PM UTC 24
Finished Sep 24 07:48:30 PM UTC 24
Peak memory 210240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425413219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2425413219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.2044770633
Short name T461
Test name
Test status
Simulation time 349173771 ps
CPU time 21.15 seconds
Started Sep 24 07:48:01 PM UTC 24
Finished Sep 24 07:48:23 PM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044770633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2044770633
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.2354266990
Short name T493
Test name
Test status
Simulation time 11839631595 ps
CPU time 556.57 seconds
Started Sep 24 07:47:58 PM UTC 24
Finished Sep 24 07:57:21 PM UTC 24
Peak memory 702000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354266990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2354266990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_error.2851375631
Short name T475
Test name
Test status
Simulation time 11677844944 ps
CPU time 119.96 seconds
Started Sep 24 07:48:05 PM UTC 24
Finished Sep 24 07:50:07 PM UTC 24
Peak memory 210464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851375631 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2851375631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_long_msg.1099923071
Short name T473
Test name
Test status
Simulation time 1819441982 ps
CPU time 137.05 seconds
Started Sep 24 07:47:47 PM UTC 24
Finished Sep 24 07:50:07 PM UTC 24
Peak memory 210288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099923071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1099923071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_smoke.920089911
Short name T459
Test name
Test status
Simulation time 991260514 ps
CPU time 18.53 seconds
Started Sep 24 07:47:44 PM UTC 24
Finished Sep 24 07:48:04 PM UTC 24
Peak memory 210552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920089911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.920089911
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_stress_all.2709119947
Short name T525
Test name
Test status
Simulation time 1360088174169 ps
CPU time 5092.77 seconds
Started Sep 24 07:48:24 PM UTC 24
Finished Sep 24 09:14:08 PM UTC 24
Peak memory 853312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709119947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2709119947
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.1157503637
Short name T467
Test name
Test status
Simulation time 5145025330 ps
CPU time 77.79 seconds
Started Sep 24 07:48:16 PM UTC 24
Finished Sep 24 07:49:36 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157503637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1157503637
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_alert_test.4179691276
Short name T471
Test name
Test status
Simulation time 13504085 ps
CPU time 0.74 seconds
Started Sep 24 07:49:54 PM UTC 24
Finished Sep 24 07:49:56 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179691276 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.4179691276
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.559848339
Short name T476
Test name
Test status
Simulation time 4426165423 ps
CPU time 99.57 seconds
Started Sep 24 07:48:36 PM UTC 24
Finished Sep 24 07:50:18 PM UTC 24
Peak memory 226932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559848339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.559848339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.3099586269
Short name T470
Test name
Test status
Simulation time 207097113 ps
CPU time 14.78 seconds
Started Sep 24 07:49:37 PM UTC 24
Finished Sep 24 07:49:53 PM UTC 24
Peak memory 210348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099586269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3099586269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.2561828127
Short name T494
Test name
Test status
Simulation time 3307804781 ps
CPU time 624.17 seconds
Started Sep 24 07:48:48 PM UTC 24
Finished Sep 24 07:59:19 PM UTC 24
Peak memory 703824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561828127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2561828127
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_error.2665700322
Short name T480
Test name
Test status
Simulation time 3007890768 ps
CPU time 81.63 seconds
Started Sep 24 07:49:41 PM UTC 24
Finished Sep 24 07:51:05 PM UTC 24
Peak memory 210240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665700322 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2665700322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2947941479
Short name T468
Test name
Test status
Simulation time 10344895196 ps
CPU time 61.52 seconds
Started Sep 24 07:48:35 PM UTC 24
Finished Sep 24 07:49:38 PM UTC 24
Peak memory 221136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947941479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2947941479
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_smoke.4184197363
Short name T466
Test name
Test status
Simulation time 4713982275 ps
CPU time 11.09 seconds
Started Sep 24 07:48:34 PM UTC 24
Finished Sep 24 07:48:46 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184197363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4184197363
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_stress_all.1523443808
Short name T517
Test name
Test status
Simulation time 37044907358 ps
CPU time 1357.31 seconds
Started Sep 24 07:49:43 PM UTC 24
Finished Sep 24 08:12:36 PM UTC 24
Peak memory 771328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523443808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1523443808
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.2759475620
Short name T478
Test name
Test status
Simulation time 84455205047 ps
CPU time 74.27 seconds
Started Sep 24 07:49:41 PM UTC 24
Finished Sep 24 07:50:57 PM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759475620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2759475620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_alert_test.1295846676
Short name T40
Test name
Test status
Simulation time 98399345 ps
CPU time 0.88 seconds
Started Sep 24 07:15:36 PM UTC 24
Finished Sep 24 07:15:38 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295846676 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1295846676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.1534710990
Short name T38
Test name
Test status
Simulation time 2818260429 ps
CPU time 14.41 seconds
Started Sep 24 07:15:21 PM UTC 24
Finished Sep 24 07:15:36 PM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534710990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1534710990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.1144864949
Short name T134
Test name
Test status
Simulation time 908107757 ps
CPU time 49.4 seconds
Started Sep 24 07:15:23 PM UTC 24
Finished Sep 24 07:16:14 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144864949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1144864949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.3206154784
Short name T185
Test name
Test status
Simulation time 461119245 ps
CPU time 90.6 seconds
Started Sep 24 07:15:23 PM UTC 24
Finished Sep 24 07:16:55 PM UTC 24
Peak memory 367460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206154784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3206154784
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_long_msg.257462391
Short name T158
Test name
Test status
Simulation time 15634684218 ps
CPU time 99.93 seconds
Started Sep 24 07:15:21 PM UTC 24
Finished Sep 24 07:17:03 PM UTC 24
Peak memory 210444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257462391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.257462391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_smoke.870656760
Short name T41
Test name
Test status
Simulation time 2863668762 ps
CPU time 18.62 seconds
Started Sep 24 07:15:21 PM UTC 24
Finished Sep 24 07:15:41 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870656760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.870656760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3182184801
Short name T77
Test name
Test status
Simulation time 86274202302 ps
CPU time 1378.43 seconds
Started Sep 24 07:15:31 PM UTC 24
Finished Sep 24 07:38:46 PM UTC 24
Peak memory 455928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182184801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3182184801
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.724546263
Short name T130
Test name
Test status
Simulation time 2308068663 ps
CPU time 46.29 seconds
Started Sep 24 07:15:27 PM UTC 24
Finished Sep 24 07:16:15 PM UTC 24
Peak memory 210420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724546263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.724546263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_alert_test.703256644
Short name T173
Test name
Test status
Simulation time 81616548 ps
CPU time 0.97 seconds
Started Sep 24 07:15:49 PM UTC 24
Finished Sep 24 07:15:51 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703256644 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.703256644
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.3284980015
Short name T129
Test name
Test status
Simulation time 68831033 ps
CPU time 6.25 seconds
Started Sep 24 07:15:38 PM UTC 24
Finished Sep 24 07:15:46 PM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284980015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3284980015
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.3794305401
Short name T128
Test name
Test status
Simulation time 42358108 ps
CPU time 2.9 seconds
Started Sep 24 07:15:42 PM UTC 24
Finished Sep 24 07:15:46 PM UTC 24
Peak memory 210508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794305401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3794305401
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.155815562
Short name T226
Test name
Test status
Simulation time 13286052371 ps
CPU time 478.67 seconds
Started Sep 24 07:15:39 PM UTC 24
Finished Sep 24 07:23:44 PM UTC 24
Peak memory 695604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155815562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.155815562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_error.226116026
Short name T59
Test name
Test status
Simulation time 8075069528 ps
CPU time 66.17 seconds
Started Sep 24 07:15:45 PM UTC 24
Finished Sep 24 07:16:53 PM UTC 24
Peak memory 210496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226116026 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.226116026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_long_msg.2369105749
Short name T42
Test name
Test status
Simulation time 346920259 ps
CPU time 6.19 seconds
Started Sep 24 07:15:37 PM UTC 24
Finished Sep 24 07:15:44 PM UTC 24
Peak memory 210400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369105749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2369105749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_smoke.3737706603
Short name T135
Test name
Test status
Simulation time 419641735 ps
CPU time 10.42 seconds
Started Sep 24 07:15:36 PM UTC 24
Finished Sep 24 07:15:48 PM UTC 24
Peak memory 210340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737706603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3737706603
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_stress_all.1218503750
Short name T324
Test name
Test status
Simulation time 11650492233 ps
CPU time 1035.43 seconds
Started Sep 24 07:15:48 PM UTC 24
Finished Sep 24 07:33:15 PM UTC 24
Peak memory 742776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218503750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1218503750
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.1101091703
Short name T131
Test name
Test status
Simulation time 24950579639 ps
CPU time 100.02 seconds
Started Sep 24 07:15:48 PM UTC 24
Finished Sep 24 07:17:30 PM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101091703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1101091703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_alert_test.3501908135
Short name T179
Test name
Test status
Simulation time 12675641 ps
CPU time 0.94 seconds
Started Sep 24 07:16:15 PM UTC 24
Finished Sep 24 07:16:17 PM UTC 24
Peak memory 207400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501908135 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3501908135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.217284137
Short name T181
Test name
Test status
Simulation time 1089318589 ps
CPU time 31.82 seconds
Started Sep 24 07:15:56 PM UTC 24
Finished Sep 24 07:16:29 PM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217284137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.217284137
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.3342513522
Short name T168
Test name
Test status
Simulation time 3870602039 ps
CPU time 50.81 seconds
Started Sep 24 07:16:03 PM UTC 24
Finished Sep 24 07:16:56 PM UTC 24
Peak memory 210512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342513522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3342513522
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.3521366700
Short name T90
Test name
Test status
Simulation time 1419777880 ps
CPU time 239.3 seconds
Started Sep 24 07:16:01 PM UTC 24
Finished Sep 24 07:20:04 PM UTC 24
Peak memory 441560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521366700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3521366700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_error.2546928298
Short name T197
Test name
Test status
Simulation time 8675690935 ps
CPU time 165.06 seconds
Started Sep 24 07:16:07 PM UTC 24
Finished Sep 24 07:18:55 PM UTC 24
Peak memory 210484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546928298 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2546928298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_smoke.890962550
Short name T149
Test name
Test status
Simulation time 2246502464 ps
CPU time 16.22 seconds
Started Sep 24 07:15:52 PM UTC 24
Finished Sep 24 07:16:09 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890962550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.890962550
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_stress_all.3637728430
Short name T76
Test name
Test status
Simulation time 224035032077 ps
CPU time 986.97 seconds
Started Sep 24 07:16:10 PM UTC 24
Finished Sep 24 07:32:51 PM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637728430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3637728430
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.832310362
Short name T68
Test name
Test status
Simulation time 120476582510 ps
CPU time 714.5 seconds
Started Sep 24 07:16:15 PM UTC 24
Finished Sep 24 07:28:18 PM UTC 24
Peak memory 679292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83231036
2 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.832310362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.3506268423
Short name T132
Test name
Test status
Simulation time 23253810314 ps
CPU time 133.71 seconds
Started Sep 24 07:16:08 PM UTC 24
Finished Sep 24 07:18:25 PM UTC 24
Peak memory 210500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506268423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3506268423
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_alert_test.76986461
Short name T184
Test name
Test status
Simulation time 13115208 ps
CPU time 0.91 seconds
Started Sep 24 07:16:47 PM UTC 24
Finished Sep 24 07:16:49 PM UTC 24
Peak memory 207340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76986461 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.76986461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.2966271813
Short name T183
Test name
Test status
Simulation time 386826658 ps
CPU time 27.22 seconds
Started Sep 24 07:16:17 PM UTC 24
Finished Sep 24 07:16:46 PM UTC 24
Peak memory 210608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966271813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2966271813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.2778847359
Short name T162
Test name
Test status
Simulation time 1267449372 ps
CPU time 70.27 seconds
Started Sep 24 07:16:30 PM UTC 24
Finished Sep 24 07:17:42 PM UTC 24
Peak memory 218804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778847359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2778847359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.1091770562
Short name T259
Test name
Test status
Simulation time 44153715940 ps
CPU time 660.66 seconds
Started Sep 24 07:16:23 PM UTC 24
Finished Sep 24 07:27:31 PM UTC 24
Peak memory 734556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091770562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1091770562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_error.3809784173
Short name T84
Test name
Test status
Simulation time 2756735204 ps
CPU time 184.69 seconds
Started Sep 24 07:16:33 PM UTC 24
Finished Sep 24 07:19:41 PM UTC 24
Peak memory 210592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809784173 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3809784173
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_long_msg.1766360835
Short name T188
Test name
Test status
Simulation time 44683838256 ps
CPU time 63.13 seconds
Started Sep 24 07:16:16 PM UTC 24
Finished Sep 24 07:17:21 PM UTC 24
Peak memory 210860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766360835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1766360835
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_smoke.823526
Short name T180
Test name
Test status
Simulation time 692677715 ps
CPU time 6.14 seconds
Started Sep 24 07:16:15 PM UTC 24
Finished Sep 24 07:16:22 PM UTC 24
Peak memory 210284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.hmac_smoke.823526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_stress_all.3435350968
Short name T411
Test name
Test status
Simulation time 39407233912 ps
CPU time 1605.4 seconds
Started Sep 24 07:16:43 PM UTC 24
Finished Sep 24 07:43:47 PM UTC 24
Peak memory 734472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435350968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3435350968
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.3598499630
Short name T202
Test name
Test status
Simulation time 8335558332 ps
CPU time 205.9 seconds
Started Sep 24 07:16:41 PM UTC 24
Finished Sep 24 07:20:10 PM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598499630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3598499630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_alert_test.1995580825
Short name T187
Test name
Test status
Simulation time 28501105 ps
CPU time 0.88 seconds
Started Sep 24 07:17:13 PM UTC 24
Finished Sep 24 07:17:15 PM UTC 24
Peak memory 205356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995580825 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1995580825
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.2280158176
Short name T198
Test name
Test status
Simulation time 1645603858 ps
CPU time 127.68 seconds
Started Sep 24 07:16:57 PM UTC 24
Finished Sep 24 07:19:07 PM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280158176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2280158176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.1719847933
Short name T159
Test name
Test status
Simulation time 3910610184 ps
CPU time 87.88 seconds
Started Sep 24 07:16:57 PM UTC 24
Finished Sep 24 07:18:27 PM UTC 24
Peak memory 219000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719847933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1719847933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.3791670192
Short name T405
Test name
Test status
Simulation time 27896645548 ps
CPU time 1524.13 seconds
Started Sep 24 07:16:57 PM UTC 24
Finished Sep 24 07:42:38 PM UTC 24
Peak memory 789840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791670192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3791670192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_error.824729008
Short name T186
Test name
Test status
Simulation time 24736770 ps
CPU time 1.07 seconds
Started Sep 24 07:16:57 PM UTC 24
Finished Sep 24 07:17:00 PM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824729008 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.824729008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_long_msg.1995622512
Short name T192
Test name
Test status
Simulation time 3023587059 ps
CPU time 57.76 seconds
Started Sep 24 07:16:54 PM UTC 24
Finished Sep 24 07:17:55 PM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995622512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1995622512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_smoke.3780839464
Short name T152
Test name
Test status
Simulation time 966868572 ps
CPU time 16.97 seconds
Started Sep 24 07:16:50 PM UTC 24
Finished Sep 24 07:17:08 PM UTC 24
Peak memory 210368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780839464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3780839464
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_stress_all.2915823779
Short name T79
Test name
Test status
Simulation time 222635396394 ps
CPU time 2140.83 seconds
Started Sep 24 07:17:04 PM UTC 24
Finished Sep 24 07:53:10 PM UTC 24
Peak memory 732796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_09_23/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915823779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2915823779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.135912157
Short name T153
Test name
Test status
Simulation time 997712203 ps
CPU time 10.65 seconds
Started Sep 24 07:17:00 PM UTC 24
Finished Sep 24 07:17:12 PM UTC 24
Peak memory 210376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135912157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.135912157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/hmac-sim-vcs/9.hmac_wipe_secret/latest
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