Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17436083	1			T1	1094		T4	2874		T5	335
all_values[1]	17436083	1			T1	1094		T4	2874		T5	335
all_values[2]	17436083	1			T1	1094		T4	2874		T5	335

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

288581

1

T1

2

T5

25

T6

210

auto[1]

52019668

1

T1

3280

T4

8622

T5

980

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44620631

1

T1

2857

T4

8539

T5

858

auto[1]

7687618

1

T1

425

T4

83

T5

147

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83969	1			T6	103		T11	57		T13	1
all_values[0]	auto[0]	auto[1]	353	1			T6	2		T11	2		T14	5
all_values[0]	auto[1]	auto[0]	17332686	1			T1	1084		T4	2868		T5	330
all_values[0]	auto[1]	auto[1]	19075	1			T1	10		T4	6		T5	5
all_values[1]	auto[0]	auto[0]	122724	1			T5	25		T125	2		T49	78
all_values[1]	auto[0]	auto[1]	194	1			T14	2		T19	5		T20	5
all_values[1]	auto[1]	auto[0]	17312861	1			T1	1094		T4	2874		T5	310
all_values[1]	auto[1]	auto[1]	304	1			T11	1		T13	3		T14	4
all_values[2]	auto[0]	auto[0]	31710	1			T1	1		T6	105		T8	1
all_values[2]	auto[0]	auto[1]	49631	1			T1	1		T8	331		T14	4
all_values[2]	auto[1]	auto[0]	9736681	1			T1	678		T4	2797		T5	193
all_values[2]	auto[1]	auto[1]	7618061	1			T1	414		T4	77		T5	142