Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116203

1

T1

20

T4

2

T5

8

auto[1]

109958

1

T1

18

T4

8

T5

4

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	85438	1			T4	5		T8	10		T10	357
len_1026_2046	5664	1			T1	2		T10	35		T12	2
len_514_1022	3478	1			T1	2		T5	2		T7	1
len_2_510	3568	1			T1	2		T10	6		T11	9
len_2056	164	1			T1	3		T7	6		T38	4
len_2048	324	1			T8	1		T125	3		T65	1
len_2040	140	1			T1	1		T7	2		T145	1
len_1032	209	1			T6	2		T14	1		T38	7
len_1024	1753	1			T5	1		T6	1		T10	1
len_1016	183	1			T6	2		T125	2		T38	5
len_520	160	1			T6	3		T125	1		T38	1
len_512	339	1			T1	3		T5	1		T7	1
len_504	172	1			T5	2		T6	3		T7	1
len_8	1030	1			T66	3		T39	1		T146	3
len_0	10457	1			T1	6		T6	5		T7	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

135

1

T8

2

T10

1

T11

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	46668	1			T4	1		T8	5		T10	266
auto[0]	len_1026_2046	2665	1			T1	2		T10	22		T11	19
auto[0]	len_514_1022	1924	1			T1	2		T5	2		T10	11
auto[0]	len_2_510	2169	1			T10	6		T11	3		T125	2
auto[0]	len_2056	112	1			T1	2		T7	4		T38	3
auto[0]	len_2048	171	1			T125	3		T65	1		T38	1
auto[0]	len_2040	70	1			T7	1		T145	1		T147	1
auto[0]	len_1032	91	1			T14	1		T38	3		T148	2
auto[0]	len_1024	224	1			T11	1		T125	1		T13	1
auto[0]	len_1016	97	1			T38	4		T86	2		T18	1
auto[0]	len_520	82	1			T6	1		T38	1		T77	2
auto[0]	len_512	197	1			T1	1		T5	1		T7	1
auto[0]	len_504	109	1			T5	1		T125	2		T38	5
auto[0]	len_8	22	1			T149	2		T150	1		T151	2
auto[0]	len_0	3499	1			T1	3		T6	3		T7	1
auto[1]	len_2050_plus	38770	1			T4	4		T8	5		T10	91
auto[1]	len_1026_2046	2999	1			T10	13		T12	2		T11	9
auto[1]	len_514_1022	1554	1			T7	1		T10	2		T11	3
auto[1]	len_2_510	1399	1			T1	2		T11	6		T13	164
auto[1]	len_2056	52	1			T1	1		T7	2		T38	1
auto[1]	len_2048	153	1			T8	1		T38	2		T152	1
auto[1]	len_2040	70	1			T1	1		T7	1		T153	3
auto[1]	len_1032	118	1			T6	2		T38	4		T154	2
auto[1]	len_1024	1529	1			T5	1		T6	1		T10	1
auto[1]	len_1016	86	1			T6	2		T125	2		T38	1
auto[1]	len_520	78	1			T6	2		T125	1		T145	1
auto[1]	len_512	142	1			T1	2		T10	1		T11	2
auto[1]	len_504	63	1			T5	1		T6	3		T7	1
auto[1]	len_8	1008	1			T66	3		T39	1		T146	3
auto[1]	len_0	6958	1			T1	3		T6	2		T10	112

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

78

1

T8

1

T49

2

T155

3

auto[1]

len_upper

57

1

T8

1

T10

1

T11

2