Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4529433

1

T1

196

T4

714

T5

114

auto[1]

2661848

1

T1

269

T4

732

T5

63

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2690943

1

T1

375

T4

1227

T5

104

auto[1]

4500338

1

T1

90

T4

219

T5

73

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3245009

1

T1

177

T4

202

T5

101

auto[1]

3946272

1

T1

288

T4

1244

T5

76

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4422816

1

T1

380

T4

731

T5

47

auto[1]

2768465

1

T1

85

T4

715

T5

130

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6515193	1			T1	431		T4	1403		T5	176
fifo_depth[1]	112302	1			T1	3		T4	30		T5	1
fifo_depth[2]	86272	1			T1	6		T4	10		T6	6
fifo_depth[3]	68876	1			T1	5		T4	3		T6	1
fifo_depth[4]	62107	1			T1	5		T6	1		T7	4
fifo_depth[5]	48387	1			T1	4		T7	10		T10	3
fifo_depth[6]	38597	1			T1	3		T7	7		T10	7
fifo_depth[7]	25246	1			T1	4		T7	3		T10	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676088

1

T1

34

T4

43

T5

1

auto[1]

6515193

1

T1

431

T4

1403

T5

176

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7178411

1

T1

465

T4

1446

T5

177

auto[1]

12870

1

T11

222

T13

66

T17

40

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

21745

1

T1

5

T7

14

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

32424

1

T7

6

T11

983

T14

75

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

34176

1

T6

1

T8

1

T9

223

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26087

1

T7

6

T8

1

T11

272

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

161901

1

T4

7

T11

1154

T49

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30798

1

T11

19

T13

894

T17

369

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29049

1

T1

5

T7

11

T13

29

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34999

1

T10

10

T12

32

T13

996

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40416

1

T4

17

T10

12

T15

435

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

32837

1

T6

1

T7

5

T11

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42226

1

T1

13

T7

11

T12

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34546

1

T1

11

T4

19

T6

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46929

1

T6

6

T11

332

T126

1266

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35746

1

T5

1

T8

1

T9

15

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

38680

1

T8

1

T10

11

T125

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33529

1

T6

1

T10

26

T125

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

152299

1

T1

112

T6

8

T7

25

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

181327

1

T1

1

T5

58

T7

47

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

152622

1

T1

12

T5

15

T6

51

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

161759

1

T7

46

T8

1

T11

13

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1706420

1

T4

195

T6

42

T9

200

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

189386

1

T12

256

T11

61

T125

24

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

168535

1

T1

40

T5

12

T7

27

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

161482

1

T1

2

T5

16

T6

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

466747

1

T1

77

T4

495

T7

22

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

456263

1

T1

1

T5

31

T6

12

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

407705

1

T1

95

T7

3

T10

423

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

447764

1

T1

48

T4

696

T6

189

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

549111

1

T6

58

T8

1

T12

202

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

425084

1

T5

24

T6

62

T9

42

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

404255

1

T1

21

T4

17

T5

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

484434

1

T1

22

T6

9

T7

29

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

173629

1

T1

117

T6

8

T7

39

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

213050

1

T1

1

T5

58

T7

53

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

186380

1

T1

12

T5

15

T6

52

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

186852

1

T7

52

T8

2

T11

285

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1865895

1

T4

202

T6

42

T9

200

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

219638

1

T12

256

T11

80

T125

24

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

197181

1

T1

45

T5

12

T7

38

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

195547

1

T1

2

T5

16

T6

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

506032

1

T1

77

T4

512

T7

22

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

488987

1

T1

1

T5

31

T6

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

449021

1

T1

108

T7

14

T10

423

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

481976

1

T1

59

T4

715

T6

193

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

595365

1

T6

64

T8

1

T12

202

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

460566

1

T5

25

T6

62

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

440756

1

T1

21

T4

17

T5

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

517536

1

T1

22

T6

10

T7

29

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

415

1

T11

11

T41

59

T163

18

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

701

1

T11

83

T40

32

T41

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

418

1

T40

1

T41

7

T164

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

994

1

T13

12

T41

191

T163

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

2426

1

T11

22

T165

1540

T40

29

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

546

1

T13

7

T17

12

T41

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

403

1

T165

3

T134

75

T21

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

934

1

T13

44

T17

28

T41

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1131

1

T160

48

T40

82

T166

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

113

1

T164

10

T134

6

T167

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

910

1

T11

46

T13

3

T41

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

334

1

T11

60

T160

97

T164

94

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

675

1

T40

42

T41

292

T163

60

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

264

1

T168

2

T134

72

T169

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

2179

1

T164

550

T134

7

T170

48

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

427

1

T41

17

T164

206

T171

26

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

152299

1

T1

112

T6

8

T7

25

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

181327

1

T1

1

T5

58

T7

47

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

152622

1

T1

12

T5

15

T6

51

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

161759

1

T7

46

T8

1

T11

13

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1706420

1

T4

195

T6

42

T9

200

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

189386

1

T12

256

T11

61

T125

24

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

168535

1

T1

40

T5

12

T7

27

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

161482

1

T1

2

T5

16

T6

1

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

466747

1

T1

77

T4

495

T7

22

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

456263

1

T1

1

T5

31

T6

12

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

407705

1

T1

95

T7

3

T10

423

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

447764

1

T1

48

T4

696

T6

189

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

549111

1

T6

58

T8

1

T12

202

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

425084

1

T5

24

T6

62

T9

42

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

404255

1

T1

21

T4

17

T5

20

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

484434

1

T1

22

T6

9

T7

29

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3137

1

T1

1

T7

2

T8

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3273

1

T7

1

T14

11

T26

5

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3548

1

T9

37

T15

35

T65

1

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3136

1

T7

2

T11

2

T38

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

40036

1

T4

5

T11

3

T17

51

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

4061

1

T11

1

T45

4

T160

75

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3790

1

T7

4

T13

1

T160

11

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3328

1

T10

10

T12

18

T13

7

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6104

1

T4

12

T10

5

T15

82

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5501

1

T6

1

T7

1

T11

3

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5911

1

T1

1

T7

1

T13

2

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6216

1

T1

1

T4

13

T6

2

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7825

1

T6

2

T11

11

T126

219

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5549

1

T5

1

T8

1

T9

3

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5638

1

T13

1

T172

4

T173

6

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

5249

1

T10

4

T14

50

T38

1

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2171

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14

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