Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17436083	1			T1	1094		T4	2874		T5	335
all_pins[1]	17436083	1			T1	1094		T4	2874		T5	335
all_pins[2]	17436083	1			T1	1094		T4	2874		T5	335

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44670030	1			T1	2857		T4	8537		T5	858
values[0x1]	7638219	1			T1	425		T4	85		T5	147
transitions[0x0=>0x1]	7638064	1			T1	425		T4	85		T5	147
transitions[0x1=>0x0]	7638080	1			T1	425		T4	85		T5	147

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17416261	1			T1	1083		T4	2866		T5	330
all_pins[0]	values[0x1]	19822	1			T1	11		T4	8		T5	5
all_pins[0]	transitions[0x0=>0x1]	19761	1			T1	11		T4	8		T5	5
all_pins[0]	transitions[0x1=>0x0]	7618016	1			T1	414		T4	77		T5	142
all_pins[1]	values[0x0]	17435747	1			T1	1094		T4	2874		T5	335
all_pins[1]	values[0x1]	336	1			T11	2		T13	3		T14	4
all_pins[1]	transitions[0x0=>0x1]	287	1			T11	2		T13	3		T14	2
all_pins[1]	transitions[0x1=>0x0]	19773	1			T1	11		T4	8		T5	5
all_pins[2]	values[0x0]	9818022	1			T1	680		T4	2797		T5	193
all_pins[2]	values[0x1]	7618061	1			T1	414		T4	77		T5	142
all_pins[2]	transitions[0x0=>0x1]	7618016	1			T1	414		T4	77		T5	142
all_pins[2]	transitions[0x1=>0x0]	291	1			T11	2		T13	3		T14	3