Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 901 1 T14 10 T19 21 T20 18
all_values[1] 901 1 T14 10 T19 21 T20 18
all_values[2] 901 1 T14 10 T19 21 T20 18


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1356 1 T14 16 T19 24 T20 27
auto[1] 1347 1 T14 14 T19 39 T20 27


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 963 1 T14 4 T19 16 T20 18
auto[1] 1740 1 T14 26 T19 47 T20 36


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1547 1 T14 14 T19 31 T20 32
auto[1] 1156 1 T14 16 T19 32 T20 22


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 167 1 T19 2 T20 6 T133 1
all_values[0] auto[0] auto[0] auto[1] 94 1 T14 2 T19 3 T20 1
all_values[0] auto[0] auto[1] auto[0] 153 1 T19 5 T20 5 T133 3
all_values[0] auto[0] auto[1] auto[1] 85 1 T14 2 T19 1 T20 1
all_values[0] auto[1] auto[0] auto[1] 209 1 T14 5 T19 1 T20 1
all_values[0] auto[1] auto[1] auto[1] 193 1 T14 1 T19 9 T20 4
all_values[1] auto[0] auto[0] auto[0] 142 1 T19 3 T20 2 T133 1
all_values[1] auto[0] auto[0] auto[1] 111 1 T19 3 T20 4 T134 2
all_values[1] auto[0] auto[1] auto[0] 137 1 T14 1 T19 2 T133 1
all_values[1] auto[0] auto[1] auto[1] 120 1 T14 3 T19 2 T20 2
all_values[1] auto[1] auto[0] auto[1] 197 1 T14 3 T19 3 T20 3
all_values[1] auto[1] auto[1] auto[1] 194 1 T14 3 T19 8 T20 7
all_values[2] auto[0] auto[0] auto[0] 167 1 T14 1 T19 3 T20 3
all_values[2] auto[0] auto[0] auto[1] 85 1 T14 2 T19 1 T20 3
all_values[2] auto[0] auto[1] auto[0] 197 1 T14 2 T19 1 T20 2
all_values[2] auto[0] auto[1] auto[1] 89 1 T14 1 T19 5 T20 3
all_values[2] auto[1] auto[0] auto[1] 184 1 T14 3 T19 5 T20 4
all_values[2] auto[1] auto[1] auto[1] 179 1 T14 1 T19 6 T20 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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