Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3897	1			T1	5		T5	1		T6	6
sha2_none	3974	1			T1	8		T4	2		T5	1
sha2_512	7288	1			T1	7		T4	3		T5	5
sha2_384	7174	1			T5	1		T6	1		T7	1
sha2_256	5964	1			T1	3		T6	7		T7	4

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18071

1

T1

11

T4

2

T5

3

auto[1]

10601

1

T1

13

T4

3

T5

5

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10483

1

T1

17

T4

3

T5

3

auto[1]

18189

1

T1

7

T4

2

T5

5

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14863

1

T1

13

T4

4

T5

3

disabled

13809

1

T1

11

T4

1

T5

5

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4326	1			T1	3		T4	1		T5	3
key_none	7529	1			T1	4		T5	2		T6	2
key_1024	4281	1			T1	6		T4	1		T7	5
key_512	3606	1			T1	2		T4	2		T5	1
key_384	3169	1			T1	3		T4	1		T6	5
key_256	2893	1			T1	1		T5	1		T6	3
key_128	2789	1			T1	5		T5	1		T6	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18165

1

T1

17

T4

3

T5

4

auto[1]

10507

1

T1

7

T4

2

T5

4

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28495

1

T1

24

T4

5

T5

8

disabled

177

1

T45

2

T46

1

T47

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1530

1

T1

5

T4

1

T7

1

enabled

auto[0]

auto[0]

auto[1]

1516

1

T1

1

T5

1

T6

1

enabled

auto[0]

auto[1]

auto[0]

1532

1

T1

3

T7

1

T10

3

enabled

auto[0]

auto[1]

auto[1]

1492

1

T1

2

T4

2

T6

6

enabled

auto[1]

auto[0]

auto[0]

4229

1

T6

4

T8

1

T12

1

enabled

auto[1]

auto[0]

auto[1]

1463

1

T5

1

T6

2

T8

2

enabled

auto[1]

auto[1]

auto[0]

1587

1

T1

1

T4

1

T5

1

enabled

auto[1]

auto[1]

auto[1]

1514

1

T1

1

T6

1

T7

1

disabled

auto[0]

auto[0]

auto[0]

1100

1

T1

4

T6

2

T7

1

disabled

auto[0]

auto[0]

auto[1]

1135

1

T1

1

T5

1

T7

2

disabled

auto[0]

auto[1]

auto[0]

1086

1

T1

1

T5

1

T6

2

disabled

auto[0]

auto[1]

auto[1]

1092

1

T7

4

T8

3

T11

2

disabled

auto[1]

auto[0]

auto[0]

5937

1

T4

1

T6

1

T9

1

disabled

auto[1]

auto[0]

auto[1]

1161

1

T12

1

T11

2

T125

2

disabled

auto[1]

auto[1]

auto[0]

1164

1

T1

3

T5

2

T7

2

disabled

auto[1]

auto[1]

auto[1]

1134

1

T1

2

T5

1

T6

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14775

1

T1

13

T4

4

T5

3

enabled

disabled

88

1

T45

1

T47

3

T48

2

disabled

disabled

89

1

T45

1

T46

1

T47

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13720

1

T1

11

T4

1

T5

5

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	986	1			T7	1		T13	1		T17	1
key_invalid	sha2_none	853	1			T1	1		T4	1		T5	1
key_invalid	sha2_512	785	1			T1	1		T5	1		T6	1
key_invalid	sha2_384	823	1			T5	1		T125	1		T13	2
key_invalid	sha2_256	790	1			T1	1		T10	1		T9	1
key_none	sha2_invalid	458	1			T1	1		T5	1		T6	1
key_none	sha2_none	519	1			T1	3		T10	1		T9	2
key_none	sha2_512	2519	1			T5	1		T6	1		T8	1
key_none	sha2_384	2475	1			T8	1		T10	1		T11	1
key_none	sha2_256	1517	1			T9	1		T12	1		T13	1
key_1024	sha2_invalid	482	1			T1	1		T12	2		T125	1
key_1024	sha2_none	546	1			T1	1		T7	3		T8	1
key_1024	sha2_512	1701	1			T1	2		T4	1		T7	1
key_1024	sha2_384	942	1			T9	1		T11	1		T13	1
key_512	sha2_invalid	513	1			T12	1		T125	1		T13	1
key_512	sha2_none	496	1			T1	1		T4	1		T6	1
key_512	sha2_512	588	1			T1	1		T4	1		T5	1
key_512	sha2_384	1139	1			T10	1		T11	3		T13	2
key_512	sha2_256	827	1			T6	2		T7	1		T10	1
key_384	sha2_invalid	450	1			T1	1		T6	1		T10	1
key_384	sha2_none	535	1			T1	1		T6	1		T9	1
key_384	sha2_512	555	1			T1	1		T4	1		T6	1
key_384	sha2_384	606	1			T6	1		T9	1		T13	1
key_384	sha2_256	986	1			T6	1		T8	2		T10	4
key_256	sha2_invalid	463	1			T6	1		T11	1		T17	1
key_256	sha2_none	516	1			T10	1		T11	1		T125	2
key_256	sha2_512	585	1			T1	1		T5	1		T7	1
key_256	sha2_384	589	1			T7	1		T12	1		T125	2
key_256	sha2_256	682	1			T6	2		T10	2		T9	1
key_128	sha2_invalid	530	1			T1	2		T6	3		T10	1
key_128	sha2_none	492	1			T1	1		T12	1		T11	2
key_128	sha2_512	538	1			T1	1		T5	1		T8	1
key_128	sha2_384	587	1			T125	2		T15	1		T65	2
key_128	sha2_256	585	1			T1	1		T6	2		T7	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

560

1

T1

1

T7

1

T8

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	986	1			T7	1		T13	1		T17	1
key_invalid	sha2_none	853	1			T1	1		T4	1		T5	1
key_invalid	sha2_512	785	1			T1	1		T5	1		T6	1
key_invalid	sha2_384	823	1			T5	1		T125	1		T13	2
key_invalid	sha2_256	790	1			T1	1		T10	1		T9	1
key_none	sha2_invalid	458	1			T1	1		T5	1		T6	1
key_none	sha2_none	519	1			T1	3		T10	1		T9	2
key_none	sha2_512	2519	1			T5	1		T6	1		T8	1
key_none	sha2_384	2475	1			T8	1		T10	1		T11	1
key_none	sha2_256	1517	1			T9	1		T12	1		T13	1
key_1024	sha2_invalid	482	1			T1	1		T12	2		T125	1
key_1024	sha2_none	546	1			T1	1		T7	3		T8	1
key_1024	sha2_512	1701	1			T1	2		T4	1		T7	1
key_1024	sha2_384	942	1			T9	1		T11	1		T13	1
key_1024	sha2_256	560	1			T1	1		T7	1		T8	1
key_512	sha2_invalid	513	1			T12	1		T125	1		T13	1
key_512	sha2_none	496	1			T1	1		T4	1		T6	1
key_512	sha2_512	588	1			T1	1		T4	1		T5	1
key_512	sha2_384	1139	1			T10	1		T11	3		T13	2
key_512	sha2_256	827	1			T6	2		T7	1		T10	1
key_384	sha2_invalid	450	1			T1	1		T6	1		T10	1
key_384	sha2_none	535	1			T1	1		T6	1		T9	1
key_384	sha2_512	555	1			T1	1		T4	1		T6	1
key_384	sha2_384	606	1			T6	1		T9	1		T13	1
key_384	sha2_256	986	1			T6	1		T8	2		T10	4
key_256	sha2_invalid	463	1			T6	1		T11	1		T17	1
key_256	sha2_none	516	1			T10	1		T11	1		T125	2
key_256	sha2_512	585	1			T1	1		T5	1		T7	1
key_256	sha2_384	589	1			T7	1		T12	1		T125	2
key_256	sha2_256	682	1			T6	2		T10	2		T9	1
key_128	sha2_invalid	530	1			T1	2		T6	3		T10	1
key_128	sha2_none	492	1			T1	1		T12	1		T11	2
key_128	sha2_512	538	1			T1	1		T5	1		T8	1
key_128	sha2_384	587	1			T125	2		T15	1		T65	2
key_128	sha2_256	585	1			T1	1		T6	2		T7	2