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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 95.37 97.22 100.00 94.12 98.25 98.52 99.85


Total test records in report: 655
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T118 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.268094387 Oct 12 12:37:55 AM UTC 24 Oct 12 12:37:59 AM UTC 24 555173992 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1431365608 Oct 12 12:37:56 AM UTC 24 Oct 12 12:37:59 AM UTC 24 45041326 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.755412160 Oct 12 12:37:55 AM UTC 24 Oct 12 12:37:59 AM UTC 24 46603697 ps
T536 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.827114119 Oct 12 12:37:58 AM UTC 24 Oct 12 12:38:00 AM UTC 24 13025356 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3943129553 Oct 12 12:37:59 AM UTC 24 Oct 12 12:38:01 AM UTC 24 40240563 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1611981368 Oct 12 12:38:22 AM UTC 24 Oct 12 12:38:28 AM UTC 24 141956417 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3811519488 Oct 12 12:37:58 AM UTC 24 Oct 12 12:38:01 AM UTC 24 322493191 ps
T537 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1969255983 Oct 12 12:37:58 AM UTC 24 Oct 12 12:38:02 AM UTC 24 997616575 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1162791002 Oct 12 12:38:00 AM UTC 24 Oct 12 12:38:02 AM UTC 24 33161888 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1290107287 Oct 12 12:38:00 AM UTC 24 Oct 12 12:38:03 AM UTC 24 116774931 ps
T538 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.280041499 Oct 12 12:38:00 AM UTC 24 Oct 12 12:38:03 AM UTC 24 69798457 ps
T539 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.582654248 Oct 12 12:37:55 AM UTC 24 Oct 12 12:38:04 AM UTC 24 336001516 ps
T540 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.4120116332 Oct 12 12:38:00 AM UTC 24 Oct 12 12:38:05 AM UTC 24 53223562 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.3956669838 Oct 12 12:37:56 AM UTC 24 Oct 12 12:38:06 AM UTC 24 301195586 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1997323929 Oct 12 12:38:01 AM UTC 24 Oct 12 12:38:06 AM UTC 24 117154415 ps
T541 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1440069251 Oct 12 12:38:26 AM UTC 24 Oct 12 12:38:28 AM UTC 24 35093172 ps
T542 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.399655131 Oct 12 12:37:56 AM UTC 24 Oct 12 12:38:08 AM UTC 24 859095076 ps
T543 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.4191103979 Oct 12 12:38:06 AM UTC 24 Oct 12 12:38:08 AM UTC 24 15246633 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.203317244 Oct 12 12:38:00 AM UTC 24 Oct 12 12:38:08 AM UTC 24 308463439 ps
T544 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.3254812638 Oct 12 12:38:06 AM UTC 24 Oct 12 12:38:08 AM UTC 24 13219857 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3643562201 Oct 12 12:38:06 AM UTC 24 Oct 12 12:38:08 AM UTC 24 159891983 ps
T545 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.2534489175 Oct 12 12:38:08 AM UTC 24 Oct 12 12:38:09 AM UTC 24 55169196 ps
T546 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.3349661208 Oct 12 12:38:08 AM UTC 24 Oct 12 12:38:10 AM UTC 24 19816988 ps
T547 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1692479372 Oct 12 12:38:07 AM UTC 24 Oct 12 12:38:11 AM UTC 24 241983512 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.866235617 Oct 12 12:38:09 AM UTC 24 Oct 12 12:38:11 AM UTC 24 20794287 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4231257292 Oct 12 12:38:07 AM UTC 24 Oct 12 12:38:11 AM UTC 24 428423708 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1952179543 Oct 12 12:38:07 AM UTC 24 Oct 12 12:38:11 AM UTC 24 196850353 ps
T548 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.1869129249 Oct 12 12:38:10 AM UTC 24 Oct 12 12:38:12 AM UTC 24 36076184 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1056275928 Oct 12 12:38:00 AM UTC 24 Oct 12 12:38:12 AM UTC 24 289301206 ps
T549 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2564433557 Oct 12 12:38:09 AM UTC 24 Oct 12 12:38:12 AM UTC 24 34941313 ps
T550 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1394611343 Oct 12 12:38:07 AM UTC 24 Oct 12 12:38:12 AM UTC 24 356860899 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2419891476 Oct 12 12:38:09 AM UTC 24 Oct 12 12:38:13 AM UTC 24 73250893 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.3608190237 Oct 12 12:38:10 AM UTC 24 Oct 12 12:38:13 AM UTC 24 161486141 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.322803750 Oct 12 12:38:11 AM UTC 24 Oct 12 12:38:14 AM UTC 24 36044335 ps
T551 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2737915064 Oct 12 12:38:13 AM UTC 24 Oct 12 12:38:14 AM UTC 24 48143040 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3127408960 Oct 12 12:38:11 AM UTC 24 Oct 12 12:38:15 AM UTC 24 132404358 ps
T552 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3918549771 Oct 12 12:38:09 AM UTC 24 Oct 12 12:38:15 AM UTC 24 1075429839 ps
T553 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2107948165 Oct 12 12:37:54 AM UTC 24 Oct 12 12:38:15 AM UTC 24 2138164684 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1426990602 Oct 12 12:38:14 AM UTC 24 Oct 12 12:38:16 AM UTC 24 14137644 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.48328137 Oct 12 12:38:12 AM UTC 24 Oct 12 12:38:16 AM UTC 24 637025149 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3075158569 Oct 12 12:38:14 AM UTC 24 Oct 12 12:38:16 AM UTC 24 24253397 ps
T554 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3688002910 Oct 12 12:38:12 AM UTC 24 Oct 12 12:38:17 AM UTC 24 49101471 ps
T555 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1781170704 Oct 12 12:38:15 AM UTC 24 Oct 12 12:38:17 AM UTC 24 38781227 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2647728506 Oct 12 12:38:15 AM UTC 24 Oct 12 12:38:17 AM UTC 24 32462100 ps
T556 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4238904770 Oct 12 12:38:12 AM UTC 24 Oct 12 12:38:17 AM UTC 24 647878753 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.91252791 Oct 12 12:38:15 AM UTC 24 Oct 12 12:38:18 AM UTC 24 986810920 ps
T557 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1876353262 Oct 12 12:38:07 AM UTC 24 Oct 12 12:38:18 AM UTC 24 1143749799 ps
T558 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.3200978699 Oct 12 12:38:14 AM UTC 24 Oct 12 12:38:19 AM UTC 24 197311824 ps
T559 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1784198631 Oct 12 12:38:17 AM UTC 24 Oct 12 12:38:19 AM UTC 24 15015079 ps
T560 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3932988579 Oct 12 12:38:16 AM UTC 24 Oct 12 12:38:20 AM UTC 24 484679335 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.562847095 Oct 12 12:38:17 AM UTC 24 Oct 12 12:38:20 AM UTC 24 36258836 ps
T561 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1195830412 Oct 12 12:38:19 AM UTC 24 Oct 12 12:38:21 AM UTC 24 35441091 ps
T562 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.2504095362 Oct 12 12:38:19 AM UTC 24 Oct 12 12:38:21 AM UTC 24 20445064 ps
T563 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.642608458 Oct 12 12:38:18 AM UTC 24 Oct 12 12:38:21 AM UTC 24 309411664 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.706485994 Oct 12 12:38:16 AM UTC 24 Oct 12 12:38:21 AM UTC 24 591052790 ps
T564 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.546969018 Oct 12 12:38:16 AM UTC 24 Oct 12 12:38:21 AM UTC 24 216623636 ps
T565 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.4290322217 Oct 12 12:38:09 AM UTC 24 Oct 12 12:38:22 AM UTC 24 305682121 ps
T566 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3123250094 Oct 12 12:38:18 AM UTC 24 Oct 12 12:38:22 AM UTC 24 90987383 ps
T567 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.4051053153 Oct 12 12:38:18 AM UTC 24 Oct 12 12:38:22 AM UTC 24 162900288 ps
T568 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.3024950044 Oct 12 12:38:16 AM UTC 24 Oct 12 12:38:22 AM UTC 24 76086487 ps
T569 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.381311556 Oct 12 12:38:20 AM UTC 24 Oct 12 12:38:23 AM UTC 24 394376818 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.1492854057 Oct 12 12:38:19 AM UTC 24 Oct 12 12:38:23 AM UTC 24 310854546 ps
T570 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2089248512 Oct 12 12:38:21 AM UTC 24 Oct 12 12:38:23 AM UTC 24 35577685 ps
T571 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1005318779 Oct 12 12:38:20 AM UTC 24 Oct 12 12:38:23 AM UTC 24 59134868 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.3465069189 Oct 12 12:38:21 AM UTC 24 Oct 12 12:38:24 AM UTC 24 34609751 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.4070656815 Oct 12 12:38:21 AM UTC 24 Oct 12 12:38:24 AM UTC 24 107942988 ps
T572 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1519723836 Oct 12 12:38:26 AM UTC 24 Oct 12 12:38:28 AM UTC 24 19317159 ps
T573 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2840710518 Oct 12 12:38:21 AM UTC 24 Oct 12 12:38:24 AM UTC 24 83761478 ps
T574 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.4235034026 Oct 12 12:38:23 AM UTC 24 Oct 12 12:38:24 AM UTC 24 44009010 ps
T575 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.3807159649 Oct 12 12:38:23 AM UTC 24 Oct 12 12:38:25 AM UTC 24 98676138 ps
T576 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3685293127 Oct 12 12:38:06 AM UTC 24 Oct 12 12:38:26 AM UTC 24 324751445 ps
T577 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2917141874 Oct 12 12:38:21 AM UTC 24 Oct 12 12:38:26 AM UTC 24 878587213 ps
T578 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.2121371876 Oct 12 12:38:24 AM UTC 24 Oct 12 12:38:26 AM UTC 24 14607888 ps
T579 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1336006439 Oct 12 12:38:24 AM UTC 24 Oct 12 12:38:27 AM UTC 24 118916372 ps
T580 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2846525090 Oct 12 12:38:24 AM UTC 24 Oct 12 12:38:29 AM UTC 24 83098132 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4282307818 Oct 12 12:38:09 AM UTC 24 Oct 12 12:38:27 AM UTC 24 312232101 ps
T581 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.4118734641 Oct 12 12:38:25 AM UTC 24 Oct 12 12:38:27 AM UTC 24 53084910 ps
T582 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2001703814 Oct 12 12:38:22 AM UTC 24 Oct 12 12:38:28 AM UTC 24 98055972 ps
T583 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3264847825 Oct 12 12:38:24 AM UTC 24 Oct 12 12:38:28 AM UTC 24 178704021 ps
T584 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2746896978 Oct 12 12:38:25 AM UTC 24 Oct 12 12:38:29 AM UTC 24 64390710 ps
T585 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1415908331 Oct 12 12:38:25 AM UTC 24 Oct 12 12:38:29 AM UTC 24 267674266 ps
T586 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4070414787 Oct 12 12:38:26 AM UTC 24 Oct 12 12:38:29 AM UTC 24 151053047 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2686740878 Oct 12 12:38:24 AM UTC 24 Oct 12 12:38:30 AM UTC 24 237872017 ps
T587 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2236278845 Oct 12 12:38:25 AM UTC 24 Oct 12 12:38:30 AM UTC 24 176203882 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.162358513 Oct 12 12:38:22 AM UTC 24 Oct 12 12:38:30 AM UTC 24 587394390 ps
T588 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.280368358 Oct 12 12:38:29 AM UTC 24 Oct 12 12:38:31 AM UTC 24 41955291 ps
T589 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.3656724769 Oct 12 12:38:29 AM UTC 24 Oct 12 12:38:31 AM UTC 24 35281667 ps
T590 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2255569774 Oct 12 12:38:29 AM UTC 24 Oct 12 12:38:31 AM UTC 24 45244547 ps
T591 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2385441045 Oct 12 12:38:30 AM UTC 24 Oct 12 12:38:32 AM UTC 24 40830645 ps
T592 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.427601218 Oct 12 12:38:28 AM UTC 24 Oct 12 12:38:32 AM UTC 24 96965748 ps
T593 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2594951913 Oct 12 12:38:30 AM UTC 24 Oct 12 12:38:32 AM UTC 24 19544485 ps
T594 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1630912406 Oct 12 12:38:26 AM UTC 24 Oct 12 12:38:32 AM UTC 24 509813088 ps
T595 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2086813878 Oct 12 12:38:31 AM UTC 24 Oct 12 12:38:33 AM UTC 24 18094401 ps
T596 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2094468244 Oct 12 12:38:30 AM UTC 24 Oct 12 12:38:33 AM UTC 24 68206451 ps
T597 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1445948136 Oct 12 12:38:28 AM UTC 24 Oct 12 12:38:33 AM UTC 24 810661986 ps
T598 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2921107710 Oct 12 12:38:30 AM UTC 24 Oct 12 12:38:34 AM UTC 24 37473384 ps
T599 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.3281599039 Oct 12 12:38:31 AM UTC 24 Oct 12 12:38:34 AM UTC 24 69426437 ps
T600 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.2128376601 Oct 12 12:38:33 AM UTC 24 Oct 12 12:38:35 AM UTC 24 234971661 ps
T601 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4007659425 Oct 12 12:38:31 AM UTC 24 Oct 12 12:38:35 AM UTC 24 273103421 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3660678782 Oct 12 12:38:30 AM UTC 24 Oct 12 12:38:35 AM UTC 24 124145175 ps
T602 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3430231998 Oct 12 12:38:29 AM UTC 24 Oct 12 12:38:35 AM UTC 24 135772759 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1958938330 Oct 12 12:38:31 AM UTC 24 Oct 12 12:38:35 AM UTC 24 81962972 ps
T603 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.4131884777 Oct 12 12:38:30 AM UTC 24 Oct 12 12:38:35 AM UTC 24 75451151 ps
T604 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.657043759 Oct 12 12:38:33 AM UTC 24 Oct 12 12:38:35 AM UTC 24 104456493 ps
T605 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3350768311 Oct 12 12:38:34 AM UTC 24 Oct 12 12:38:36 AM UTC 24 12003076 ps
T606 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3226209154 Oct 12 12:38:34 AM UTC 24 Oct 12 12:38:36 AM UTC 24 59632213 ps
T607 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3440514041 Oct 12 12:38:33 AM UTC 24 Oct 12 12:38:36 AM UTC 24 355234497 ps
T608 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3605973102 Oct 12 12:38:34 AM UTC 24 Oct 12 12:38:37 AM UTC 24 132072845 ps
T609 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3889921070 Oct 12 12:38:35 AM UTC 24 Oct 12 12:38:37 AM UTC 24 15637756 ps
T610 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.3489237026 Oct 12 12:38:35 AM UTC 24 Oct 12 12:38:38 AM UTC 24 64983416 ps
T611 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.2850121425 Oct 12 12:38:37 AM UTC 24 Oct 12 12:38:38 AM UTC 24 32357301 ps
T612 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3843284909 Oct 12 12:38:35 AM UTC 24 Oct 12 12:38:39 AM UTC 24 701099181 ps
T613 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2552871854 Oct 12 12:38:36 AM UTC 24 Oct 12 12:38:39 AM UTC 24 34876434 ps
T614 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.307851242 Oct 12 12:38:36 AM UTC 24 Oct 12 12:38:39 AM UTC 24 48879054 ps
T615 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.1057768692 Oct 12 12:38:37 AM UTC 24 Oct 12 12:38:39 AM UTC 24 45902350 ps
T616 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.3861574642 Oct 12 12:38:34 AM UTC 24 Oct 12 12:38:39 AM UTC 24 157130369 ps
T617 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2561409723 Oct 12 12:38:36 AM UTC 24 Oct 12 12:38:39 AM UTC 24 34339104 ps
T618 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3570779788 Oct 12 12:38:35 AM UTC 24 Oct 12 12:38:39 AM UTC 24 434840657 ps
T619 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.4226591947 Oct 12 12:38:34 AM UTC 24 Oct 12 12:38:39 AM UTC 24 537425724 ps
T620 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.358715577 Oct 12 12:38:37 AM UTC 24 Oct 12 12:38:40 AM UTC 24 83858903 ps
T621 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.3356335750 Oct 12 12:38:38 AM UTC 24 Oct 12 12:38:40 AM UTC 24 28437163 ps
T622 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1079419015 Oct 12 12:38:37 AM UTC 24 Oct 12 12:38:40 AM UTC 24 79327776 ps
T623 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.934665267 Oct 12 12:38:38 AM UTC 24 Oct 12 12:38:40 AM UTC 24 12647508 ps
T624 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.2766686672 Oct 12 12:38:38 AM UTC 24 Oct 12 12:38:40 AM UTC 24 11433714 ps
T625 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3957802869 Oct 12 12:38:37 AM UTC 24 Oct 12 12:38:40 AM UTC 24 126484153 ps
T626 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1925925121 Oct 12 12:38:37 AM UTC 24 Oct 12 12:38:41 AM UTC 24 604109078 ps
T627 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.3420852767 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 48676349 ps
T628 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2207477107 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 23444603 ps
T629 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.2442840940 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 14675691 ps
T630 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2432268655 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 17423177 ps
T631 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2047261422 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 38751465 ps
T632 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3851387429 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 71178066 ps
T633 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.1724819938 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 35595170 ps
T634 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3456922444 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 17602127 ps
T635 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2464097950 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 155476652 ps
T636 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1686449308 Oct 12 12:38:40 AM UTC 24 Oct 12 12:38:42 AM UTC 24 15386005 ps
T637 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3815021739 Oct 12 12:38:41 AM UTC 24 Oct 12 12:38:42 AM UTC 24 14445258 ps
T638 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.453916590 Oct 12 12:38:41 AM UTC 24 Oct 12 12:38:42 AM UTC 24 37166898 ps
T639 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.1384842828 Oct 12 12:38:41 AM UTC 24 Oct 12 12:38:42 AM UTC 24 11927046 ps
T640 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.365455083 Oct 12 12:38:41 AM UTC 24 Oct 12 12:38:43 AM UTC 24 39731518 ps
T641 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1758210677 Oct 12 12:38:42 AM UTC 24 Oct 12 12:38:44 AM UTC 24 13892243 ps
T642 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3422681357 Oct 12 12:38:42 AM UTC 24 Oct 12 12:38:44 AM UTC 24 50437948 ps
T643 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2099376118 Oct 12 12:38:42 AM UTC 24 Oct 12 12:38:44 AM UTC 24 13082794 ps
T644 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.360779722 Oct 12 12:38:42 AM UTC 24 Oct 12 12:38:44 AM UTC 24 20817253 ps
T645 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2187596947 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 26146519 ps
T646 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.884887948 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 14927160 ps
T647 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.2543843720 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 17254431 ps
T648 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.3693244002 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 76877366 ps
T649 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.525609856 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 12877594 ps
T650 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.2667387074 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 36330216 ps
T651 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2778286876 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 33862386 ps
T652 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1179238883 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 31473064 ps
T653 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1205715079 Oct 12 12:38:43 AM UTC 24 Oct 12 12:38:45 AM UTC 24 122037588 ps
T654 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.51753666 Oct 12 12:38:14 AM UTC 24 Oct 12 12:44:19 AM UTC 24 51787643222 ps
T655 /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1897272077 Oct 12 12:37:56 AM UTC 24 Oct 12 12:52:23 AM UTC 24 351331784693 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.2282585330
Short name T8
Test name
Test status
Simulation time 402653240 ps
CPU time 22.6 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:05:41 AM UTC 24
Peak memory 218472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282585330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2282585330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.2333748470
Short name T13
Test name
Test status
Simulation time 2230785232 ps
CPU time 36.84 seconds
Started Oct 12 12:05:25 AM UTC 24
Finished Oct 12 12:06:03 AM UTC 24
Peak memory 218540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333748470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2333748470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.2520498711
Short name T20
Test name
Test status
Simulation time 48175354640 ps
CPU time 681.04 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:16:48 AM UTC 24
Peak memory 725808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25204987
11 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2520498711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.3948446738
Short name T11
Test name
Test status
Simulation time 740790019 ps
CPU time 38.7 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:05:59 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948446738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3948446738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.1982663835
Short name T85
Test name
Test status
Simulation time 1019004471 ps
CPU time 51.77 seconds
Started Oct 12 12:07:52 AM UTC 24
Finished Oct 12 12:08:46 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982663835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1982663835
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1997323929
Short name T135
Test name
Test status
Simulation time 117154415 ps
CPU time 3.95 seconds
Started Oct 12 12:38:01 AM UTC 24
Finished Oct 12 12:38:06 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997323929 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1997323929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_smoke.3823500992
Short name T38
Test name
Test status
Simulation time 3877164706 ps
CPU time 21.48 seconds
Started Oct 12 12:06:20 AM UTC 24
Finished Oct 12 12:06:43 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823500992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.3823500992
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_error.1967467041
Short name T47
Test name
Test status
Simulation time 7678798465 ps
CPU time 147.21 seconds
Started Oct 12 12:06:23 AM UTC 24
Finished Oct 12 12:08:52 AM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967467041 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1967467041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.545436654
Short name T3
Test name
Test status
Simulation time 67939991 ps
CPU time 0.98 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:05:21 AM UTC 24
Peak memory 238008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545436654 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.545436654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_stress_all.3823605861
Short name T21
Test name
Test status
Simulation time 36773030009 ps
CPU time 631.01 seconds
Started Oct 12 12:10:01 AM UTC 24
Finished Oct 12 12:20:39 AM UTC 24
Peak memory 438944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823605861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3823605861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.990244812
Short name T104
Test name
Test status
Simulation time 25634720 ps
CPU time 1.25 seconds
Started Oct 12 12:37:56 AM UTC 24
Finished Oct 12 12:37:58 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990244812 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.990244812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.1710296029
Short name T94
Test name
Test status
Simulation time 1811250935 ps
CPU time 96.45 seconds
Started Oct 12 12:09:15 AM UTC 24
Finished Oct 12 12:10:54 AM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710296029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1710296029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_smoke.845064523
Short name T6
Test name
Test status
Simulation time 832753626 ps
CPU time 6.82 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:05:25 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845064523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.845064523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.162358513
Short name T60
Test name
Test status
Simulation time 587394390 ps
CPU time 6.87 seconds
Started Oct 12 12:38:22 AM UTC 24
Finished Oct 12 12:38:30 AM UTC 24
Peak memory 207808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162358513 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.162358513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_long_msg.1020394076
Short name T162
Test name
Test status
Simulation time 10808677820 ps
CPU time 197.28 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:08:38 AM UTC 24
Peak memory 226168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020394076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1020394076
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_stress_all.2396502438
Short name T134
Test name
Test status
Simulation time 21571088384 ps
CPU time 556.46 seconds
Started Oct 12 12:08:47 AM UTC 24
Finished Oct 12 12:18:11 AM UTC 24
Peak memory 672308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396502438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2396502438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_alert_test.584165341
Short name T2
Test name
Test status
Simulation time 11879451 ps
CPU time 0.75 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:05:21 AM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584165341 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.584165341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.593234419
Short name T40
Test name
Test status
Simulation time 982530275 ps
CPU time 63.82 seconds
Started Oct 12 12:08:45 AM UTC 24
Finished Oct 12 12:09:50 AM UTC 24
Peak memory 218348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593234419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.593234419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.1492854057
Short name T138
Test name
Test status
Simulation time 310854546 ps
CPU time 3.17 seconds
Started Oct 12 12:38:19 AM UTC 24
Finished Oct 12 12:38:23 AM UTC 24
Peak memory 207632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492854057 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1492854057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_smoke.1637102885
Short name T1
Test name
Test status
Simulation time 144035970 ps
CPU time 6.68 seconds
Started Oct 12 12:08:56 AM UTC 24
Finished Oct 12 12:09:03 AM UTC 24
Peak memory 209620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637102885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1637102885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.268094387
Short name T118
Test name
Test status
Simulation time 555173992 ps
CPU time 2.82 seconds
Started Oct 12 12:37:55 AM UTC 24
Finished Oct 12 12:37:59 AM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268094387 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.268094387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.2975925824
Short name T10
Test name
Test status
Simulation time 10806662284 ps
CPU time 23.91 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:05:42 AM UTC 24
Peak memory 218388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975925824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2975925824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.1754044091
Short name T282
Test name
Test status
Simulation time 52262562947 ps
CPU time 705.57 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:17:12 AM UTC 24
Peak memory 213368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754044091 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1754044091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.582654248
Short name T539
Test name
Test status
Simulation time 336001516 ps
CPU time 7.93 seconds
Started Oct 12 12:37:55 AM UTC 24
Finished Oct 12 12:38:04 AM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582654248 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.582654248
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2107948165
Short name T553
Test name
Test status
Simulation time 2138164684 ps
CPU time 19.9 seconds
Started Oct 12 12:37:54 AM UTC 24
Finished Oct 12 12:38:15 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107948165 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2107948165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.2819668049
Short name T101
Test name
Test status
Simulation time 35475421 ps
CPU time 1.43 seconds
Started Oct 12 12:37:54 AM UTC 24
Finished Oct 12 12:37:56 AM UTC 24
Peak memory 206924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819668049 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2819668049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4191420505
Short name T62
Test name
Test status
Simulation time 116466381 ps
CPU time 1.84 seconds
Started Oct 12 12:37:55 AM UTC 24
Finished Oct 12 12:37:58 AM UTC 24
Peak memory 206756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4191420505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.4191420505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.3988585496
Short name T102
Test name
Test status
Simulation time 329416730 ps
CPU time 1.44 seconds
Started Oct 12 12:37:54 AM UTC 24
Finished Oct 12 12:37:56 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988585496 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3988585496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.270139071
Short name T534
Test name
Test status
Simulation time 33520630 ps
CPU time 0.84 seconds
Started Oct 12 12:37:52 AM UTC 24
Finished Oct 12 12:37:54 AM UTC 24
Peak memory 204536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270139071 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.270139071
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.917368373
Short name T61
Test name
Test status
Simulation time 66124100 ps
CPU time 2.4 seconds
Started Oct 12 12:37:52 AM UTC 24
Finished Oct 12 12:37:56 AM UTC 24
Peak memory 207476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917368373 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.917368373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.472321412
Short name T56
Test name
Test status
Simulation time 55035412 ps
CPU time 1.82 seconds
Started Oct 12 12:37:52 AM UTC 24
Finished Oct 12 12:37:55 AM UTC 24
Peak memory 206584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472321412 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.472321412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.3956669838
Short name T107
Test name
Test status
Simulation time 301195586 ps
CPU time 8.23 seconds
Started Oct 12 12:37:56 AM UTC 24
Finished Oct 12 12:38:06 AM UTC 24
Peak memory 207744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956669838 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3956669838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.399655131
Short name T542
Test name
Test status
Simulation time 859095076 ps
CPU time 10.23 seconds
Started Oct 12 12:37:56 AM UTC 24
Finished Oct 12 12:38:08 AM UTC 24
Peak memory 207768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399655131 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.399655131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2842913874
Short name T103
Test name
Test status
Simulation time 94344121 ps
CPU time 1.2 seconds
Started Oct 12 12:37:56 AM UTC 24
Finished Oct 12 12:37:58 AM UTC 24
Peak memory 206744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842913874 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2842913874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1897272077
Short name T655
Test name
Test status
Simulation time 351331784693 ps
CPU time 857.62 seconds
Started Oct 12 12:37:56 AM UTC 24
Finished Oct 12 12:52:23 AM UTC 24
Peak memory 219920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1897272077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.1897272077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.1952564622
Short name T535
Test name
Test status
Simulation time 53535805 ps
CPU time 1 seconds
Started Oct 12 12:37:55 AM UTC 24
Finished Oct 12 12:37:57 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952564622 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1952564622
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1431365608
Short name T119
Test name
Test status
Simulation time 45041326 ps
CPU time 1.41 seconds
Started Oct 12 12:37:56 AM UTC 24
Finished Oct 12 12:37:59 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431365608 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.1431365608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.755412160
Short name T63
Test name
Test status
Simulation time 46603697 ps
CPU time 2.91 seconds
Started Oct 12 12:37:55 AM UTC 24
Finished Oct 12 12:37:59 AM UTC 24
Peak memory 207612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755412160 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.755412160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.234020293
Short name T57
Test name
Test status
Simulation time 95639192 ps
CPU time 2.6 seconds
Started Oct 12 12:37:55 AM UTC 24
Finished Oct 12 12:37:59 AM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234020293 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.234020293
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2001703814
Short name T582
Test name
Test status
Simulation time 98055972 ps
CPU time 4.17 seconds
Started Oct 12 12:38:22 AM UTC 24
Finished Oct 12 12:38:28 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2001703814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_
reset.2001703814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.3465069189
Short name T116
Test name
Test status
Simulation time 34609751 ps
CPU time 1.32 seconds
Started Oct 12 12:38:21 AM UTC 24
Finished Oct 12 12:38:24 AM UTC 24
Peak memory 207096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465069189 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3465069189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.2089248512
Short name T570
Test name
Test status
Simulation time 35577685 ps
CPU time 0.82 seconds
Started Oct 12 12:38:21 AM UTC 24
Finished Oct 12 12:38:23 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089248512 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2089248512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2840710518
Short name T573
Test name
Test status
Simulation time 83761478 ps
CPU time 1.84 seconds
Started Oct 12 12:38:21 AM UTC 24
Finished Oct 12 12:38:24 AM UTC 24
Peak memory 206652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840710518 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.2840710518
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.2917141874
Short name T577
Test name
Test status
Simulation time 878587213 ps
CPU time 3.62 seconds
Started Oct 12 12:38:21 AM UTC 24
Finished Oct 12 12:38:26 AM UTC 24
Peak memory 207756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917141874 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2917141874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.4070656815
Short name T143
Test name
Test status
Simulation time 107942988 ps
CPU time 1.98 seconds
Started Oct 12 12:38:21 AM UTC 24
Finished Oct 12 12:38:24 AM UTC 24
Peak memory 206464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070656815 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4070656815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3264847825
Short name T583
Test name
Test status
Simulation time 178704021 ps
CPU time 3.66 seconds
Started Oct 12 12:38:24 AM UTC 24
Finished Oct 12 12:38:28 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3264847825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.3264847825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.3807159649
Short name T575
Test name
Test status
Simulation time 98676138 ps
CPU time 1.16 seconds
Started Oct 12 12:38:23 AM UTC 24
Finished Oct 12 12:38:25 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807159649 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3807159649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.4235034026
Short name T574
Test name
Test status
Simulation time 44009010 ps
CPU time 0.85 seconds
Started Oct 12 12:38:23 AM UTC 24
Finished Oct 12 12:38:24 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235034026 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.4235034026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1336006439
Short name T579
Test name
Test status
Simulation time 118916372 ps
CPU time 2.03 seconds
Started Oct 12 12:38:24 AM UTC 24
Finished Oct 12 12:38:27 AM UTC 24
Peak memory 207592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336006439 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.1336006439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.1611981368
Short name T84
Test name
Test status
Simulation time 141956417 ps
CPU time 4.19 seconds
Started Oct 12 12:38:22 AM UTC 24
Finished Oct 12 12:38:28 AM UTC 24
Peak memory 207756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611981368 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1611981368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2746896978
Short name T584
Test name
Test status
Simulation time 64390710 ps
CPU time 2.38 seconds
Started Oct 12 12:38:25 AM UTC 24
Finished Oct 12 12:38:29 AM UTC 24
Peak memory 207916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2746896978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_
reset.2746896978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.4118734641
Short name T581
Test name
Test status
Simulation time 53084910 ps
CPU time 1.34 seconds
Started Oct 12 12:38:25 AM UTC 24
Finished Oct 12 12:38:27 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118734641 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4118734641
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.2121371876
Short name T578
Test name
Test status
Simulation time 14607888 ps
CPU time 0.86 seconds
Started Oct 12 12:38:24 AM UTC 24
Finished Oct 12 12:38:26 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121371876 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2121371876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2236278845
Short name T587
Test name
Test status
Simulation time 176203882 ps
CPU time 3.72 seconds
Started Oct 12 12:38:25 AM UTC 24
Finished Oct 12 12:38:30 AM UTC 24
Peak memory 207424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236278845 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.2236278845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.2846525090
Short name T580
Test name
Test status
Simulation time 83098132 ps
CPU time 3.66 seconds
Started Oct 12 12:38:24 AM UTC 24
Finished Oct 12 12:38:29 AM UTC 24
Peak memory 207548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846525090 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2846525090
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.2686740878
Short name T139
Test name
Test status
Simulation time 237872017 ps
CPU time 4.78 seconds
Started Oct 12 12:38:24 AM UTC 24
Finished Oct 12 12:38:30 AM UTC 24
Peak memory 207616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686740878 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2686740878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.427601218
Short name T592
Test name
Test status
Simulation time 96965748 ps
CPU time 3.63 seconds
Started Oct 12 12:38:28 AM UTC 24
Finished Oct 12 12:38:32 AM UTC 24
Peak memory 216048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=427601218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_r
eset.427601218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.1519723836
Short name T572
Test name
Test status
Simulation time 19317159 ps
CPU time 1.06 seconds
Started Oct 12 12:38:26 AM UTC 24
Finished Oct 12 12:38:28 AM UTC 24
Peak memory 206680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519723836 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1519723836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.1440069251
Short name T541
Test name
Test status
Simulation time 35093172 ps
CPU time 0.86 seconds
Started Oct 12 12:38:26 AM UTC 24
Finished Oct 12 12:38:28 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440069251 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1440069251
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4070414787
Short name T586
Test name
Test status
Simulation time 151053047 ps
CPU time 1.48 seconds
Started Oct 12 12:38:26 AM UTC 24
Finished Oct 12 12:38:29 AM UTC 24
Peak memory 206860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070414787 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.4070414787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.1415908331
Short name T585
Test name
Test status
Simulation time 267674266 ps
CPU time 2.55 seconds
Started Oct 12 12:38:25 AM UTC 24
Finished Oct 12 12:38:29 AM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415908331 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1415908331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1630912406
Short name T594
Test name
Test status
Simulation time 509813088 ps
CPU time 5.06 seconds
Started Oct 12 12:38:26 AM UTC 24
Finished Oct 12 12:38:32 AM UTC 24
Peak memory 207636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630912406 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1630912406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2921107710
Short name T598
Test name
Test status
Simulation time 37473384 ps
CPU time 3.29 seconds
Started Oct 12 12:38:30 AM UTC 24
Finished Oct 12 12:38:34 AM UTC 24
Peak memory 215884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2921107710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.2921107710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.3656724769
Short name T589
Test name
Test status
Simulation time 35281667 ps
CPU time 1.28 seconds
Started Oct 12 12:38:29 AM UTC 24
Finished Oct 12 12:38:31 AM UTC 24
Peak memory 206620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656724769 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3656724769
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.280368358
Short name T588
Test name
Test status
Simulation time 41955291 ps
CPU time 0.9 seconds
Started Oct 12 12:38:29 AM UTC 24
Finished Oct 12 12:38:31 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280368358 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.280368358
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2255569774
Short name T590
Test name
Test status
Simulation time 45244547 ps
CPU time 1.54 seconds
Started Oct 12 12:38:29 AM UTC 24
Finished Oct 12 12:38:31 AM UTC 24
Peak memory 206644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255569774 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.2255569774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.1445948136
Short name T597
Test name
Test status
Simulation time 810661986 ps
CPU time 4.81 seconds
Started Oct 12 12:38:28 AM UTC 24
Finished Oct 12 12:38:33 AM UTC 24
Peak memory 207476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445948136 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1445948136
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.3430231998
Short name T602
Test name
Test status
Simulation time 135772759 ps
CPU time 5.31 seconds
Started Oct 12 12:38:29 AM UTC 24
Finished Oct 12 12:38:35 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430231998 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3430231998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4007659425
Short name T601
Test name
Test status
Simulation time 273103421 ps
CPU time 2.51 seconds
Started Oct 12 12:38:31 AM UTC 24
Finished Oct 12 12:38:35 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4007659425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.4007659425
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.2594951913
Short name T593
Test name
Test status
Simulation time 19544485 ps
CPU time 1.25 seconds
Started Oct 12 12:38:30 AM UTC 24
Finished Oct 12 12:38:32 AM UTC 24
Peak memory 206620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594951913 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2594951913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.2385441045
Short name T591
Test name
Test status
Simulation time 40830645 ps
CPU time 0.72 seconds
Started Oct 12 12:38:30 AM UTC 24
Finished Oct 12 12:38:32 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385441045 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2385441045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2094468244
Short name T596
Test name
Test status
Simulation time 68206451 ps
CPU time 2.23 seconds
Started Oct 12 12:38:30 AM UTC 24
Finished Oct 12 12:38:33 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094468244 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.2094468244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.4131884777
Short name T603
Test name
Test status
Simulation time 75451151 ps
CPU time 4.36 seconds
Started Oct 12 12:38:30 AM UTC 24
Finished Oct 12 12:38:35 AM UTC 24
Peak memory 207544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131884777 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4131884777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.3660678782
Short name T141
Test name
Test status
Simulation time 124145175 ps
CPU time 4.01 seconds
Started Oct 12 12:38:30 AM UTC 24
Finished Oct 12 12:38:35 AM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660678782 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3660678782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.657043759
Short name T604
Test name
Test status
Simulation time 104456493 ps
CPU time 1.88 seconds
Started Oct 12 12:38:33 AM UTC 24
Finished Oct 12 12:38:35 AM UTC 24
Peak memory 206652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=657043759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_r
eset.657043759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.2128376601
Short name T600
Test name
Test status
Simulation time 234971661 ps
CPU time 1.23 seconds
Started Oct 12 12:38:33 AM UTC 24
Finished Oct 12 12:38:35 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128376601 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2128376601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.2086813878
Short name T595
Test name
Test status
Simulation time 18094401 ps
CPU time 0.88 seconds
Started Oct 12 12:38:31 AM UTC 24
Finished Oct 12 12:38:33 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086813878 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2086813878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3440514041
Short name T607
Test name
Test status
Simulation time 355234497 ps
CPU time 2.49 seconds
Started Oct 12 12:38:33 AM UTC 24
Finished Oct 12 12:38:36 AM UTC 24
Peak memory 207472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440514041 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.3440514041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.3281599039
Short name T599
Test name
Test status
Simulation time 69426437 ps
CPU time 1.94 seconds
Started Oct 12 12:38:31 AM UTC 24
Finished Oct 12 12:38:34 AM UTC 24
Peak memory 206480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281599039 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3281599039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.1958938330
Short name T144
Test name
Test status
Simulation time 81962972 ps
CPU time 2.95 seconds
Started Oct 12 12:38:31 AM UTC 24
Finished Oct 12 12:38:35 AM UTC 24
Peak memory 207572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958938330 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1958938330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3570779788
Short name T618
Test name
Test status
Simulation time 434840657 ps
CPU time 3.26 seconds
Started Oct 12 12:38:35 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 215744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3570779788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.3570779788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3226209154
Short name T606
Test name
Test status
Simulation time 59632213 ps
CPU time 1 seconds
Started Oct 12 12:38:34 AM UTC 24
Finished Oct 12 12:38:36 AM UTC 24
Peak memory 206568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226209154 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3226209154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3350768311
Short name T605
Test name
Test status
Simulation time 12003076 ps
CPU time 0.87 seconds
Started Oct 12 12:38:34 AM UTC 24
Finished Oct 12 12:38:36 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350768311 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3350768311
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3605973102
Short name T608
Test name
Test status
Simulation time 132072845 ps
CPU time 1.86 seconds
Started Oct 12 12:38:34 AM UTC 24
Finished Oct 12 12:38:37 AM UTC 24
Peak memory 206644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605973102 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.3605973102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.3861574642
Short name T616
Test name
Test status
Simulation time 157130369 ps
CPU time 4.16 seconds
Started Oct 12 12:38:34 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 207804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861574642 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3861574642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.4226591947
Short name T619
Test name
Test status
Simulation time 537425724 ps
CPU time 4.43 seconds
Started Oct 12 12:38:34 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 207708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226591947 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4226591947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2561409723
Short name T617
Test name
Test status
Simulation time 34339104 ps
CPU time 1.77 seconds
Started Oct 12 12:38:36 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 206692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2561409723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_
reset.2561409723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.2552871854
Short name T613
Test name
Test status
Simulation time 34876434 ps
CPU time 1.29 seconds
Started Oct 12 12:38:36 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 206628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552871854 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2552871854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3889921070
Short name T609
Test name
Test status
Simulation time 15637756 ps
CPU time 0.79 seconds
Started Oct 12 12:38:35 AM UTC 24
Finished Oct 12 12:38:37 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889921070 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3889921070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.307851242
Short name T614
Test name
Test status
Simulation time 48879054 ps
CPU time 1.25 seconds
Started Oct 12 12:38:36 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307851242 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.307851242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.3489237026
Short name T610
Test name
Test status
Simulation time 64983416 ps
CPU time 2.16 seconds
Started Oct 12 12:38:35 AM UTC 24
Finished Oct 12 12:38:38 AM UTC 24
Peak memory 207756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489237026 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3489237026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.3843284909
Short name T612
Test name
Test status
Simulation time 701099181 ps
CPU time 2.33 seconds
Started Oct 12 12:38:35 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843284909 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3843284909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.358715577
Short name T620
Test name
Test status
Simulation time 83858903 ps
CPU time 1.75 seconds
Started Oct 12 12:38:37 AM UTC 24
Finished Oct 12 12:38:40 AM UTC 24
Peak memory 206632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=358715577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_r
eset.358715577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.1057768692
Short name T615
Test name
Test status
Simulation time 45902350 ps
CPU time 1.02 seconds
Started Oct 12 12:38:37 AM UTC 24
Finished Oct 12 12:38:39 AM UTC 24
Peak memory 206560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057768692 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1057768692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.2850121425
Short name T611
Test name
Test status
Simulation time 32357301 ps
CPU time 0.77 seconds
Started Oct 12 12:38:37 AM UTC 24
Finished Oct 12 12:38:38 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850121425 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2850121425
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1079419015
Short name T622
Test name
Test status
Simulation time 79327776 ps
CPU time 1.93 seconds
Started Oct 12 12:38:37 AM UTC 24
Finished Oct 12 12:38:40 AM UTC 24
Peak memory 206584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079419015 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.1079419015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.3957802869
Short name T625
Test name
Test status
Simulation time 126484153 ps
CPU time 2.89 seconds
Started Oct 12 12:38:37 AM UTC 24
Finished Oct 12 12:38:40 AM UTC 24
Peak memory 207608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957802869 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3957802869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.1925925121
Short name T626
Test name
Test status
Simulation time 604109078 ps
CPU time 3.35 seconds
Started Oct 12 12:38:37 AM UTC 24
Finished Oct 12 12:38:41 AM UTC 24
Peak memory 207420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925925121 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1925925121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.203317244
Short name T108
Test name
Test status
Simulation time 308463439 ps
CPU time 6.98 seconds
Started Oct 12 12:38:00 AM UTC 24
Finished Oct 12 12:38:08 AM UTC 24
Peak memory 207764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203317244 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.203317244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.1056275928
Short name T111
Test name
Test status
Simulation time 289301206 ps
CPU time 11 seconds
Started Oct 12 12:38:00 AM UTC 24
Finished Oct 12 12:38:12 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056275928 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1056275928
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.3943129553
Short name T105
Test name
Test status
Simulation time 40240563 ps
CPU time 1.24 seconds
Started Oct 12 12:37:59 AM UTC 24
Finished Oct 12 12:38:01 AM UTC 24
Peak memory 207104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943129553 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3943129553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.280041499
Short name T538
Test name
Test status
Simulation time 69798457 ps
CPU time 1.89 seconds
Started Oct 12 12:38:00 AM UTC 24
Finished Oct 12 12:38:03 AM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=280041499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_re
set.280041499
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.1162791002
Short name T106
Test name
Test status
Simulation time 33161888 ps
CPU time 1.32 seconds
Started Oct 12 12:38:00 AM UTC 24
Finished Oct 12 12:38:02 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162791002 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1162791002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.827114119
Short name T536
Test name
Test status
Simulation time 13025356 ps
CPU time 0.86 seconds
Started Oct 12 12:37:58 AM UTC 24
Finished Oct 12 12:38:00 AM UTC 24
Peak memory 203096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827114119 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.827114119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1290107287
Short name T120
Test name
Test status
Simulation time 116774931 ps
CPU time 1.84 seconds
Started Oct 12 12:38:00 AM UTC 24
Finished Oct 12 12:38:03 AM UTC 24
Peak memory 206588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290107287 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.1290107287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1969255983
Short name T537
Test name
Test status
Simulation time 997616575 ps
CPU time 3.19 seconds
Started Oct 12 12:37:58 AM UTC 24
Finished Oct 12 12:38:02 AM UTC 24
Peak memory 207476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969255983 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1969255983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3811519488
Short name T58
Test name
Test status
Simulation time 322493191 ps
CPU time 2.76 seconds
Started Oct 12 12:37:58 AM UTC 24
Finished Oct 12 12:38:01 AM UTC 24
Peak memory 207764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811519488 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3811519488
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.3356335750
Short name T621
Test name
Test status
Simulation time 28437163 ps
CPU time 0.84 seconds
Started Oct 12 12:38:38 AM UTC 24
Finished Oct 12 12:38:40 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356335750 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3356335750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.934665267
Short name T623
Test name
Test status
Simulation time 12647508 ps
CPU time 0.88 seconds
Started Oct 12 12:38:38 AM UTC 24
Finished Oct 12 12:38:40 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934665267 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.934665267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.2766686672
Short name T624
Test name
Test status
Simulation time 11433714 ps
CPU time 0.93 seconds
Started Oct 12 12:38:38 AM UTC 24
Finished Oct 12 12:38:40 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766686672 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2766686672
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2432268655
Short name T630
Test name
Test status
Simulation time 17423177 ps
CPU time 0.88 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432268655 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2432268655
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.2442840940
Short name T629
Test name
Test status
Simulation time 14675691 ps
CPU time 0.92 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442840940 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2442840940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.3420852767
Short name T627
Test name
Test status
Simulation time 48676349 ps
CPU time 0.68 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420852767 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3420852767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.2207477107
Short name T628
Test name
Test status
Simulation time 23444603 ps
CPU time 0.78 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207477107 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2207477107
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.2047261422
Short name T631
Test name
Test status
Simulation time 38751465 ps
CPU time 0.85 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047261422 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2047261422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.3456922444
Short name T634
Test name
Test status
Simulation time 17602127 ps
CPU time 0.86 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456922444 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3456922444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.3851387429
Short name T632
Test name
Test status
Simulation time 71178066 ps
CPU time 0.8 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851387429 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3851387429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.1876353262
Short name T557
Test name
Test status
Simulation time 1143749799 ps
CPU time 9.94 seconds
Started Oct 12 12:38:07 AM UTC 24
Finished Oct 12 12:38:18 AM UTC 24
Peak memory 207444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876353262 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1876353262
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3685293127
Short name T576
Test name
Test status
Simulation time 324751445 ps
CPU time 18.34 seconds
Started Oct 12 12:38:06 AM UTC 24
Finished Oct 12 12:38:26 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685293127 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3685293127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.3254812638
Short name T544
Test name
Test status
Simulation time 13219857 ps
CPU time 1.04 seconds
Started Oct 12 12:38:06 AM UTC 24
Finished Oct 12 12:38:08 AM UTC 24
Peak memory 206900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254812638 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3254812638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1394611343
Short name T550
Test name
Test status
Simulation time 356860899 ps
CPU time 3.73 seconds
Started Oct 12 12:38:07 AM UTC 24
Finished Oct 12 12:38:12 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1394611343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.1394611343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3643562201
Short name T109
Test name
Test status
Simulation time 159891983 ps
CPU time 1.07 seconds
Started Oct 12 12:38:06 AM UTC 24
Finished Oct 12 12:38:08 AM UTC 24
Peak memory 206564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643562201 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3643562201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.4191103979
Short name T543
Test name
Test status
Simulation time 15246633 ps
CPU time 0.9 seconds
Started Oct 12 12:38:06 AM UTC 24
Finished Oct 12 12:38:08 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191103979 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4191103979
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4231257292
Short name T121
Test name
Test status
Simulation time 428423708 ps
CPU time 2.64 seconds
Started Oct 12 12:38:07 AM UTC 24
Finished Oct 12 12:38:11 AM UTC 24
Peak memory 207704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231257292 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.4231257292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.4120116332
Short name T540
Test name
Test status
Simulation time 53223562 ps
CPU time 3.66 seconds
Started Oct 12 12:38:00 AM UTC 24
Finished Oct 12 12:38:05 AM UTC 24
Peak memory 207804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120116332 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4120116332
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2464097950
Short name T635
Test name
Test status
Simulation time 155476652 ps
CPU time 0.82 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464097950 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2464097950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.1724819938
Short name T633
Test name
Test status
Simulation time 35595170 ps
CPU time 0.68 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724819938 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1724819938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1686449308
Short name T636
Test name
Test status
Simulation time 15386005 ps
CPU time 0.82 seconds
Started Oct 12 12:38:40 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686449308 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1686449308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.3815021739
Short name T637
Test name
Test status
Simulation time 14445258 ps
CPU time 0.78 seconds
Started Oct 12 12:38:41 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815021739 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3815021739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.453916590
Short name T638
Test name
Test status
Simulation time 37166898 ps
CPU time 0.84 seconds
Started Oct 12 12:38:41 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453916590 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.453916590
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.365455083
Short name T640
Test name
Test status
Simulation time 39731518 ps
CPU time 0.85 seconds
Started Oct 12 12:38:41 AM UTC 24
Finished Oct 12 12:38:43 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365455083 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.365455083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.1384842828
Short name T639
Test name
Test status
Simulation time 11927046 ps
CPU time 0.64 seconds
Started Oct 12 12:38:41 AM UTC 24
Finished Oct 12 12:38:42 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384842828 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1384842828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.2099376118
Short name T643
Test name
Test status
Simulation time 13082794 ps
CPU time 0.88 seconds
Started Oct 12 12:38:42 AM UTC 24
Finished Oct 12 12:38:44 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099376118 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2099376118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.1758210677
Short name T641
Test name
Test status
Simulation time 13892243 ps
CPU time 0.84 seconds
Started Oct 12 12:38:42 AM UTC 24
Finished Oct 12 12:38:44 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758210677 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1758210677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.360779722
Short name T644
Test name
Test status
Simulation time 20817253 ps
CPU time 0.86 seconds
Started Oct 12 12:38:42 AM UTC 24
Finished Oct 12 12:38:44 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360779722 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.360779722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.4290322217
Short name T565
Test name
Test status
Simulation time 305682121 ps
CPU time 11.49 seconds
Started Oct 12 12:38:09 AM UTC 24
Finished Oct 12 12:38:22 AM UTC 24
Peak memory 207540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290322217 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4290322217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.4282307818
Short name T117
Test name
Test status
Simulation time 312232101 ps
CPU time 16.81 seconds
Started Oct 12 12:38:09 AM UTC 24
Finished Oct 12 12:38:27 AM UTC 24
Peak memory 207448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282307818 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4282307818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.3349661208
Short name T546
Test name
Test status
Simulation time 19816988 ps
CPU time 1.04 seconds
Started Oct 12 12:38:08 AM UTC 24
Finished Oct 12 12:38:10 AM UTC 24
Peak memory 206424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349661208 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3349661208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2564433557
Short name T549
Test name
Test status
Simulation time 34941313 ps
CPU time 2.25 seconds
Started Oct 12 12:38:09 AM UTC 24
Finished Oct 12 12:38:12 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2564433557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.2564433557
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.866235617
Short name T110
Test name
Test status
Simulation time 20794287 ps
CPU time 1.01 seconds
Started Oct 12 12:38:09 AM UTC 24
Finished Oct 12 12:38:11 AM UTC 24
Peak memory 207160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866235617 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.866235617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.2534489175
Short name T545
Test name
Test status
Simulation time 55169196 ps
CPU time 0.82 seconds
Started Oct 12 12:38:08 AM UTC 24
Finished Oct 12 12:38:09 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534489175 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2534489175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2419891476
Short name T122
Test name
Test status
Simulation time 73250893 ps
CPU time 3.29 seconds
Started Oct 12 12:38:09 AM UTC 24
Finished Oct 12 12:38:13 AM UTC 24
Peak memory 207520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419891476 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.2419891476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.1692479372
Short name T547
Test name
Test status
Simulation time 241983512 ps
CPU time 2.24 seconds
Started Oct 12 12:38:07 AM UTC 24
Finished Oct 12 12:38:11 AM UTC 24
Peak memory 207528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692479372 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1692479372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.1952179543
Short name T136
Test name
Test status
Simulation time 196850353 ps
CPU time 2.88 seconds
Started Oct 12 12:38:07 AM UTC 24
Finished Oct 12 12:38:11 AM UTC 24
Peak memory 207500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952179543 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1952179543
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3422681357
Short name T642
Test name
Test status
Simulation time 50437948 ps
CPU time 0.77 seconds
Started Oct 12 12:38:42 AM UTC 24
Finished Oct 12 12:38:44 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422681357 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3422681357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2187596947
Short name T645
Test name
Test status
Simulation time 26146519 ps
CPU time 0.72 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187596947 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2187596947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.884887948
Short name T646
Test name
Test status
Simulation time 14927160 ps
CPU time 0.79 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884887948 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.884887948
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.3693244002
Short name T648
Test name
Test status
Simulation time 76877366 ps
CPU time 0.75 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693244002 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3693244002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.2543843720
Short name T647
Test name
Test status
Simulation time 17254431 ps
CPU time 0.8 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543843720 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2543843720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.2667387074
Short name T650
Test name
Test status
Simulation time 36330216 ps
CPU time 0.86 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667387074 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2667387074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.525609856
Short name T649
Test name
Test status
Simulation time 12877594 ps
CPU time 0.81 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525609856 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.525609856
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1179238883
Short name T652
Test name
Test status
Simulation time 31473064 ps
CPU time 0.81 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179238883 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1179238883
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.2778286876
Short name T651
Test name
Test status
Simulation time 33862386 ps
CPU time 0.83 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778286876 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2778286876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.1205715079
Short name T653
Test name
Test status
Simulation time 122037588 ps
CPU time 0.94 seconds
Started Oct 12 12:38:43 AM UTC 24
Finished Oct 12 12:38:45 AM UTC 24
Peak memory 203088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205715079 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1205715079
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4238904770
Short name T556
Test name
Test status
Simulation time 647878753 ps
CPU time 3.63 seconds
Started Oct 12 12:38:12 AM UTC 24
Finished Oct 12 12:38:17 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4238904770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.4238904770
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.322803750
Short name T115
Test name
Test status
Simulation time 36044335 ps
CPU time 1.29 seconds
Started Oct 12 12:38:11 AM UTC 24
Finished Oct 12 12:38:14 AM UTC 24
Peak memory 206632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322803750 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.322803750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.1869129249
Short name T548
Test name
Test status
Simulation time 36076184 ps
CPU time 0.82 seconds
Started Oct 12 12:38:10 AM UTC 24
Finished Oct 12 12:38:12 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869129249 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1869129249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3127408960
Short name T123
Test name
Test status
Simulation time 132404358 ps
CPU time 2.43 seconds
Started Oct 12 12:38:11 AM UTC 24
Finished Oct 12 12:38:15 AM UTC 24
Peak memory 207448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127408960 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.3127408960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3918549771
Short name T552
Test name
Test status
Simulation time 1075429839 ps
CPU time 4.74 seconds
Started Oct 12 12:38:09 AM UTC 24
Finished Oct 12 12:38:15 AM UTC 24
Peak memory 207544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918549771 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3918549771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.3608190237
Short name T140
Test name
Test status
Simulation time 161486141 ps
CPU time 2.29 seconds
Started Oct 12 12:38:10 AM UTC 24
Finished Oct 12 12:38:13 AM UTC 24
Peak memory 207496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608190237 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3608190237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.51753666
Short name T654
Test name
Test status
Simulation time 51787643222 ps
CPU time 360.78 seconds
Started Oct 12 12:38:14 AM UTC 24
Finished Oct 12 12:44:19 AM UTC 24
Peak memory 215864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=51753666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.51753666
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.1426990602
Short name T112
Test name
Test status
Simulation time 14137644 ps
CPU time 1.19 seconds
Started Oct 12 12:38:14 AM UTC 24
Finished Oct 12 12:38:16 AM UTC 24
Peak memory 206572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426990602 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1426990602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.2737915064
Short name T551
Test name
Test status
Simulation time 48143040 ps
CPU time 0.89 seconds
Started Oct 12 12:38:13 AM UTC 24
Finished Oct 12 12:38:14 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737915064 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2737915064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3075158569
Short name T124
Test name
Test status
Simulation time 24253397 ps
CPU time 1.69 seconds
Started Oct 12 12:38:14 AM UTC 24
Finished Oct 12 12:38:16 AM UTC 24
Peak memory 206620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075158569 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.3075158569
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.3688002910
Short name T554
Test name
Test status
Simulation time 49101471 ps
CPU time 3.03 seconds
Started Oct 12 12:38:12 AM UTC 24
Finished Oct 12 12:38:17 AM UTC 24
Peak memory 207472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688002910 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3688002910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.48328137
Short name T142
Test name
Test status
Simulation time 637025149 ps
CPU time 2.64 seconds
Started Oct 12 12:38:12 AM UTC 24
Finished Oct 12 12:38:16 AM UTC 24
Peak memory 207768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48328137 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.48328137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.546969018
Short name T564
Test name
Test status
Simulation time 216623636 ps
CPU time 4.15 seconds
Started Oct 12 12:38:16 AM UTC 24
Finished Oct 12 12:38:21 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=546969018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_re
set.546969018
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2647728506
Short name T113
Test name
Test status
Simulation time 32462100 ps
CPU time 1.04 seconds
Started Oct 12 12:38:15 AM UTC 24
Finished Oct 12 12:38:17 AM UTC 24
Peak memory 205772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647728506 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2647728506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.1781170704
Short name T555
Test name
Test status
Simulation time 38781227 ps
CPU time 0.85 seconds
Started Oct 12 12:38:15 AM UTC 24
Finished Oct 12 12:38:17 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781170704 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1781170704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3932988579
Short name T560
Test name
Test status
Simulation time 484679335 ps
CPU time 2.66 seconds
Started Oct 12 12:38:16 AM UTC 24
Finished Oct 12 12:38:20 AM UTC 24
Peak memory 207568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932988579 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.3932988579
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.3200978699
Short name T558
Test name
Test status
Simulation time 197311824 ps
CPU time 4.27 seconds
Started Oct 12 12:38:14 AM UTC 24
Finished Oct 12 12:38:19 AM UTC 24
Peak memory 207436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200978699 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3200978699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.91252791
Short name T59
Test name
Test status
Simulation time 986810920 ps
CPU time 2.33 seconds
Started Oct 12 12:38:15 AM UTC 24
Finished Oct 12 12:38:18 AM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91252791 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.91252791
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3123250094
Short name T566
Test name
Test status
Simulation time 90987383 ps
CPU time 3.19 seconds
Started Oct 12 12:38:18 AM UTC 24
Finished Oct 12 12:38:22 AM UTC 24
Peak memory 216128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3123250094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.3123250094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.562847095
Short name T114
Test name
Test status
Simulation time 36258836 ps
CPU time 1.37 seconds
Started Oct 12 12:38:17 AM UTC 24
Finished Oct 12 12:38:20 AM UTC 24
Peak memory 206804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562847095 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.562847095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1784198631
Short name T559
Test name
Test status
Simulation time 15015079 ps
CPU time 0.86 seconds
Started Oct 12 12:38:17 AM UTC 24
Finished Oct 12 12:38:19 AM UTC 24
Peak memory 203092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784198631 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1784198631
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.642608458
Short name T563
Test name
Test status
Simulation time 309411664 ps
CPU time 2.25 seconds
Started Oct 12 12:38:18 AM UTC 24
Finished Oct 12 12:38:21 AM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642608458 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.642608458
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.3024950044
Short name T568
Test name
Test status
Simulation time 76086487 ps
CPU time 5.2 seconds
Started Oct 12 12:38:16 AM UTC 24
Finished Oct 12 12:38:22 AM UTC 24
Peak memory 207740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024950044 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3024950044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.706485994
Short name T137
Test name
Test status
Simulation time 591052790 ps
CPU time 3.83 seconds
Started Oct 12 12:38:16 AM UTC 24
Finished Oct 12 12:38:21 AM UTC 24
Peak memory 207492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706485994 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.706485994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.381311556
Short name T569
Test name
Test status
Simulation time 394376818 ps
CPU time 1.66 seconds
Started Oct 12 12:38:20 AM UTC 24
Finished Oct 12 12:38:23 AM UTC 24
Peak memory 206628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=381311556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_re
set.381311556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.2504095362
Short name T562
Test name
Test status
Simulation time 20445064 ps
CPU time 0.84 seconds
Started Oct 12 12:38:19 AM UTC 24
Finished Oct 12 12:38:21 AM UTC 24
Peak memory 205772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504095362 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2504095362
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.1195830412
Short name T561
Test name
Test status
Simulation time 35441091 ps
CPU time 0.85 seconds
Started Oct 12 12:38:19 AM UTC 24
Finished Oct 12 12:38:21 AM UTC 24
Peak memory 203008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195830412 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1195830412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1005318779
Short name T571
Test name
Test status
Simulation time 59134868 ps
CPU time 2.3 seconds
Started Oct 12 12:38:20 AM UTC 24
Finished Oct 12 12:38:23 AM UTC 24
Peak memory 207476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005318779 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.1005318779
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.4051053153
Short name T567
Test name
Test status
Simulation time 162900288 ps
CPU time 3.31 seconds
Started Oct 12 12:38:18 AM UTC 24
Finished Oct 12 12:38:22 AM UTC 24
Peak memory 207476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051053153 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4051053153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.3762526925
Short name T285
Test name
Test status
Simulation time 16450103156 ps
CPU time 715.12 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:17:20 AM UTC 24
Peak memory 678444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762526925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3762526925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_error.2023187468
Short name T45
Test name
Test status
Simulation time 5460023337 ps
CPU time 62.02 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:06:21 AM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023187468 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2023187468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_stress_all.775593391
Short name T74
Test name
Test status
Simulation time 285546290216 ps
CPU time 1988.71 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:38:49 AM UTC 24
Peak memory 707052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775593391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.775593391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.2774151075
Short name T43
Test name
Test status
Simulation time 4448602094 ps
CPU time 70.25 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:06:29 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774151075 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2774151075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.881626064
Short name T44
Test name
Test status
Simulation time 5927889064 ps
CPU time 106.97 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:07:07 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881626064 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.881626064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.3765579630
Short name T179
Test name
Test status
Simulation time 31771190667 ps
CPU time 112.55 seconds
Started Oct 12 12:05:18 AM UTC 24
Finished Oct 12 12:07:12 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765579630 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3765579630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.2169502548
Short name T504
Test name
Test status
Simulation time 168184970378 ps
CPU time 2274.55 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:43:37 AM UTC 24
Peak memory 223664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169502548 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2169502548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.3249045956
Short name T506
Test name
Test status
Simulation time 168745326596 ps
CPU time 2351.85 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:44:55 AM UTC 24
Peak memory 223588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249045956 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3249045956
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.3702325012
Short name T9
Test name
Test status
Simulation time 2584171071 ps
CPU time 29.13 seconds
Started Oct 12 12:05:17 AM UTC 24
Finished Oct 12 12:05:48 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702325012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3702325012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_alert_test.766193550
Short name T25
Test name
Test status
Simulation time 14958538 ps
CPU time 0.88 seconds
Started Oct 12 12:05:23 AM UTC 24
Finished Oct 12 12:05:25 AM UTC 24
Peak memory 206136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766193550 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.766193550
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.196425252
Short name T49
Test name
Test status
Simulation time 858405996 ps
CPU time 45.4 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:06:06 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196425252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.196425252
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.3621636909
Short name T291
Test name
Test status
Simulation time 59012904746 ps
CPU time 721.97 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:17:29 AM UTC 24
Peak memory 619044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621636909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3621636909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_error.2216341285
Short name T42
Test name
Test status
Simulation time 907555126 ps
CPU time 59.54 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:06:20 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216341285 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2216341285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_long_msg.3868053580
Short name T15
Test name
Test status
Simulation time 4006978440 ps
CPU time 59.99 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:06:20 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868053580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3868053580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.3430182593
Short name T24
Test name
Test status
Simulation time 150169467 ps
CPU time 1.62 seconds
Started Oct 12 12:05:21 AM UTC 24
Finished Oct 12 12:05:24 AM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430182593 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3430182593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_smoke.2665233094
Short name T5
Test name
Test status
Simulation time 228216921 ps
CPU time 4.73 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:05:25 AM UTC 24
Peak memory 209432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665233094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2665233094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_stress_all.581858368
Short name T71
Test name
Test status
Simulation time 163957151192 ps
CPU time 1714.26 seconds
Started Oct 12 12:05:21 AM UTC 24
Finished Oct 12 12:34:13 AM UTC 24
Peak memory 729620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581858368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.581858368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.2943902387
Short name T126
Test name
Test status
Simulation time 2152746476 ps
CPU time 45.6 seconds
Started Oct 12 12:05:21 AM UTC 24
Finished Oct 12 12:06:08 AM UTC 24
Peak memory 209788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943902387 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.2943902387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.1606030309
Short name T50
Test name
Test status
Simulation time 4508552974 ps
CPU time 79.15 seconds
Started Oct 12 12:05:21 AM UTC 24
Finished Oct 12 12:06:42 AM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606030309 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1606030309
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.2920989044
Short name T185
Test name
Test status
Simulation time 95525644829 ps
CPU time 126.58 seconds
Started Oct 12 12:05:21 AM UTC 24
Finished Oct 12 12:07:30 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920989044 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2920989044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.1362562209
Short name T150
Test name
Test status
Simulation time 298676588958 ps
CPU time 612.2 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:15:39 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362562209 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1362562209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.1999581549
Short name T510
Test name
Test status
Simulation time 813216193161 ps
CPU time 2499.89 seconds
Started Oct 12 12:05:21 AM UTC 24
Finished Oct 12 12:47:29 AM UTC 24
Peak memory 229936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999581549 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1999581549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.197390214
Short name T522
Test name
Test status
Simulation time 220181084641 ps
CPU time 2953.91 seconds
Started Oct 12 12:05:21 AM UTC 24
Finished Oct 12 12:55:07 AM UTC 24
Peak memory 229684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197390214 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.197390214
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.1888851276
Short name T12
Test name
Test status
Simulation time 3308693579 ps
CPU time 34.2 seconds
Started Oct 12 12:05:19 AM UTC 24
Finished Oct 12 12:05:55 AM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888851276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1888851276
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_alert_test.3498936222
Short name T90
Test name
Test status
Simulation time 11780411 ps
CPU time 0.87 seconds
Started Oct 12 12:08:52 AM UTC 24
Finished Oct 12 12:08:54 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498936222 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3498936222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.2409577361
Short name T16
Test name
Test status
Simulation time 371592343 ps
CPU time 23.63 seconds
Started Oct 12 12:08:41 AM UTC 24
Finished Oct 12 12:09:06 AM UTC 24
Peak memory 209896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409577361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2409577361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.3176989420
Short name T433
Test name
Test status
Simulation time 12352617462 ps
CPU time 1239.53 seconds
Started Oct 12 12:08:45 AM UTC 24
Finished Oct 12 12:29:37 AM UTC 24
Peak memory 746032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176989420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3176989420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_error.2398356006
Short name T79
Test name
Test status
Simulation time 2749137414 ps
CPU time 51.12 seconds
Started Oct 12 12:08:45 AM UTC 24
Finished Oct 12 12:09:38 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398356006 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2398356006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_long_msg.2842072727
Short name T4
Test name
Test status
Simulation time 2618371340 ps
CPU time 22.19 seconds
Started Oct 12 12:08:40 AM UTC 24
Finished Oct 12 12:09:03 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842072727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2842072727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_smoke.3612232383
Short name T86
Test name
Test status
Simulation time 779714033 ps
CPU time 12.75 seconds
Started Oct 12 12:08:33 AM UTC 24
Finished Oct 12 12:08:46 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612232383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3612232383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.645504475
Short name T129
Test name
Test status
Simulation time 10857580858 ps
CPU time 95.7 seconds
Started Oct 12 12:08:47 AM UTC 24
Finished Oct 12 12:10:25 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645504475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.645504475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_alert_test.2521150333
Short name T93
Test name
Test status
Simulation time 14267794 ps
CPU time 0.92 seconds
Started Oct 12 12:09:05 AM UTC 24
Finished Oct 12 12:09:07 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521150333 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2521150333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.3857721628
Short name T92
Test name
Test status
Simulation time 387614808 ps
CPU time 7.24 seconds
Started Oct 12 12:08:56 AM UTC 24
Finished Oct 12 12:09:04 AM UTC 24
Peak memory 209892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857721628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3857721628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.2554117279
Short name T165
Test name
Test status
Simulation time 1655769521 ps
CPU time 14.51 seconds
Started Oct 12 12:08:59 AM UTC 24
Finished Oct 12 12:09:15 AM UTC 24
Peak memory 209896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554117279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2554117279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.2206946656
Short name T208
Test name
Test status
Simulation time 3691070187 ps
CPU time 62.49 seconds
Started Oct 12 12:08:56 AM UTC 24
Finished Oct 12 12:10:00 AM UTC 24
Peak memory 358320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206946656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2206946656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_error.2779667807
Short name T214
Test name
Test status
Simulation time 11289157438 ps
CPU time 81.37 seconds
Started Oct 12 12:09:04 AM UTC 24
Finished Oct 12 12:10:27 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779667807 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2779667807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_long_msg.1723696807
Short name T212
Test name
Test status
Simulation time 3421653936 ps
CPU time 69 seconds
Started Oct 12 12:08:56 AM UTC 24
Finished Oct 12 12:10:06 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723696807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1723696807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_stress_all.2653268392
Short name T344
Test name
Test status
Simulation time 43138781489 ps
CPU time 793.69 seconds
Started Oct 12 12:09:04 AM UTC 24
Finished Oct 12 12:22:26 AM UTC 24
Peak memory 469564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653268392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2653268392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.20170384
Short name T130
Test name
Test status
Simulation time 7668793093 ps
CPU time 100.41 seconds
Started Oct 12 12:09:04 AM UTC 24
Finished Oct 12 12:10:46 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20170384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.20170384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_alert_test.812991756
Short name T207
Test name
Test status
Simulation time 16649079 ps
CPU time 0.85 seconds
Started Oct 12 12:09:20 AM UTC 24
Finished Oct 12 12:09:22 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812991756 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.812991756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.977172335
Short name T75
Test name
Test status
Simulation time 734328633 ps
CPU time 16.66 seconds
Started Oct 12 12:09:09 AM UTC 24
Finished Oct 12 12:09:27 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977172335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.977172335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.1632270107
Short name T177
Test name
Test status
Simulation time 586789577 ps
CPU time 10.3 seconds
Started Oct 12 12:09:11 AM UTC 24
Finished Oct 12 12:09:22 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632270107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1632270107
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.3806158821
Short name T266
Test name
Test status
Simulation time 9321698773 ps
CPU time 390.21 seconds
Started Oct 12 12:09:11 AM UTC 24
Finished Oct 12 12:15:46 AM UTC 24
Peak memory 508440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806158821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3806158821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_error.3582086812
Short name T233
Test name
Test status
Simulation time 2761386373 ps
CPU time 166.08 seconds
Started Oct 12 12:09:15 AM UTC 24
Finished Oct 12 12:12:04 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582086812 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3582086812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_long_msg.381941516
Short name T82
Test name
Test status
Simulation time 469013506 ps
CPU time 32.89 seconds
Started Oct 12 12:09:07 AM UTC 24
Finished Oct 12 12:09:42 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381941516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.381941516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_smoke.1783712561
Short name T206
Test name
Test status
Simulation time 31253010 ps
CPU time 1.49 seconds
Started Oct 12 12:09:07 AM UTC 24
Finished Oct 12 12:09:10 AM UTC 24
Peak memory 208496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783712561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1783712561
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/12.hmac_stress_all.3134978804
Short name T96
Test name
Test status
Simulation time 18744309498 ps
CPU time 432.8 seconds
Started Oct 12 12:09:15 AM UTC 24
Finished Oct 12 12:16:34 AM UTC 24
Peak memory 222692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134978804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3134978804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_alert_test.188067736
Short name T83
Test name
Test status
Simulation time 42259479 ps
CPU time 0.91 seconds
Started Oct 12 12:09:41 AM UTC 24
Finished Oct 12 12:09:43 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188067736 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.188067736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.1174763647
Short name T213
Test name
Test status
Simulation time 13913859946 ps
CPU time 50.56 seconds
Started Oct 12 12:09:25 AM UTC 24
Finished Oct 12 12:10:17 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174763647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1174763647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.3547957345
Short name T81
Test name
Test status
Simulation time 1630711405 ps
CPU time 9.29 seconds
Started Oct 12 12:09:29 AM UTC 24
Finished Oct 12 12:09:40 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547957345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3547957345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.1258633009
Short name T334
Test name
Test status
Simulation time 4170987177 ps
CPU time 725.98 seconds
Started Oct 12 12:09:28 AM UTC 24
Finished Oct 12 12:21:42 AM UTC 24
Peak memory 703220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258633009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1258633009
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_error.1856126378
Short name T229
Test name
Test status
Simulation time 35964104330 ps
CPU time 119.66 seconds
Started Oct 12 12:09:29 AM UTC 24
Finished Oct 12 12:11:32 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856126378 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1856126378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_long_msg.734398171
Short name T158
Test name
Test status
Simulation time 9560010628 ps
CPU time 143.56 seconds
Started Oct 12 12:09:23 AM UTC 24
Finished Oct 12 12:11:50 AM UTC 24
Peak memory 218408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734398171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.734398171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_smoke.3695653614
Short name T77
Test name
Test status
Simulation time 75250697 ps
CPU time 4.37 seconds
Started Oct 12 12:09:23 AM UTC 24
Finished Oct 12 12:09:29 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695653614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3695653614
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_stress_all.1445176065
Short name T23
Test name
Test status
Simulation time 42501534851 ps
CPU time 1652.33 seconds
Started Oct 12 12:09:39 AM UTC 24
Finished Oct 12 12:37:29 AM UTC 24
Peak memory 686708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445176065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1445176065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.3022479606
Short name T232
Test name
Test status
Simulation time 30006152643 ps
CPU time 140.17 seconds
Started Oct 12 12:09:34 AM UTC 24
Finished Oct 12 12:11:58 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022479606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3022479606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_alert_test.619044721
Short name T211
Test name
Test status
Simulation time 45720044 ps
CPU time 0.9 seconds
Started Oct 12 12:10:04 AM UTC 24
Finished Oct 12 12:10:06 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619044721 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.619044721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1684374615
Short name T210
Test name
Test status
Simulation time 381086436 ps
CPU time 18.15 seconds
Started Oct 12 12:09:43 AM UTC 24
Finished Oct 12 12:10:03 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684374615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1684374615
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.1870789929
Short name T166
Test name
Test status
Simulation time 281923386 ps
CPU time 4.82 seconds
Started Oct 12 12:09:51 AM UTC 24
Finished Oct 12 12:09:58 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870789929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1870789929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.1139625576
Short name T286
Test name
Test status
Simulation time 11018092912 ps
CPU time 450.38 seconds
Started Oct 12 12:09:44 AM UTC 24
Finished Oct 12 12:17:20 AM UTC 24
Peak memory 733936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139625576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1139625576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_error.3052435013
Short name T221
Test name
Test status
Simulation time 619392526 ps
CPU time 43.44 seconds
Started Oct 12 12:09:58 AM UTC 24
Finished Oct 12 12:10:43 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052435013 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3052435013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_long_msg.2843741659
Short name T216
Test name
Test status
Simulation time 1219118140 ps
CPU time 44.64 seconds
Started Oct 12 12:09:43 AM UTC 24
Finished Oct 12 12:10:29 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843741659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2843741659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_smoke.932842341
Short name T209
Test name
Test status
Simulation time 1578433673 ps
CPU time 18.08 seconds
Started Oct 12 12:09:41 AM UTC 24
Finished Oct 12 12:10:00 AM UTC 24
Peak memory 209852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932842341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.932842341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.2217132914
Short name T131
Test name
Test status
Simulation time 5514297119 ps
CPU time 92.85 seconds
Started Oct 12 12:10:01 AM UTC 24
Finished Oct 12 12:11:36 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217132914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2217132914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_alert_test.568292680
Short name T218
Test name
Test status
Simulation time 131656034 ps
CPU time 0.83 seconds
Started Oct 12 12:10:31 AM UTC 24
Finished Oct 12 12:10:33 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568292680 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.568292680
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.2343964879
Short name T222
Test name
Test status
Simulation time 372643030 ps
CPU time 25.09 seconds
Started Oct 12 12:10:18 AM UTC 24
Finished Oct 12 12:10:45 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343964879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2343964879
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.2796259911
Short name T219
Test name
Test status
Simulation time 1209577714 ps
CPU time 12.79 seconds
Started Oct 12 12:10:23 AM UTC 24
Finished Oct 12 12:10:37 AM UTC 24
Peak memory 209668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796259911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2796259911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.2275914807
Short name T270
Test name
Test status
Simulation time 6406578927 ps
CPU time 358.12 seconds
Started Oct 12 12:10:18 AM UTC 24
Finished Oct 12 12:16:22 AM UTC 24
Peak memory 703020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275914807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2275914807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_error.1959787279
Short name T248
Test name
Test status
Simulation time 31243666790 ps
CPU time 170.72 seconds
Started Oct 12 12:10:26 AM UTC 24
Finished Oct 12 12:13:20 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959787279 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1959787279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_long_msg.2209984872
Short name T215
Test name
Test status
Simulation time 592722337 ps
CPU time 20.61 seconds
Started Oct 12 12:10:07 AM UTC 24
Finished Oct 12 12:10:29 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209984872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2209984872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_smoke.1868480473
Short name T153
Test name
Test status
Simulation time 1570125161 ps
CPU time 14.18 seconds
Started Oct 12 12:10:07 AM UTC 24
Finished Oct 12 12:10:23 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868480473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1868480473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_stress_all.1739297744
Short name T426
Test name
Test status
Simulation time 109776430654 ps
CPU time 1097 seconds
Started Oct 12 12:10:31 AM UTC 24
Finished Oct 12 12:29:00 AM UTC 24
Peak memory 672300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739297744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1739297744
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.3111199691
Short name T132
Test name
Test status
Simulation time 1092717198 ps
CPU time 74.36 seconds
Started Oct 12 12:10:28 AM UTC 24
Finished Oct 12 12:11:45 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111199691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3111199691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_alert_test.565020905
Short name T224
Test name
Test status
Simulation time 29932805 ps
CPU time 0.9 seconds
Started Oct 12 12:10:56 AM UTC 24
Finished Oct 12 12:10:58 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565020905 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.565020905
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.433681181
Short name T230
Test name
Test status
Simulation time 3171032058 ps
CPU time 59.09 seconds
Started Oct 12 12:10:38 AM UTC 24
Finished Oct 12 12:11:39 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433681181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.433681181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.3726151401
Short name T41
Test name
Test status
Simulation time 1383338359 ps
CPU time 69.07 seconds
Started Oct 12 12:10:44 AM UTC 24
Finished Oct 12 12:11:55 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726151401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3726151401
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.2785008430
Short name T257
Test name
Test status
Simulation time 5249192860 ps
CPU time 224.23 seconds
Started Oct 12 12:10:43 AM UTC 24
Finished Oct 12 12:14:31 AM UTC 24
Peak memory 631516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785008430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2785008430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_error.2535464122
Short name T255
Test name
Test status
Simulation time 2856387812 ps
CPU time 178.48 seconds
Started Oct 12 12:10:46 AM UTC 24
Finished Oct 12 12:13:47 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535464122 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2535464122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_long_msg.3041649268
Short name T225
Test name
Test status
Simulation time 2123295485 ps
CPU time 29.41 seconds
Started Oct 12 12:10:34 AM UTC 24
Finished Oct 12 12:11:05 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041649268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3041649268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_smoke.3150086398
Short name T220
Test name
Test status
Simulation time 212646041 ps
CPU time 7.1 seconds
Started Oct 12 12:10:34 AM UTC 24
Finished Oct 12 12:10:42 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150086398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3150086398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_stress_all.2839191837
Short name T513
Test name
Test status
Simulation time 17494593684 ps
CPU time 2258.77 seconds
Started Oct 12 12:10:56 AM UTC 24
Finished Oct 12 12:48:58 AM UTC 24
Peak memory 786988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839191837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2839191837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.2220892051
Short name T228
Test name
Test status
Simulation time 3984583920 ps
CPU time 37.04 seconds
Started Oct 12 12:10:47 AM UTC 24
Finished Oct 12 12:11:26 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220892051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2220892051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_alert_test.574042529
Short name T231
Test name
Test status
Simulation time 12535659 ps
CPU time 0.81 seconds
Started Oct 12 12:11:47 AM UTC 24
Finished Oct 12 12:11:49 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574042529 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.574042529
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.3155580295
Short name T240
Test name
Test status
Simulation time 1461105044 ps
CPU time 90.17 seconds
Started Oct 12 12:11:12 AM UTC 24
Finished Oct 12 12:12:44 AM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155580295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3155580295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.4271065049
Short name T164
Test name
Test status
Simulation time 4896771695 ps
CPU time 126.74 seconds
Started Oct 12 12:11:27 AM UTC 24
Finished Oct 12 12:13:36 AM UTC 24
Peak memory 209780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271065049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4271065049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.3240975474
Short name T298
Test name
Test status
Simulation time 2059446700 ps
CPU time 383.96 seconds
Started Oct 12 12:11:26 AM UTC 24
Finished Oct 12 12:17:55 AM UTC 24
Peak memory 723500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240975474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3240975474
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_error.2203519771
Short name T237
Test name
Test status
Simulation time 4418305065 ps
CPU time 61.5 seconds
Started Oct 12 12:11:33 AM UTC 24
Finished Oct 12 12:12:36 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203519771 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2203519771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_long_msg.2151505721
Short name T241
Test name
Test status
Simulation time 27578386896 ps
CPU time 96.69 seconds
Started Oct 12 12:11:06 AM UTC 24
Finished Oct 12 12:12:44 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151505721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2151505721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_smoke.3000936842
Short name T227
Test name
Test status
Simulation time 1076063973 ps
CPU time 24.34 seconds
Started Oct 12 12:10:59 AM UTC 24
Finished Oct 12 12:11:25 AM UTC 24
Peak memory 209648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000936842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3000936842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_stress_all.3914338115
Short name T238
Test name
Test status
Simulation time 2873736184 ps
CPU time 55.33 seconds
Started Oct 12 12:11:42 AM UTC 24
Finished Oct 12 12:12:39 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914338115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3914338115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.3948195350
Short name T243
Test name
Test status
Simulation time 11429190046 ps
CPU time 67.08 seconds
Started Oct 12 12:11:39 AM UTC 24
Finished Oct 12 12:12:48 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948195350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3948195350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_alert_test.2824304632
Short name T236
Test name
Test status
Simulation time 39091213 ps
CPU time 0.82 seconds
Started Oct 12 12:12:34 AM UTC 24
Finished Oct 12 12:12:36 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824304632 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2824304632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.2475241607
Short name T249
Test name
Test status
Simulation time 2989400764 ps
CPU time 95.06 seconds
Started Oct 12 12:11:52 AM UTC 24
Finished Oct 12 12:13:29 AM UTC 24
Peak memory 226124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475241607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2475241607
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.2919758074
Short name T235
Test name
Test status
Simulation time 18863798469 ps
CPU time 31.05 seconds
Started Oct 12 12:12:01 AM UTC 24
Finished Oct 12 12:12:33 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919758074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2919758074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.3010690410
Short name T489
Test name
Test status
Simulation time 7431669885 ps
CPU time 1473.33 seconds
Started Oct 12 12:11:56 AM UTC 24
Finished Oct 12 12:36:44 AM UTC 24
Peak memory 709072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010690410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3010690410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_error.4118460577
Short name T234
Test name
Test status
Simulation time 3572104431 ps
CPU time 17.99 seconds
Started Oct 12 12:12:06 AM UTC 24
Finished Oct 12 12:12:25 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118460577 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4118460577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_long_msg.772185862
Short name T258
Test name
Test status
Simulation time 12798028953 ps
CPU time 158.72 seconds
Started Oct 12 12:11:52 AM UTC 24
Finished Oct 12 12:14:33 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772185862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.772185862
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_smoke.2815539084
Short name T147
Test name
Test status
Simulation time 1074006790 ps
CPU time 15.82 seconds
Started Oct 12 12:11:47 AM UTC 24
Finished Oct 12 12:12:04 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815539084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2815539084
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_stress_all.4108283932
Short name T73
Test name
Test status
Simulation time 141529245841 ps
CPU time 1423.14 seconds
Started Oct 12 12:12:26 AM UTC 24
Finished Oct 12 12:36:25 AM UTC 24
Peak memory 684584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108283932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4108283932
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.1337158893
Short name T246
Test name
Test status
Simulation time 12076999471 ps
CPU time 59.29 seconds
Started Oct 12 12:12:06 AM UTC 24
Finished Oct 12 12:13:07 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337158893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1337158893
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_alert_test.1680481219
Short name T245
Test name
Test status
Simulation time 13178629 ps
CPU time 0.88 seconds
Started Oct 12 12:12:56 AM UTC 24
Finished Oct 12 12:12:58 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680481219 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1680481219
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.4111458906
Short name T242
Test name
Test status
Simulation time 65660229 ps
CPU time 2.55 seconds
Started Oct 12 12:12:41 AM UTC 24
Finished Oct 12 12:12:44 AM UTC 24
Peak memory 209808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111458906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4111458906
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.1554724365
Short name T163
Test name
Test status
Simulation time 541836715 ps
CPU time 37.85 seconds
Started Oct 12 12:12:46 AM UTC 24
Finished Oct 12 12:13:26 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554724365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1554724365
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.321048166
Short name T391
Test name
Test status
Simulation time 15333804378 ps
CPU time 816.62 seconds
Started Oct 12 12:12:43 AM UTC 24
Finished Oct 12 12:26:29 AM UTC 24
Peak memory 532976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321048166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.321048166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_error.1263302996
Short name T244
Test name
Test status
Simulation time 328497630 ps
CPU time 6.67 seconds
Started Oct 12 12:12:46 AM UTC 24
Finished Oct 12 12:12:54 AM UTC 24
Peak memory 209508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263302996 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1263302996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_long_msg.2470321065
Short name T276
Test name
Test status
Simulation time 21242387828 ps
CPU time 236.41 seconds
Started Oct 12 12:12:39 AM UTC 24
Finished Oct 12 12:16:39 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470321065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2470321065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_smoke.3469208404
Short name T239
Test name
Test status
Simulation time 129190377 ps
CPU time 2.28 seconds
Started Oct 12 12:12:39 AM UTC 24
Finished Oct 12 12:12:42 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469208404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3469208404
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_stress_all.2856865094
Short name T133
Test name
Test status
Simulation time 8236993194 ps
CPU time 251.04 seconds
Started Oct 12 12:12:49 AM UTC 24
Finished Oct 12 12:17:04 AM UTC 24
Peak memory 226224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856865094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2856865094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1735681804
Short name T95
Test name
Test status
Simulation time 23073096591 ps
CPU time 150.56 seconds
Started Oct 12 12:12:46 AM UTC 24
Finished Oct 12 12:15:20 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735681804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1735681804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_alert_test.2430120940
Short name T52
Test name
Test status
Simulation time 14547754 ps
CPU time 0.91 seconds
Started Oct 12 12:05:49 AM UTC 24
Finished Oct 12 12:05:51 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430120940 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2430120940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.182531942
Short name T65
Test name
Test status
Simulation time 1185663968 ps
CPU time 57.02 seconds
Started Oct 12 12:05:24 AM UTC 24
Finished Oct 12 12:06:23 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182531942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.182531942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.1397290122
Short name T30
Test name
Test status
Simulation time 26681926232 ps
CPU time 912.79 seconds
Started Oct 12 12:05:25 AM UTC 24
Finished Oct 12 12:20:49 AM UTC 24
Peak memory 729620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397290122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1397290122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_error.3114723837
Short name T46
Test name
Test status
Simulation time 10084338130 ps
CPU time 141.47 seconds
Started Oct 12 12:05:26 AM UTC 24
Finished Oct 12 12:07:50 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114723837 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3114723837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_long_msg.44047179
Short name T152
Test name
Test status
Simulation time 25857517689 ps
CPU time 113.03 seconds
Started Oct 12 12:05:23 AM UTC 24
Finished Oct 12 12:07:18 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44047179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.44047179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.663241106
Short name T53
Test name
Test status
Simulation time 118720071 ps
CPU time 1.31 seconds
Started Oct 12 12:05:49 AM UTC 24
Finished Oct 12 12:05:51 AM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663241106 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.663241106
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_smoke.474878124
Short name T7
Test name
Test status
Simulation time 234688900 ps
CPU time 6.8 seconds
Started Oct 12 12:05:23 AM UTC 24
Finished Oct 12 12:05:31 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474878124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.474878124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_stress_all.165016605
Short name T447
Test name
Test status
Simulation time 22769055717 ps
CPU time 1522.86 seconds
Started Oct 12 12:05:44 AM UTC 24
Finished Oct 12 12:31:24 AM UTC 24
Peak memory 645620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165016605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.165016605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.996616835
Short name T14
Test name
Test status
Simulation time 3205951901 ps
CPU time 29.36 seconds
Started Oct 12 12:05:47 AM UTC 24
Finished Oct 12 12:06:18 AM UTC 24
Peak memory 218452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99661683
5 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.996616835
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.3733591208
Short name T51
Test name
Test status
Simulation time 24850345072 ps
CPU time 59.33 seconds
Started Oct 12 12:05:42 AM UTC 24
Finished Oct 12 12:06:43 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733591208 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3733591208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.3023782670
Short name T186
Test name
Test status
Simulation time 66964640310 ps
CPU time 116.6 seconds
Started Oct 12 12:05:42 AM UTC 24
Finished Oct 12 12:07:41 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023782670 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3023782670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.3104681240
Short name T190
Test name
Test status
Simulation time 3214701219 ps
CPU time 123.81 seconds
Started Oct 12 12:05:44 AM UTC 24
Finished Oct 12 12:07:50 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104681240 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3104681240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.832303907
Short name T302
Test name
Test status
Simulation time 57030699691 ps
CPU time 748.68 seconds
Started Oct 12 12:05:30 AM UTC 24
Finished Oct 12 12:18:08 AM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832303907 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.832303907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.3354997996
Short name T505
Test name
Test status
Simulation time 42059208569 ps
CPU time 2299.79 seconds
Started Oct 12 12:05:31 AM UTC 24
Finished Oct 12 12:44:16 AM UTC 24
Peak memory 223792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354997996 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3354997996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.1507776195
Short name T517
Test name
Test status
Simulation time 724414786565 ps
CPU time 2741.76 seconds
Started Oct 12 12:05:38 AM UTC 24
Finished Oct 12 12:51:51 AM UTC 24
Peak memory 223588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507776195 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1507776195
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.3400856312
Short name T127
Test name
Test status
Simulation time 11179697736 ps
CPU time 144.54 seconds
Started Oct 12 12:05:30 AM UTC 24
Finished Oct 12 12:07:57 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400856312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3400856312
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_alert_test.2030187176
Short name T253
Test name
Test status
Simulation time 55253342 ps
CPU time 0.84 seconds
Started Oct 12 12:13:40 AM UTC 24
Finished Oct 12 12:13:42 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030187176 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2030187176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.1373017383
Short name T251
Test name
Test status
Simulation time 582753383 ps
CPU time 21.3 seconds
Started Oct 12 12:13:17 AM UTC 24
Finished Oct 12 12:13:39 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373017383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1373017383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.3949147372
Short name T250
Test name
Test status
Simulation time 4800423365 ps
CPU time 15.88 seconds
Started Oct 12 12:13:22 AM UTC 24
Finished Oct 12 12:13:39 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949147372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3949147372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2507342288
Short name T322
Test name
Test status
Simulation time 16099578702 ps
CPU time 386.19 seconds
Started Oct 12 12:13:18 AM UTC 24
Finished Oct 12 12:19:49 AM UTC 24
Peak memory 696812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507342288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2507342288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_error.2657678038
Short name T76
Test name
Test status
Simulation time 19918950227 ps
CPU time 116.98 seconds
Started Oct 12 12:13:27 AM UTC 24
Finished Oct 12 12:15:26 AM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657678038 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2657678038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_long_msg.835765000
Short name T259
Test name
Test status
Simulation time 5729633918 ps
CPU time 99.01 seconds
Started Oct 12 12:13:09 AM UTC 24
Finished Oct 12 12:14:50 AM UTC 24
Peak memory 209840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835765000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.835765000
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_smoke.3021087604
Short name T247
Test name
Test status
Simulation time 5233324612 ps
CPU time 13.12 seconds
Started Oct 12 12:13:00 AM UTC 24
Finished Oct 12 12:13:14 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021087604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3021087604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_stress_all.3423065377
Short name T526
Test name
Test status
Simulation time 212798967224 ps
CPU time 3014.33 seconds
Started Oct 12 12:13:38 AM UTC 24
Finished Oct 12 01:04:23 AM UTC 24
Peak memory 813532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423065377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3423065377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.4055715916
Short name T261
Test name
Test status
Simulation time 4538682522 ps
CPU time 81.55 seconds
Started Oct 12 12:13:31 AM UTC 24
Finished Oct 12 12:14:54 AM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055715916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4055715916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_alert_test.516261090
Short name T260
Test name
Test status
Simulation time 17190531 ps
CPU time 0.77 seconds
Started Oct 12 12:14:51 AM UTC 24
Finished Oct 12 12:14:54 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516261090 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.516261090
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.4287121572
Short name T263
Test name
Test status
Simulation time 1334681692 ps
CPU time 105.19 seconds
Started Oct 12 12:13:43 AM UTC 24
Finished Oct 12 12:15:31 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287121572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4287121572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.500539244
Short name T256
Test name
Test status
Simulation time 1794139500 ps
CPU time 16.82 seconds
Started Oct 12 12:13:49 AM UTC 24
Finished Oct 12 12:14:07 AM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500539244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.500539244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.1246026729
Short name T349
Test name
Test status
Simulation time 6697261669 ps
CPU time 556.64 seconds
Started Oct 12 12:13:46 AM UTC 24
Finished Oct 12 12:23:09 AM UTC 24
Peak memory 707116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246026729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1246026729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_error.2201300733
Short name T272
Test name
Test status
Simulation time 137770129122 ps
CPU time 134.81 seconds
Started Oct 12 12:14:08 AM UTC 24
Finished Oct 12 12:16:26 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201300733 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2201300733
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_long_msg.1519210954
Short name T268
Test name
Test status
Simulation time 4039204688 ps
CPU time 135.57 seconds
Started Oct 12 12:13:42 AM UTC 24
Finished Oct 12 12:16:00 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519210954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1519210954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_smoke.2363834333
Short name T254
Test name
Test status
Simulation time 373754858 ps
CPU time 2.69 seconds
Started Oct 12 12:13:42 AM UTC 24
Finished Oct 12 12:13:46 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363834333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2363834333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_stress_all.79935065
Short name T374
Test name
Test status
Simulation time 137236351580 ps
CPU time 609.92 seconds
Started Oct 12 12:14:35 AM UTC 24
Finished Oct 12 12:24:53 AM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79935065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.79935065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.2579509006
Short name T128
Test name
Test status
Simulation time 65055231341 ps
CPU time 64.57 seconds
Started Oct 12 12:14:32 AM UTC 24
Finished Oct 12 12:15:38 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579509006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2579509006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_alert_test.3603807809
Short name T265
Test name
Test status
Simulation time 49756697 ps
CPU time 0.73 seconds
Started Oct 12 12:15:43 AM UTC 24
Finished Oct 12 12:15:45 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603807809 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3603807809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.2481747546
Short name T264
Test name
Test status
Simulation time 581036897 ps
CPU time 36.11 seconds
Started Oct 12 12:15:04 AM UTC 24
Finished Oct 12 12:15:42 AM UTC 24
Peak memory 209668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481747546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2481747546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.3005979461
Short name T269
Test name
Test status
Simulation time 11269261957 ps
CPU time 54.08 seconds
Started Oct 12 12:15:21 AM UTC 24
Finished Oct 12 12:16:17 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005979461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3005979461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.158342066
Short name T457
Test name
Test status
Simulation time 5085718446 ps
CPU time 1030.38 seconds
Started Oct 12 12:15:14 AM UTC 24
Finished Oct 12 12:32:36 AM UTC 24
Peak memory 772732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158342066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.158342066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_error.1489688059
Short name T274
Test name
Test status
Simulation time 6879886694 ps
CPU time 61.74 seconds
Started Oct 12 12:15:28 AM UTC 24
Finished Oct 12 12:16:31 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489688059 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1489688059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_long_msg.2811825528
Short name T262
Test name
Test status
Simulation time 335190321 ps
CPU time 6.59 seconds
Started Oct 12 12:14:55 AM UTC 24
Finished Oct 12 12:15:03 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811825528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2811825528
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_smoke.1260521303
Short name T149
Test name
Test status
Simulation time 667309322 ps
CPU time 16.57 seconds
Started Oct 12 12:14:55 AM UTC 24
Finished Oct 12 12:15:13 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260521303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1260521303
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_stress_all.3259487200
Short name T329
Test name
Test status
Simulation time 11155265491 ps
CPU time 272.78 seconds
Started Oct 12 12:15:43 AM UTC 24
Finished Oct 12 12:20:20 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259487200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3259487200
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.64730120
Short name T97
Test name
Test status
Simulation time 12168019119 ps
CPU time 209.97 seconds
Started Oct 12 12:15:32 AM UTC 24
Finished Oct 12 12:19:05 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64730120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.64730120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_alert_test.3467023094
Short name T273
Test name
Test status
Simulation time 40300212 ps
CPU time 0.88 seconds
Started Oct 12 12:16:27 AM UTC 24
Finished Oct 12 12:16:29 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467023094 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3467023094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.34999727
Short name T281
Test name
Test status
Simulation time 4215667379 ps
CPU time 83.83 seconds
Started Oct 12 12:15:45 AM UTC 24
Finished Oct 12 12:17:11 AM UTC 24
Peak memory 226196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34999727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.34999727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.3283467475
Short name T279
Test name
Test status
Simulation time 52558239868 ps
CPU time 58.31 seconds
Started Oct 12 12:16:00 AM UTC 24
Finished Oct 12 12:17:00 AM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283467475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3283467475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.2850092217
Short name T364
Test name
Test status
Simulation time 24554840764 ps
CPU time 511.87 seconds
Started Oct 12 12:15:47 AM UTC 24
Finished Oct 12 12:24:25 AM UTC 24
Peak memory 723636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850092217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2850092217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_error.2003022415
Short name T275
Test name
Test status
Simulation time 437285237 ps
CPU time 29.53 seconds
Started Oct 12 12:16:01 AM UTC 24
Finished Oct 12 12:16:32 AM UTC 24
Peak memory 209504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003022415 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2003022415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_long_msg.456426737
Short name T307
Test name
Test status
Simulation time 16816010431 ps
CPU time 160.81 seconds
Started Oct 12 12:15:44 AM UTC 24
Finished Oct 12 12:18:28 AM UTC 24
Peak memory 220580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456426737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.456426737
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_smoke.3791722617
Short name T267
Test name
Test status
Simulation time 426919806 ps
CPU time 14.29 seconds
Started Oct 12 12:15:43 AM UTC 24
Finished Oct 12 12:15:58 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791722617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3791722617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_stress_all.470007078
Short name T28
Test name
Test status
Simulation time 29069557293 ps
CPU time 3200.7 seconds
Started Oct 12 12:16:23 AM UTC 24
Finished Oct 12 01:10:15 AM UTC 24
Peak memory 830128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470007078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.470007078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.3394683398
Short name T271
Test name
Test status
Simulation time 74515148 ps
CPU time 5.3 seconds
Started Oct 12 12:16:19 AM UTC 24
Finished Oct 12 12:16:25 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394683398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3394683398
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_alert_test.2158683789
Short name T278
Test name
Test status
Simulation time 14914353 ps
CPU time 0.84 seconds
Started Oct 12 12:16:56 AM UTC 24
Finished Oct 12 12:16:58 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158683789 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2158683789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.3423854137
Short name T289
Test name
Test status
Simulation time 9112817246 ps
CPU time 52.15 seconds
Started Oct 12 12:16:32 AM UTC 24
Finished Oct 12 12:17:26 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423854137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3423854137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.953849759
Short name T283
Test name
Test status
Simulation time 2580538753 ps
CPU time 36.33 seconds
Started Oct 12 12:16:38 AM UTC 24
Finished Oct 12 12:17:16 AM UTC 24
Peak memory 209784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953849759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.953849759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.1965929792
Short name T493
Test name
Test status
Simulation time 22893672876 ps
CPU time 1328.2 seconds
Started Oct 12 12:16:34 AM UTC 24
Finished Oct 12 12:38:56 AM UTC 24
Peak memory 729844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965929792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1965929792
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_error.1414206608
Short name T320
Test name
Test status
Simulation time 6210511522 ps
CPU time 178.67 seconds
Started Oct 12 12:16:41 AM UTC 24
Finished Oct 12 12:19:43 AM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414206608 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1414206608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_long_msg.1461481103
Short name T294
Test name
Test status
Simulation time 4741146941 ps
CPU time 64.49 seconds
Started Oct 12 12:16:30 AM UTC 24
Finished Oct 12 12:17:37 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461481103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1461481103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_smoke.409639908
Short name T277
Test name
Test status
Simulation time 3784800012 ps
CPU time 14.41 seconds
Started Oct 12 12:16:27 AM UTC 24
Finished Oct 12 12:16:43 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409639908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.409639908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_stress_all.1262487190
Short name T316
Test name
Test status
Simulation time 9101274002 ps
CPU time 156.34 seconds
Started Oct 12 12:16:50 AM UTC 24
Finished Oct 12 12:19:29 AM UTC 24
Peak memory 220380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262487190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1262487190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.3894792739
Short name T287
Test name
Test status
Simulation time 6909019349 ps
CPU time 39.82 seconds
Started Oct 12 12:16:43 AM UTC 24
Finished Oct 12 12:17:25 AM UTC 24
Peak memory 209680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894792739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3894792739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_alert_test.5903163
Short name T288
Test name
Test status
Simulation time 23770676 ps
CPU time 0.81 seconds
Started Oct 12 12:17:24 AM UTC 24
Finished Oct 12 12:17:26 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5903163 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.5903163
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.2494493269
Short name T293
Test name
Test status
Simulation time 468200007 ps
CPU time 28.7 seconds
Started Oct 12 12:17:05 AM UTC 24
Finished Oct 12 12:17:35 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494493269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2494493269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.2093846765
Short name T168
Test name
Test status
Simulation time 3819938890 ps
CPU time 52.55 seconds
Started Oct 12 12:17:16 AM UTC 24
Finished Oct 12 12:18:10 AM UTC 24
Peak memory 209740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093846765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2093846765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.175214731
Short name T356
Test name
Test status
Simulation time 3307748032 ps
CPU time 393.1 seconds
Started Oct 12 12:17:11 AM UTC 24
Finished Oct 12 12:23:49 AM UTC 24
Peak memory 709184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175214731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.175214731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_error.3610811048
Short name T303
Test name
Test status
Simulation time 45438022068 ps
CPU time 57.46 seconds
Started Oct 12 12:17:16 AM UTC 24
Finished Oct 12 12:18:15 AM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610811048 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3610811048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_long_msg.2778560968
Short name T292
Test name
Test status
Simulation time 4760937996 ps
CPU time 32.37 seconds
Started Oct 12 12:17:01 AM UTC 24
Finished Oct 12 12:17:35 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778560968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2778560968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_smoke.3769026849
Short name T280
Test name
Test status
Simulation time 302132165 ps
CPU time 10.85 seconds
Started Oct 12 12:16:59 AM UTC 24
Finished Oct 12 12:17:11 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769026849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3769026849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_stress_all.309725346
Short name T421
Test name
Test status
Simulation time 17985965701 ps
CPU time 665.98 seconds
Started Oct 12 12:17:20 AM UTC 24
Finished Oct 12 12:28:35 AM UTC 24
Peak memory 715404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309725346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.309725346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.3280958400
Short name T310
Test name
Test status
Simulation time 4771861434 ps
CPU time 108.11 seconds
Started Oct 12 12:17:17 AM UTC 24
Finished Oct 12 12:19:07 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280958400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3280958400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_alert_test.2973301335
Short name T295
Test name
Test status
Simulation time 25211131 ps
CPU time 0.85 seconds
Started Oct 12 12:17:38 AM UTC 24
Finished Oct 12 12:17:39 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973301335 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2973301335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.1635506324
Short name T296
Test name
Test status
Simulation time 784059436 ps
CPU time 13.66 seconds
Started Oct 12 12:17:26 AM UTC 24
Finished Oct 12 12:17:41 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635506324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1635506324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.1848341847
Short name T301
Test name
Test status
Simulation time 2519129074 ps
CPU time 32.69 seconds
Started Oct 12 12:17:29 AM UTC 24
Finished Oct 12 12:18:03 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848341847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1848341847
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.3541893860
Short name T497
Test name
Test status
Simulation time 6981643383 ps
CPU time 1325.65 seconds
Started Oct 12 12:17:28 AM UTC 24
Finished Oct 12 12:39:48 AM UTC 24
Peak memory 793128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541893860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3541893860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_error.4188999005
Short name T336
Test name
Test status
Simulation time 16785993788 ps
CPU time 259.66 seconds
Started Oct 12 12:17:32 AM UTC 24
Finished Oct 12 12:21:55 AM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188999005 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4188999005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_long_msg.3645429797
Short name T297
Test name
Test status
Simulation time 6465751129 ps
CPU time 26.05 seconds
Started Oct 12 12:17:26 AM UTC 24
Finished Oct 12 12:17:54 AM UTC 24
Peak memory 209968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645429797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3645429797
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_smoke.1663078313
Short name T290
Test name
Test status
Simulation time 213074679 ps
CPU time 3.1 seconds
Started Oct 12 12:17:24 AM UTC 24
Finished Oct 12 12:17:28 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663078313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1663078313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_stress_all.4277570646
Short name T512
Test name
Test status
Simulation time 54492799557 ps
CPU time 1846.29 seconds
Started Oct 12 12:17:36 AM UTC 24
Finished Oct 12 12:48:41 AM UTC 24
Peak memory 791132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277570646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4277570646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.1649774619
Short name T314
Test name
Test status
Simulation time 83493490088 ps
CPU time 106.81 seconds
Started Oct 12 12:17:36 AM UTC 24
Finished Oct 12 12:19:25 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649774619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1649774619
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_alert_test.4281569687
Short name T304
Test name
Test status
Simulation time 23430910 ps
CPU time 0.85 seconds
Started Oct 12 12:18:14 AM UTC 24
Finished Oct 12 12:18:16 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281569687 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4281569687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.3956343032
Short name T300
Test name
Test status
Simulation time 305772834 ps
CPU time 6.1 seconds
Started Oct 12 12:17:55 AM UTC 24
Finished Oct 12 12:18:02 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956343032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3956343032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.1028708851
Short name T170
Test name
Test status
Simulation time 2027107470 ps
CPU time 28.46 seconds
Started Oct 12 12:17:58 AM UTC 24
Finished Oct 12 12:18:28 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028708851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1028708851
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.2887921809
Short name T499
Test name
Test status
Simulation time 24572124680 ps
CPU time 1381.17 seconds
Started Oct 12 12:17:57 AM UTC 24
Finished Oct 12 12:41:13 AM UTC 24
Peak memory 739872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887921809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2887921809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_error.969062258
Short name T318
Test name
Test status
Simulation time 5565662823 ps
CPU time 92.76 seconds
Started Oct 12 12:18:03 AM UTC 24
Finished Oct 12 12:19:38 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969062258 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.969062258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_long_msg.358118061
Short name T315
Test name
Test status
Simulation time 8106256125 ps
CPU time 102.15 seconds
Started Oct 12 12:17:42 AM UTC 24
Finished Oct 12 12:19:26 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358118061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.358118061
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_smoke.2502454624
Short name T299
Test name
Test status
Simulation time 1359122432 ps
CPU time 15.3 seconds
Started Oct 12 12:17:41 AM UTC 24
Finished Oct 12 12:17:57 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502454624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2502454624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_stress_all.290832022
Short name T167
Test name
Test status
Simulation time 3002297852 ps
CPU time 224.02 seconds
Started Oct 12 12:18:14 AM UTC 24
Finished Oct 12 12:22:02 AM UTC 24
Peak memory 211820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290832022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.290832022
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.1229782329
Short name T313
Test name
Test status
Simulation time 6201061607 ps
CPU time 74.59 seconds
Started Oct 12 12:18:04 AM UTC 24
Finished Oct 12 12:19:21 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229782329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1229782329
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_alert_test.1120862844
Short name T309
Test name
Test status
Simulation time 33200908 ps
CPU time 0.81 seconds
Started Oct 12 12:18:51 AM UTC 24
Finished Oct 12 12:18:53 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120862844 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1120862844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.1800403294
Short name T308
Test name
Test status
Simulation time 2256345154 ps
CPU time 31.76 seconds
Started Oct 12 12:18:17 AM UTC 24
Finished Oct 12 12:18:50 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800403294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1800403294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.3889268465
Short name T171
Test name
Test status
Simulation time 1412345844 ps
CPU time 43.89 seconds
Started Oct 12 12:18:30 AM UTC 24
Finished Oct 12 12:19:15 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889268465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3889268465
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.3593344102
Short name T507
Test name
Test status
Simulation time 8865524725 ps
CPU time 1614.77 seconds
Started Oct 12 12:18:20 AM UTC 24
Finished Oct 12 12:45:30 AM UTC 24
Peak memory 785080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593344102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3593344102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_error.4100780386
Short name T362
Test name
Test status
Simulation time 201262600536 ps
CPU time 338.23 seconds
Started Oct 12 12:18:32 AM UTC 24
Finished Oct 12 12:24:15 AM UTC 24
Peak memory 210000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100780386 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4100780386
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_long_msg.493036481
Short name T327
Test name
Test status
Simulation time 1489820994 ps
CPU time 107.53 seconds
Started Oct 12 12:18:16 AM UTC 24
Finished Oct 12 12:20:05 AM UTC 24
Peak memory 209848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493036481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.493036481
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_smoke.82614674
Short name T305
Test name
Test status
Simulation time 73923615 ps
CPU time 2.87 seconds
Started Oct 12 12:18:16 AM UTC 24
Finished Oct 12 12:18:19 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82614674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 28.hmac_smoke.82614674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_stress_all.3831698796
Short name T70
Test name
Test status
Simulation time 70972623450 ps
CPU time 850.06 seconds
Started Oct 12 12:18:42 AM UTC 24
Finished Oct 12 12:33:01 AM UTC 24
Peak memory 715248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831698796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3831698796
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.2524418401
Short name T312
Test name
Test status
Simulation time 11696814081 ps
CPU time 44.33 seconds
Started Oct 12 12:18:32 AM UTC 24
Finished Oct 12 12:19:18 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524418401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2524418401
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_alert_test.2174421430
Short name T317
Test name
Test status
Simulation time 15671935 ps
CPU time 0.92 seconds
Started Oct 12 12:19:27 AM UTC 24
Finished Oct 12 12:19:29 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174421430 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2174421430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.38769225
Short name T325
Test name
Test status
Simulation time 3186879024 ps
CPU time 49.32 seconds
Started Oct 12 12:19:09 AM UTC 24
Finished Oct 12 12:20:00 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38769225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.38769225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.756017815
Short name T332
Test name
Test status
Simulation time 16683292394 ps
CPU time 74.49 seconds
Started Oct 12 12:19:16 AM UTC 24
Finished Oct 12 12:20:32 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756017815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.756017815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.153453091
Short name T328
Test name
Test status
Simulation time 419245547 ps
CPU time 65.46 seconds
Started Oct 12 12:19:10 AM UTC 24
Finished Oct 12 12:20:17 AM UTC 24
Peak memory 400992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153453091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.153453091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_error.2355316873
Short name T319
Test name
Test status
Simulation time 1130092612 ps
CPU time 19.19 seconds
Started Oct 12 12:19:18 AM UTC 24
Finished Oct 12 12:19:39 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355316873 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2355316873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_long_msg.2170257526
Short name T343
Test name
Test status
Simulation time 11032889487 ps
CPU time 191.17 seconds
Started Oct 12 12:19:07 AM UTC 24
Finished Oct 12 12:22:21 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170257526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2170257526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_smoke.1284266570
Short name T311
Test name
Test status
Simulation time 3645225289 ps
CPU time 13.29 seconds
Started Oct 12 12:18:54 AM UTC 24
Finished Oct 12 12:19:09 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284266570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1284266570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_stress_all.1379870446
Short name T518
Test name
Test status
Simulation time 36999405298 ps
CPU time 1939.33 seconds
Started Oct 12 12:19:27 AM UTC 24
Finished Oct 12 12:52:06 AM UTC 24
Peak memory 764456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379870446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1379870446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.1233740293
Short name T29
Test name
Test status
Simulation time 3202161774 ps
CPU time 81.15 seconds
Started Oct 12 12:19:22 AM UTC 24
Finished Oct 12 12:20:45 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233740293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1233740293
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_alert_test.3967223431
Short name T64
Test name
Test status
Simulation time 13764318 ps
CPU time 0.92 seconds
Started Oct 12 12:06:19 AM UTC 24
Finished Oct 12 12:06:21 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967223431 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3967223431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.3782606315
Short name T157
Test name
Test status
Simulation time 857519383 ps
CPU time 47.93 seconds
Started Oct 12 12:05:52 AM UTC 24
Finished Oct 12 12:06:41 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782606315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3782606315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.36649809
Short name T17
Test name
Test status
Simulation time 5073545780 ps
CPU time 22.1 seconds
Started Oct 12 12:05:56 AM UTC 24
Finished Oct 12 12:06:20 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36649809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.36649809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.214554429
Short name T252
Test name
Test status
Simulation time 10316447994 ps
CPU time 462.37 seconds
Started Oct 12 12:05:52 AM UTC 24
Finished Oct 12 12:13:40 AM UTC 24
Peak memory 660228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214554429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.214554429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_error.2679842729
Short name T48
Test name
Test status
Simulation time 14314203320 ps
CPU time 160.64 seconds
Started Oct 12 12:05:59 AM UTC 24
Finished Oct 12 12:08:42 AM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679842729 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2679842729
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_long_msg.93305622
Short name T174
Test name
Test status
Simulation time 7334834616 ps
CPU time 98.6 seconds
Started Oct 12 12:05:51 AM UTC 24
Finished Oct 12 12:07:31 AM UTC 24
Peak memory 218352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93305622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.93305622
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.2011334828
Short name T54
Test name
Test status
Simulation time 209986427 ps
CPU time 1.25 seconds
Started Oct 12 12:06:19 AM UTC 24
Finished Oct 12 12:06:21 AM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011334828 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2011334828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_smoke.3518104061
Short name T125
Test name
Test status
Simulation time 2226137719 ps
CPU time 9.37 seconds
Started Oct 12 12:05:49 AM UTC 24
Finished Oct 12 12:06:00 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518104061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3518104061
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_stress_all.1003816894
Short name T475
Test name
Test status
Simulation time 285671656292 ps
CPU time 1672.22 seconds
Started Oct 12 12:06:13 AM UTC 24
Finished Oct 12 12:34:24 AM UTC 24
Peak memory 741940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003816894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1003816894
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.1824749862
Short name T180
Test name
Test status
Simulation time 3167471499 ps
CPU time 62.78 seconds
Started Oct 12 12:06:10 AM UTC 24
Finished Oct 12 12:07:14 AM UTC 24
Peak memory 209916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824749862 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1824749862
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.3957840860
Short name T183
Test name
Test status
Simulation time 14899144364 ps
CPU time 71.8 seconds
Started Oct 12 12:06:10 AM UTC 24
Finished Oct 12 12:07:24 AM UTC 24
Peak memory 209972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957840860 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3957840860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.1847245802
Short name T182
Test name
Test status
Simulation time 2148429914 ps
CPU time 67.23 seconds
Started Oct 12 12:06:10 AM UTC 24
Finished Oct 12 12:07:19 AM UTC 24
Peak memory 209980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847245802 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1847245802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.2509362303
Short name T284
Test name
Test status
Simulation time 248351012503 ps
CPU time 667.93 seconds
Started Oct 12 12:06:00 AM UTC 24
Finished Oct 12 12:17:16 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509362303 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2509362303
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.2224077235
Short name T520
Test name
Test status
Simulation time 807225125482 ps
CPU time 2754.5 seconds
Started Oct 12 12:06:01 AM UTC 24
Finished Oct 12 12:52:26 AM UTC 24
Peak memory 223792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224077235 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2224077235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.4009181886
Short name T521
Test name
Test status
Simulation time 1694047919170 ps
CPU time 2832.32 seconds
Started Oct 12 12:06:04 AM UTC 24
Finished Oct 12 12:53:48 AM UTC 24
Peak memory 229732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009181886 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.4009181886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.1441994032
Short name T88
Test name
Test status
Simulation time 117534021812 ps
CPU time 169.05 seconds
Started Oct 12 12:06:00 AM UTC 24
Finished Oct 12 12:08:52 AM UTC 24
Peak memory 209780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441994032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1441994032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_alert_test.304779507
Short name T326
Test name
Test status
Simulation time 11810963 ps
CPU time 0.92 seconds
Started Oct 12 12:20:02 AM UTC 24
Finished Oct 12 12:20:04 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304779507 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.304779507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3217918419
Short name T323
Test name
Test status
Simulation time 156802239 ps
CPU time 11.69 seconds
Started Oct 12 12:19:39 AM UTC 24
Finished Oct 12 12:19:52 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217918419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3217918419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.2865957064
Short name T169
Test name
Test status
Simulation time 798258960 ps
CPU time 49.56 seconds
Started Oct 12 12:19:45 AM UTC 24
Finished Oct 12 12:20:36 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865957064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2865957064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.3557252752
Short name T419
Test name
Test status
Simulation time 10921326742 ps
CPU time 526.65 seconds
Started Oct 12 12:19:40 AM UTC 24
Finished Oct 12 12:28:33 AM UTC 24
Peak memory 739960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557252752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3557252752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_error.1942904987
Short name T347
Test name
Test status
Simulation time 3317030337 ps
CPU time 191.83 seconds
Started Oct 12 12:19:46 AM UTC 24
Finished Oct 12 12:23:01 AM UTC 24
Peak memory 209892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942904987 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1942904987
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_long_msg.3784459481
Short name T331
Test name
Test status
Simulation time 11011188671 ps
CPU time 47 seconds
Started Oct 12 12:19:31 AM UTC 24
Finished Oct 12 12:20:20 AM UTC 24
Peak memory 209612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784459481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3784459481
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_smoke.1672845534
Short name T321
Test name
Test status
Simulation time 2732342569 ps
CPU time 12.67 seconds
Started Oct 12 12:19:31 AM UTC 24
Finished Oct 12 12:19:45 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672845534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1672845534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_stress_all.1313880074
Short name T68
Test name
Test status
Simulation time 22265329669 ps
CPU time 317.55 seconds
Started Oct 12 12:19:52 AM UTC 24
Finished Oct 12 12:25:14 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313880074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1313880074
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.692319821
Short name T34
Test name
Test status
Simulation time 19726096580 ps
CPU time 71.74 seconds
Started Oct 12 12:19:51 AM UTC 24
Finished Oct 12 12:21:05 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692319821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.692319821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_alert_test.4154476721
Short name T333
Test name
Test status
Simulation time 20321618 ps
CPU time 0.84 seconds
Started Oct 12 12:20:37 AM UTC 24
Finished Oct 12 12:20:39 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154476721 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4154476721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.2573956319
Short name T37
Test name
Test status
Simulation time 5508205209 ps
CPU time 91.17 seconds
Started Oct 12 12:20:07 AM UTC 24
Finished Oct 12 12:21:40 AM UTC 24
Peak memory 218268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573956319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2573956319
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.2562865480
Short name T33
Test name
Test status
Simulation time 2250472861 ps
CPU time 37.88 seconds
Started Oct 12 12:20:22 AM UTC 24
Finished Oct 12 12:21:02 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562865480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2562865480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.3736104546
Short name T498
Test name
Test status
Simulation time 6132686468 ps
CPU time 1201.6 seconds
Started Oct 12 12:20:18 AM UTC 24
Finished Oct 12 12:40:32 AM UTC 24
Peak memory 725536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736104546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3736104546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_error.381798461
Short name T337
Test name
Test status
Simulation time 4418224212 ps
CPU time 92.2 seconds
Started Oct 12 12:20:22 AM UTC 24
Finished Oct 12 12:21:57 AM UTC 24
Peak memory 209728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381798461 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.381798461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_long_msg.1078173228
Short name T345
Test name
Test status
Simulation time 8093702212 ps
CPU time 143.15 seconds
Started Oct 12 12:20:04 AM UTC 24
Finished Oct 12 12:22:30 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078173228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1078173228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_smoke.2087011664
Short name T330
Test name
Test status
Simulation time 257208683 ps
CPU time 15.42 seconds
Started Oct 12 12:20:03 AM UTC 24
Finished Oct 12 12:20:20 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087011664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2087011664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_stress_all.2288621809
Short name T98
Test name
Test status
Simulation time 56592416900 ps
CPU time 265.07 seconds
Started Oct 12 12:20:34 AM UTC 24
Finished Oct 12 12:25:02 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288621809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2288621809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.1553857749
Short name T341
Test name
Test status
Simulation time 17949901013 ps
CPU time 111.77 seconds
Started Oct 12 12:20:23 AM UTC 24
Finished Oct 12 12:22:17 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553857749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1553857749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_alert_test.1361941104
Short name T36
Test name
Test status
Simulation time 32682091 ps
CPU time 0.87 seconds
Started Oct 12 12:21:38 AM UTC 24
Finished Oct 12 12:21:40 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361941104 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1361941104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.2404127880
Short name T35
Test name
Test status
Simulation time 2167466359 ps
CPU time 48.72 seconds
Started Oct 12 12:20:47 AM UTC 24
Finished Oct 12 12:21:37 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404127880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2404127880
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.1134445305
Short name T338
Test name
Test status
Simulation time 1006183234 ps
CPU time 63.1 seconds
Started Oct 12 12:20:53 AM UTC 24
Finished Oct 12 12:21:57 AM UTC 24
Peak memory 218328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134445305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1134445305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.138513919
Short name T441
Test name
Test status
Simulation time 3378171228 ps
CPU time 575.94 seconds
Started Oct 12 12:20:52 AM UTC 24
Finished Oct 12 12:30:34 AM UTC 24
Peak memory 701124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138513919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.138513919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_error.3728480805
Short name T353
Test name
Test status
Simulation time 8250582976 ps
CPU time 141.15 seconds
Started Oct 12 12:20:53 AM UTC 24
Finished Oct 12 12:23:16 AM UTC 24
Peak memory 209892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728480805 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3728480805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_long_msg.301961148
Short name T32
Test name
Test status
Simulation time 531931349 ps
CPU time 5.77 seconds
Started Oct 12 12:20:44 AM UTC 24
Finished Oct 12 12:20:51 AM UTC 24
Peak memory 209580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301961148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.301961148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_smoke.166327066
Short name T31
Test name
Test status
Simulation time 1393482145 ps
CPU time 5.51 seconds
Started Oct 12 12:20:44 AM UTC 24
Finished Oct 12 12:20:51 AM UTC 24
Peak memory 209848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166327066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.166327066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_stress_all.2665311834
Short name T528
Test name
Test status
Simulation time 335345428074 ps
CPU time 2704.09 seconds
Started Oct 12 12:21:06 AM UTC 24
Finished Oct 12 01:06:37 AM UTC 24
Peak memory 762400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665311834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2665311834
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.1895776310
Short name T354
Test name
Test status
Simulation time 25231496394 ps
CPU time 155.68 seconds
Started Oct 12 12:21:03 AM UTC 24
Finished Oct 12 12:23:41 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895776310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1895776310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_alert_test.1982882372
Short name T340
Test name
Test status
Simulation time 52483280 ps
CPU time 0.88 seconds
Started Oct 12 12:22:03 AM UTC 24
Finished Oct 12 12:22:05 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982882372 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1982882372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.2367263674
Short name T346
Test name
Test status
Simulation time 1060375106 ps
CPU time 68.2 seconds
Started Oct 12 12:21:45 AM UTC 24
Finished Oct 12 12:22:55 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367263674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2367263674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.3039242080
Short name T339
Test name
Test status
Simulation time 44594722 ps
CPU time 3.43 seconds
Started Oct 12 12:21:57 AM UTC 24
Finished Oct 12 12:22:01 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039242080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3039242080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.145228330
Short name T503
Test name
Test status
Simulation time 27230965014 ps
CPU time 1247.6 seconds
Started Oct 12 12:21:46 AM UTC 24
Finished Oct 12 12:42:46 AM UTC 24
Peak memory 768500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145228330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.145228330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_error.3610948150
Short name T383
Test name
Test status
Simulation time 94701952326 ps
CPU time 220.19 seconds
Started Oct 12 12:21:58 AM UTC 24
Finished Oct 12 12:25:42 AM UTC 24
Peak memory 210020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610948150 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3610948150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_long_msg.3110099629
Short name T363
Test name
Test status
Simulation time 10308093700 ps
CPU time 154.85 seconds
Started Oct 12 12:21:42 AM UTC 24
Finished Oct 12 12:24:19 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110099629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3110099629
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_smoke.962249560
Short name T335
Test name
Test status
Simulation time 228382797 ps
CPU time 2.09 seconds
Started Oct 12 12:21:42 AM UTC 24
Finished Oct 12 12:21:45 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962249560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.962249560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_stress_all.345247176
Short name T69
Test name
Test status
Simulation time 45259331811 ps
CPU time 209.31 seconds
Started Oct 12 12:22:03 AM UTC 24
Finished Oct 12 12:25:35 AM UTC 24
Peak memory 218340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345247176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.345247176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.4174246364
Short name T367
Test name
Test status
Simulation time 15248880019 ps
CPU time 151.27 seconds
Started Oct 12 12:21:58 AM UTC 24
Finished Oct 12 12:24:32 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174246364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4174246364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_alert_test.76311325
Short name T348
Test name
Test status
Simulation time 12023067 ps
CPU time 0.82 seconds
Started Oct 12 12:23:03 AM UTC 24
Finished Oct 12 12:23:05 AM UTC 24
Peak memory 204324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76311325 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.76311325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.3154925377
Short name T370
Test name
Test status
Simulation time 8466381235 ps
CPU time 139.32 seconds
Started Oct 12 12:22:21 AM UTC 24
Finished Oct 12 12:24:44 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154925377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3154925377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.2496497816
Short name T352
Test name
Test status
Simulation time 1692511619 ps
CPU time 43.45 seconds
Started Oct 12 12:22:29 AM UTC 24
Finished Oct 12 12:23:14 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496497816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2496497816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.2477105638
Short name T492
Test name
Test status
Simulation time 19102785630 ps
CPU time 963.58 seconds
Started Oct 12 12:22:23 AM UTC 24
Finished Oct 12 12:38:38 AM UTC 24
Peak memory 731628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477105638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2477105638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_error.2969719122
Short name T351
Test name
Test status
Simulation time 5574799478 ps
CPU time 39.26 seconds
Started Oct 12 12:22:31 AM UTC 24
Finished Oct 12 12:23:12 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969719122 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2969719122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_long_msg.3938699485
Short name T361
Test name
Test status
Simulation time 120960322717 ps
CPU time 113.8 seconds
Started Oct 12 12:22:18 AM UTC 24
Finished Oct 12 12:24:14 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938699485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3938699485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_smoke.1946353853
Short name T342
Test name
Test status
Simulation time 244358248 ps
CPU time 12.62 seconds
Started Oct 12 12:22:06 AM UTC 24
Finished Oct 12 12:22:20 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946353853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1946353853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_stress_all.311545383
Short name T532
Test name
Test status
Simulation time 409462519633 ps
CPU time 3499.72 seconds
Started Oct 12 12:22:56 AM UTC 24
Finished Oct 12 01:21:50 AM UTC 24
Peak memory 809400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311545383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.311545383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.1087769631
Short name T360
Test name
Test status
Simulation time 6787840459 ps
CPU time 77.29 seconds
Started Oct 12 12:22:48 AM UTC 24
Finished Oct 12 12:24:08 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087769631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1087769631
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_alert_test.3887507644
Short name T358
Test name
Test status
Simulation time 35735340 ps
CPU time 0.87 seconds
Started Oct 12 12:23:51 AM UTC 24
Finished Oct 12 12:23:53 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887507644 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3887507644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.123608310
Short name T357
Test name
Test status
Simulation time 2509093045 ps
CPU time 39.68 seconds
Started Oct 12 12:23:10 AM UTC 24
Finished Oct 12 12:23:52 AM UTC 24
Peak memory 218536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123608310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.123608310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.3000904882
Short name T369
Test name
Test status
Simulation time 4540951871 ps
CPU time 80.11 seconds
Started Oct 12 12:23:15 AM UTC 24
Finished Oct 12 12:24:37 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000904882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3000904882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.2238998482
Short name T439
Test name
Test status
Simulation time 2787472705 ps
CPU time 418.57 seconds
Started Oct 12 12:23:13 AM UTC 24
Finished Oct 12 12:30:16 AM UTC 24
Peak memory 633324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238998482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2238998482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_error.3041364635
Short name T384
Test name
Test status
Simulation time 64980466616 ps
CPU time 143.46 seconds
Started Oct 12 12:23:17 AM UTC 24
Finished Oct 12 12:25:44 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041364635 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3041364635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_long_msg.2729465727
Short name T355
Test name
Test status
Simulation time 5655208838 ps
CPU time 33.81 seconds
Started Oct 12 12:23:10 AM UTC 24
Finished Oct 12 12:23:46 AM UTC 24
Peak memory 209904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729465727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2729465727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_smoke.2896037854
Short name T350
Test name
Test status
Simulation time 425163538 ps
CPU time 3.21 seconds
Started Oct 12 12:23:05 AM UTC 24
Finished Oct 12 12:23:09 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896037854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2896037854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_stress_all.3724189587
Short name T511
Test name
Test status
Simulation time 138538692431 ps
CPU time 1417.37 seconds
Started Oct 12 12:23:47 AM UTC 24
Finished Oct 12 12:47:40 AM UTC 24
Peak memory 485932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724189587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3724189587
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.4248291953
Short name T373
Test name
Test status
Simulation time 3137311933 ps
CPU time 66.68 seconds
Started Oct 12 12:23:42 AM UTC 24
Finished Oct 12 12:24:51 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248291953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.4248291953
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_alert_test.157046848
Short name T366
Test name
Test status
Simulation time 21913590 ps
CPU time 0.92 seconds
Started Oct 12 12:24:29 AM UTC 24
Finished Oct 12 12:24:31 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157046848 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.157046848
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.3180649452
Short name T372
Test name
Test status
Simulation time 2724059721 ps
CPU time 51.28 seconds
Started Oct 12 12:23:56 AM UTC 24
Finished Oct 12 12:24:49 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180649452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3180649452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.3146120116
Short name T368
Test name
Test status
Simulation time 7975686604 ps
CPU time 17.2 seconds
Started Oct 12 12:24:17 AM UTC 24
Finished Oct 12 12:24:35 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146120116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3146120116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.4022512789
Short name T515
Test name
Test status
Simulation time 7421608013 ps
CPU time 1523.9 seconds
Started Oct 12 12:24:09 AM UTC 24
Finished Oct 12 12:49:48 AM UTC 24
Peak memory 815600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022512789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.4022512789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_error.154964397
Short name T376
Test name
Test status
Simulation time 5422148196 ps
CPU time 42.04 seconds
Started Oct 12 12:24:17 AM UTC 24
Finished Oct 12 12:25:01 AM UTC 24
Peak memory 209632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154964397 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.154964397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_long_msg.1592525640
Short name T365
Test name
Test status
Simulation time 1901826050 ps
CPU time 32.71 seconds
Started Oct 12 12:23:54 AM UTC 24
Finished Oct 12 12:24:28 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592525640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1592525640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_smoke.2910798248
Short name T359
Test name
Test status
Simulation time 78708486 ps
CPU time 1.23 seconds
Started Oct 12 12:23:52 AM UTC 24
Finished Oct 12 12:23:55 AM UTC 24
Peak memory 208496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910798248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2910798248
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_stress_all.1487964925
Short name T530
Test name
Test status
Simulation time 44755672208 ps
CPU time 2916.05 seconds
Started Oct 12 12:24:27 AM UTC 24
Finished Oct 12 01:13:32 AM UTC 24
Peak memory 854512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487964925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1487964925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.2257341725
Short name T388
Test name
Test status
Simulation time 4352291571 ps
CPU time 106.58 seconds
Started Oct 12 12:24:21 AM UTC 24
Finished Oct 12 12:26:10 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257341725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2257341725
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_alert_test.1782588586
Short name T375
Test name
Test status
Simulation time 34004305 ps
CPU time 0.87 seconds
Started Oct 12 12:24:57 AM UTC 24
Finished Oct 12 12:24:58 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782588586 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1782588586
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.3176954554
Short name T382
Test name
Test status
Simulation time 1039894157 ps
CPU time 61.84 seconds
Started Oct 12 12:24:37 AM UTC 24
Finished Oct 12 12:25:40 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176954554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3176954554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.3739307707
Short name T380
Test name
Test status
Simulation time 2047356435 ps
CPU time 42.71 seconds
Started Oct 12 12:24:46 AM UTC 24
Finished Oct 12 12:25:30 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739307707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3739307707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.1537552078
Short name T408
Test name
Test status
Simulation time 1345602848 ps
CPU time 184.4 seconds
Started Oct 12 12:24:38 AM UTC 24
Finished Oct 12 12:27:45 AM UTC 24
Peak memory 471728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537552078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1537552078
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_error.1494849847
Short name T404
Test name
Test status
Simulation time 3223456657 ps
CPU time 172.92 seconds
Started Oct 12 12:24:47 AM UTC 24
Finished Oct 12 12:27:43 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494849847 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1494849847
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_long_msg.3588017785
Short name T398
Test name
Test status
Simulation time 16609181129 ps
CPU time 139.55 seconds
Started Oct 12 12:24:34 AM UTC 24
Finished Oct 12 12:26:56 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588017785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3588017785
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_smoke.3915563304
Short name T371
Test name
Test status
Simulation time 2732217544 ps
CPU time 13.29 seconds
Started Oct 12 12:24:32 AM UTC 24
Finished Oct 12 12:24:46 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915563304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3915563304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_stress_all.3320062813
Short name T395
Test name
Test status
Simulation time 35148314304 ps
CPU time 109.95 seconds
Started Oct 12 12:24:52 AM UTC 24
Finished Oct 12 12:26:44 AM UTC 24
Peak memory 209836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320062813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3320062813
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.364624081
Short name T389
Test name
Test status
Simulation time 6232561870 ps
CPU time 90.36 seconds
Started Oct 12 12:24:50 AM UTC 24
Finished Oct 12 12:26:22 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364624081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.364624081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_alert_test.3369450713
Short name T381
Test name
Test status
Simulation time 29720836 ps
CPU time 0.87 seconds
Started Oct 12 12:25:37 AM UTC 24
Finished Oct 12 12:25:39 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369450713 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3369450713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.839464221
Short name T387
Test name
Test status
Simulation time 1865758258 ps
CPU time 50.61 seconds
Started Oct 12 12:25:04 AM UTC 24
Finished Oct 12 12:25:57 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839464221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.839464221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.625652424
Short name T392
Test name
Test status
Simulation time 8654083616 ps
CPU time 70.77 seconds
Started Oct 12 12:25:17 AM UTC 24
Finished Oct 12 12:26:29 AM UTC 24
Peak memory 218320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625652424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.625652424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.1370094810
Short name T379
Test name
Test status
Simulation time 549412706 ps
CPU time 18.94 seconds
Started Oct 12 12:25:05 AM UTC 24
Finished Oct 12 12:25:25 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370094810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1370094810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_error.2198641426
Short name T409
Test name
Test status
Simulation time 7650002260 ps
CPU time 140.02 seconds
Started Oct 12 12:25:23 AM UTC 24
Finished Oct 12 12:27:46 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198641426 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2198641426
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_long_msg.665542075
Short name T378
Test name
Test status
Simulation time 891241440 ps
CPU time 19.33 seconds
Started Oct 12 12:25:02 AM UTC 24
Finished Oct 12 12:25:22 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665542075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.665542075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_smoke.2358363961
Short name T377
Test name
Test status
Simulation time 29483958 ps
CPU time 1.28 seconds
Started Oct 12 12:25:00 AM UTC 24
Finished Oct 12 12:25:02 AM UTC 24
Peak memory 208496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358363961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2358363961
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_stress_all.462797023
Short name T402
Test name
Test status
Simulation time 7652769428 ps
CPU time 117.28 seconds
Started Oct 12 12:25:31 AM UTC 24
Finished Oct 12 12:27:31 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462797023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.462797023
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.703138107
Short name T397
Test name
Test status
Simulation time 11221490124 ps
CPU time 85.26 seconds
Started Oct 12 12:25:25 AM UTC 24
Finished Oct 12 12:26:53 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703138107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.703138107
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_alert_test.1104810825
Short name T390
Test name
Test status
Simulation time 51742668 ps
CPU time 0.93 seconds
Started Oct 12 12:26:24 AM UTC 24
Finished Oct 12 12:26:26 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104810825 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1104810825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.2800846173
Short name T394
Test name
Test status
Simulation time 5339300690 ps
CPU time 51.87 seconds
Started Oct 12 12:25:45 AM UTC 24
Finished Oct 12 12:26:38 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800846173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2800846173
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.1002993923
Short name T393
Test name
Test status
Simulation time 625863385 ps
CPU time 41.4 seconds
Started Oct 12 12:25:51 AM UTC 24
Finished Oct 12 12:26:34 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002993923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1002993923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.3475198894
Short name T484
Test name
Test status
Simulation time 11536623305 ps
CPU time 590.68 seconds
Started Oct 12 12:25:45 AM UTC 24
Finished Oct 12 12:35:43 AM UTC 24
Peak memory 655984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475198894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3475198894
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_error.1945318883
Short name T412
Test name
Test status
Simulation time 10454857261 ps
CPU time 134.91 seconds
Started Oct 12 12:25:52 AM UTC 24
Finished Oct 12 12:28:10 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945318883 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1945318883
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_long_msg.1168858978
Short name T386
Test name
Test status
Simulation time 108369432 ps
CPU time 8.27 seconds
Started Oct 12 12:25:42 AM UTC 24
Finished Oct 12 12:25:52 AM UTC 24
Peak memory 209608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168858978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1168858978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_smoke.2352645667
Short name T385
Test name
Test status
Simulation time 1733157624 ps
CPU time 9.18 seconds
Started Oct 12 12:25:40 AM UTC 24
Finished Oct 12 12:25:51 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352645667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2352645667
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_stress_all.4071139494
Short name T474
Test name
Test status
Simulation time 15234271810 ps
CPU time 483.11 seconds
Started Oct 12 12:26:11 AM UTC 24
Finished Oct 12 12:34:20 AM UTC 24
Peak memory 475768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071139494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4071139494
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.3184057075
Short name T99
Test name
Test status
Simulation time 16358378295 ps
CPU time 54.09 seconds
Started Oct 12 12:25:58 AM UTC 24
Finished Oct 12 12:26:54 AM UTC 24
Peak memory 209956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184057075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3184057075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_alert_test.125305264
Short name T178
Test name
Test status
Simulation time 34674556 ps
CPU time 0.93 seconds
Started Oct 12 12:06:53 AM UTC 24
Finished Oct 12 12:06:55 AM UTC 24
Peak memory 206308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125305264 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.125305264
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.184933105
Short name T156
Test name
Test status
Simulation time 818733771 ps
CPU time 17.12 seconds
Started Oct 12 12:06:22 AM UTC 24
Finished Oct 12 12:06:41 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184933105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.184933105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.2466246075
Short name T160
Test name
Test status
Simulation time 2692009359 ps
CPU time 43.12 seconds
Started Oct 12 12:06:23 AM UTC 24
Finished Oct 12 12:07:07 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466246075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2466246075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.1029756230
Short name T66
Test name
Test status
Simulation time 39423954 ps
CPU time 1.4 seconds
Started Oct 12 12:06:22 AM UTC 24
Finished Oct 12 12:06:25 AM UTC 24
Peak memory 217316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029756230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1029756230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_long_msg.1087243058
Short name T172
Test name
Test status
Simulation time 2548114981 ps
CPU time 44.53 seconds
Started Oct 12 12:06:22 AM UTC 24
Finished Oct 12 12:07:08 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087243058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1087243058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.3017503268
Short name T55
Test name
Test status
Simulation time 103749737 ps
CPU time 1.47 seconds
Started Oct 12 12:06:50 AM UTC 24
Finished Oct 12 12:06:52 AM UTC 24
Peak memory 238012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017503268 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3017503268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_stress_all.702373921
Short name T448
Test name
Test status
Simulation time 59763031513 ps
CPU time 1467 seconds
Started Oct 12 12:06:44 AM UTC 24
Finished Oct 12 12:31:27 AM UTC 24
Peak memory 719392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702373921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.702373921
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_stress_all_with_rand_reset.1259324285
Short name T18
Test name
Test status
Simulation time 84524809418 ps
CPU time 155.08 seconds
Started Oct 12 12:06:46 AM UTC 24
Finished Oct 12 12:09:24 AM UTC 24
Peak memory 484144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12593242
85 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1259324285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.399274383
Short name T191
Test name
Test status
Simulation time 15200139135 ps
CPU time 65.96 seconds
Started Oct 12 12:06:42 AM UTC 24
Finished Oct 12 12:07:50 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399274383 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.399274383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.2065341111
Short name T203
Test name
Test status
Simulation time 9916178309 ps
CPU time 116.68 seconds
Started Oct 12 12:06:44 AM UTC 24
Finished Oct 12 12:08:43 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065341111 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2065341111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.1839921443
Short name T194
Test name
Test status
Simulation time 4293663558 ps
CPU time 74 seconds
Started Oct 12 12:06:44 AM UTC 24
Finished Oct 12 12:08:00 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839921443 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1839921443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.2739981978
Short name T151
Test name
Test status
Simulation time 42719032463 ps
CPU time 619.6 seconds
Started Oct 12 12:06:25 AM UTC 24
Finished Oct 12 12:16:53 AM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739981978 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2739981978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.8447825
Short name T508
Test name
Test status
Simulation time 40725498653 ps
CPU time 2342.63 seconds
Started Oct 12 12:06:31 AM UTC 24
Finished Oct 12 12:45:59 AM UTC 24
Peak memory 229748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8447825 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.8447825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.2311996926
Short name T509
Test name
Test status
Simulation time 165801965219 ps
CPU time 2368.94 seconds
Started Oct 12 12:06:42 AM UTC 24
Finished Oct 12 12:46:37 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311996926 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2311996926
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.2635950096
Short name T26
Test name
Test status
Simulation time 5645677624 ps
CPU time 35.45 seconds
Started Oct 12 12:06:24 AM UTC 24
Finished Oct 12 12:07:01 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635950096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2635950096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_alert_test.1218632173
Short name T399
Test name
Test status
Simulation time 14636925 ps
CPU time 0.87 seconds
Started Oct 12 12:26:55 AM UTC 24
Finished Oct 12 12:26:57 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218632173 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1218632173
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.3391329136
Short name T407
Test name
Test status
Simulation time 1114581569 ps
CPU time 70.87 seconds
Started Oct 12 12:26:32 AM UTC 24
Finished Oct 12 12:27:44 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391329136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.3391329136
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.3929225425
Short name T401
Test name
Test status
Simulation time 1138582392 ps
CPU time 22.04 seconds
Started Oct 12 12:26:39 AM UTC 24
Finished Oct 12 12:27:03 AM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929225425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3929225425
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.3959204724
Short name T496
Test name
Test status
Simulation time 17597291332 ps
CPU time 768.32 seconds
Started Oct 12 12:26:35 AM UTC 24
Finished Oct 12 12:39:31 AM UTC 24
Peak memory 760348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959204724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3959204724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_error.352728020
Short name T405
Test name
Test status
Simulation time 754682953 ps
CPU time 56.29 seconds
Started Oct 12 12:26:46 AM UTC 24
Finished Oct 12 12:27:44 AM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352728020 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.352728020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_long_msg.3047583504
Short name T403
Test name
Test status
Simulation time 3732912110 ps
CPU time 58.88 seconds
Started Oct 12 12:26:32 AM UTC 24
Finished Oct 12 12:27:32 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047583504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3047583504
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_smoke.2122518834
Short name T396
Test name
Test status
Simulation time 1327819012 ps
CPU time 19.58 seconds
Started Oct 12 12:26:27 AM UTC 24
Finished Oct 12 12:26:48 AM UTC 24
Peak memory 209700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122518834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2122518834
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_stress_all.3660108085
Short name T533
Test name
Test status
Simulation time 61290396332 ps
CPU time 3819.89 seconds
Started Oct 12 12:26:54 AM UTC 24
Finished Oct 12 01:31:09 AM UTC 24
Peak memory 907892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660108085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3660108085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.2849405418
Short name T418
Test name
Test status
Simulation time 10118051856 ps
CPU time 97.02 seconds
Started Oct 12 12:26:49 AM UTC 24
Finished Oct 12 12:28:28 AM UTC 24
Peak memory 210024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849405418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2849405418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_alert_test.1520393147
Short name T410
Test name
Test status
Simulation time 11226866 ps
CPU time 0.82 seconds
Started Oct 12 12:27:46 AM UTC 24
Finished Oct 12 12:27:48 AM UTC 24
Peak memory 204328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520393147 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1520393147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.2378299134
Short name T413
Test name
Test status
Simulation time 3955442416 ps
CPU time 66.23 seconds
Started Oct 12 12:27:02 AM UTC 24
Finished Oct 12 12:28:10 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378299134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2378299134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.2156047297
Short name T416
Test name
Test status
Simulation time 11926610637 ps
CPU time 45.92 seconds
Started Oct 12 12:27:33 AM UTC 24
Finished Oct 12 12:28:21 AM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156047297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2156047297
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.4191416663
Short name T494
Test name
Test status
Simulation time 7039627994 ps
CPU time 729.51 seconds
Started Oct 12 12:27:03 AM UTC 24
Finished Oct 12 12:39:21 AM UTC 24
Peak memory 764456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191416663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.4191416663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_error.1643355539
Short name T428
Test name
Test status
Simulation time 8972979094 ps
CPU time 99.01 seconds
Started Oct 12 12:27:33 AM UTC 24
Finished Oct 12 12:29:14 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643355539 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1643355539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_long_msg.2244917534
Short name T406
Test name
Test status
Simulation time 8166704145 ps
CPU time 44.62 seconds
Started Oct 12 12:26:58 AM UTC 24
Finished Oct 12 12:27:44 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244917534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2244917534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_smoke.1315272878
Short name T400
Test name
Test status
Simulation time 551658454 ps
CPU time 3.29 seconds
Started Oct 12 12:26:57 AM UTC 24
Finished Oct 12 12:27:01 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315272878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1315272878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_stress_all.2504491579
Short name T529
Test name
Test status
Simulation time 974089239818 ps
CPU time 2567.01 seconds
Started Oct 12 12:27:45 AM UTC 24
Finished Oct 12 01:10:58 AM UTC 24
Peak memory 815660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504491579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2504491579
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.1449959580
Short name T415
Test name
Test status
Simulation time 581701361 ps
CPU time 30.95 seconds
Started Oct 12 12:27:45 AM UTC 24
Finished Oct 12 12:28:18 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449959580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1449959580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_alert_test.1513539424
Short name T417
Test name
Test status
Simulation time 40855093 ps
CPU time 0.85 seconds
Started Oct 12 12:28:19 AM UTC 24
Finished Oct 12 12:28:21 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513539424 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1513539424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.205814523
Short name T414
Test name
Test status
Simulation time 923308483 ps
CPU time 27.46 seconds
Started Oct 12 12:27:48 AM UTC 24
Finished Oct 12 12:28:17 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205814523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.205814523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.2281520408
Short name T424
Test name
Test status
Simulation time 923074281 ps
CPU time 61.45 seconds
Started Oct 12 12:27:51 AM UTC 24
Finished Oct 12 12:28:54 AM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281520408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2281520408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.4187906497
Short name T501
Test name
Test status
Simulation time 21716664631 ps
CPU time 863.77 seconds
Started Oct 12 12:27:49 AM UTC 24
Finished Oct 12 12:42:22 AM UTC 24
Peak memory 733936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187906497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.4187906497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_error.531204464
Short name T422
Test name
Test status
Simulation time 698373081 ps
CPU time 39.16 seconds
Started Oct 12 12:28:12 AM UTC 24
Finished Oct 12 12:28:53 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531204464 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.531204464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_long_msg.1760418552
Short name T446
Test name
Test status
Simulation time 6503741350 ps
CPU time 200.67 seconds
Started Oct 12 12:27:48 AM UTC 24
Finished Oct 12 12:31:12 AM UTC 24
Peak memory 209688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760418552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1760418552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_smoke.1375450607
Short name T411
Test name
Test status
Simulation time 182255755 ps
CPU time 3.1 seconds
Started Oct 12 12:27:46 AM UTC 24
Finished Oct 12 12:27:50 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375450607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1375450607
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_stress_all.3029960392
Short name T531
Test name
Test status
Simulation time 508297222804 ps
CPU time 3071.56 seconds
Started Oct 12 12:28:18 AM UTC 24
Finished Oct 12 01:20:01 AM UTC 24
Peak memory 803372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029960392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3029960392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.2140494637
Short name T440
Test name
Test status
Simulation time 15365230318 ps
CPU time 134.37 seconds
Started Oct 12 12:28:12 AM UTC 24
Finished Oct 12 12:30:29 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140494637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2140494637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_alert_test.1813888585
Short name T425
Test name
Test status
Simulation time 56911090 ps
CPU time 0.91 seconds
Started Oct 12 12:28:55 AM UTC 24
Finished Oct 12 12:28:57 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813888585 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1813888585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.674064931
Short name T423
Test name
Test status
Simulation time 6016412414 ps
CPU time 21.88 seconds
Started Oct 12 12:28:30 AM UTC 24
Finished Oct 12 12:28:53 AM UTC 24
Peak memory 209692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674064931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.674064931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.28042844
Short name T431
Test name
Test status
Simulation time 3820835396 ps
CPU time 50.64 seconds
Started Oct 12 12:28:35 AM UTC 24
Finished Oct 12 12:29:27 AM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28042844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.28042844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.1379141968
Short name T478
Test name
Test status
Simulation time 1806161001 ps
CPU time 364.51 seconds
Started Oct 12 12:28:35 AM UTC 24
Finished Oct 12 12:34:43 AM UTC 24
Peak memory 713328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379141968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1379141968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_error.112565359
Short name T462
Test name
Test status
Simulation time 34582853270 ps
CPU time 268.23 seconds
Started Oct 12 12:28:39 AM UTC 24
Finished Oct 12 12:33:11 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112565359 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.112565359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_long_msg.899126703
Short name T427
Test name
Test status
Simulation time 753544019 ps
CPU time 44.26 seconds
Started Oct 12 12:28:22 AM UTC 24
Finished Oct 12 12:29:08 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899126703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.899126703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_smoke.3772270679
Short name T420
Test name
Test status
Simulation time 1838109682 ps
CPU time 11.44 seconds
Started Oct 12 12:28:21 AM UTC 24
Finished Oct 12 12:28:34 AM UTC 24
Peak memory 209876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772270679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3772270679
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_stress_all.580239564
Short name T495
Test name
Test status
Simulation time 40509229511 ps
CPU time 624.81 seconds
Started Oct 12 12:28:54 AM UTC 24
Finished Oct 12 12:39:27 AM UTC 24
Peak memory 451076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580239564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.580239564
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.935300664
Short name T435
Test name
Test status
Simulation time 15903486393 ps
CPU time 55 seconds
Started Oct 12 12:28:54 AM UTC 24
Finished Oct 12 12:29:51 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935300664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.935300664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_alert_test.2505615465
Short name T434
Test name
Test status
Simulation time 15104959 ps
CPU time 0.96 seconds
Started Oct 12 12:29:40 AM UTC 24
Finished Oct 12 12:29:42 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505615465 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2505615465
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.2098948793
Short name T430
Test name
Test status
Simulation time 448875756 ps
CPU time 9.8 seconds
Started Oct 12 12:29:09 AM UTC 24
Finished Oct 12 12:29:20 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098948793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2098948793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.500294192
Short name T436
Test name
Test status
Simulation time 1690966649 ps
CPU time 37.54 seconds
Started Oct 12 12:29:21 AM UTC 24
Finished Oct 12 12:30:00 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500294192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.500294192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.536133241
Short name T471
Test name
Test status
Simulation time 1875488130 ps
CPU time 296.48 seconds
Started Oct 12 12:29:16 AM UTC 24
Finished Oct 12 12:34:16 AM UTC 24
Peak memory 670188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536133241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.536133241
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_error.993905473
Short name T438
Test name
Test status
Simulation time 602183758 ps
CPU time 42.4 seconds
Started Oct 12 12:29:21 AM UTC 24
Finished Oct 12 12:30:05 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993905473 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.993905473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_long_msg.2070903771
Short name T432
Test name
Test status
Simulation time 1205117367 ps
CPU time 26.61 seconds
Started Oct 12 12:29:02 AM UTC 24
Finished Oct 12 12:29:30 AM UTC 24
Peak memory 209628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070903771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2070903771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_smoke.363927224
Short name T429
Test name
Test status
Simulation time 1241879418 ps
CPU time 20.75 seconds
Started Oct 12 12:28:58 AM UTC 24
Finished Oct 12 12:29:20 AM UTC 24
Peak memory 209908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363927224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.363927224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_stress_all.4002123288
Short name T519
Test name
Test status
Simulation time 44738875081 ps
CPU time 1346.92 seconds
Started Oct 12 12:29:31 AM UTC 24
Finished Oct 12 12:52:11 AM UTC 24
Peak memory 786932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002123288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.4002123288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.352018507
Short name T449
Test name
Test status
Simulation time 10268228333 ps
CPU time 122.7 seconds
Started Oct 12 12:29:27 AM UTC 24
Finished Oct 12 12:31:32 AM UTC 24
Peak memory 209936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352018507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.352018507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_alert_test.1040465564
Short name T442
Test name
Test status
Simulation time 12916578 ps
CPU time 0.83 seconds
Started Oct 12 12:30:46 AM UTC 24
Finished Oct 12 12:30:47 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040465564 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1040465564
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.1436682463
Short name T22
Test name
Test status
Simulation time 4927317449 ps
CPU time 71.19 seconds
Started Oct 12 12:30:01 AM UTC 24
Finished Oct 12 12:31:14 AM UTC 24
Peak memory 218324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436682463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1436682463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.2728195441
Short name T445
Test name
Test status
Simulation time 8709649918 ps
CPU time 63.12 seconds
Started Oct 12 12:30:06 AM UTC 24
Finished Oct 12 12:31:11 AM UTC 24
Peak memory 209748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728195441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2728195441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.4125929851
Short name T464
Test name
Test status
Simulation time 1993361155 ps
CPU time 210.23 seconds
Started Oct 12 12:30:02 AM UTC 24
Finished Oct 12 12:33:35 AM UTC 24
Peak memory 713192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125929851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.4125929851
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_error.3838550924
Short name T444
Test name
Test status
Simulation time 12203700921 ps
CPU time 44.79 seconds
Started Oct 12 12:30:18 AM UTC 24
Finished Oct 12 12:31:05 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838550924 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3838550924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_long_msg.5134700
Short name T454
Test name
Test status
Simulation time 3629008960 ps
CPU time 123.76 seconds
Started Oct 12 12:29:52 AM UTC 24
Finished Oct 12 12:31:58 AM UTC 24
Peak memory 209832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5134700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.5134700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_smoke.2970903726
Short name T437
Test name
Test status
Simulation time 856504536 ps
CPU time 16.06 seconds
Started Oct 12 12:29:43 AM UTC 24
Finished Oct 12 12:30:01 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970903726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2970903726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_stress_all.102177253
Short name T527
Test name
Test status
Simulation time 106316751397 ps
CPU time 2009.59 seconds
Started Oct 12 12:30:37 AM UTC 24
Finished Oct 12 01:04:26 AM UTC 24
Peak memory 717372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102177253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.102177253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.842725563
Short name T453
Test name
Test status
Simulation time 5151997466 ps
CPU time 75.61 seconds
Started Oct 12 12:30:31 AM UTC 24
Finished Oct 12 12:31:49 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842725563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.842725563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_alert_test.2838012847
Short name T451
Test name
Test status
Simulation time 14224730 ps
CPU time 0.84 seconds
Started Oct 12 12:31:41 AM UTC 24
Finished Oct 12 12:31:43 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838012847 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2838012847
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.764237869
Short name T455
Test name
Test status
Simulation time 1485892019 ps
CPU time 67.08 seconds
Started Oct 12 12:31:06 AM UTC 24
Finished Oct 12 12:32:15 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764237869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.764237869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.2244288133
Short name T450
Test name
Test status
Simulation time 8527121333 ps
CPU time 21.62 seconds
Started Oct 12 12:31:15 AM UTC 24
Finished Oct 12 12:31:38 AM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244288133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2244288133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.1898896967
Short name T502
Test name
Test status
Simulation time 23807519291 ps
CPU time 678.85 seconds
Started Oct 12 12:31:12 AM UTC 24
Finished Oct 12 12:42:39 AM UTC 24
Peak memory 723440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898896967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1898896967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_error.175859006
Short name T483
Test name
Test status
Simulation time 4140189150 ps
CPU time 247.82 seconds
Started Oct 12 12:31:15 AM UTC 24
Finished Oct 12 12:35:27 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175859006 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.175859006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_long_msg.3990753969
Short name T458
Test name
Test status
Simulation time 1436780459 ps
CPU time 104.36 seconds
Started Oct 12 12:31:04 AM UTC 24
Finished Oct 12 12:32:50 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990753969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3990753969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_smoke.169621079
Short name T443
Test name
Test status
Simulation time 4078211290 ps
CPU time 12.67 seconds
Started Oct 12 12:30:49 AM UTC 24
Finished Oct 12 12:31:03 AM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169621079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.169621079
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_stress_all.479551470
Short name T525
Test name
Test status
Simulation time 983958344143 ps
CPU time 1687.98 seconds
Started Oct 12 12:31:39 AM UTC 24
Finished Oct 12 01:00:05 AM UTC 24
Peak memory 713284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479551470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.479551470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.670493962
Short name T473
Test name
Test status
Simulation time 36183940794 ps
CPU time 157.44 seconds
Started Oct 12 12:31:39 AM UTC 24
Finished Oct 12 12:34:20 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670493962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.670493962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_alert_test.576232095
Short name T459
Test name
Test status
Simulation time 23923224 ps
CPU time 0.88 seconds
Started Oct 12 12:32:52 AM UTC 24
Finished Oct 12 12:32:54 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576232095 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.576232095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.2388071201
Short name T460
Test name
Test status
Simulation time 2182778971 ps
CPU time 69.48 seconds
Started Oct 12 12:31:48 AM UTC 24
Finished Oct 12 12:33:00 AM UTC 24
Peak memory 209812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388071201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2388071201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.2946831880
Short name T456
Test name
Test status
Simulation time 1853019913 ps
CPU time 31.84 seconds
Started Oct 12 12:32:00 AM UTC 24
Finished Oct 12 12:32:33 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946831880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2946831880
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.3350467516
Short name T516
Test name
Test status
Simulation time 16866702954 ps
CPU time 1155.59 seconds
Started Oct 12 12:31:50 AM UTC 24
Finished Oct 12 12:51:18 AM UTC 24
Peak memory 744176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350467516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3350467516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_error.1119937805
Short name T463
Test name
Test status
Simulation time 8059243665 ps
CPU time 74.49 seconds
Started Oct 12 12:32:16 AM UTC 24
Finished Oct 12 12:33:33 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119937805 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1119937805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_long_msg.586213723
Short name T470
Test name
Test status
Simulation time 14222927920 ps
CPU time 141.55 seconds
Started Oct 12 12:31:44 AM UTC 24
Finished Oct 12 12:34:08 AM UTC 24
Peak memory 209784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586213723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.586213723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_smoke.632083583
Short name T452
Test name
Test status
Simulation time 938328864 ps
CPU time 5.74 seconds
Started Oct 12 12:31:41 AM UTC 24
Finished Oct 12 12:31:48 AM UTC 24
Peak memory 209900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632083583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.632083583
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_stress_all.3253271898
Short name T490
Test name
Test status
Simulation time 114270493988 ps
CPU time 279.07 seconds
Started Oct 12 12:32:39 AM UTC 24
Finished Oct 12 12:37:22 AM UTC 24
Peak memory 209964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253271898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3253271898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.2106284133
Short name T465
Test name
Test status
Simulation time 19031378318 ps
CPU time 63.02 seconds
Started Oct 12 12:32:33 AM UTC 24
Finished Oct 12 12:33:38 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106284133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2106284133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_alert_test.2827348928
Short name T467
Test name
Test status
Simulation time 19267680 ps
CPU time 0.88 seconds
Started Oct 12 12:33:49 AM UTC 24
Finished Oct 12 12:33:52 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827348928 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2827348928
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.1057914257
Short name T468
Test name
Test status
Simulation time 1660235428 ps
CPU time 58.47 seconds
Started Oct 12 12:33:05 AM UTC 24
Finished Oct 12 12:34:05 AM UTC 24
Peak memory 209636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057914257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1057914257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.3170154418
Short name T466
Test name
Test status
Simulation time 7618780665 ps
CPU time 34.22 seconds
Started Oct 12 12:33:13 AM UTC 24
Finished Oct 12 12:33:49 AM UTC 24
Peak memory 218404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170154418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3170154418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.2312279727
Short name T500
Test name
Test status
Simulation time 11694927732 ps
CPU time 518.87 seconds
Started Oct 12 12:33:09 AM UTC 24
Finished Oct 12 12:41:54 AM UTC 24
Peak memory 717292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312279727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2312279727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_error.3820740105
Short name T487
Test name
Test status
Simulation time 13780250934 ps
CPU time 169.64 seconds
Started Oct 12 12:33:34 AM UTC 24
Finished Oct 12 12:36:28 AM UTC 24
Peak memory 209752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820740105 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3820740105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_long_msg.2350980655
Short name T472
Test name
Test status
Simulation time 5238251755 ps
CPU time 75.67 seconds
Started Oct 12 12:33:01 AM UTC 24
Finished Oct 12 12:34:19 AM UTC 24
Peak memory 210028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350980655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2350980655
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_smoke.1122141943
Short name T461
Test name
Test status
Simulation time 600181155 ps
CPU time 11.66 seconds
Started Oct 12 12:32:55 AM UTC 24
Finished Oct 12 12:33:08 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122141943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1122141943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_stress_all.3465159707
Short name T514
Test name
Test status
Simulation time 76222109981 ps
CPU time 955.09 seconds
Started Oct 12 12:33:39 AM UTC 24
Finished Oct 12 12:49:45 AM UTC 24
Peak memory 504316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465159707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3465159707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.607559068
Short name T476
Test name
Test status
Simulation time 8841448240 ps
CPU time 52.3 seconds
Started Oct 12 12:33:37 AM UTC 24
Finished Oct 12 12:34:31 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607559068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.607559068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_alert_test.463849981
Short name T477
Test name
Test status
Simulation time 192462273 ps
CPU time 0.83 seconds
Started Oct 12 12:34:33 AM UTC 24
Finished Oct 12 12:34:35 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463849981 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.463849981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.2681774015
Short name T482
Test name
Test status
Simulation time 1005867557 ps
CPU time 72.4 seconds
Started Oct 12 12:34:08 AM UTC 24
Finished Oct 12 12:35:23 AM UTC 24
Peak memory 209644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681774015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2681774015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.541609267
Short name T481
Test name
Test status
Simulation time 5445371409 ps
CPU time 49.95 seconds
Started Oct 12 12:34:20 AM UTC 24
Finished Oct 12 12:35:12 AM UTC 24
Peak memory 218412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541609267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.541609267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.2488561186
Short name T485
Test name
Test status
Simulation time 2358635315 ps
CPU time 110.97 seconds
Started Oct 12 12:34:10 AM UTC 24
Finished Oct 12 12:36:03 AM UTC 24
Peak memory 395944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488561186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2488561186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_error.4247273159
Short name T488
Test name
Test status
Simulation time 7154098878 ps
CPU time 113.46 seconds
Started Oct 12 12:34:33 AM UTC 24
Finished Oct 12 12:36:29 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247273159 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4247273159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_long_msg.1155315519
Short name T479
Test name
Test status
Simulation time 2785721105 ps
CPU time 39.48 seconds
Started Oct 12 12:34:06 AM UTC 24
Finished Oct 12 12:34:47 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155315519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1155315519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_smoke.3817067275
Short name T469
Test name
Test status
Simulation time 1581549478 ps
CPU time 13.17 seconds
Started Oct 12 12:33:53 AM UTC 24
Finished Oct 12 12:34:07 AM UTC 24
Peak memory 209844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817067275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3817067275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_stress_all.3164184806
Short name T523
Test name
Test status
Simulation time 33098748034 ps
CPU time 1260.12 seconds
Started Oct 12 12:34:33 AM UTC 24
Finished Oct 12 12:55:47 AM UTC 24
Peak memory 717432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164184806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3164184806
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.1323370663
Short name T486
Test name
Test status
Simulation time 17361174118 ps
CPU time 106.19 seconds
Started Oct 12 12:34:33 AM UTC 24
Finished Oct 12 12:36:22 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323370663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1323370663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_alert_test.938198978
Short name T181
Test name
Test status
Simulation time 45012459 ps
CPU time 0.9 seconds
Started Oct 12 12:07:14 AM UTC 24
Finished Oct 12 12:07:16 AM UTC 24
Peak memory 206368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938198978 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.938198978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.139739021
Short name T89
Test name
Test status
Simulation time 1334270728 ps
CPU time 101.62 seconds
Started Oct 12 12:07:09 AM UTC 24
Finished Oct 12 12:08:52 AM UTC 24
Peak memory 209664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139739021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.139739021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.1073678767
Short name T159
Test name
Test status
Simulation time 5088641358 ps
CPU time 32.25 seconds
Started Oct 12 12:07:09 AM UTC 24
Finished Oct 12 12:07:42 AM UTC 24
Peak memory 218348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073678767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1073678767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.2065754623
Short name T146
Test name
Test status
Simulation time 1583637871 ps
CPU time 271.74 seconds
Started Oct 12 12:07:09 AM UTC 24
Finished Oct 12 12:11:44 AM UTC 24
Peak memory 682748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065754623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2065754623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_error.958349581
Short name T217
Test name
Test status
Simulation time 39120253441 ps
CPU time 200.23 seconds
Started Oct 12 12:07:09 AM UTC 24
Finished Oct 12 12:10:32 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958349581 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.958349581
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_long_msg.26056013
Short name T189
Test name
Test status
Simulation time 3315009108 ps
CPU time 44.87 seconds
Started Oct 12 12:07:02 AM UTC 24
Finished Oct 12 12:07:49 AM UTC 24
Peak memory 209912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26056013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.26056013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_smoke.3227755009
Short name T154
Test name
Test status
Simulation time 758725463 ps
CPU time 14.92 seconds
Started Oct 12 12:06:56 AM UTC 24
Finished Oct 12 12:07:12 AM UTC 24
Peak memory 209680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227755009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3227755009
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_stress_all.334455763
Short name T72
Test name
Test status
Simulation time 80387400239 ps
CPU time 1674.08 seconds
Started Oct 12 12:07:11 AM UTC 24
Finished Oct 12 12:35:23 AM UTC 24
Peak memory 686712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334455763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.334455763
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.702930080
Short name T173
Test name
Test status
Simulation time 1262711610 ps
CPU time 33.48 seconds
Started Oct 12 12:07:11 AM UTC 24
Finished Oct 12 12:07:46 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702930080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.702930080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_alert_test.219744787
Short name T188
Test name
Test status
Simulation time 16286234 ps
CPU time 0.96 seconds
Started Oct 12 12:07:43 AM UTC 24
Finished Oct 12 12:07:45 AM UTC 24
Peak memory 206308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219744787 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.219744787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.3265417301
Short name T187
Test name
Test status
Simulation time 1740347583 ps
CPU time 23.19 seconds
Started Oct 12 12:07:20 AM UTC 24
Finished Oct 12 12:07:45 AM UTC 24
Peak memory 209640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265417301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3265417301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.746102007
Short name T155
Test name
Test status
Simulation time 15109489571 ps
CPU time 47.47 seconds
Started Oct 12 12:07:25 AM UTC 24
Finished Oct 12 12:08:14 AM UTC 24
Peak memory 218264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746102007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.746102007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.3551177380
Short name T306
Test name
Test status
Simulation time 8235271649 ps
CPU time 659.29 seconds
Started Oct 12 12:07:20 AM UTC 24
Finished Oct 12 12:18:27 AM UTC 24
Peak memory 518772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551177380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3551177380
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_error.745120966
Short name T193
Test name
Test status
Simulation time 9697750264 ps
CPU time 33.3 seconds
Started Oct 12 12:07:25 AM UTC 24
Finished Oct 12 12:08:00 AM UTC 24
Peak memory 209648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745120966 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.745120966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_long_msg.1423730692
Short name T175
Test name
Test status
Simulation time 21157393360 ps
CPU time 41.77 seconds
Started Oct 12 12:07:16 AM UTC 24
Finished Oct 12 12:07:59 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423730692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1423730692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_smoke.1539262130
Short name T184
Test name
Test status
Simulation time 384446866 ps
CPU time 7.46 seconds
Started Oct 12 12:07:15 AM UTC 24
Finished Oct 12 12:07:24 AM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539262130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1539262130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_stress_all.3557294478
Short name T524
Test name
Test status
Simulation time 57595069908 ps
CPU time 2892.43 seconds
Started Oct 12 12:07:33 AM UTC 24
Finished Oct 12 12:56:16 AM UTC 24
Peak memory 805464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557294478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3557294478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.377681072
Short name T87
Test name
Test status
Simulation time 15104347049 ps
CPU time 77.43 seconds
Started Oct 12 12:07:32 AM UTC 24
Finished Oct 12 12:08:51 AM UTC 24
Peak memory 209764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377681072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.377681072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_alert_test.1558459864
Short name T192
Test name
Test status
Simulation time 35325923 ps
CPU time 0.91 seconds
Started Oct 12 12:07:55 AM UTC 24
Finished Oct 12 12:07:58 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558459864 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1558459864
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.3816284876
Short name T199
Test name
Test status
Simulation time 719065244 ps
CPU time 38.31 seconds
Started Oct 12 12:07:48 AM UTC 24
Finished Oct 12 12:08:27 AM UTC 24
Peak memory 209888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816284876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3816284876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.3410480616
Short name T161
Test name
Test status
Simulation time 35456323898 ps
CPU time 32.8 seconds
Started Oct 12 12:07:52 AM UTC 24
Finished Oct 12 12:08:27 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410480616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3410480616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.807599204
Short name T39
Test name
Test status
Simulation time 222063510 ps
CPU time 20.25 seconds
Started Oct 12 12:07:50 AM UTC 24
Finished Oct 12 12:08:12 AM UTC 24
Peak memory 242076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807599204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.807599204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_error.1810955462
Short name T202
Test name
Test status
Simulation time 2017281469 ps
CPU time 46.25 seconds
Started Oct 12 12:07:52 AM UTC 24
Finished Oct 12 12:08:40 AM UTC 24
Peak memory 209892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810955462 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1810955462
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_long_msg.2204931801
Short name T78
Test name
Test status
Simulation time 22700091901 ps
CPU time 104.01 seconds
Started Oct 12 12:07:46 AM UTC 24
Finished Oct 12 12:09:33 AM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204931801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2204931801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_smoke.2159159553
Short name T145
Test name
Test status
Simulation time 1898831592 ps
CPU time 6.93 seconds
Started Oct 12 12:07:46 AM UTC 24
Finished Oct 12 12:07:55 AM UTC 24
Peak memory 209616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159159553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2159159553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_stress_all.3439080123
Short name T491
Test name
Test status
Simulation time 32026704260 ps
CPU time 1786.65 seconds
Started Oct 12 12:07:55 AM UTC 24
Finished Oct 12 12:38:01 AM UTC 24
Peak memory 739888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439080123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3439080123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/7.hmac_stress_all_with_rand_reset.4229593469
Short name T19
Test name
Test status
Simulation time 13347272781 ps
CPU time 459.07 seconds
Started Oct 12 12:07:55 AM UTC 24
Finished Oct 12 12:15:41 AM UTC 24
Peak memory 702996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42295934
69 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.4229593469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_alert_test.2488906910
Short name T195
Test name
Test status
Simulation time 41430718 ps
CPU time 0.88 seconds
Started Oct 12 12:08:13 AM UTC 24
Finished Oct 12 12:08:15 AM UTC 24
Peak memory 206164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488906910 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2488906910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.2941390357
Short name T196
Test name
Test status
Simulation time 281964578 ps
CPU time 16.22 seconds
Started Oct 12 12:07:59 AM UTC 24
Finished Oct 12 12:08:16 AM UTC 24
Peak memory 209672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941390357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2941390357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.617712640
Short name T197
Test name
Test status
Simulation time 3985878554 ps
CPU time 15.15 seconds
Started Oct 12 12:08:00 AM UTC 24
Finished Oct 12 12:08:17 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617712640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.617712640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.1243973372
Short name T480
Test name
Test status
Simulation time 7531698299 ps
CPU time 1609.99 seconds
Started Oct 12 12:08:00 AM UTC 24
Finished Oct 12 12:35:06 AM UTC 24
Peak memory 782936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243973372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1243973372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_error.933814238
Short name T223
Test name
Test status
Simulation time 12183092101 ps
CPU time 168.62 seconds
Started Oct 12 12:08:02 AM UTC 24
Finished Oct 12 12:10:54 AM UTC 24
Peak memory 209756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933814238 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.933814238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_long_msg.3855692984
Short name T226
Test name
Test status
Simulation time 39290291226 ps
CPU time 187.44 seconds
Started Oct 12 12:07:59 AM UTC 24
Finished Oct 12 12:11:10 AM UTC 24
Peak memory 209712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855692984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3855692984
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_smoke.3512348304
Short name T148
Test name
Test status
Simulation time 733857441 ps
CPU time 3.46 seconds
Started Oct 12 12:07:57 AM UTC 24
Finished Oct 12 12:08:02 AM UTC 24
Peak memory 209704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512348304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3512348304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_stress_all.3579828885
Short name T67
Test name
Test status
Simulation time 264807797312 ps
CPU time 866.53 seconds
Started Oct 12 12:08:07 AM UTC 24
Finished Oct 12 12:22:44 AM UTC 24
Peak memory 209760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579828885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3579828885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.4281047844
Short name T91
Test name
Test status
Simulation time 3380615399 ps
CPU time 54.24 seconds
Started Oct 12 12:08:02 AM UTC 24
Finished Oct 12 12:08:58 AM UTC 24
Peak memory 209716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281047844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.4281047844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2451502227
Short name T201
Test name
Test status
Simulation time 20429405 ps
CPU time 0.92 seconds
Started Oct 12 12:08:29 AM UTC 24
Finished Oct 12 12:08:31 AM UTC 24
Peak memory 206376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451502227 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2451502227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.1750937821
Short name T200
Test name
Test status
Simulation time 999726970 ps
CPU time 10.18 seconds
Started Oct 12 12:08:17 AM UTC 24
Finished Oct 12 12:08:29 AM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750937821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1750937821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.388134598
Short name T176
Test name
Test status
Simulation time 18925684860 ps
CPU time 55.6 seconds
Started Oct 12 12:08:17 AM UTC 24
Finished Oct 12 12:09:14 AM UTC 24
Peak memory 218384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388134598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.388134598
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.3092336950
Short name T324
Test name
Test status
Simulation time 11697652582 ps
CPU time 694.53 seconds
Started Oct 12 12:08:17 AM UTC 24
Finished Oct 12 12:19:59 AM UTC 24
Peak memory 737840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092336950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3092336950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_error.1985849174
Short name T80
Test name
Test status
Simulation time 984778605 ps
CPU time 70.37 seconds
Started Oct 12 12:08:28 AM UTC 24
Finished Oct 12 12:09:40 AM UTC 24
Peak memory 209768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985849174 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1985849174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_long_msg.60632461
Short name T205
Test name
Test status
Simulation time 1035607887 ps
CPU time 48.37 seconds
Started Oct 12 12:08:17 AM UTC 24
Finished Oct 12 12:09:07 AM UTC 24
Peak memory 209696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60632461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.60632461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_smoke.489645818
Short name T198
Test name
Test status
Simulation time 3049248842 ps
CPU time 10.36 seconds
Started Oct 12 12:08:15 AM UTC 24
Finished Oct 12 12:08:26 AM UTC 24
Peak memory 209960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489645818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.489645818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_stress_all.1959048104
Short name T100
Test name
Test status
Simulation time 64313065939 ps
CPU time 1316.2 seconds
Started Oct 12 12:08:29 AM UTC 24
Finished Oct 12 12:30:40 AM UTC 24
Peak memory 715256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959048104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1959048104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.3440009064
Short name T27
Test name
Test status
Simulation time 65187787701 ps
CPU time 602.73 seconds
Started Oct 12 12:08:29 AM UTC 24
Finished Oct 12 12:18:39 AM UTC 24
Peak memory 713500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34400090
64 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3440009064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.2742603085
Short name T204
Test name
Test status
Simulation time 9853376945 ps
CPU time 14.7 seconds
Started Oct 12 12:08:28 AM UTC 24
Finished Oct 12 12:08:44 AM UTC 24
Peak memory 209776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742603085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2742603085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/hmac-sim-vcs/9.hmac_wipe_secret/latest
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