Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7104704	1			T28	1		T30	8		T69	8
all_values[1]	7104704	1			T28	1		T30	8		T69	8
all_values[2]	7104704	1			T28	1		T30	8		T69	8
all_values[3]	7104704	1			T28	1		T30	8		T69	8
all_values[4]	7104704	1			T28	1		T30	8		T69	8
all_values[5]	7104704	1			T28	1		T30	8		T69	8
all_values[6]	7104704	1			T28	1		T30	8		T69	8
all_values[7]	7104704	1			T28	1		T30	8		T69	8
all_values[8]	7104704	1			T28	1		T30	8		T69	8
all_values[9]	7104704	1			T28	1		T30	8		T69	8
all_values[10]	7104704	1			T28	1		T30	8		T69	8
all_values[11]	7104704	1			T28	1		T30	8		T69	8
all_values[12]	7104704	1			T28	1		T30	8		T69	8
all_values[13]	7104704	1			T28	1		T30	8		T69	8
all_values[14]	7104704	1			T28	1		T30	8		T69	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101133093

1

T28

15

T30

78

T69

68

auto[1]

5437467

1

T30

42

T69

52

T70

53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100592694

1

T28

15

T30

24

T69

8

auto[1]

5977866

1

T30

96

T69

112

T70

108

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	6030821	1			T28	1		T30	1		T1	3
all_values[0]	auto[0]	auto[1]	230752	1			T30	6		T69	4		T70	6
all_values[0]	auto[1]	auto[0]	772888	1			T7	1		T8	1		T9	5
all_values[0]	auto[1]	auto[1]	70243	1			T30	1		T69	4		T70	2
all_values[1]	auto[0]	auto[0]	6075681	1			T28	1		T30	1		T70	3
all_values[1]	auto[0]	auto[1]	414091	1			T30	5		T69	4		T70	1
all_values[1]	auto[1]	auto[0]	571098	1			T9	88		T10	4591		T41	205
all_values[1]	auto[1]	auto[1]	43834	1			T30	2		T69	4		T70	4
all_values[2]	auto[0]	auto[0]	6666025	1			T28	1		T69	3		T70	1
all_values[2]	auto[0]	auto[1]	438500	1			T30	2		T69	1		T70	7
all_values[2]	auto[1]	auto[1]	179	1			T30	6		T69	4		T91	1
all_values[3]	auto[0]	auto[0]	6747330	1			T28	1		T30	4		T1	3
all_values[3]	auto[0]	auto[1]	357194	1			T30	1		T69	6		T70	3
all_values[3]	auto[1]	auto[1]	180	1			T30	3		T69	2		T70	5
all_values[4]	auto[0]	auto[0]	6722392	1			T28	1		T30	2		T91	1
all_values[4]	auto[0]	auto[1]	382100	1			T30	5		T69	4		T70	1
all_values[4]	auto[1]	auto[0]	20	1			T53	20		-	-		-	-
all_values[4]	auto[1]	auto[1]	192	1			T30	1		T69	4		T70	7
all_values[5]	auto[0]	auto[0]	6682836	1			T28	1		T30	1		T70	1
all_values[5]	auto[0]	auto[1]	421671	1			T30	3		T69	7		T70	1
all_values[5]	auto[1]	auto[1]	197	1			T30	4		T69	1		T70	6
all_values[6]	auto[0]	auto[0]	5930527	1			T28	1		T30	1		T70	4
all_values[6]	auto[0]	auto[1]	276571	1			T30	2		T69	3		T70	1
all_values[6]	auto[1]	auto[0]	825357	1			T7	1		T8	2		T9	40
all_values[6]	auto[1]	auto[1]	72249	1			T30	5		T69	5		T70	3
all_values[7]	auto[0]	auto[0]	6396324	1			T28	1		T91	1		T1	3
all_values[7]	auto[0]	auto[1]	379540	1			T30	4		T69	1		T70	5
all_values[7]	auto[1]	auto[0]	306557	1			T7	1		T8	1136		T9	1614
all_values[7]	auto[1]	auto[1]	22283	1			T30	4		T69	7		T70	3
all_values[8]	auto[0]	auto[0]	5651851	1			T28	1		T30	1		T70	1
all_values[8]	auto[0]	auto[1]	373334	1			T30	7		T69	5		T70	4
all_values[8]	auto[1]	auto[0]	1000134	1			T7	1		T8	357		T9	546
all_values[8]	auto[1]	auto[1]	79385	1			T69	3		T70	3		T91	3
all_values[9]	auto[0]	auto[0]	5675138	1			T28	1		T30	3		T69	2
all_values[9]	auto[0]	auto[1]	360050	1			T30	1		T69	4		T70	5
all_values[9]	auto[1]	auto[0]	998495	1			T1	1		T2	1		T7	1
all_values[9]	auto[1]	auto[1]	71021	1			T30	4		T69	2		T70	2
all_values[10]	auto[0]	auto[0]	6504193	1			T28	1		T91	1		T1	3
all_values[10]	auto[0]	auto[1]	452544	1			T30	4		T69	4		T70	3
all_values[10]	auto[1]	auto[0]	147780	1			T17	2082		T18	2115		T19	2397
all_values[10]	auto[1]	auto[1]	187	1			T30	4		T69	4		T70	5
all_values[11]	auto[0]	auto[0]	6298470	1			T28	1		T30	2		T1	3
all_values[11]	auto[0]	auto[1]	351596	1			T30	4		T69	2		T70	8
all_values[11]	auto[1]	auto[0]	454471	1			T17	3755		T18	4560		T19	6864
all_values[11]	auto[1]	auto[1]	167	1			T30	2		T69	6		T91	3
all_values[12]	auto[0]	auto[0]	6747356	1			T28	1		T30	3		T69	2
all_values[12]	auto[0]	auto[1]	357190	1			T30	3		T69	4		T70	2
all_values[12]	auto[1]	auto[1]	158	1			T30	2		T69	2		T70	5
all_values[13]	auto[0]	auto[0]	6711717	1			T28	1		T30	5		T91	2
all_values[13]	auto[0]	auto[1]	392798	1			T30	1		T69	6		T70	4
all_values[13]	auto[1]	auto[0]	7	1			T162	1		T163	1		T164	1
all_values[13]	auto[1]	auto[1]	182	1			T30	2		T69	2		T70	4
all_values[14]	auto[0]	auto[0]	6675226	1			T28	1		T69	1		T91	1
all_values[14]	auto[0]	auto[1]	429275	1			T30	6		T69	5		T70	4
all_values[14]	auto[1]	auto[1]	203	1			T30	2		T69	2		T70	4