Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_reset_cg

Group : i2c_env_pkg::i2c_fifo_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.82	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_fifo_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	24	6	18	75.00

Variables for Group i2c_env_pkg::i2c_fifo_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_overflow	2	0	2	100.00	100	1	1	2
cp_acqrst	2	0	2	100.00	100	1	1	2
cp_fmt_overflow	2	1	1	50.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmtrst	2	0	2	100.00	100	1	1	2
cp_rx_overflow	2	1	1	50.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rxrst	2	0	2	100.00	100	1	1	2
cp_tx_overflow	2	0	2	100.00	100	1	1	2
cp_txrst	2	0	2	100.00	100	1	1	2

Crosses for Group i2c_env_pkg::i2c_fifo_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fmt_threshold_cross	4	0	4	100.00	100	1	1	0
cp_rx_threshold_cross	4	0	4	100.00	100	1	1	0
cp_fmt_overflow_cross	4	2	2	50.00	100	1	1	0
cp_rx_overflow_cross	4	2	2	50.00	100	1	1	0
cp_acq_overflow_cross	4	1	3	75.00	100	1	1	0
cp_tx_overflow_cross	4	1	3	75.00	100	1	1	0

Summary for Variable cp_acq_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31244

1

T1

3

T2

6

T3

15

auto[1]

230

1

T32

4

T61

4

T141

3

---

Summary for Variable cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28835

1

T1

2

T2

5

T3

14

auto[1]

2639

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_fmt_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_fmt_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31474

1

T1

3

T2

6

T3

15

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25745

1

T1

3

T2

6

T3

15

auto[1]

5729

1

T7

16

T56

13

T10

22

---

Summary for Variable cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28716

1

T1

2

T2

5

T3

14

auto[1]

2758

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_rx_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31474

1

T1

3

T2

6

T3

15

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27735

1

T1

3

T2

6

T3

15

auto[1]

3739

1

T10

23

T11

14

T13

18

---

Summary for Variable cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29042

1

T1

2

T2

5

T3

14

auto[1]

2432

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_tx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_overflow

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31443

1

T1

3

T2

6

T3

15

auto[1]

31

1

T17

2

T142

1

T143

2

---

Summary for Variable cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28845

1

T1

2

T2

5

T3

14

auto[1]

2629

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_fmt_threshold_cross

Samples crossed: cp_fmt_threshold cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_fmt_threshold_cross

Bins

cp_fmt_threshold

cp_fmtrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23268

1

T1

2

T2

5

T3

14

auto[0]

auto[1]

2477

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

5448

1

T7

16

T56

7

T10

22

auto[1]

auto[1]

281

1

T56

6

T57

9

T58

5

---

Summary for Cross cp_rx_threshold_cross

Samples crossed: cp_rx_threshold cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_rx_threshold_cross

Bins

cp_rx_threshold

cp_rxrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

25323

1

T1

2

T2

5

T3

14

auto[0]

auto[1]

2412

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

3719

1

T10

23

T11

14

T13

18

auto[1]

auto[1]

20

1

T144

1

T145

1

T98

1

---

Summary for Cross cp_fmt_overflow_cross

Samples crossed: cp_fmt_overflow cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cp_fmt_overflow_cross

Element holes

cp_fmt_overflow	cp_fmtrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Covered bins

cp_fmt_overflow

cp_fmtrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

28716

1

T1

2

T2

5

T3

14

auto[0]

auto[1]

2758

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_rx_overflow_cross

Samples crossed: cp_rx_overflow cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cp_rx_overflow_cross

Element holes

cp_rx_overflow	cp_rxrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Covered bins

cp_rx_overflow

cp_rxrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

29042

1

T1

2

T2

5

T3

14

auto[0]

auto[1]

2432

1

T1

1

T2

1

T3

1

---

Summary for Cross cp_acq_overflow_cross

Samples crossed: cp_acq_overflow cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cp_acq_overflow_cross

Uncovered bins

cp_acq_overflow	cp_acqrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_acq_overflow

cp_acqrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

28605

1

T1

2

T2

5

T3

14

auto[0]

auto[1]

2639

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

230

1

T32

4

T61

4

T141

3

---

Summary for Cross cp_tx_overflow_cross

Samples crossed: cp_tx_overflow cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cp_tx_overflow_cross

Uncovered bins

cp_tx_overflow	cp_txrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_tx_overflow

cp_txrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

28814

1

T1

2

T2

5

T3

14

auto[0]

auto[1]

2629

1

T1

1

T2

1

T3

1

auto[1]

auto[0]

31

1

T17

2

T142

1

T143

2