Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7104704	1			T28	1		T30	8		T69	8
all_pins[1]	7104704	1			T28	1		T30	8		T69	8
all_pins[2]	7104704	1			T28	1		T30	8		T69	8
all_pins[3]	7104704	1			T28	1		T30	8		T69	8
all_pins[4]	7104704	1			T28	1		T30	8		T69	8
all_pins[5]	7104704	1			T28	1		T30	8		T69	8
all_pins[6]	7104704	1			T28	1		T30	8		T69	8
all_pins[7]	7104704	1			T28	1		T30	8		T69	8
all_pins[8]	7104704	1			T28	1		T30	8		T69	8
all_pins[9]	7104704	1			T28	1		T30	8		T69	8
all_pins[10]	7104704	1			T28	1		T30	8		T69	8
all_pins[11]	7104704	1			T28	1		T30	8		T69	8
all_pins[12]	7104704	1			T28	1		T30	8		T69	8
all_pins[13]	7104704	1			T28	1		T30	8		T69	8
all_pins[14]	7104704	1			T28	1		T30	8		T69	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	101062035	1			T28	15		T30	104		T69	91
values[0x1]	5508525	1			T30	16		T69	29		T70	26
transitions[0x0=>0x1]	3731188	1			T30	12		T69	19		T70	21
transitions[0x1=>0x0]	3731195	1			T30	13		T69	19		T70	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6261362	1			T28	1		T30	8		T69	6
all_pins[0]	values[0x1]	843342	1			T69	2		T70	1		T91	1
all_pins[0]	transitions[0x0=>0x1]	251023	1			T69	2		T70	1		T91	1
all_pins[0]	transitions[0x1=>0x0]	25042	1			T30	1		T69	3		T70	1
all_pins[1]	values[0x0]	6487343	1			T28	1		T30	7		T69	5
all_pins[1]	values[0x1]	617361	1			T30	1		T69	3		T70	1
all_pins[1]	transitions[0x0=>0x1]	617329	1			T69	1		T70	1		T91	2
all_pins[1]	transitions[0x1=>0x0]	66	1			T30	2		T91	1		T118	3
all_pins[2]	values[0x0]	7104606	1			T28	1		T30	5		T69	6
all_pins[2]	values[0x1]	98	1			T30	3		T69	2		T91	1
all_pins[2]	transitions[0x0=>0x1]	76	1			T30	2		T69	2		T91	1
all_pins[2]	transitions[0x1=>0x0]	68	1			T69	1		T70	5		T11	3
all_pins[3]	values[0x0]	7104614	1			T28	1		T30	7		T69	7
all_pins[3]	values[0x1]	90	1			T30	1		T69	1		T70	5
all_pins[3]	transitions[0x0=>0x1]	64	1			T30	1		T70	2		T11	2
all_pins[3]	transitions[0x1=>0x0]	103	1			T30	1		T69	2		T70	1
all_pins[4]	values[0x0]	7104575	1			T28	1		T30	7		T69	5
all_pins[4]	values[0x1]	129	1			T30	1		T69	3		T70	4
all_pins[4]	transitions[0x0=>0x1]	106	1			T30	1		T69	2		T70	4
all_pins[4]	transitions[0x1=>0x0]	90	1			T30	1		T70	1		T11	3
all_pins[5]	values[0x0]	7104591	1			T28	1		T30	7		T69	7
all_pins[5]	values[0x1]	113	1			T30	1		T69	1		T70	1
all_pins[5]	transitions[0x0=>0x1]	75	1			T30	1		T70	1		T11	3
all_pins[5]	transitions[0x1=>0x0]	900896	1			T30	2		T69	2		T70	1
all_pins[6]	values[0x0]	6203770	1			T28	1		T30	6		T69	5
all_pins[6]	values[0x1]	900934	1			T30	2		T69	3		T70	1
all_pins[6]	transitions[0x0=>0x1]	880286	1			T30	1		T69	1		T70	1
all_pins[6]	transitions[0x1=>0x0]	347397	1			T30	1		T69	2		T70	2
all_pins[7]	values[0x0]	6736659	1			T28	1		T30	6		T69	4
all_pins[7]	values[0x1]	368045	1			T30	2		T69	4		T70	2
all_pins[7]	transitions[0x0=>0x1]	303996	1			T30	2		T69	4		T70	2
all_pins[7]	transitions[0x1=>0x0]	1040940	1			T91	1		T8	82		T9	513
all_pins[8]	values[0x0]	5999715	1			T28	1		T30	8		T69	8
all_pins[8]	values[0x1]	1104989	1			T91	1		T7	1		T8	411
all_pins[8]	transitions[0x0=>0x1]	235974	1			T91	1		T8	411		T9	630
all_pins[8]	transitions[0x1=>0x0]	201436	1			T69	1		T70	1		T91	2
all_pins[9]	values[0x0]	6034253	1			T28	1		T30	8		T69	7
all_pins[9]	values[0x1]	1070451	1			T69	1		T70	1		T91	2
all_pins[9]	transitions[0x0=>0x1]	983576	1			T91	2		T1	1		T2	1
all_pins[9]	transitions[0x1=>0x0]	61268	1			T30	3		T69	2		T70	3
all_pins[10]	values[0x0]	6956561	1			T28	1		T30	5		T69	5
all_pins[10]	values[0x1]	148143	1			T30	3		T69	3		T70	4
all_pins[10]	transitions[0x0=>0x1]	3927	1			T30	3		T69	2		T70	4
all_pins[10]	transitions[0x1=>0x0]	310342	1			T69	2		T91	2		T17	1849
all_pins[11]	values[0x0]	6650146	1			T28	1		T30	8		T69	5
all_pins[11]	values[0x1]	454558	1			T69	3		T91	2		T17	3755
all_pins[11]	transitions[0x0=>0x1]	454547	1			T69	2		T91	2		T17	3755
all_pins[11]	transitions[0x1=>0x0]	69	1			T30	1		T69	1		T70	3
all_pins[12]	values[0x0]	7104624	1			T28	1		T30	7		T69	6
all_pins[12]	values[0x1]	80	1			T30	1		T69	2		T70	3
all_pins[12]	transitions[0x0=>0x1]	61	1			T30	1		T69	2		T70	3
all_pins[12]	transitions[0x1=>0x0]	86	1			T69	1		T70	1		T11	1
all_pins[13]	values[0x0]	7104599	1			T28	1		T30	8		T69	7
all_pins[13]	values[0x1]	105	1			T69	1		T70	1		T11	1
all_pins[13]	transitions[0x0=>0x1]	86	1			T69	1		T11	1		T118	1
all_pins[13]	transitions[0x1=>0x0]	68	1			T30	1		T70	1		T11	1
all_pins[14]	values[0x0]	7104617	1			T28	1		T30	7		T69	8
all_pins[14]	values[0x1]	87	1			T30	1		T70	2		T11	1
all_pins[14]	transitions[0x0=>0x1]	62	1			T70	2		T11	1		T118	2
all_pins[14]	transitions[0x1=>0x0]	843324	1			T69	2		T70	1		T91	1