Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	421	1			T30	7		T69	7		T70	7
all_values[1]	421	1			T30	7		T69	7		T70	7
all_values[2]	421	1			T30	7		T69	7		T70	7
all_values[3]	421	1			T30	7		T69	7		T70	7
all_values[4]	421	1			T30	7		T69	7		T70	7
all_values[5]	421	1			T30	7		T69	7		T70	7
all_values[6]	421	1			T30	7		T69	7		T70	7
all_values[7]	421	1			T30	7		T69	7		T70	7
all_values[8]	421	1			T30	7		T69	7		T70	7
all_values[9]	421	1			T30	7		T69	7		T70	7
all_values[10]	421	1			T30	7		T69	7		T70	7
all_values[11]	421	1			T30	7		T69	7		T70	7
all_values[12]	421	1			T30	7		T69	7		T70	7
all_values[13]	421	1			T30	7		T69	7		T70	7
all_values[14]	421	1			T30	7		T69	7		T70	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3334

1

T30

56

T69

56

T70

47

auto[1]

2981

1

T30

49

T69

49

T70

58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T30

24

T69

8

T70

12

auto[1]

5267

1

T30

81

T69

97

T70

93

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3732

1

T30

62

T69

62

T70

54

auto[1]

2583

1

T30

43

T69

43

T70

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	40	1			T30	1		T173	2		T182	1
all_values[0]	auto[0]	auto[0]	auto[1]	95	1			T30	3		T69	3		T70	1
all_values[0]	auto[0]	auto[1]	auto[0]	25	1			T80	1		T126	1		T138	4
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T30	1		T69	1		T70	4
all_values[0]	auto[1]	auto[0]	auto[1]	94	1			T30	1		T69	2		T70	1
all_values[0]	auto[1]	auto[1]	auto[1]	70	1			T30	1		T69	1		T70	1
all_values[1]	auto[0]	auto[0]	auto[0]	36	1			T30	1		T70	3		T49	1
all_values[1]	auto[0]	auto[0]	auto[1]	78	1			T30	2		T69	1		T70	2
all_values[1]	auto[0]	auto[1]	auto[0]	27	1			T49	2		T149	1		T138	1
all_values[1]	auto[0]	auto[1]	auto[1]	102	1			T30	1		T69	3		T91	2
all_values[1]	auto[1]	auto[0]	auto[1]	89	1			T30	1		T69	1		T70	1
all_values[1]	auto[1]	auto[1]	auto[1]	89	1			T30	2		T69	2		T70	1
all_values[2]	auto[0]	auto[0]	auto[0]	44	1			T69	2		T70	1		T91	1
all_values[2]	auto[0]	auto[0]	auto[1]	93	1			T30	1		T69	1		T91	2
all_values[2]	auto[0]	auto[1]	auto[0]	26	1			T69	1		T11	2		T118	1
all_values[2]	auto[0]	auto[1]	auto[1]	95	1			T30	2		T69	2		T70	5
all_values[2]	auto[1]	auto[0]	auto[1]	83	1			T30	2		T70	1		T11	2
all_values[2]	auto[1]	auto[1]	auto[1]	80	1			T30	2		T69	1		T91	1
all_values[3]	auto[0]	auto[0]	auto[0]	35	1			T30	2		T11	2		T80	1
all_values[3]	auto[0]	auto[0]	auto[1]	100	1			T30	1		T69	3		T91	1
all_values[3]	auto[0]	auto[1]	auto[0]	32	1			T30	2		T118	1		T80	1
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T69	1		T70	3		T11	1
all_values[3]	auto[1]	auto[0]	auto[1]	96	1			T69	2		T70	2		T91	3
all_values[3]	auto[1]	auto[1]	auto[1]	67	1			T30	2		T69	1		T70	2
all_values[4]	auto[0]	auto[0]	auto[0]	55	1			T30	1		T91	1		T126	2
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T11	1		T118	2		T49	2
all_values[4]	auto[0]	auto[1]	auto[0]	22	1			T30	1		T11	1		T49	1
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T30	3		T69	4		T70	2
all_values[4]	auto[1]	auto[0]	auto[1]	77	1			T69	2		T70	3		T91	1
all_values[4]	auto[1]	auto[1]	auto[1]	89	1			T30	2		T69	1		T70	2
all_values[5]	auto[0]	auto[0]	auto[0]	39	1			T30	1		T70	1		T91	1
all_values[5]	auto[0]	auto[0]	auto[1]	66	1			T30	3		T69	2		T70	2
all_values[5]	auto[0]	auto[1]	auto[0]	30	1			T118	1		T119	3		T53	3
all_values[5]	auto[0]	auto[1]	auto[1]	104	1			T69	3		T91	2		T11	2
all_values[5]	auto[1]	auto[0]	auto[1]	96	1			T30	1		T69	2		T70	2
all_values[5]	auto[1]	auto[1]	auto[1]	86	1			T30	2		T70	2		T11	4
all_values[6]	auto[0]	auto[0]	auto[0]	37	1			T30	1		T70	1		T91	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T30	1		T70	2		T91	2
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T70	3		T11	2		T138	1
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T69	1		T11	1		T118	2
all_values[6]	auto[1]	auto[0]	auto[1]	98	1			T30	1		T69	3		T91	1
all_values[6]	auto[1]	auto[1]	auto[1]	81	1			T30	4		T69	3		T70	1
all_values[7]	auto[0]	auto[0]	auto[0]	46	1			T91	1		T11	1		T118	2
all_values[7]	auto[0]	auto[0]	auto[1]	77	1			T30	2		T69	1		T91	2
all_values[7]	auto[0]	auto[1]	auto[0]	30	1			T11	2		T118	3		T49	3
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T30	1		T69	3		T70	2
all_values[7]	auto[1]	auto[0]	auto[1]	102	1			T30	1		T69	2		T70	2
all_values[7]	auto[1]	auto[1]	auto[1]	86	1			T30	3		T69	1		T70	3
all_values[8]	auto[0]	auto[0]	auto[0]	54	1			T30	1		T70	1		T91	1
all_values[8]	auto[0]	auto[0]	auto[1]	81	1			T30	2		T69	2		T70	2
all_values[8]	auto[0]	auto[1]	auto[0]	17	1			T80	1		T126	1		T183	1
all_values[8]	auto[0]	auto[1]	auto[1]	105	1			T30	2		T69	2		T70	2
all_values[8]	auto[1]	auto[0]	auto[1]	96	1			T69	3		T70	2		T118	2
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T30	2		T91	1		T11	1
all_values[9]	auto[0]	auto[0]	auto[0]	40	1			T30	3		T69	2		T70	1
all_values[9]	auto[0]	auto[0]	auto[1]	87	1			T30	1		T69	1		T70	1
all_values[9]	auto[0]	auto[1]	auto[0]	28	1			T118	1		T119	2		T80	1
all_values[9]	auto[0]	auto[1]	auto[1]	87	1			T70	2		T91	1		T118	4
all_values[9]	auto[1]	auto[0]	auto[1]	107	1			T30	3		T69	3		T70	1
all_values[9]	auto[1]	auto[1]	auto[1]	72	1			T69	1		T70	2		T91	1
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T91	1		T126	1		T184	1
all_values[10]	auto[0]	auto[0]	auto[1]	93	1			T30	1		T69	2		T11	3
all_values[10]	auto[0]	auto[1]	auto[0]	26	1			T80	4		T149	1		T126	3
all_values[10]	auto[0]	auto[1]	auto[1]	82	1			T30	2		T69	1		T70	2
all_values[10]	auto[1]	auto[0]	auto[1]	91	1			T30	1		T69	2		T70	2
all_values[10]	auto[1]	auto[1]	auto[1]	96	1			T30	3		T69	2		T70	3
all_values[11]	auto[0]	auto[0]	auto[0]	54	1			T30	1		T53	2		T138	7
all_values[11]	auto[0]	auto[0]	auto[1]	86	1			T69	3		T70	2		T11	1
all_values[11]	auto[0]	auto[1]	auto[0]	27	1			T30	1		T11	2		T80	2
all_values[11]	auto[0]	auto[1]	auto[1]	94	1			T30	3		T69	2		T70	3
all_values[11]	auto[1]	auto[0]	auto[1]	93	1			T30	2		T69	1		T70	1
all_values[11]	auto[1]	auto[1]	auto[1]	67	1			T69	1		T70	1		T91	2
all_values[12]	auto[0]	auto[0]	auto[0]	42	1			T30	2		T69	1		T70	1
all_values[12]	auto[0]	auto[0]	auto[1]	88	1			T30	1		T11	3		T118	4
all_values[12]	auto[0]	auto[1]	auto[0]	41	1			T30	1		T69	1		T118	1
all_values[12]	auto[0]	auto[1]	auto[1]	92	1			T30	1		T69	3		T70	1
all_values[12]	auto[1]	auto[0]	auto[1]	87	1			T30	1		T91	1		T11	2
all_values[12]	auto[1]	auto[1]	auto[1]	71	1			T30	1		T69	2		T70	5
all_values[13]	auto[0]	auto[0]	auto[0]	50	1			T30	4		T91	1		T11	2
all_values[13]	auto[0]	auto[0]	auto[1]	78	1			T30	1		T69	3		T91	1
all_values[13]	auto[0]	auto[1]	auto[0]	19	1			T30	1		T91	1		T118	1
all_values[13]	auto[0]	auto[1]	auto[1]	95	1			T69	2		T70	2		T11	3
all_values[13]	auto[1]	auto[0]	auto[1]	97	1			T30	1		T69	1		T70	4
all_values[13]	auto[1]	auto[1]	auto[1]	82	1			T69	1		T70	1		T118	2
all_values[14]	auto[0]	auto[0]	auto[0]	36	1			T69	1		T91	1		T11	2
all_values[14]	auto[0]	auto[0]	auto[1]	100	1			T30	2		T69	2		T70	1
all_values[14]	auto[0]	auto[1]	auto[0]	31	1			T118	1		T49	3		T119	1
all_values[14]	auto[0]	auto[1]	auto[1]	81	1			T30	1		T69	2		T70	1
all_values[14]	auto[1]	auto[0]	auto[1]	96	1			T30	2		T69	2		T70	3
all_values[14]	auto[1]	auto[1]	auto[1]	77	1			T30	2		T70	2		T91	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal