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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 99.17 96.66 100.00 96.52 98.24 100.00 92.75


Total test records in report: 1476
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T1279 /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3077940215 Jan 07 01:43:54 PM PST 24 Jan 07 01:44:12 PM PST 24 985315556 ps
T1280 /workspace/coverage/default/31.i2c_target_hrst.948865346 Jan 07 01:45:24 PM PST 24 Jan 07 01:46:02 PM PST 24 7838960450 ps
T1281 /workspace/coverage/default/35.i2c_target_timeout.4206918457 Jan 07 01:46:42 PM PST 24 Jan 07 01:47:29 PM PST 24 6678025817 ps
T1282 /workspace/coverage/default/6.i2c_host_perf.1991792399 Jan 07 01:43:14 PM PST 24 Jan 07 01:50:17 PM PST 24 26557960073 ps
T1283 /workspace/coverage/default/40.i2c_host_fifo_overflow.2054585965 Jan 07 01:46:11 PM PST 24 Jan 07 01:53:28 PM PST 24 5939469196 ps
T1284 /workspace/coverage/default/47.i2c_target_stretch.2879962604 Jan 07 01:46:34 PM PST 24 Jan 07 01:48:41 PM PST 24 34021549609 ps
T1285 /workspace/coverage/default/22.i2c_host_override.1575657764 Jan 07 01:45:02 PM PST 24 Jan 07 01:45:25 PM PST 24 90403473 ps
T1286 /workspace/coverage/default/17.i2c_target_intr_smoke.4057505100 Jan 07 01:44:21 PM PST 24 Jan 07 01:44:29 PM PST 24 16696694201 ps
T198 /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3023394436 Jan 07 01:45:10 PM PST 24 Jan 07 01:45:40 PM PST 24 473311331 ps
T1287 /workspace/coverage/default/8.i2c_alert_test.1296500068 Jan 07 01:43:24 PM PST 24 Jan 07 01:43:41 PM PST 24 16223778 ps
T1288 /workspace/coverage/default/21.i2c_host_stress_all.1979726030 Jan 07 01:45:33 PM PST 24 Jan 07 02:18:42 PM PST 24 20449594885 ps
T1289 /workspace/coverage/default/32.i2c_target_hrst.652612826 Jan 07 01:45:00 PM PST 24 Jan 07 01:45:19 PM PST 24 700858742 ps
T1290 /workspace/coverage/default/25.i2c_host_stress_all.1888374597 Jan 07 01:44:41 PM PST 24 Jan 07 01:58:46 PM PST 24 76035559889 ps
T1291 /workspace/coverage/default/26.i2c_host_fifo_full.1340626091 Jan 07 01:45:18 PM PST 24 Jan 07 01:50:30 PM PST 24 3252543867 ps
T1292 /workspace/coverage/default/28.i2c_target_intr_stress_wr.1907283050 Jan 07 01:45:28 PM PST 24 Jan 07 01:46:37 PM PST 24 10968368310 ps
T1293 /workspace/coverage/default/7.i2c_host_mode_toggle.406573316 Jan 07 01:43:16 PM PST 24 Jan 07 01:45:16 PM PST 24 11281222527 ps
T1294 /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1600232900 Jan 07 01:43:09 PM PST 24 Jan 07 01:43:30 PM PST 24 913892293 ps
T1295 /workspace/coverage/default/49.i2c_target_bad_addr.1500066364 Jan 07 01:46:56 PM PST 24 Jan 07 01:47:35 PM PST 24 5934052141 ps
T1296 /workspace/coverage/default/2.i2c_target_intr_stress_wr.153049004 Jan 07 01:43:30 PM PST 24 Jan 07 02:39:31 PM PST 24 48254686300 ps
T1297 /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1534797192 Jan 07 01:46:35 PM PST 24 Jan 07 01:48:15 PM PST 24 10027492743 ps
T1298 /workspace/coverage/default/12.i2c_target_smoke.2456070188 Jan 07 01:44:57 PM PST 24 Jan 07 01:45:30 PM PST 24 992671307 ps
T1299 /workspace/coverage/default/40.i2c_host_stretch_timeout.2584259431 Jan 07 01:46:36 PM PST 24 Jan 07 01:47:28 PM PST 24 1730660558 ps
T1300 /workspace/coverage/default/20.i2c_target_unexp_stop.1406408799 Jan 07 01:45:01 PM PST 24 Jan 07 01:45:25 PM PST 24 2588129657 ps
T1301 /workspace/coverage/default/9.i2c_target_intr_stress_wr.3844984866 Jan 07 01:43:10 PM PST 24 Jan 07 01:43:28 PM PST 24 5225340212 ps
T101 /workspace/coverage/default/18.i2c_host_stress_all_with_rand_reset.1229916501 Jan 07 01:44:59 PM PST 24 Jan 07 01:58:07 PM PST 24 11833007402 ps
T1302 /workspace/coverage/default/12.i2c_target_tx_ovf.612025182 Jan 07 01:44:05 PM PST 24 Jan 07 01:45:54 PM PST 24 5937549635 ps
T1303 /workspace/coverage/default/39.i2c_host_smoke.2203083208 Jan 07 01:45:55 PM PST 24 Jan 07 01:47:07 PM PST 24 5925898601 ps
T1304 /workspace/coverage/default/17.i2c_target_perf.3614911269 Jan 07 01:44:03 PM PST 24 Jan 07 01:44:16 PM PST 24 14720212755 ps
T1305 /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3654743684 Jan 07 01:45:00 PM PST 24 Jan 07 01:45:42 PM PST 24 514049579 ps
T1306 /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3627907209 Jan 07 01:45:50 PM PST 24 Jan 07 01:46:40 PM PST 24 1090964948 ps
T1307 /workspace/coverage/default/1.i2c_host_perf.1160298903 Jan 07 01:43:08 PM PST 24 Jan 07 01:43:25 PM PST 24 2809596835 ps
T1308 /workspace/coverage/default/15.i2c_host_rx_oversample.3454696525 Jan 07 01:43:54 PM PST 24 Jan 07 01:45:18 PM PST 24 8844164413 ps
T1309 /workspace/coverage/default/14.i2c_host_error_intr.436857284 Jan 07 01:44:38 PM PST 24 Jan 07 01:44:41 PM PST 24 91944764 ps
T1310 /workspace/coverage/default/15.i2c_target_stress_rd.1492032114 Jan 07 01:43:52 PM PST 24 Jan 07 01:44:18 PM PST 24 2030359666 ps
T1311 /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3123731170 Jan 07 01:45:54 PM PST 24 Jan 07 01:46:37 PM PST 24 524823005 ps
T1312 /workspace/coverage/default/30.i2c_host_fifo_overflow.3155701073 Jan 07 01:45:02 PM PST 24 Jan 07 01:56:13 PM PST 24 10061848644 ps
T1313 /workspace/coverage/default/34.i2c_target_timeout.3844442282 Jan 07 01:45:33 PM PST 24 Jan 07 01:46:20 PM PST 24 7788237101 ps
T1314 /workspace/coverage/default/10.i2c_host_fifo_full.1044957235 Jan 07 01:43:15 PM PST 24 Jan 07 01:44:48 PM PST 24 16434430977 ps
T1315 /workspace/coverage/default/20.i2c_target_timeout.2052202111 Jan 07 01:44:25 PM PST 24 Jan 07 01:44:34 PM PST 24 1344143449 ps
T1316 /workspace/coverage/default/10.i2c_target_intr_smoke.347676128 Jan 07 01:43:40 PM PST 24 Jan 07 01:44:02 PM PST 24 2995997251 ps
T1317 /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1083604893 Jan 07 01:45:36 PM PST 24 Jan 07 01:47:34 PM PST 24 10135642825 ps
T1318 /workspace/coverage/default/27.i2c_target_hrst.712622880 Jan 07 01:45:10 PM PST 24 Jan 07 01:45:41 PM PST 24 526534303 ps
T1319 /workspace/coverage/default/41.i2c_host_error_intr.1532526896 Jan 07 01:46:34 PM PST 24 Jan 07 01:47:07 PM PST 24 117702369 ps
T1320 /workspace/coverage/default/30.i2c_target_perf.3578163605 Jan 07 01:45:19 PM PST 24 Jan 07 01:45:58 PM PST 24 2914271049 ps
T1321 /workspace/coverage/default/37.i2c_target_stress_all.2736973294 Jan 07 01:45:43 PM PST 24 Jan 07 02:15:25 PM PST 24 123232095321 ps
T1322 /workspace/coverage/default/38.i2c_target_stress_rd.3972522882 Jan 07 01:45:36 PM PST 24 Jan 07 01:47:10 PM PST 24 1514138597 ps
T1323 /workspace/coverage/default/46.i2c_target_hrst.2887337758 Jan 07 01:46:36 PM PST 24 Jan 07 01:47:16 PM PST 24 545532742 ps
T1324 /workspace/coverage/default/18.i2c_target_stretch.2166370705 Jan 07 01:45:00 PM PST 24 Jan 07 01:45:48 PM PST 24 7465543775 ps
T1325 /workspace/coverage/default/33.i2c_target_tx_ovf.3816219583 Jan 07 01:45:34 PM PST 24 Jan 07 01:46:49 PM PST 24 10801234037 ps
T1326 /workspace/coverage/default/40.i2c_host_stress_all.2944013693 Jan 07 01:46:12 PM PST 24 Jan 07 02:40:49 PM PST 24 113603170551 ps
T171 /workspace/coverage/default/0.i2c_host_rx_oversample.3946031562 Jan 07 01:43:55 PM PST 24 Jan 07 01:46:36 PM PST 24 3132804481 ps
T1327 /workspace/coverage/default/29.i2c_target_smoke.64019761 Jan 07 01:44:57 PM PST 24 Jan 07 01:45:14 PM PST 24 1045387616 ps
T1328 /workspace/coverage/default/23.i2c_target_bad_addr.1625018762 Jan 07 01:45:02 PM PST 24 Jan 07 01:45:28 PM PST 24 2095434654 ps
T1329 /workspace/coverage/default/5.i2c_host_rx_oversample.4123347166 Jan 07 01:43:28 PM PST 24 Jan 07 01:44:49 PM PST 24 6054634732 ps
T1330 /workspace/coverage/default/16.i2c_target_unexp_stop.3826217594 Jan 07 01:45:24 PM PST 24 Jan 07 01:46:04 PM PST 24 5014636267 ps
T1331 /workspace/coverage/default/43.i2c_target_bad_addr.2306782842 Jan 07 01:46:13 PM PST 24 Jan 07 01:46:59 PM PST 24 1423333719 ps
T1332 /workspace/coverage/default/29.i2c_host_stretch_timeout.3675470828 Jan 07 01:45:12 PM PST 24 Jan 07 01:46:07 PM PST 24 616303710 ps
T1333 /workspace/coverage/default/43.i2c_host_fifo_watermark.1464752503 Jan 07 01:46:12 PM PST 24 Jan 07 01:54:35 PM PST 24 6659552355 ps
T1334 /workspace/coverage/default/42.i2c_target_tx_ovf.3740898467 Jan 07 01:46:36 PM PST 24 Jan 07 01:49:57 PM PST 24 5466868991 ps
T1335 /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3779568842 Jan 07 01:46:13 PM PST 24 Jan 07 01:46:59 PM PST 24 1161664954 ps
T1336 /workspace/coverage/default/27.i2c_host_fifo_full.2776451974 Jan 07 01:45:23 PM PST 24 Jan 07 01:47:59 PM PST 24 12192085128 ps
T1337 /workspace/coverage/default/29.i2c_target_perf.3535342025 Jan 07 01:45:06 PM PST 24 Jan 07 01:45:36 PM PST 24 879355493 ps
T1338 /workspace/coverage/default/17.i2c_target_bad_addr.1743153877 Jan 07 01:44:06 PM PST 24 Jan 07 01:44:17 PM PST 24 7015866168 ps
T1339 /workspace/coverage/default/10.i2c_target_intr_stress_wr.1484040954 Jan 07 01:43:48 PM PST 24 Jan 07 01:46:19 PM PST 24 13860178767 ps
T1340 /workspace/coverage/default/46.i2c_host_perf.1674830478 Jan 07 01:46:33 PM PST 24 Jan 07 01:53:27 PM PST 24 7830001736 ps
T1341 /workspace/coverage/default/49.i2c_target_tx_ovf.4201860864 Jan 07 01:46:53 PM PST 24 Jan 07 01:48:04 PM PST 24 8631261705 ps
T1342 /workspace/coverage/default/4.i2c_alert_test.3780543852 Jan 07 01:43:41 PM PST 24 Jan 07 01:43:57 PM PST 24 59459467 ps
T1343 /workspace/coverage/default/26.i2c_target_unexp_stop.3978819542 Jan 07 01:45:13 PM PST 24 Jan 07 01:45:48 PM PST 24 2782082751 ps
T1344 /workspace/coverage/default/31.i2c_target_fifo_reset_tx.967663748 Jan 07 01:45:07 PM PST 24 Jan 07 01:45:49 PM PST 24 10423769696 ps
T1345 /workspace/coverage/default/31.i2c_target_stress_wr.3728732670 Jan 07 01:45:26 PM PST 24 Jan 07 01:53:11 PM PST 24 19674029157 ps
T1346 /workspace/coverage/default/1.i2c_alert_test.1947475833 Jan 07 01:43:18 PM PST 24 Jan 07 01:43:34 PM PST 24 55835823 ps
T1347 /workspace/coverage/default/23.i2c_host_stretch_timeout.1000801494 Jan 07 01:45:36 PM PST 24 Jan 07 01:46:30 PM PST 24 3384294517 ps
T1348 /workspace/coverage/default/0.i2c_host_mode_toggle.54348242 Jan 07 01:43:16 PM PST 24 Jan 07 01:44:12 PM PST 24 6665906139 ps
T1349 /workspace/coverage/default/21.i2c_target_perf.3362942955 Jan 07 01:45:29 PM PST 24 Jan 07 01:46:10 PM PST 24 836109808 ps
T1350 /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3952280480 Jan 07 01:45:51 PM PST 24 Jan 07 01:46:32 PM PST 24 96228400 ps
T1351 /workspace/coverage/default/20.i2c_target_stress_all.3020009804 Jan 07 01:44:43 PM PST 24 Jan 07 01:48:06 PM PST 24 9938735932 ps
T1352 /workspace/coverage/default/26.i2c_host_stretch_timeout.3765783029 Jan 07 01:45:00 PM PST 24 Jan 07 01:45:26 PM PST 24 2479060316 ps
T1353 /workspace/coverage/default/40.i2c_host_perf.3476964276 Jan 07 01:46:34 PM PST 24 Jan 07 01:47:07 PM PST 24 404950917 ps
T1354 /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3972661117 Jan 07 01:44:58 PM PST 24 Jan 07 01:45:13 PM PST 24 468464012 ps
T1355 /workspace/coverage/default/0.i2c_host_perf.3510762624 Jan 07 01:43:38 PM PST 24 Jan 07 01:45:37 PM PST 24 6883644485 ps
T1356 /workspace/coverage/default/16.i2c_target_perf.2778442849 Jan 07 01:45:21 PM PST 24 Jan 07 01:46:00 PM PST 24 4068207357 ps
T1357 /workspace/coverage/default/18.i2c_target_tx_ovf.2262116143 Jan 07 01:44:03 PM PST 24 Jan 07 01:45:11 PM PST 24 4752622710 ps
T1358 /workspace/coverage/default/30.i2c_host_fifo_full.3031064293 Jan 07 01:45:11 PM PST 24 Jan 07 01:49:16 PM PST 24 3466956581 ps
T1359 /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2358667095 Jan 07 01:45:01 PM PST 24 Jan 07 01:46:22 PM PST 24 10067350370 ps
T1360 /workspace/coverage/default/49.i2c_host_mode_toggle.86018941 Jan 07 01:46:53 PM PST 24 Jan 07 01:50:14 PM PST 24 2615778843 ps
T1361 /workspace/coverage/default/14.i2c_host_stretch_timeout.3808139038 Jan 07 01:44:38 PM PST 24 Jan 07 01:44:59 PM PST 24 1119703050 ps
T1362 /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.659009565 Jan 07 01:45:50 PM PST 24 Jan 07 01:46:36 PM PST 24 989858824 ps
T1363 /workspace/coverage/default/17.i2c_target_stress_wr.2383815534 Jan 07 01:44:18 PM PST 24 Jan 07 02:42:00 PM PST 24 48233897435 ps
T1364 /workspace/coverage/default/37.i2c_host_smoke.1116413561 Jan 07 01:45:59 PM PST 24 Jan 07 01:48:10 PM PST 24 10779736849 ps
T1365 /workspace/coverage/default/26.i2c_target_timeout.2249799729 Jan 07 01:45:07 PM PST 24 Jan 07 01:45:43 PM PST 24 3679950169 ps
T1366 /workspace/coverage/default/13.i2c_host_stretch_timeout.638560398 Jan 07 01:44:06 PM PST 24 Jan 07 01:44:30 PM PST 24 2270340444 ps
T1367 /workspace/coverage/default/29.i2c_alert_test.195330035 Jan 07 01:45:01 PM PST 24 Jan 07 01:45:21 PM PST 24 14959268 ps
T1368 /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1469356733 Jan 07 01:43:30 PM PST 24 Jan 07 01:44:01 PM PST 24 516273321 ps
T1369 /workspace/coverage/default/18.i2c_host_error_intr.2094151472 Jan 07 01:44:06 PM PST 24 Jan 07 01:44:15 PM PST 24 103755387 ps
T1370 /workspace/coverage/default/17.i2c_target_stress_all.2648544201 Jan 07 01:44:03 PM PST 24 Jan 07 01:51:59 PM PST 24 12631547937 ps
T1371 /workspace/coverage/default/8.i2c_target_intr_smoke.836462496 Jan 07 01:43:31 PM PST 24 Jan 07 01:43:56 PM PST 24 1403014871 ps
T160 /workspace/coverage/default/1.i2c_host_stress_all.218570519 Jan 07 01:42:58 PM PST 24 Jan 07 02:27:22 PM PST 24 116161173404 ps
T1372 /workspace/coverage/default/28.i2c_target_hrst.2598774152 Jan 07 01:45:08 PM PST 24 Jan 07 01:45:40 PM PST 24 272438278 ps
T1373 /workspace/coverage/default/21.i2c_host_perf.2206621442 Jan 07 01:45:02 PM PST 24 Jan 07 02:00:38 PM PST 24 51564811084 ps
T1374 /workspace/coverage/default/28.i2c_alert_test.3086410251 Jan 07 01:44:42 PM PST 24 Jan 07 01:44:45 PM PST 24 121965285 ps
T1375 /workspace/coverage/default/1.i2c_host_override.119753829 Jan 07 01:43:19 PM PST 24 Jan 07 01:43:35 PM PST 24 18758105 ps
T1376 /workspace/coverage/default/40.i2c_target_bad_addr.1314144034 Jan 07 01:46:02 PM PST 24 Jan 07 01:46:44 PM PST 24 3782680905 ps
T1377 /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2438499933 Jan 07 01:45:29 PM PST 24 Jan 07 01:46:11 PM PST 24 10405053795 ps
T1378 /workspace/coverage/default/30.i2c_target_intr_smoke.1209027 Jan 07 01:45:14 PM PST 24 Jan 07 01:45:48 PM PST 24 1926560354 ps
T86 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2619466190 Jan 07 12:49:22 PM PST 24 Jan 07 12:50:28 PM PST 24 116678958 ps
T102 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2945777264 Jan 07 12:49:40 PM PST 24 Jan 07 12:50:55 PM PST 24 132122893 ps
T1379 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1373424512 Jan 07 12:49:42 PM PST 24 Jan 07 12:51:03 PM PST 24 21875873 ps
T103 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3772616236 Jan 07 12:49:26 PM PST 24 Jan 07 12:50:33 PM PST 24 58390180 ps
T1380 /workspace/coverage/cover_reg_top/23.i2c_intr_test.574298291 Jan 07 12:49:22 PM PST 24 Jan 07 12:50:50 PM PST 24 18994886 ps
T87 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.577555355 Jan 07 12:51:02 PM PST 24 Jan 07 12:52:28 PM PST 24 258654091 ps
T120 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3383316619 Jan 07 12:49:17 PM PST 24 Jan 07 12:50:31 PM PST 24 48908778 ps
T1381 /workspace/coverage/cover_reg_top/44.i2c_intr_test.4158794295 Jan 07 12:49:57 PM PST 24 Jan 07 12:51:43 PM PST 24 43486205 ps
T113 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2762687098 Jan 07 12:49:27 PM PST 24 Jan 07 12:50:41 PM PST 24 46265708 ps
T161 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3057624364 Jan 07 12:49:41 PM PST 24 Jan 07 12:50:58 PM PST 24 235425210 ps
T1382 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2413274428 Jan 07 12:49:34 PM PST 24 Jan 07 12:50:44 PM PST 24 15790766 ps
T1383 /workspace/coverage/cover_reg_top/13.i2c_intr_test.583300208 Jan 07 12:49:37 PM PST 24 Jan 07 12:50:40 PM PST 24 26398784 ps
T114 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1445511005 Jan 07 12:49:36 PM PST 24 Jan 07 12:50:40 PM PST 24 42158877 ps
T1384 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2360188652 Jan 07 12:49:10 PM PST 24 Jan 07 12:50:14 PM PST 24 21876391 ps
T1385 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3453222655 Jan 07 12:49:17 PM PST 24 Jan 07 12:50:34 PM PST 24 25785307 ps
T83 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.460570901 Jan 07 12:49:16 PM PST 24 Jan 07 12:51:19 PM PST 24 135945018 ps
T1386 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.970929620 Jan 07 12:49:56 PM PST 24 Jan 07 12:51:13 PM PST 24 19941481 ps
T1387 /workspace/coverage/cover_reg_top/46.i2c_intr_test.304671630 Jan 07 12:50:05 PM PST 24 Jan 07 12:51:21 PM PST 24 20024945 ps
T1388 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2371155106 Jan 07 12:49:19 PM PST 24 Jan 07 12:50:35 PM PST 24 17422883 ps
T121 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1345730452 Jan 07 12:49:51 PM PST 24 Jan 07 12:50:57 PM PST 24 73291923 ps
T1389 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.231883949 Jan 07 12:49:55 PM PST 24 Jan 07 12:51:19 PM PST 24 24199285 ps
T1390 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3081238311 Jan 07 12:49:58 PM PST 24 Jan 07 12:51:05 PM PST 24 87736336 ps
T115 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2028219244 Jan 07 12:49:45 PM PST 24 Jan 07 12:51:06 PM PST 24 48145587 ps
T1391 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1464050760 Jan 07 12:50:19 PM PST 24 Jan 07 12:51:23 PM PST 24 44653667 ps
T1392 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1042650678 Jan 07 12:49:20 PM PST 24 Jan 07 12:50:33 PM PST 24 28690293 ps
T107 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3408648612 Jan 07 12:49:45 PM PST 24 Jan 07 12:50:50 PM PST 24 41316349 ps
T1393 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3932186700 Jan 07 12:49:39 PM PST 24 Jan 07 12:50:55 PM PST 24 49669994 ps
T116 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.315042511 Jan 07 12:49:19 PM PST 24 Jan 07 12:50:33 PM PST 24 30164685 ps
T1394 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1641316697 Jan 07 12:50:01 PM PST 24 Jan 07 12:51:10 PM PST 24 29711937 ps
T1395 /workspace/coverage/cover_reg_top/4.i2c_intr_test.870669272 Jan 07 12:50:58 PM PST 24 Jan 07 12:52:14 PM PST 24 18460967 ps
T1396 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1610349446 Jan 07 12:50:03 PM PST 24 Jan 07 12:51:15 PM PST 24 39962562 ps
T1397 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1576350072 Jan 07 12:50:00 PM PST 24 Jan 07 12:51:13 PM PST 24 18073986 ps
T1398 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2494051744 Jan 07 12:49:27 PM PST 24 Jan 07 12:50:33 PM PST 24 35849508 ps
T1399 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2929401646 Jan 07 12:49:56 PM PST 24 Jan 07 12:51:32 PM PST 24 155048452 ps
T108 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1998836747 Jan 07 12:48:55 PM PST 24 Jan 07 12:50:15 PM PST 24 52342621 ps
T1400 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1832818909 Jan 07 12:49:26 PM PST 24 Jan 07 12:51:07 PM PST 24 25937427 ps
T1401 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3141253488 Jan 07 12:49:49 PM PST 24 Jan 07 12:51:36 PM PST 24 46257338 ps
T1402 /workspace/coverage/cover_reg_top/18.i2c_intr_test.21312637 Jan 07 12:49:52 PM PST 24 Jan 07 12:51:03 PM PST 24 25354336 ps
T1403 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3060082381 Jan 07 12:50:04 PM PST 24 Jan 07 12:51:36 PM PST 24 60976120 ps
T112 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.883450175 Jan 07 12:49:41 PM PST 24 Jan 07 12:50:55 PM PST 24 61482357 ps
T1404 /workspace/coverage/cover_reg_top/38.i2c_intr_test.641046596 Jan 07 12:49:47 PM PST 24 Jan 07 12:51:06 PM PST 24 40364963 ps
T132 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2114120428 Jan 07 12:49:53 PM PST 24 Jan 07 12:51:26 PM PST 24 155732658 ps
T1405 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.652361012 Jan 07 12:49:34 PM PST 24 Jan 07 12:50:38 PM PST 24 23812341 ps
T1406 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3101775458 Jan 07 12:49:54 PM PST 24 Jan 07 12:51:10 PM PST 24 40468882 ps
T1407 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1802065243 Jan 07 12:49:22 PM PST 24 Jan 07 12:50:40 PM PST 24 44933650 ps
T1408 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1275864423 Jan 07 12:50:13 PM PST 24 Jan 07 12:52:02 PM PST 24 227538438 ps
T81 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3671362416 Jan 07 12:50:01 PM PST 24 Jan 07 12:51:27 PM PST 24 48199578 ps
T109 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1463080256 Jan 07 12:50:08 PM PST 24 Jan 07 12:51:33 PM PST 24 20037905 ps
T1409 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2236219659 Jan 07 12:49:50 PM PST 24 Jan 07 12:51:10 PM PST 24 29738758 ps
T1410 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3412059465 Jan 07 12:50:26 PM PST 24 Jan 07 12:51:47 PM PST 24 19277656 ps
T1411 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.235618386 Jan 07 12:49:38 PM PST 24 Jan 07 12:51:04 PM PST 24 21926363 ps
T1412 /workspace/coverage/cover_reg_top/8.i2c_intr_test.733037782 Jan 07 12:49:06 PM PST 24 Jan 07 12:50:01 PM PST 24 18655954 ps
T1413 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3587602730 Jan 07 12:49:51 PM PST 24 Jan 07 12:51:03 PM PST 24 112326551 ps
T1414 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2666976116 Jan 07 12:49:50 PM PST 24 Jan 07 12:51:42 PM PST 24 41604198 ps
T1415 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1181454704 Jan 07 12:49:46 PM PST 24 Jan 07 12:51:12 PM PST 24 34083876 ps
T1416 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.579295610 Jan 07 12:49:33 PM PST 24 Jan 07 12:50:42 PM PST 24 76413962 ps
T1417 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1457389182 Jan 07 12:49:45 PM PST 24 Jan 07 12:50:57 PM PST 24 19502663 ps
T1418 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2845841686 Jan 07 12:49:54 PM PST 24 Jan 07 12:51:37 PM PST 24 156095390 ps
T82 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2347671450 Jan 07 12:49:36 PM PST 24 Jan 07 12:50:50 PM PST 24 117339693 ps
T1419 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.565288834 Jan 07 12:49:30 PM PST 24 Jan 07 12:50:33 PM PST 24 59486678 ps
T1420 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.4266561003 Jan 07 12:49:28 PM PST 24 Jan 07 12:51:00 PM PST 24 51550912 ps
T1421 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3660928880 Jan 07 12:49:57 PM PST 24 Jan 07 12:51:04 PM PST 24 144581079 ps
T1422 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3279857003 Jan 07 12:49:53 PM PST 24 Jan 07 12:52:05 PM PST 24 411937964 ps
T1423 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.348869571 Jan 07 12:50:00 PM PST 24 Jan 07 12:51:24 PM PST 24 442255514 ps
T1424 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1513996062 Jan 07 12:49:43 PM PST 24 Jan 07 12:51:26 PM PST 24 23924252 ps
T1425 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3866356085 Jan 07 12:49:50 PM PST 24 Jan 07 12:51:07 PM PST 24 86009938 ps
T1426 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2869568381 Jan 07 12:50:01 PM PST 24 Jan 07 12:51:07 PM PST 24 76003245 ps
T1427 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3423445817 Jan 07 12:50:28 PM PST 24 Jan 07 12:51:55 PM PST 24 16826290 ps
T1428 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3263471820 Jan 07 12:49:22 PM PST 24 Jan 07 12:50:36 PM PST 24 20963453 ps
T1429 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3859193584 Jan 07 12:49:28 PM PST 24 Jan 07 12:50:34 PM PST 24 108970168 ps
T1430 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4019317856 Jan 07 12:50:20 PM PST 24 Jan 07 12:51:37 PM PST 24 40669824 ps
T1431 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2156647335 Jan 07 12:49:25 PM PST 24 Jan 07 12:50:33 PM PST 24 17930296 ps
T88 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1433615357 Jan 07 12:49:10 PM PST 24 Jan 07 12:50:07 PM PST 24 119502691 ps
T110 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4248044308 Jan 07 12:49:48 PM PST 24 Jan 07 12:51:22 PM PST 24 257427292 ps
T1432 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2140272530 Jan 07 12:49:39 PM PST 24 Jan 07 12:51:36 PM PST 24 17113113 ps
T1433 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.874455849 Jan 07 12:49:33 PM PST 24 Jan 07 12:50:45 PM PST 24 51849948 ps
T1434 /workspace/coverage/cover_reg_top/7.i2c_intr_test.996359817 Jan 07 12:49:19 PM PST 24 Jan 07 12:50:39 PM PST 24 17843324 ps
T1435 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.452697209 Jan 07 12:49:29 PM PST 24 Jan 07 12:51:21 PM PST 24 21791292 ps
T1436 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.74214552 Jan 07 12:49:42 PM PST 24 Jan 07 12:50:52 PM PST 24 189028687 ps
T1437 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2314214207 Jan 07 12:51:33 PM PST 24 Jan 07 12:52:45 PM PST 24 384787365 ps
T1438 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2588827275 Jan 07 12:50:01 PM PST 24 Jan 07 12:51:17 PM PST 24 36408028 ps
T1439 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2346548092 Jan 07 12:49:29 PM PST 24 Jan 07 12:50:38 PM PST 24 436444336 ps
T1440 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1096933488 Jan 07 12:49:25 PM PST 24 Jan 07 12:50:40 PM PST 24 24535131 ps
T1441 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1374960693 Jan 07 12:49:10 PM PST 24 Jan 07 12:50:33 PM PST 24 32447300 ps
T1442 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2041547318 Jan 07 12:49:20 PM PST 24 Jan 07 12:50:20 PM PST 24 48229028 ps
T1443 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2151565602 Jan 07 12:49:54 PM PST 24 Jan 07 12:51:10 PM PST 24 22169982 ps
T1444 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4219964440 Jan 07 12:50:03 PM PST 24 Jan 07 12:51:33 PM PST 24 21296661 ps
T85 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2918990510 Jan 07 12:49:43 PM PST 24 Jan 07 12:51:20 PM PST 24 112809213 ps
T1445 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.4071393200 Jan 07 12:49:19 PM PST 24 Jan 07 12:50:59 PM PST 24 74030343 ps
T84 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.403262862 Jan 07 12:49:59 PM PST 24 Jan 07 12:51:27 PM PST 24 396578295 ps
T1446 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.600953738 Jan 07 12:50:00 PM PST 24 Jan 07 12:51:26 PM PST 24 51504118 ps
T1447 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4292789089 Jan 07 12:49:50 PM PST 24 Jan 07 12:51:06 PM PST 24 72813896 ps
T1448 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3525960972 Jan 07 12:49:37 PM PST 24 Jan 07 12:51:16 PM PST 24 431485757 ps
T1449 /workspace/coverage/cover_reg_top/28.i2c_intr_test.1942729628 Jan 07 12:49:43 PM PST 24 Jan 07 12:50:52 PM PST 24 18769582 ps
T1450 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2665115547 Jan 07 12:49:50 PM PST 24 Jan 07 12:51:26 PM PST 24 54440569 ps
T1451 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1601883359 Jan 07 12:49:38 PM PST 24 Jan 07 12:50:42 PM PST 24 38470797 ps
T1452 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3577457396 Jan 07 12:49:19 PM PST 24 Jan 07 12:50:35 PM PST 24 19117853 ps
T1453 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1502973141 Jan 07 12:50:01 PM PST 24 Jan 07 12:51:25 PM PST 24 15441373 ps
T1454 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2638277627 Jan 07 12:49:58 PM PST 24 Jan 07 12:51:53 PM PST 24 148959503 ps
T1455 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3484651911 Jan 07 12:49:01 PM PST 24 Jan 07 12:50:25 PM PST 24 110298824 ps
T1456 /workspace/coverage/cover_reg_top/41.i2c_intr_test.815462752 Jan 07 12:50:10 PM PST 24 Jan 07 12:51:33 PM PST 24 43493154 ps
T1457 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.474186920 Jan 07 12:49:53 PM PST 24 Jan 07 12:51:24 PM PST 24 27039602 ps
T1458 /workspace/coverage/cover_reg_top/27.i2c_intr_test.214164581 Jan 07 12:50:00 PM PST 24 Jan 07 12:51:09 PM PST 24 28950183 ps
T1459 /workspace/coverage/cover_reg_top/31.i2c_intr_test.588671782 Jan 07 12:49:51 PM PST 24 Jan 07 12:50:57 PM PST 24 17489437 ps
T1460 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.28630229 Jan 07 12:49:37 PM PST 24 Jan 07 12:50:53 PM PST 24 25717952 ps
T1461 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3806101149 Jan 07 12:49:50 PM PST 24 Jan 07 12:51:18 PM PST 24 99025851 ps
T1462 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1180698404 Jan 07 12:49:57 PM PST 24 Jan 07 12:51:04 PM PST 24 24898290 ps
T1463 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3565230926 Jan 07 12:49:14 PM PST 24 Jan 07 12:50:26 PM PST 24 65349718 ps
T1464 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2626553130 Jan 07 12:50:01 PM PST 24 Jan 07 12:51:14 PM PST 24 281395532 ps
T1465 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.664432305 Jan 07 12:49:51 PM PST 24 Jan 07 12:51:21 PM PST 24 17582359 ps
T1466 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.445251296 Jan 07 12:49:44 PM PST 24 Jan 07 12:51:30 PM PST 24 37025809 ps
T1467 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3149571623 Jan 07 12:50:14 PM PST 24 Jan 07 12:51:48 PM PST 24 45344282 ps
T1468 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4255661102 Jan 07 12:49:19 PM PST 24 Jan 07 12:51:11 PM PST 24 83648508 ps
T1469 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3075576129 Jan 07 12:49:48 PM PST 24 Jan 07 12:51:07 PM PST 24 181363163 ps
T1470 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3781151983 Jan 07 12:49:51 PM PST 24 Jan 07 12:51:07 PM PST 24 21490024 ps
T1471 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3657558567 Jan 07 12:49:32 PM PST 24 Jan 07 12:50:42 PM PST 24 16071251 ps
T1472 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3358560848 Jan 07 12:49:24 PM PST 24 Jan 07 12:50:42 PM PST 24 58289643 ps
T1473 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1196301918 Jan 07 12:50:10 PM PST 24 Jan 07 12:51:37 PM PST 24 17847407 ps
T1474 /workspace/coverage/cover_reg_top/48.i2c_intr_test.831857325 Jan 07 12:49:54 PM PST 24 Jan 07 12:51:10 PM PST 24 91711705 ps
T1475 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1639254319 Jan 07 12:49:46 PM PST 24 Jan 07 12:51:21 PM PST 24 56373695 ps
T1476 /workspace/coverage/cover_reg_top/22.i2c_intr_test.3862838016 Jan 07 12:50:03 PM PST 24 Jan 07 12:51:15 PM PST 24 16701711 ps
T111 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.268602013 Jan 07 12:49:52 PM PST 24 Jan 07 12:51:40 PM PST 24 16371872 ps

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2720957030
Short name T22
Test name
Test status
Simulation time 43846712 ps
CPU time 1.02 seconds
Started Jan 07 12:49:20 PM PST 24
Finished Jan 07 12:50:20 PM PST 24
Peak memory 202812 kb
Host smart-098c4fbf-4fbf-4b39-a0a4-fcee4e942fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720957030 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2720957030
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2659922363
Short name T7
Test name
Test status
Simulation time 2021374249 ps
CPU time 10.46 seconds
Started Jan 07 01:43:04 PM PST 24
Finished Jan 07 01:43:28 PM PST 24
Peak memory 324364 kb
Host smart-1be4d5d2-8ae7-4138-b7e3-569602cf5ad9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659922363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2659922363
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.177489316
Short name T11
Test name
Test status
Simulation time 68117218078 ps
CPU time 3036.76 seconds
Started Jan 07 01:46:58 PM PST 24
Finished Jan 07 02:38:08 PM PST 24
Peak memory 2606488 kb
Host smart-cf9df04a-64a7-4d30-b777-c77e230919a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177489316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.177489316
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.3206087735
Short name T32
Test name
Test status
Simulation time 34296761849 ps
CPU time 1484.05 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 02:08:29 PM PST 24
Peak memory 5297432 kb
Host smart-ece066f3-0303-4a51-aeb3-c854ee6d2591
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206087735 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.3206087735
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2701990545
Short name T25
Test name
Test status
Simulation time 27418020 ps
CPU time 0.72 seconds
Started Jan 07 12:50:11 PM PST 24
Finished Jan 07 12:51:17 PM PST 24
Peak memory 202652 kb
Host smart-eeadc1ad-c52d-485d-b411-7865ce382597
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701990545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2701990545
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1504929912
Short name T30
Test name
Test status
Simulation time 30658837 ps
CPU time 0.63 seconds
Started Jan 07 12:49:53 PM PST 24
Finished Jan 07 12:51:25 PM PST 24
Peak memory 202712 kb
Host smart-a3500b32-b575-4a2c-94cc-b0bcc3d1a9f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504929912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1504929912
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1070022949
Short name T77
Test name
Test status
Simulation time 128359562 ps
CPU time 0.79 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:43:29 PM PST 24
Peak memory 219688 kb
Host smart-98f558b9-e6d7-4e5e-b6e2-a82a15ddc1d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070022949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1070022949
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/10.i2c_host_override.1752764988
Short name T130
Test name
Test status
Simulation time 20920920 ps
CPU time 0.65 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:43:32 PM PST 24
Peak memory 202444 kb
Host smart-40e14203-5c6b-4686-ad2c-92a4cf84b335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752764988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1752764988
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_target_tx_ovf.1215941303
Short name T17
Test name
Test status
Simulation time 2995238123 ps
CPU time 109.54 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 01:49:11 PM PST 24
Peak memory 341584 kb
Host smart-4b125573-56e7-4873-8588-d1551f5c10f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215941303 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_tx_ovf.1215941303
Directory /workspace/48.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all_with_rand_reset.2094534377
Short name T80
Test name
Test status
Simulation time 32957246854 ps
CPU time 685.74 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:55:13 PM PST 24
Peak memory 1491744 kb
Host smart-d08df09f-643a-49d0-bfab-fa4d5c5cd7b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094534377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.i2c_host_stress_all_with_rand_reset.2094534377
Directory /workspace/8.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1862083146
Short name T76
Test name
Test status
Simulation time 216728490 ps
CPU time 1.15 seconds
Started Jan 07 12:49:19 PM PST 24
Finished Jan 07 12:50:21 PM PST 24
Peak memory 203000 kb
Host smart-2c86e990-5858-4a12-bdfc-9d9a51c1a19a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862083146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1862083146
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3242677295
Short name T52
Test name
Test status
Simulation time 30249862524 ps
CPU time 3227.73 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 02:39:23 PM PST 24
Peak memory 4730476 kb
Host smart-c2d9d281-6a40-4dc6-bd45-d8253c763ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242677295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3242677295
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.1024785059
Short name T9
Test name
Test status
Simulation time 10255596847 ps
CPU time 145.04 seconds
Started Jan 07 01:43:58 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 259780 kb
Host smart-6cccd4a4-7840-4907-b092-f00e986ba100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024785059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1024785059
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3904098490
Short name T59
Test name
Test status
Simulation time 1100946180 ps
CPU time 4.82 seconds
Started Jan 07 01:42:38 PM PST 24
Finished Jan 07 01:43:03 PM PST 24
Peak memory 203492 kb
Host smart-8d2957db-d2d6-4dd5-9558-98bf7c2b1945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904098490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3904098490
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1744824013
Short name T173
Test name
Test status
Simulation time 53103670219 ps
CPU time 1272.91 seconds
Started Jan 07 01:45:43 PM PST 24
Finished Jan 07 02:07:35 PM PST 24
Peak memory 2771508 kb
Host smart-a6b2a099-dd46-4591-b4c8-a132e9830bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744824013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1744824013
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.4179295465
Short name T57
Test name
Test status
Simulation time 510461325 ps
CPU time 1.08 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:43:51 PM PST 24
Peak memory 203172 kb
Host smart-8ef7833f-655d-493f-b406-1b0ad16cad42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179295465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.4179295465
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2039258082
Short name T140
Test name
Test status
Simulation time 1372135801 ps
CPU time 3.85 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:45:41 PM PST 24
Peak memory 211520 kb
Host smart-236092fe-b281-49d7-a010-888885be1c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039258082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2039258082
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2792797604
Short name T1094
Test name
Test status
Simulation time 17495305926 ps
CPU time 273.32 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:50:40 PM PST 24
Peak memory 1018704 kb
Host smart-2ccef38e-4c07-473e-941b-24a3e9042d26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792797604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2792797604
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3862714334
Short name T255
Test name
Test status
Simulation time 746917849 ps
CPU time 3.38 seconds
Started Jan 07 01:44:19 PM PST 24
Finished Jan 07 01:44:24 PM PST 24
Peak memory 203348 kb
Host smart-8e5317a6-9753-4203-ae5e-f9ac424fea23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862714334 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3862714334
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3750665886
Short name T146
Test name
Test status
Simulation time 1516735773 ps
CPU time 38.81 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:42 PM PST 24
Peak memory 298608 kb
Host smart-3108eab4-ae1b-43ae-bb72-907eb50f7156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750665886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3750665886
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.580967904
Short name T70
Test name
Test status
Simulation time 15156674 ps
CPU time 0.64 seconds
Started Jan 07 12:49:44 PM PST 24
Finished Jan 07 12:51:20 PM PST 24
Peak memory 202652 kb
Host smart-4bcf8734-e431-4825-9213-1e883b51ffd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580967904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.580967904
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2918990510
Short name T85
Test name
Test status
Simulation time 112809213 ps
CPU time 1.73 seconds
Started Jan 07 12:49:43 PM PST 24
Finished Jan 07 12:51:20 PM PST 24
Peak memory 202896 kb
Host smart-25e7a2c2-7ef5-4ebd-87f7-58c3a2caa7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918990510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2918990510
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all_with_rand_reset.3145331554
Short name T48
Test name
Test status
Simulation time 39754193729 ps
CPU time 589.97 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:56:04 PM PST 24
Peak memory 1988704 kb
Host smart-ac4c05f9-b195-42d0-ac46-537e3939754e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145331554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.i2c_host_stress_all_with_rand_reset.3145331554
Directory /workspace/31.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.403262862
Short name T84
Test name
Test status
Simulation time 396578295 ps
CPU time 1.74 seconds
Started Jan 07 12:49:59 PM PST 24
Finished Jan 07 12:51:27 PM PST 24
Peak memory 202976 kb
Host smart-022e725c-ea54-4c4c-ba73-d47580504bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403262862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.403262862
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.870669272
Short name T1395
Test name
Test status
Simulation time 18460967 ps
CPU time 0.64 seconds
Started Jan 07 12:50:58 PM PST 24
Finished Jan 07 12:52:14 PM PST 24
Peak memory 202288 kb
Host smart-19febf28-18a8-49eb-916c-f299d824b410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870669272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.870669272
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.28630229
Short name T1460
Test name
Test status
Simulation time 25717952 ps
CPU time 0.91 seconds
Started Jan 07 12:49:37 PM PST 24
Finished Jan 07 12:50:53 PM PST 24
Peak memory 202884 kb
Host smart-9d03ac17-c509-4da2-8fad-8c20c6c62626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outs
tanding.28630229
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.584967723
Short name T1029
Test name
Test status
Simulation time 990756664 ps
CPU time 2.48 seconds
Started Jan 07 01:43:25 PM PST 24
Finished Jan 07 01:43:44 PM PST 24
Peak memory 203328 kb
Host smart-bd677dd8-53d0-4bae-84f2-e67659ff58f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584967723 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.584967723
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.4155897997
Short name T448
Test name
Test status
Simulation time 64840028571 ps
CPU time 3367.32 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 02:41:25 PM PST 24
Peak memory 2951080 kb
Host smart-2f7d5ee3-a59d-4510-ae40-b94b17e63d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155897997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.4155897997
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.4017913369
Short name T178
Test name
Test status
Simulation time 10167827822 ps
CPU time 73.71 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:46:42 PM PST 24
Peak memory 761392 kb
Host smart-b02d1e99-4b4e-4721-b3b7-8817defa3c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017913369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.4017913369
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3804483758
Short name T189
Test name
Test status
Simulation time 10164791600 ps
CPU time 24.04 seconds
Started Jan 07 01:46:39 PM PST 24
Finished Jan 07 01:47:43 PM PST 24
Peak memory 324192 kb
Host smart-b5333957-b0f0-43f7-b9a8-fed905ddce06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804483758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3804483758
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_host_rx_oversample.3430330753
Short name T170
Test name
Test status
Simulation time 2781654596 ps
CPU time 140.17 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 01:46:00 PM PST 24
Peak memory 329160 kb
Host smart-2963838d-a54a-4528-a2a5-35028e299e8f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430330753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_rx_oversample.
3430330753
Directory /workspace/7.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2714351732
Short name T365
Test name
Test status
Simulation time 18768408 ps
CPU time 0.59 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:43:30 PM PST 24
Peak memory 202208 kb
Host smart-96a4a531-2a4e-407f-801c-c8d7e4be811e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714351732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2714351732
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2184867456
Short name T419
Test name
Test status
Simulation time 568970061 ps
CPU time 4.13 seconds
Started Jan 07 01:43:25 PM PST 24
Finished Jan 07 01:43:47 PM PST 24
Peak memory 232804 kb
Host smart-e23021b3-e82c-4ad2-a748-ef85552278db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184867456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2184867456
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_target_perf.679743765
Short name T159
Test name
Test status
Simulation time 2687405010 ps
CPU time 4.2 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:44:15 PM PST 24
Peak memory 203440 kb
Host smart-faa9589e-2103-4bae-a213-8d36747ac367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679743765 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_perf.679743765
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3023394436
Short name T198
Test name
Test status
Simulation time 473311331 ps
CPU time 0.93 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:45:40 PM PST 24
Peak memory 202800 kb
Host smart-a9bfb77c-f65a-4aa0-8520-418e806ef866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023394436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3023394436
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1602811740
Short name T53
Test name
Test status
Simulation time 120141414893 ps
CPU time 2167.66 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 02:23:30 PM PST 24
Peak memory 1122624 kb
Host smart-6d23b4bf-6a43-4fee-84be-cc2faf86f309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602811740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1602811740
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.3656645793
Short name T165
Test name
Test status
Simulation time 6860832783 ps
CPU time 5.75 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 203380 kb
Host smart-9fe2585b-dd70-4ef9-a0f9-b6f24aa42c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656645793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.3656645793
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1950133507
Short name T73
Test name
Test status
Simulation time 10241302481 ps
CPU time 23.97 seconds
Started Jan 07 01:43:48 PM PST 24
Finished Jan 07 01:44:24 PM PST 24
Peak memory 353448 kb
Host smart-66555021-777d-460d-a84e-adf676edc1f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950133507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1950133507
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3504288337
Short name T50
Test name
Test status
Simulation time 43927789 ps
CPU time 1.3 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 212936 kb
Host smart-6fcaf70b-ddf4-405d-ae84-6742fd51a338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504288337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3504288337
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3484651911
Short name T1455
Test name
Test status
Simulation time 110298824 ps
CPU time 0.9 seconds
Started Jan 07 12:49:01 PM PST 24
Finished Jan 07 12:50:25 PM PST 24
Peak memory 202724 kb
Host smart-51bea121-0753-47c2-95b8-7a2d99a82cc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484651911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3484651911
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.452697209
Short name T1435
Test name
Test status
Simulation time 21791292 ps
CPU time 0.71 seconds
Started Jan 07 12:49:29 PM PST 24
Finished Jan 07 12:51:21 PM PST 24
Peak memory 202732 kb
Host smart-776c1b0b-00a8-4f4b-94a5-8a029d71468a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452697209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.452697209
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.268602013
Short name T111
Test name
Test status
Simulation time 16371872 ps
CPU time 0.64 seconds
Started Jan 07 12:49:52 PM PST 24
Finished Jan 07 12:51:40 PM PST 24
Peak memory 202020 kb
Host smart-0ca54d3d-b3e9-4778-8f37-5a33118ec794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268602013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.268602013
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.315042511
Short name T116
Test name
Test status
Simulation time 30164685 ps
CPU time 0.77 seconds
Started Jan 07 12:49:19 PM PST 24
Finished Jan 07 12:50:33 PM PST 24
Peak memory 202124 kb
Host smart-f9eb953a-b146-43ba-a75d-ae08134544e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315042511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out
standing.315042511
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.4071393200
Short name T1445
Test name
Test status
Simulation time 74030343 ps
CPU time 1.59 seconds
Started Jan 07 12:49:19 PM PST 24
Finished Jan 07 12:50:59 PM PST 24
Peak memory 202996 kb
Host smart-c3cfeec3-a5d9-4a31-8893-3e836b21ecce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071393200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.4071393200
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3671362416
Short name T81
Test name
Test status
Simulation time 48199578 ps
CPU time 1.17 seconds
Started Jan 07 12:50:01 PM PST 24
Finished Jan 07 12:51:27 PM PST 24
Peak memory 202816 kb
Host smart-597b5c18-95c2-4126-a0d9-979e6364e732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671362416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3671362416
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2041547318
Short name T1442
Test name
Test status
Simulation time 48229028 ps
CPU time 0.95 seconds
Started Jan 07 12:49:20 PM PST 24
Finished Jan 07 12:50:20 PM PST 24
Peak memory 202752 kb
Host smart-f3217446-a357-4edc-92fb-713d4d92ac10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041547318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2041547318
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1373424512
Short name T1379
Test name
Test status
Simulation time 21875873 ps
CPU time 0.69 seconds
Started Jan 07 12:49:42 PM PST 24
Finished Jan 07 12:51:03 PM PST 24
Peak memory 202688 kb
Host smart-d891167b-90ae-403c-ac3b-d8fe76b3674e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373424512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1373424512
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2360188652
Short name T1384
Test name
Test status
Simulation time 21876391 ps
CPU time 0.74 seconds
Started Jan 07 12:49:10 PM PST 24
Finished Jan 07 12:50:14 PM PST 24
Peak memory 202804 kb
Host smart-e9752a49-a710-4521-98ea-466fd92e6e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360188652 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2360188652
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.48017950
Short name T26
Test name
Test status
Simulation time 23944154 ps
CPU time 0.71 seconds
Started Jan 07 12:49:51 PM PST 24
Finished Jan 07 12:51:10 PM PST 24
Peak memory 202676 kb
Host smart-16b15933-2092-4f3e-9f21-4b87d39ef0cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48017950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.48017950
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3806101149
Short name T1461
Test name
Test status
Simulation time 99025851 ps
CPU time 0.65 seconds
Started Jan 07 12:49:50 PM PST 24
Finished Jan 07 12:51:18 PM PST 24
Peak memory 202668 kb
Host smart-cdd71c56-ad31-42a3-8ac4-b610a5523bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806101149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3806101149
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2346548092
Short name T1439
Test name
Test status
Simulation time 436444336 ps
CPU time 2.2 seconds
Started Jan 07 12:49:29 PM PST 24
Finished Jan 07 12:50:38 PM PST 24
Peak memory 202960 kb
Host smart-65658d70-f19d-452e-8142-4f5d6a73c800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346548092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2346548092
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3057624364
Short name T161
Test name
Test status
Simulation time 235425210 ps
CPU time 1.81 seconds
Started Jan 07 12:49:41 PM PST 24
Finished Jan 07 12:50:58 PM PST 24
Peak memory 203032 kb
Host smart-8df630de-5fb1-4f04-ba97-da655250dac3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057624364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3057624364
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2236219659
Short name T1409
Test name
Test status
Simulation time 29738758 ps
CPU time 0.83 seconds
Started Jan 07 12:49:50 PM PST 24
Finished Jan 07 12:51:10 PM PST 24
Peak memory 202880 kb
Host smart-d8bb7b07-0856-4962-9b49-d3970c453553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236219659 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2236219659
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2052844199
Short name T24
Test name
Test status
Simulation time 15310658 ps
CPU time 0.66 seconds
Started Jan 07 12:49:37 PM PST 24
Finished Jan 07 12:50:49 PM PST 24
Peak memory 202604 kb
Host smart-4ad9f57b-32b2-486e-813f-d9f9c0151a17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052844199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2052844199
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3657558567
Short name T1471
Test name
Test status
Simulation time 16071251 ps
CPU time 0.66 seconds
Started Jan 07 12:49:32 PM PST 24
Finished Jan 07 12:50:42 PM PST 24
Peak memory 202632 kb
Host smart-91722636-c719-49b6-95d6-8e7e59e644c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657558567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3657558567
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3075576129
Short name T1469
Test name
Test status
Simulation time 181363163 ps
CPU time 0.78 seconds
Started Jan 07 12:49:48 PM PST 24
Finished Jan 07 12:51:07 PM PST 24
Peak memory 202680 kb
Host smart-6718cdb8-9a08-47f4-9dfa-413541094c6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075576129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3075576129
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2114120428
Short name T132
Test name
Test status
Simulation time 155732658 ps
CPU time 1.35 seconds
Started Jan 07 12:49:53 PM PST 24
Finished Jan 07 12:51:26 PM PST 24
Peak memory 202924 kb
Host smart-83ba876c-10c5-4875-bb73-6ac73efde078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114120428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2114120428
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.460570901
Short name T83
Test name
Test status
Simulation time 135945018 ps
CPU time 1.23 seconds
Started Jan 07 12:49:16 PM PST 24
Finished Jan 07 12:51:19 PM PST 24
Peak memory 202872 kb
Host smart-2284a7ab-2dc9-4e98-bc36-6b3db6f12a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460570901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.460570901
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1180698404
Short name T1462
Test name
Test status
Simulation time 24898290 ps
CPU time 0.71 seconds
Started Jan 07 12:49:57 PM PST 24
Finished Jan 07 12:51:04 PM PST 24
Peak memory 202812 kb
Host smart-6bc24a1f-58d1-4334-a505-678df14e59bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180698404 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1180698404
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.235618386
Short name T1411
Test name
Test status
Simulation time 21926363 ps
CPU time 0.68 seconds
Started Jan 07 12:49:38 PM PST 24
Finished Jan 07 12:51:04 PM PST 24
Peak memory 202100 kb
Host smart-eac4ad1c-c0b1-4435-9d70-44f608c39ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235618386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.235618386
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3149571623
Short name T1467
Test name
Test status
Simulation time 45344282 ps
CPU time 0.64 seconds
Started Jan 07 12:50:14 PM PST 24
Finished Jan 07 12:51:48 PM PST 24
Peak memory 202664 kb
Host smart-89812883-e38b-4859-9ab8-aeb7b1d4a84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149571623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3149571623
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.4266561003
Short name T1420
Test name
Test status
Simulation time 51550912 ps
CPU time 0.73 seconds
Started Jan 07 12:49:28 PM PST 24
Finished Jan 07 12:51:00 PM PST 24
Peak memory 202652 kb
Host smart-eb74e195-7f02-4037-89b5-788a95b71284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266561003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.4266561003
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1464050760
Short name T1391
Test name
Test status
Simulation time 44653667 ps
CPU time 1.14 seconds
Started Jan 07 12:50:19 PM PST 24
Finished Jan 07 12:51:23 PM PST 24
Peak memory 202856 kb
Host smart-8bb578bf-a189-4e09-ae96-ce3bcb748a95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464050760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1464050760
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.565288834
Short name T1419
Test name
Test status
Simulation time 59486678 ps
CPU time 0.88 seconds
Started Jan 07 12:49:30 PM PST 24
Finished Jan 07 12:50:33 PM PST 24
Peak memory 202748 kb
Host smart-74bd87a6-6a8d-4b3d-91b7-1467f9924db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565288834 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.565288834
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1641316697
Short name T1394
Test name
Test status
Simulation time 29711937 ps
CPU time 0.69 seconds
Started Jan 07 12:50:01 PM PST 24
Finished Jan 07 12:51:10 PM PST 24
Peak memory 202608 kb
Host smart-e31799aa-a0e3-4840-bccb-b454538b825a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641316697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1641316697
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1601883359
Short name T1451
Test name
Test status
Simulation time 38470797 ps
CPU time 0.66 seconds
Started Jan 07 12:49:38 PM PST 24
Finished Jan 07 12:50:42 PM PST 24
Peak memory 202720 kb
Host smart-ce257378-2469-4854-adaa-7d4001780bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601883359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1601883359
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3279857003
Short name T1422
Test name
Test status
Simulation time 411937964 ps
CPU time 0.78 seconds
Started Jan 07 12:49:53 PM PST 24
Finished Jan 07 12:52:05 PM PST 24
Peak memory 202616 kb
Host smart-a56f4569-95b9-46f1-b9d7-815470bd93e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279857003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3279857003
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3081238311
Short name T1390
Test name
Test status
Simulation time 87736336 ps
CPU time 1.5 seconds
Started Jan 07 12:49:58 PM PST 24
Finished Jan 07 12:51:05 PM PST 24
Peak memory 202920 kb
Host smart-5bb92f56-04a9-409f-8cfe-b79d13ea9e13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081238311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3081238311
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1802065243
Short name T1407
Test name
Test status
Simulation time 44933650 ps
CPU time 0.78 seconds
Started Jan 07 12:49:22 PM PST 24
Finished Jan 07 12:50:40 PM PST 24
Peak memory 202724 kb
Host smart-53c92bdf-c730-4090-8a60-9ed94dff8d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802065243 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1802065243
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.583300208
Short name T1383
Test name
Test status
Simulation time 26398784 ps
CPU time 0.61 seconds
Started Jan 07 12:49:37 PM PST 24
Finished Jan 07 12:50:40 PM PST 24
Peak memory 202616 kb
Host smart-8a67e7d3-6ca8-410e-997f-1ae4d94a2cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583300208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.583300208
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.445251296
Short name T1466
Test name
Test status
Simulation time 37025809 ps
CPU time 0.8 seconds
Started Jan 07 12:49:44 PM PST 24
Finished Jan 07 12:51:30 PM PST 24
Peak memory 202692 kb
Host smart-2f4ef16d-ffeb-47f3-ae5c-0e131fdfe7dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445251296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_ou
tstanding.445251296
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.600953738
Short name T1446
Test name
Test status
Simulation time 51504118 ps
CPU time 1.37 seconds
Started Jan 07 12:50:00 PM PST 24
Finished Jan 07 12:51:26 PM PST 24
Peak memory 202984 kb
Host smart-71f72a8c-91ae-40b7-8599-fca6713d5d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600953738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.600953738
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.2619466190
Short name T86
Test name
Test status
Simulation time 116678958 ps
CPU time 1.74 seconds
Started Jan 07 12:49:22 PM PST 24
Finished Jan 07 12:50:28 PM PST 24
Peak memory 202984 kb
Host smart-ff36a5f3-88f6-4197-9dd1-e5cc752d08d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619466190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.2619466190
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4292789089
Short name T1447
Test name
Test status
Simulation time 72813896 ps
CPU time 0.75 seconds
Started Jan 07 12:49:50 PM PST 24
Finished Jan 07 12:51:06 PM PST 24
Peak memory 202744 kb
Host smart-fa47747a-d12e-494e-9cd6-1506e7079ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292789089 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.4292789089
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2140272530
Short name T1432
Test name
Test status
Simulation time 17113113 ps
CPU time 0.69 seconds
Started Jan 07 12:49:39 PM PST 24
Finished Jan 07 12:51:36 PM PST 24
Peak memory 201740 kb
Host smart-d26f5432-bdd6-4816-82cb-9736c428ada7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140272530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2140272530
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1367229846
Short name T91
Test name
Test status
Simulation time 109392602 ps
CPU time 0.62 seconds
Started Jan 07 12:50:06 PM PST 24
Finished Jan 07 12:51:19 PM PST 24
Peak memory 202660 kb
Host smart-fa60bd34-a7ac-4e21-923b-8c3fa2653c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367229846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1367229846
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2162923381
Short name T23
Test name
Test status
Simulation time 279903513 ps
CPU time 0.81 seconds
Started Jan 07 12:49:23 PM PST 24
Finished Jan 07 12:50:35 PM PST 24
Peak memory 202632 kb
Host smart-5cc91351-75fb-4b3a-93d1-0a17cb890be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162923381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2162923381
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1275864423
Short name T1408
Test name
Test status
Simulation time 227538438 ps
CPU time 2.26 seconds
Started Jan 07 12:50:13 PM PST 24
Finished Jan 07 12:52:02 PM PST 24
Peak memory 202860 kb
Host smart-b850e4ea-2be0-4cca-b1f3-52707eb2e12a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275864423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1275864423
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3587602730
Short name T1413
Test name
Test status
Simulation time 112326551 ps
CPU time 1.24 seconds
Started Jan 07 12:49:51 PM PST 24
Finished Jan 07 12:51:03 PM PST 24
Peak memory 202956 kb
Host smart-b3f2363d-2c82-4091-8f88-5e7d9b0563dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587602730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3587602730
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.231883949
Short name T1389
Test name
Test status
Simulation time 24199285 ps
CPU time 0.76 seconds
Started Jan 07 12:49:55 PM PST 24
Finished Jan 07 12:51:19 PM PST 24
Peak memory 202688 kb
Host smart-6c47da80-582f-4201-b147-392c4649310d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231883949 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.231883949
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1445511005
Short name T114
Test name
Test status
Simulation time 42158877 ps
CPU time 0.63 seconds
Started Jan 07 12:49:36 PM PST 24
Finished Jan 07 12:50:40 PM PST 24
Peak memory 202604 kb
Host smart-c3ec6f41-372a-4160-9abf-f61bfacca446
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445511005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1445511005
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2588827275
Short name T1438
Test name
Test status
Simulation time 36408028 ps
CPU time 0.62 seconds
Started Jan 07 12:50:01 PM PST 24
Finished Jan 07 12:51:17 PM PST 24
Peak memory 202704 kb
Host smart-c3f359c7-5e20-43df-8525-7e62e9140ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588827275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2588827275
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3772616236
Short name T103
Test name
Test status
Simulation time 58390180 ps
CPU time 1.42 seconds
Started Jan 07 12:49:26 PM PST 24
Finished Jan 07 12:50:33 PM PST 24
Peak memory 202956 kb
Host smart-f44fe30c-f0cd-40a6-ae9e-d94c7a95d3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772616236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3772616236
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.74214552
Short name T1436
Test name
Test status
Simulation time 189028687 ps
CPU time 1.28 seconds
Started Jan 07 12:49:42 PM PST 24
Finished Jan 07 12:50:52 PM PST 24
Peak memory 202920 kb
Host smart-d8fe294b-4e89-4099-b799-1fac8fae75d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74214552 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.74214552
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1832818909
Short name T1400
Test name
Test status
Simulation time 25937427 ps
CPU time 0.67 seconds
Started Jan 07 12:49:26 PM PST 24
Finished Jan 07 12:51:07 PM PST 24
Peak memory 202596 kb
Host smart-3d14a1ae-450c-48ca-a978-5465fe127ba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832818909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1832818909
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3263471820
Short name T1428
Test name
Test status
Simulation time 20963453 ps
CPU time 0.64 seconds
Started Jan 07 12:49:22 PM PST 24
Finished Jan 07 12:50:36 PM PST 24
Peak memory 202588 kb
Host smart-b060458b-9a90-4820-801b-bfe1bdc9c9b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263471820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3263471820
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.652361012
Short name T1405
Test name
Test status
Simulation time 23812341 ps
CPU time 1.05 seconds
Started Jan 07 12:49:34 PM PST 24
Finished Jan 07 12:50:38 PM PST 24
Peak memory 202952 kb
Host smart-319c1342-a2fc-4c3b-b6d0-39c7f9773a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652361012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.652361012
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.348869571
Short name T1423
Test name
Test status
Simulation time 442255514 ps
CPU time 1.79 seconds
Started Jan 07 12:50:00 PM PST 24
Finished Jan 07 12:51:24 PM PST 24
Peak memory 202864 kb
Host smart-f536ad05-2fed-45d0-ac84-32fbe58cce9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348869571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.348869571
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.874455849
Short name T1433
Test name
Test status
Simulation time 51849948 ps
CPU time 1.34 seconds
Started Jan 07 12:49:33 PM PST 24
Finished Jan 07 12:50:45 PM PST 24
Peak memory 203004 kb
Host smart-e4deb1ce-6707-4d5d-af73-60be2138a7cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874455849 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.874455849
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1463080256
Short name T109
Test name
Test status
Simulation time 20037905 ps
CPU time 0.7 seconds
Started Jan 07 12:50:08 PM PST 24
Finished Jan 07 12:51:33 PM PST 24
Peak memory 202660 kb
Host smart-74e700bd-47ab-40fe-9f2d-ace024e4366a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463080256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1463080256
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4219964440
Short name T1444
Test name
Test status
Simulation time 21296661 ps
CPU time 0.75 seconds
Started Jan 07 12:50:03 PM PST 24
Finished Jan 07 12:51:33 PM PST 24
Peak memory 202648 kb
Host smart-9bd6e3fc-59b4-4ac6-996c-4722e8d1e5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219964440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.4219964440
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1096933488
Short name T1440
Test name
Test status
Simulation time 24535131 ps
CPU time 1.08 seconds
Started Jan 07 12:49:25 PM PST 24
Finished Jan 07 12:50:40 PM PST 24
Peak memory 202912 kb
Host smart-8cec7697-a122-4d97-89aa-7d70c27b9c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096933488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1096933488
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2638277627
Short name T1454
Test name
Test status
Simulation time 148959503 ps
CPU time 1.43 seconds
Started Jan 07 12:49:58 PM PST 24
Finished Jan 07 12:51:53 PM PST 24
Peak memory 202956 kb
Host smart-4edf72bc-0153-42e4-aa17-1b57f68562f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638277627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2638277627
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1457389182
Short name T1417
Test name
Test status
Simulation time 19502663 ps
CPU time 0.77 seconds
Started Jan 07 12:49:45 PM PST 24
Finished Jan 07 12:50:57 PM PST 24
Peak memory 202620 kb
Host smart-54281351-e629-4fa0-9e46-6547abfc8bd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457389182 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1457389182
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.21312637
Short name T1402
Test name
Test status
Simulation time 25354336 ps
CPU time 0.63 seconds
Started Jan 07 12:49:52 PM PST 24
Finished Jan 07 12:51:03 PM PST 24
Peak memory 202728 kb
Host smart-36dc1744-13c9-4e96-8cd0-10c7db8bcada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.21312637
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2626553130
Short name T1464
Test name
Test status
Simulation time 281395532 ps
CPU time 0.88 seconds
Started Jan 07 12:50:01 PM PST 24
Finished Jan 07 12:51:14 PM PST 24
Peak memory 202988 kb
Host smart-daa1f46f-9e94-44dd-ab50-03b70acb58c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626553130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2626553130
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4255661102
Short name T1468
Test name
Test status
Simulation time 83648508 ps
CPU time 1.11 seconds
Started Jan 07 12:49:19 PM PST 24
Finished Jan 07 12:51:11 PM PST 24
Peak memory 202992 kb
Host smart-339827d8-f868-404a-85bb-68e70c1f4c75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255661102 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.4255661102
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2494051744
Short name T1398
Test name
Test status
Simulation time 35849508 ps
CPU time 0.68 seconds
Started Jan 07 12:49:27 PM PST 24
Finished Jan 07 12:50:33 PM PST 24
Peak memory 202456 kb
Host smart-de2a9fbb-327e-463d-b352-72189c722ec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494051744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2494051744
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1181454704
Short name T1415
Test name
Test status
Simulation time 34083876 ps
CPU time 0.62 seconds
Started Jan 07 12:49:46 PM PST 24
Finished Jan 07 12:51:12 PM PST 24
Peak memory 202660 kb
Host smart-56cc8307-058d-4081-bc51-1af123cbb361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181454704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1181454704
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2028219244
Short name T115
Test name
Test status
Simulation time 48145587 ps
CPU time 0.92 seconds
Started Jan 07 12:49:45 PM PST 24
Finished Jan 07 12:51:06 PM PST 24
Peak memory 202492 kb
Host smart-bab27cc0-8d3b-42d3-a276-9c5100afb96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028219244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2028219244
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3060082381
Short name T1403
Test name
Test status
Simulation time 60976120 ps
CPU time 1.56 seconds
Started Jan 07 12:50:04 PM PST 24
Finished Jan 07 12:51:36 PM PST 24
Peak memory 202968 kb
Host smart-f084bc4b-46e2-440b-b6ca-cf7010efb5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060082381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3060082381
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1398907577
Short name T27
Test name
Test status
Simulation time 82937588 ps
CPU time 0.91 seconds
Started Jan 07 12:49:00 PM PST 24
Finished Jan 07 12:50:28 PM PST 24
Peak memory 202644 kb
Host smart-e4232715-8230-42be-9aed-cea84547e2d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398907577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1398907577
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2845841686
Short name T1418
Test name
Test status
Simulation time 156095390 ps
CPU time 2.24 seconds
Started Jan 07 12:49:54 PM PST 24
Finished Jan 07 12:51:37 PM PST 24
Peak memory 202908 kb
Host smart-a6b49a41-a134-490b-a762-37cafa84578b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845841686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2845841686
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.664432305
Short name T1465
Test name
Test status
Simulation time 17582359 ps
CPU time 0.67 seconds
Started Jan 07 12:49:51 PM PST 24
Finished Jan 07 12:51:21 PM PST 24
Peak memory 201800 kb
Host smart-6cd1dc9d-351b-4be3-97a2-696c5974fb77
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664432305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.664432305
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3453222655
Short name T1385
Test name
Test status
Simulation time 25785307 ps
CPU time 1.17 seconds
Started Jan 07 12:49:17 PM PST 24
Finished Jan 07 12:50:34 PM PST 24
Peak memory 202988 kb
Host smart-43f6c93d-d54f-45c9-84f0-9085d8e51de3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453222655 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3453222655
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3577457396
Short name T1452
Test name
Test status
Simulation time 19117853 ps
CPU time 0.65 seconds
Started Jan 07 12:49:19 PM PST 24
Finished Jan 07 12:50:35 PM PST 24
Peak memory 202656 kb
Host smart-018d4bbd-6909-4fe0-9838-30f5cd52f3f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577457396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3577457396
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3859193584
Short name T1429
Test name
Test status
Simulation time 108970168 ps
CPU time 0.71 seconds
Started Jan 07 12:49:28 PM PST 24
Finished Jan 07 12:50:34 PM PST 24
Peak memory 202632 kb
Host smart-be5b8561-edc2-4fae-a5a2-734ae2c4093a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859193584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3859193584
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1513996062
Short name T1424
Test name
Test status
Simulation time 23924252 ps
CPU time 0.88 seconds
Started Jan 07 12:49:43 PM PST 24
Finished Jan 07 12:51:26 PM PST 24
Peak memory 202648 kb
Host smart-cfd8327d-a0fa-4093-b5c2-cc92919ba508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513996062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1513996062
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1345730452
Short name T121
Test name
Test status
Simulation time 73291923 ps
CPU time 1.36 seconds
Started Jan 07 12:49:51 PM PST 24
Finished Jan 07 12:50:57 PM PST 24
Peak memory 202848 kb
Host smart-c7379712-b252-4f8a-9a86-926de38b2ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345730452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1345730452
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2929401646
Short name T1399
Test name
Test status
Simulation time 155048452 ps
CPU time 1.63 seconds
Started Jan 07 12:49:56 PM PST 24
Finished Jan 07 12:51:32 PM PST 24
Peak memory 202832 kb
Host smart-e9569b00-7388-467a-b721-0a469ac074d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929401646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2929401646
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.283336687
Short name T69
Test name
Test status
Simulation time 21139638 ps
CPU time 0.68 seconds
Started Jan 07 12:49:36 PM PST 24
Finished Jan 07 12:51:01 PM PST 24
Peak memory 202624 kb
Host smart-1a743151-cb47-4dcc-aa15-308b215c8f7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283336687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.283336687
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3862838016
Short name T1476
Test name
Test status
Simulation time 16701711 ps
CPU time 0.63 seconds
Started Jan 07 12:50:03 PM PST 24
Finished Jan 07 12:51:15 PM PST 24
Peak memory 202724 kb
Host smart-0db5e0de-2f9e-4a0d-9201-a6a37766ff8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862838016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3862838016
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.574298291
Short name T1380
Test name
Test status
Simulation time 18994886 ps
CPU time 0.63 seconds
Started Jan 07 12:49:22 PM PST 24
Finished Jan 07 12:50:50 PM PST 24
Peak memory 202588 kb
Host smart-8e1afee7-eba4-44b6-8756-cea64741b41f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574298291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.574298291
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2156647335
Short name T1431
Test name
Test status
Simulation time 17930296 ps
CPU time 0.63 seconds
Started Jan 07 12:49:25 PM PST 24
Finished Jan 07 12:50:33 PM PST 24
Peak memory 202744 kb
Host smart-299249b1-0d73-48b8-bd7c-b56925727226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156647335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2156647335
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.214164581
Short name T1458
Test name
Test status
Simulation time 28950183 ps
CPU time 0.69 seconds
Started Jan 07 12:50:00 PM PST 24
Finished Jan 07 12:51:09 PM PST 24
Peak memory 202708 kb
Host smart-59fd99dd-ab7c-41fb-967e-e0340de06602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214164581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.214164581
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1942729628
Short name T1449
Test name
Test status
Simulation time 18769582 ps
CPU time 0.66 seconds
Started Jan 07 12:49:43 PM PST 24
Finished Jan 07 12:50:52 PM PST 24
Peak memory 202512 kb
Host smart-20d78ceb-bafe-4264-9923-406feb8d5e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942729628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1942729628
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.4248044308
Short name T110
Test name
Test status
Simulation time 257427292 ps
CPU time 1.29 seconds
Started Jan 07 12:49:48 PM PST 24
Finished Jan 07 12:51:22 PM PST 24
Peak memory 202844 kb
Host smart-2e9e1e70-18ca-4151-bb26-1936556c5cdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248044308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.4248044308
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.970929620
Short name T1386
Test name
Test status
Simulation time 19941481 ps
CPU time 0.67 seconds
Started Jan 07 12:49:56 PM PST 24
Finished Jan 07 12:51:13 PM PST 24
Peak memory 202664 kb
Host smart-1dbafaa3-67b9-4c54-af7c-c35c3202919f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970929620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.970929620
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2371155106
Short name T1388
Test name
Test status
Simulation time 17422883 ps
CPU time 0.65 seconds
Started Jan 07 12:49:19 PM PST 24
Finished Jan 07 12:50:35 PM PST 24
Peak memory 202648 kb
Host smart-9b00892a-bfe0-4c71-b6a8-c8c59df72407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371155106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2371155106
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3358560848
Short name T1472
Test name
Test status
Simulation time 58289643 ps
CPU time 0.77 seconds
Started Jan 07 12:49:24 PM PST 24
Finished Jan 07 12:50:42 PM PST 24
Peak memory 202656 kb
Host smart-00fc99ca-13a8-4b9f-ac41-a4b9aa2a391b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358560848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3358560848
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3525960972
Short name T1448
Test name
Test status
Simulation time 431485757 ps
CPU time 2.14 seconds
Started Jan 07 12:49:37 PM PST 24
Finished Jan 07 12:51:16 PM PST 24
Peak memory 202952 kb
Host smart-1e7b1337-54b2-4d9a-a965-764a57083839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525960972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3525960972
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2347671450
Short name T82
Test name
Test status
Simulation time 117339693 ps
CPU time 1.8 seconds
Started Jan 07 12:49:36 PM PST 24
Finished Jan 07 12:50:50 PM PST 24
Peak memory 202876 kb
Host smart-49becd50-21ba-49aa-beb8-a273e3b87c96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347671450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2347671450
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.588671782
Short name T1459
Test name
Test status
Simulation time 17489437 ps
CPU time 0.64 seconds
Started Jan 07 12:49:51 PM PST 24
Finished Jan 07 12:50:57 PM PST 24
Peak memory 202620 kb
Host smart-4b6139c4-51fb-41bb-8dd4-5e5167b2db31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588671782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.588671782
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3101775458
Short name T1406
Test name
Test status
Simulation time 40468882 ps
CPU time 0.71 seconds
Started Jan 07 12:49:54 PM PST 24
Finished Jan 07 12:51:10 PM PST 24
Peak memory 202648 kb
Host smart-d76a45e2-b3ea-4bcd-97ce-d083d0441248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101775458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3101775458
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1196301918
Short name T1473
Test name
Test status
Simulation time 17847407 ps
CPU time 0.65 seconds
Started Jan 07 12:50:10 PM PST 24
Finished Jan 07 12:51:37 PM PST 24
Peak memory 202668 kb
Host smart-272a17c4-db66-4557-8fbb-790d31d72400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196301918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1196301918
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1639254319
Short name T1475
Test name
Test status
Simulation time 56373695 ps
CPU time 0.63 seconds
Started Jan 07 12:49:46 PM PST 24
Finished Jan 07 12:51:21 PM PST 24
Peak memory 202676 kb
Host smart-99c03754-9d5d-4551-a7aa-34236d5d1f5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639254319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1639254319
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1610349446
Short name T1396
Test name
Test status
Simulation time 39962562 ps
CPU time 0.64 seconds
Started Jan 07 12:50:03 PM PST 24
Finished Jan 07 12:51:15 PM PST 24
Peak memory 202660 kb
Host smart-3e25842c-7050-4ba7-9e96-f4f7a5ffff18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610349446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1610349446
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.641046596
Short name T1404
Test name
Test status
Simulation time 40364963 ps
CPU time 0.6 seconds
Started Jan 07 12:49:47 PM PST 24
Finished Jan 07 12:51:06 PM PST 24
Peak memory 202660 kb
Host smart-512d6581-a2ed-421f-95af-eb9bd92da7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641046596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.641046596
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3408648612
Short name T107
Test name
Test status
Simulation time 41316349 ps
CPU time 0.89 seconds
Started Jan 07 12:49:45 PM PST 24
Finished Jan 07 12:50:50 PM PST 24
Peak memory 202660 kb
Host smart-ae36000e-9f15-4e52-b3f4-bada0c2bd9dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408648612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3408648612
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3490127789
Short name T117
Test name
Test status
Simulation time 55577144 ps
CPU time 2.03 seconds
Started Jan 07 12:51:04 PM PST 24
Finished Jan 07 12:52:41 PM PST 24
Peak memory 202600 kb
Host smart-88d05733-ea24-4492-92e6-5ad6796e01ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490127789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3490127789
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.579295610
Short name T1416
Test name
Test status
Simulation time 76413962 ps
CPU time 0.83 seconds
Started Jan 07 12:49:33 PM PST 24
Finished Jan 07 12:50:42 PM PST 24
Peak memory 202644 kb
Host smart-d81862ec-1e9c-4b9d-b884-12d04e9fb58e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579295610 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.579295610
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.883450175
Short name T112
Test name
Test status
Simulation time 61482357 ps
CPU time 0.72 seconds
Started Jan 07 12:49:41 PM PST 24
Finished Jan 07 12:50:55 PM PST 24
Peak memory 202464 kb
Host smart-f4e7ec19-850c-458a-a732-11d3c783cbfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883450175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.883450175
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3883757392
Short name T104
Test name
Test status
Simulation time 35314669 ps
CPU time 0.81 seconds
Started Jan 07 12:51:29 PM PST 24
Finished Jan 07 12:52:47 PM PST 24
Peak memory 202372 kb
Host smart-1718693c-84d7-454a-ba36-c0360ba75bf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883757392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.3883757392
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2945777264
Short name T102
Test name
Test status
Simulation time 132122893 ps
CPU time 1.75 seconds
Started Jan 07 12:49:40 PM PST 24
Finished Jan 07 12:50:55 PM PST 24
Peak memory 202912 kb
Host smart-971884f2-d906-44d1-9fec-f5a9778782f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945777264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2945777264
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.577555355
Short name T87
Test name
Test status
Simulation time 258654091 ps
CPU time 1.64 seconds
Started Jan 07 12:51:02 PM PST 24
Finished Jan 07 12:52:28 PM PST 24
Peak memory 202564 kb
Host smart-739feb30-a5fd-4afc-b56a-eebe07dc7a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577555355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.577555355
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2151565602
Short name T1443
Test name
Test status
Simulation time 22169982 ps
CPU time 0.66 seconds
Started Jan 07 12:49:54 PM PST 24
Finished Jan 07 12:51:10 PM PST 24
Peak memory 202684 kb
Host smart-f2b66936-a67a-4c8f-a205-8de801e7473c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151565602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2151565602
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.815462752
Short name T1456
Test name
Test status
Simulation time 43493154 ps
CPU time 0.62 seconds
Started Jan 07 12:50:10 PM PST 24
Finished Jan 07 12:51:33 PM PST 24
Peak memory 202668 kb
Host smart-b6cb6987-b860-42f9-9498-5f5f97f43020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815462752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.815462752
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2413274428
Short name T1382
Test name
Test status
Simulation time 15790766 ps
CPU time 0.68 seconds
Started Jan 07 12:49:34 PM PST 24
Finished Jan 07 12:50:44 PM PST 24
Peak memory 202644 kb
Host smart-218413ad-3aee-49d9-a220-07b7c604da64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413274428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2413274428
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3141253488
Short name T1401
Test name
Test status
Simulation time 46257338 ps
CPU time 0.68 seconds
Started Jan 07 12:49:49 PM PST 24
Finished Jan 07 12:51:36 PM PST 24
Peak memory 202676 kb
Host smart-f2875e7d-b8ae-4642-ab55-e79f9a8389cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141253488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3141253488
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.4158794295
Short name T1381
Test name
Test status
Simulation time 43486205 ps
CPU time 0.64 seconds
Started Jan 07 12:49:57 PM PST 24
Finished Jan 07 12:51:43 PM PST 24
Peak memory 202588 kb
Host smart-5ad27765-883e-4607-9d58-0e9f4449b735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158794295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.4158794295
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2869568381
Short name T1426
Test name
Test status
Simulation time 76003245 ps
CPU time 0.67 seconds
Started Jan 07 12:50:01 PM PST 24
Finished Jan 07 12:51:07 PM PST 24
Peak memory 202636 kb
Host smart-3e29e1d0-800c-4557-b9d6-3a92f69d959c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869568381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2869568381
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.304671630
Short name T1387
Test name
Test status
Simulation time 20024945 ps
CPU time 0.64 seconds
Started Jan 07 12:50:05 PM PST 24
Finished Jan 07 12:51:21 PM PST 24
Peak memory 202636 kb
Host smart-a98d1e36-69b3-4131-8baa-0121ff7f8356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304671630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.304671630
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3423445817
Short name T1427
Test name
Test status
Simulation time 16826290 ps
CPU time 0.66 seconds
Started Jan 07 12:50:28 PM PST 24
Finished Jan 07 12:51:55 PM PST 24
Peak memory 202668 kb
Host smart-6917f658-2cdf-4bad-8db9-fc1b4ab62b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423445817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3423445817
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.831857325
Short name T1474
Test name
Test status
Simulation time 91711705 ps
CPU time 0.61 seconds
Started Jan 07 12:49:54 PM PST 24
Finished Jan 07 12:51:10 PM PST 24
Peak memory 200836 kb
Host smart-e0eafa0f-edf8-43b4-afce-a195029ef341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831857325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.831857325
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3412059465
Short name T1410
Test name
Test status
Simulation time 19277656 ps
CPU time 0.64 seconds
Started Jan 07 12:50:26 PM PST 24
Finished Jan 07 12:51:47 PM PST 24
Peak memory 202644 kb
Host smart-0b5d867a-4a57-4873-aa12-4dad448e5a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412059465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3412059465
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3383316619
Short name T120
Test name
Test status
Simulation time 48908778 ps
CPU time 0.77 seconds
Started Jan 07 12:49:17 PM PST 24
Finished Jan 07 12:50:31 PM PST 24
Peak memory 202820 kb
Host smart-bb62c74c-3040-43f0-91f7-ea801963a13d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383316619 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3383316619
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1374960693
Short name T1441
Test name
Test status
Simulation time 32447300 ps
CPU time 0.69 seconds
Started Jan 07 12:49:10 PM PST 24
Finished Jan 07 12:50:33 PM PST 24
Peak memory 202716 kb
Host smart-bb93df99-5822-4127-bd76-774cc751174c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374960693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1374960693
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2762687098
Short name T113
Test name
Test status
Simulation time 46265708 ps
CPU time 0.98 seconds
Started Jan 07 12:49:27 PM PST 24
Finished Jan 07 12:50:41 PM PST 24
Peak memory 202920 kb
Host smart-b7824e97-f662-4d0a-8a10-5b9962fd202e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762687098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2762687098
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1042650678
Short name T1392
Test name
Test status
Simulation time 28690293 ps
CPU time 1.18 seconds
Started Jan 07 12:49:20 PM PST 24
Finished Jan 07 12:50:33 PM PST 24
Peak memory 203052 kb
Host smart-c7bb752f-3d3c-4937-99a6-274fd662c265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042650678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1042650678
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3932186700
Short name T1393
Test name
Test status
Simulation time 49669994 ps
CPU time 1.12 seconds
Started Jan 07 12:49:39 PM PST 24
Finished Jan 07 12:50:55 PM PST 24
Peak memory 202908 kb
Host smart-7e8e4544-4821-4661-87cb-6035d0b77d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932186700 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3932186700
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.474186920
Short name T1457
Test name
Test status
Simulation time 27039602 ps
CPU time 0.63 seconds
Started Jan 07 12:49:53 PM PST 24
Finished Jan 07 12:51:24 PM PST 24
Peak memory 202060 kb
Host smart-5b4b7e19-19de-4eca-9afc-b23f69c005c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474186920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.474186920
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1502973141
Short name T1453
Test name
Test status
Simulation time 15441373 ps
CPU time 0.64 seconds
Started Jan 07 12:50:01 PM PST 24
Finished Jan 07 12:51:25 PM PST 24
Peak memory 202692 kb
Host smart-bfc1a643-5519-436b-9ab6-c6fd8795cb3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502973141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1502973141
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2314214207
Short name T1437
Test name
Test status
Simulation time 384787365 ps
CPU time 2 seconds
Started Jan 07 12:51:33 PM PST 24
Finished Jan 07 12:52:45 PM PST 24
Peak memory 202604 kb
Host smart-e9fb589b-15cd-4b49-91d2-e379e7dc0d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314214207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2314214207
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2368106130
Short name T29
Test name
Test status
Simulation time 108166379 ps
CPU time 1.15 seconds
Started Jan 07 12:49:29 PM PST 24
Finished Jan 07 12:51:07 PM PST 24
Peak memory 202900 kb
Host smart-07483a98-8623-4b54-b479-ac09a22e775f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368106130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2368106130
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.996359817
Short name T1434
Test name
Test status
Simulation time 17843324 ps
CPU time 0.65 seconds
Started Jan 07 12:49:19 PM PST 24
Finished Jan 07 12:50:39 PM PST 24
Peak memory 202156 kb
Host smart-f1727779-7a10-43c2-807c-1a129ce1fcc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996359817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.996359817
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2665115547
Short name T1450
Test name
Test status
Simulation time 54440569 ps
CPU time 1.47 seconds
Started Jan 07 12:49:50 PM PST 24
Finished Jan 07 12:51:26 PM PST 24
Peak memory 202968 kb
Host smart-04fb2cf7-0a63-49ab-92aa-574da5629a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665115547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2665115547
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3565230926
Short name T1463
Test name
Test status
Simulation time 65349718 ps
CPU time 1.21 seconds
Started Jan 07 12:49:14 PM PST 24
Finished Jan 07 12:50:26 PM PST 24
Peak memory 202916 kb
Host smart-512fce9d-9d04-4d36-8bd1-66f0998d8f63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565230926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3565230926
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3781151983
Short name T1470
Test name
Test status
Simulation time 21490024 ps
CPU time 0.71 seconds
Started Jan 07 12:49:51 PM PST 24
Finished Jan 07 12:51:07 PM PST 24
Peak memory 202660 kb
Host smart-78bf6e1b-255c-4932-8345-6f9a81c8fb7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781151983 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3781151983
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1998836747
Short name T108
Test name
Test status
Simulation time 52342621 ps
CPU time 0.67 seconds
Started Jan 07 12:48:55 PM PST 24
Finished Jan 07 12:50:15 PM PST 24
Peak memory 202752 kb
Host smart-89b5aaac-69fd-4a48-9944-ff90501fbfc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998836747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1998836747
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.733037782
Short name T1412
Test name
Test status
Simulation time 18655954 ps
CPU time 0.6 seconds
Started Jan 07 12:49:06 PM PST 24
Finished Jan 07 12:50:01 PM PST 24
Peak memory 200716 kb
Host smart-39c6d52e-bfcb-4af6-a2bd-e836fa5b0987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733037782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.733037782
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2068774032
Short name T28
Test name
Test status
Simulation time 70280462 ps
CPU time 0.99 seconds
Started Jan 07 12:49:52 PM PST 24
Finished Jan 07 12:51:09 PM PST 24
Peak memory 202732 kb
Host smart-f923e6a1-d190-41ec-8121-a1dfb27424df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068774032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2068774032
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1243423671
Short name T31
Test name
Test status
Simulation time 118272864 ps
CPU time 1.18 seconds
Started Jan 07 12:49:20 PM PST 24
Finished Jan 07 12:50:39 PM PST 24
Peak memory 202876 kb
Host smart-cb519a77-2528-486c-9b20-80f24f6fe025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243423671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1243423671
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3866356085
Short name T1425
Test name
Test status
Simulation time 86009938 ps
CPU time 1.12 seconds
Started Jan 07 12:49:50 PM PST 24
Finished Jan 07 12:51:07 PM PST 24
Peak memory 202972 kb
Host smart-2df7705d-4fd9-476f-b43d-e55e38f4b3ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866356085 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3866356085
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3660928880
Short name T1421
Test name
Test status
Simulation time 144581079 ps
CPU time 0.66 seconds
Started Jan 07 12:49:57 PM PST 24
Finished Jan 07 12:51:04 PM PST 24
Peak memory 201940 kb
Host smart-da00f2a7-ac04-433c-9282-38c7d9de8389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660928880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3660928880
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1576350072
Short name T1397
Test name
Test status
Simulation time 18073986 ps
CPU time 0.65 seconds
Started Jan 07 12:50:00 PM PST 24
Finished Jan 07 12:51:13 PM PST 24
Peak memory 202676 kb
Host smart-1b4747f0-fbfc-4feb-8313-406e96921c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576350072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1576350072
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4019317856
Short name T1430
Test name
Test status
Simulation time 40669824 ps
CPU time 0.8 seconds
Started Jan 07 12:50:20 PM PST 24
Finished Jan 07 12:51:37 PM PST 24
Peak memory 202708 kb
Host smart-c3c1880a-e854-4d45-8a26-11d2f85c6390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019317856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.4019317856
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2666976116
Short name T1414
Test name
Test status
Simulation time 41604198 ps
CPU time 1.95 seconds
Started Jan 07 12:49:50 PM PST 24
Finished Jan 07 12:51:42 PM PST 24
Peak memory 202996 kb
Host smart-a865eef9-4b1f-4f48-87a0-fa25a1550b14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666976116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2666976116
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1433615357
Short name T88
Test name
Test status
Simulation time 119502691 ps
CPU time 1.2 seconds
Started Jan 07 12:49:10 PM PST 24
Finished Jan 07 12:50:07 PM PST 24
Peak memory 202828 kb
Host smart-cc216c1f-fcbd-4afa-a637-78be76da534b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433615357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1433615357
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2850002881
Short name T685
Test name
Test status
Simulation time 16766649 ps
CPU time 0.59 seconds
Started Jan 07 01:42:56 PM PST 24
Finished Jan 07 01:43:13 PM PST 24
Peak memory 202108 kb
Host smart-85907eda-5c6f-4e53-9075-f6872d41ea76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850002881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2850002881
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1917461853
Short name T972
Test name
Test status
Simulation time 87365967 ps
CPU time 1.21 seconds
Started Jan 07 01:42:13 PM PST 24
Finished Jan 07 01:42:24 PM PST 24
Peak memory 211332 kb
Host smart-ab5facf3-f1ce-47ca-a40e-46b6a7609a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917461853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1917461853
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3077940215
Short name T1279
Test name
Test status
Simulation time 985315556 ps
CPU time 7.68 seconds
Started Jan 07 01:43:54 PM PST 24
Finished Jan 07 01:44:12 PM PST 24
Peak memory 287092 kb
Host smart-1363e6b5-b3a8-4693-b620-c54266fdda6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077940215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3077940215
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1832344895
Short name T433
Test name
Test status
Simulation time 1950831827 ps
CPU time 63.67 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:44:54 PM PST 24
Peak memory 603876 kb
Host smart-ae9a410f-0c45-41d8-be57-6c738adf9d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832344895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1832344895
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3296346628
Short name T428
Test name
Test status
Simulation time 6189598275 ps
CPU time 873.7 seconds
Started Jan 07 01:43:46 PM PST 24
Finished Jan 07 01:58:32 PM PST 24
Peak memory 1696708 kb
Host smart-68a7c8db-9af8-4167-a78d-51b868c153cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296346628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3296346628
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3781039080
Short name T1243
Test name
Test status
Simulation time 208254784 ps
CPU time 5 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 203212 kb
Host smart-7a39d393-b6f8-4d38-8498-0e4abe382b11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781039080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3781039080
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2916570204
Short name T756
Test name
Test status
Simulation time 8044461481 ps
CPU time 346.78 seconds
Started Jan 07 01:43:25 PM PST 24
Finished Jan 07 01:49:30 PM PST 24
Peak memory 1166328 kb
Host smart-49efb1af-a965-4d94-8c2f-b0fefe417fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916570204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2916570204
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.54348242
Short name T1348
Test name
Test status
Simulation time 6665906139 ps
CPU time 41.72 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:44:12 PM PST 24
Peak memory 280436 kb
Host smart-e90436dd-35ce-4556-83af-ea3692c8f215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54348242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.54348242
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.1644879645
Short name T1227
Test name
Test status
Simulation time 17361652 ps
CPU time 0.64 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:44:06 PM PST 24
Peak memory 202396 kb
Host smart-8ff53e84-8c04-49e4-b84f-2832d9691291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644879645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1644879645
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3510762624
Short name T1355
Test name
Test status
Simulation time 6883644485 ps
CPU time 102.55 seconds
Started Jan 07 01:43:38 PM PST 24
Finished Jan 07 01:45:37 PM PST 24
Peak memory 203276 kb
Host smart-8cdaaa02-629e-4e9d-9b07-fabb7bb24112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510762624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3510762624
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_rx_oversample.3946031562
Short name T171
Test name
Test status
Simulation time 3132804481 ps
CPU time 151.47 seconds
Started Jan 07 01:43:55 PM PST 24
Finished Jan 07 01:46:36 PM PST 24
Peak memory 372244 kb
Host smart-27d67f85-1924-4ed3-b33d-2235953f33a7
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946031562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_rx_oversample.
3946031562
Directory /workspace/0.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1590014724
Short name T891
Test name
Test status
Simulation time 3115246940 ps
CPU time 60.42 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:44:46 PM PST 24
Peak memory 296672 kb
Host smart-018232cb-eaee-476a-9d72-34aa31353f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590014724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1590014724
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.451276452
Short name T1091
Test name
Test status
Simulation time 842292186 ps
CPU time 9.27 seconds
Started Jan 07 01:43:46 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 219592 kb
Host smart-ea21c8e1-308f-4da5-a0a0-d40489bc2284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451276452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.451276452
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1028054646
Short name T92
Test name
Test status
Simulation time 39059007 ps
CPU time 0.81 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 219600 kb
Host smart-6a191989-0fc5-4390-b2a4-ff32d5c37faa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028054646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1028054646
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.601108868
Short name T579
Test name
Test status
Simulation time 3188983283 ps
CPU time 3.75 seconds
Started Jan 07 01:42:34 PM PST 24
Finished Jan 07 01:42:56 PM PST 24
Peak memory 203240 kb
Host smart-18d68ca7-d01d-478e-9f99-58fe5354d8b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601108868 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.601108868
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.208383669
Short name T748
Test name
Test status
Simulation time 10244305578 ps
CPU time 15.47 seconds
Started Jan 07 01:42:59 PM PST 24
Finished Jan 07 01:43:30 PM PST 24
Peak memory 316400 kb
Host smart-aa3f6351-72d5-434b-9c6f-7eff22ffc3ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208383669 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_acq.208383669
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3687572273
Short name T963
Test name
Test status
Simulation time 10247568373 ps
CPU time 14.5 seconds
Started Jan 07 01:42:34 PM PST 24
Finished Jan 07 01:43:06 PM PST 24
Peak memory 310156 kb
Host smart-d4206709-34ce-479b-aa4b-d5acfe650503
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687572273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3687572273
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1897862111
Short name T482
Test name
Test status
Simulation time 1352757330 ps
CPU time 3.07 seconds
Started Jan 07 01:42:29 PM PST 24
Finished Jan 07 01:42:49 PM PST 24
Peak memory 203352 kb
Host smart-0eb9b26b-adf0-46ff-afca-d448c1874629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897862111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1897862111
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.309375741
Short name T555
Test name
Test status
Simulation time 5014997101 ps
CPU time 5.29 seconds
Started Jan 07 01:42:17 PM PST 24
Finished Jan 07 01:42:38 PM PST 24
Peak memory 203464 kb
Host smart-d66f0856-03d0-45a6-8b0a-1e1507966f46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309375741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.309375741
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.679938746
Short name T387
Test name
Test status
Simulation time 2443351016 ps
CPU time 3.85 seconds
Started Jan 07 01:42:36 PM PST 24
Finished Jan 07 01:42:59 PM PST 24
Peak memory 234000 kb
Host smart-369f4831-ce6a-455e-83ad-8483a7c7dcce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679938746 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.679938746
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.2063325109
Short name T460
Test name
Test status
Simulation time 789598931 ps
CPU time 4.46 seconds
Started Jan 07 01:42:38 PM PST 24
Finished Jan 07 01:43:04 PM PST 24
Peak memory 203196 kb
Host smart-0fdeb3a1-b31f-4171-ab91-f7f7d9562df5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063325109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.2063325109
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1947550451
Short name T325
Test name
Test status
Simulation time 1036208651 ps
CPU time 9.65 seconds
Started Jan 07 01:43:06 PM PST 24
Finished Jan 07 01:43:28 PM PST 24
Peak memory 203128 kb
Host smart-db5559a5-72cf-4d3a-b99d-859074d0aaeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947550451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1947550451
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.886564213
Short name T974
Test name
Test status
Simulation time 13148124787 ps
CPU time 1705.52 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 02:11:50 PM PST 24
Peak memory 1004108 kb
Host smart-78a80a8a-76e9-4f3a-8614-2cb294d1ebe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886564213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_stress_all.886564213
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.481513177
Short name T925
Test name
Test status
Simulation time 1458776369 ps
CPU time 19.18 seconds
Started Jan 07 01:43:00 PM PST 24
Finished Jan 07 01:43:35 PM PST 24
Peak memory 216324 kb
Host smart-378f331a-a334-432f-83e7-fccb4f3eac3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481513177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.481513177
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3307103088
Short name T333
Test name
Test status
Simulation time 39889555492 ps
CPU time 212.87 seconds
Started Jan 07 01:42:39 PM PST 24
Finished Jan 07 01:46:34 PM PST 24
Peak memory 2464444 kb
Host smart-35cb3708-7348-4454-a748-cee72d792af0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307103088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3307103088
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1870790092
Short name T952
Test name
Test status
Simulation time 9729895155 ps
CPU time 7.37 seconds
Started Jan 07 01:42:36 PM PST 24
Finished Jan 07 01:43:03 PM PST 24
Peak memory 210708 kb
Host smart-fe3925dd-5ee1-4859-8c34-a82b72e06bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870790092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1870790092
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_ovf.1517598334
Short name T826
Test name
Test status
Simulation time 11828631913 ps
CPU time 272.82 seconds
Started Jan 07 01:43:00 PM PST 24
Finished Jan 07 01:47:48 PM PST 24
Peak memory 505940 kb
Host smart-c64bf3cf-c223-414a-9005-6c03d3246460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517598334 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_tx_ovf.1517598334
Directory /workspace/0.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.1716459452
Short name T1272
Test name
Test status
Simulation time 6983793220 ps
CPU time 8.74 seconds
Started Jan 07 01:43:05 PM PST 24
Finished Jan 07 01:43:27 PM PST 24
Peak memory 203324 kb
Host smart-574d1589-126d-43e3-b262-e14482d24384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716459452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.1716459452
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1947475833
Short name T1346
Test name
Test status
Simulation time 55835823 ps
CPU time 0.6 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 202180 kb
Host smart-1d616d0c-ceba-45ef-af03-785a26a0e192
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947475833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1947475833
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.4001403452
Short name T742
Test name
Test status
Simulation time 41170202 ps
CPU time 1.74 seconds
Started Jan 07 01:42:49 PM PST 24
Finished Jan 07 01:43:11 PM PST 24
Peak memory 211428 kb
Host smart-2f9d8526-5141-4f66-8b0a-369e1e2c38e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001403452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.4001403452
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.4273925006
Short name T427
Test name
Test status
Simulation time 519291195 ps
CPU time 8.28 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 293704 kb
Host smart-f4e54ce6-8c9c-46e7-8876-671d09e37aca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273925006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.4273925006
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1691441661
Short name T306
Test name
Test status
Simulation time 11035276362 ps
CPU time 147.64 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 569876 kb
Host smart-d4bfae35-a5eb-4524-8fa5-a5b10adb1f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691441661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1691441661
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3079797604
Short name T1184
Test name
Test status
Simulation time 16535152113 ps
CPU time 310.08 seconds
Started Jan 07 01:43:06 PM PST 24
Finished Jan 07 01:48:28 PM PST 24
Peak memory 1402996 kb
Host smart-334f4f02-793d-4c41-b060-ea8718ddc8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079797604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3079797604
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2904586423
Short name T1168
Test name
Test status
Simulation time 364483278 ps
CPU time 0.9 seconds
Started Jan 07 01:42:55 PM PST 24
Finished Jan 07 01:43:13 PM PST 24
Peak memory 203196 kb
Host smart-53f71869-0722-4457-9d7a-e1937b811db8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904586423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2904586423
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.4143416423
Short name T915
Test name
Test status
Simulation time 34638442462 ps
CPU time 206.76 seconds
Started Jan 07 01:42:57 PM PST 24
Finished Jan 07 01:46:40 PM PST 24
Peak memory 1156924 kb
Host smart-5ecef9d1-3c46-4138-9b93-718aca02ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143416423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.4143416423
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1313541916
Short name T271
Test name
Test status
Simulation time 1921807130 ps
CPU time 98.28 seconds
Started Jan 07 01:42:50 PM PST 24
Finished Jan 07 01:44:48 PM PST 24
Peak memory 228772 kb
Host smart-9a53925b-6b1a-4eac-b41b-445e5692c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313541916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1313541916
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.119753829
Short name T1375
Test name
Test status
Simulation time 18758105 ps
CPU time 0.68 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:43:35 PM PST 24
Peak memory 202492 kb
Host smart-b573bf61-5152-4efe-8140-15bab2e83146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119753829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.119753829
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1160298903
Short name T1307
Test name
Test status
Simulation time 2809596835 ps
CPU time 6.26 seconds
Started Jan 07 01:43:08 PM PST 24
Finished Jan 07 01:43:25 PM PST 24
Peak memory 211620 kb
Host smart-10308c32-a0b4-4144-8134-2ba65a034219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160298903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1160298903
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_rx_oversample.3956986867
Short name T527
Test name
Test status
Simulation time 1765665465 ps
CPU time 154.72 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 298972 kb
Host smart-e7960ffc-bfb2-4a7f-8682-2ead303bd00c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956986867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_rx_oversample.
3956986867
Directory /workspace/1.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3138814896
Short name T675
Test name
Test status
Simulation time 8022487445 ps
CPU time 32.9 seconds
Started Jan 07 01:43:11 PM PST 24
Finished Jan 07 01:43:57 PM PST 24
Peak memory 226636 kb
Host smart-9e8fd3b6-5049-4d0c-b1ee-a8e2245d47b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138814896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3138814896
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.218570519
Short name T160
Test name
Test status
Simulation time 116161173404 ps
CPU time 2646.92 seconds
Started Jan 07 01:42:58 PM PST 24
Finished Jan 07 02:27:22 PM PST 24
Peak memory 4006708 kb
Host smart-286cbd77-215e-44c4-b6a4-0acb05073084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218570519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.218570519
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1730703339
Short name T187
Test name
Test status
Simulation time 435019922 ps
CPU time 7.87 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 01:43:35 PM PST 24
Peak memory 211396 kb
Host smart-2ac23643-ccb9-45df-8f2e-7c9f0acae5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730703339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1730703339
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3441053283
Short name T997
Test name
Test status
Simulation time 3443241284 ps
CPU time 3.12 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 01:43:29 PM PST 24
Peak memory 203400 kb
Host smart-1677349f-46b5-4cc0-b881-ad8048190d53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441053283 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3441053283
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3538455648
Short name T563
Test name
Test status
Simulation time 10035029190 ps
CPU time 91.34 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:45:03 PM PST 24
Peak memory 666128 kb
Host smart-64b5eb0e-7c80-4c30-a118-0bf2807658c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538455648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3538455648
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.889711383
Short name T60
Test name
Test status
Simulation time 1762925520 ps
CPU time 4.24 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 203564 kb
Host smart-e8f4fe05-5c94-4aea-9877-433cfacaf161
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889711383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.889711383
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.802604693
Short name T498
Test name
Test status
Simulation time 1336698948 ps
CPU time 4.86 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:43:37 PM PST 24
Peak memory 203228 kb
Host smart-a3c8f3e9-be9f-4a64-9445-c5e5da41bf75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802604693 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.802604693
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.193986189
Short name T1089
Test name
Test status
Simulation time 77547015743 ps
CPU time 920.35 seconds
Started Jan 07 01:42:54 PM PST 24
Finished Jan 07 01:58:32 PM PST 24
Peak memory 4735788 kb
Host smart-9e38f124-4808-4e1a-ac56-68780a8d1f6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193986189 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.193986189
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.121247585
Short name T1005
Test name
Test status
Simulation time 678638919 ps
CPU time 3.85 seconds
Started Jan 07 01:42:52 PM PST 24
Finished Jan 07 01:43:14 PM PST 24
Peak memory 203356 kb
Host smart-14cac526-fc61-4eea-926e-a6cff665a530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121247585 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_perf.121247585
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1464070243
Short name T1080
Test name
Test status
Simulation time 1449585815 ps
CPU time 37.06 seconds
Started Jan 07 01:42:44 PM PST 24
Finished Jan 07 01:43:41 PM PST 24
Peak memory 203312 kb
Host smart-c520072d-580d-493e-bf8f-11643deb826b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464070243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1464070243
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.852795382
Short name T157
Test name
Test status
Simulation time 47629084597 ps
CPU time 705.52 seconds
Started Jan 07 01:42:59 PM PST 24
Finished Jan 07 01:55:01 PM PST 24
Peak memory 1102524 kb
Host smart-94df37ed-6c0c-41d5-a45a-f52cba99a552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852795382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_stress_all.852795382
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1286562606
Short name T286
Test name
Test status
Simulation time 609500414 ps
CPU time 9.5 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:43:39 PM PST 24
Peak memory 204688 kb
Host smart-cb50c949-a21b-4423-8051-06934367ddf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286562606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1286562606
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3576221366
Short name T1217
Test name
Test status
Simulation time 47387583411 ps
CPU time 954.45 seconds
Started Jan 07 01:43:06 PM PST 24
Finished Jan 07 01:59:13 PM PST 24
Peak memory 5419808 kb
Host smart-adc8cb02-9982-4e53-a7e9-34041cc86d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576221366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3576221366
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1864861243
Short name T248
Test name
Test status
Simulation time 20491696654 ps
CPU time 365.86 seconds
Started Jan 07 01:42:47 PM PST 24
Finished Jan 07 01:49:14 PM PST 24
Peak memory 1050084 kb
Host smart-8834857e-76f1-4e66-9719-6cf54c02037b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864861243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1864861243
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3829995984
Short name T1252
Test name
Test status
Simulation time 1648293438 ps
CPU time 7.29 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:45 PM PST 24
Peak memory 213460 kb
Host smart-8f32326d-e51b-4446-ac79-b517f2798fa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829995984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3829995984
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_ovf.2474048473
Short name T1072
Test name
Test status
Simulation time 2997634405 ps
CPU time 96.79 seconds
Started Jan 07 01:42:45 PM PST 24
Finished Jan 07 01:44:41 PM PST 24
Peak memory 327060 kb
Host smart-fb2e4f65-c3f3-4dcf-9cbf-decea9e58983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474048473 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_tx_ovf.2474048473
Directory /workspace/1.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.805033943
Short name T670
Test name
Test status
Simulation time 52537430 ps
CPU time 1.34 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:43:50 PM PST 24
Peak memory 211468 kb
Host smart-f9dd124e-f480-46c1-8670-2de6a251f344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805033943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.805033943
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2823787936
Short name T303
Test name
Test status
Simulation time 744628292 ps
CPU time 16.25 seconds
Started Jan 07 01:43:38 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 368672 kb
Host smart-54055337-4ba7-4221-8a8c-c5ef930c7b7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823787936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2823787936
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1044957235
Short name T1314
Test name
Test status
Simulation time 16434430977 ps
CPU time 78.13 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:44:48 PM PST 24
Peak memory 684412 kb
Host smart-1d7462d2-4640-406f-b12d-632e3f93e6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044957235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1044957235
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.562704074
Short name T580
Test name
Test status
Simulation time 4441147000 ps
CPU time 496.68 seconds
Started Jan 07 01:43:41 PM PST 24
Finished Jan 07 01:52:13 PM PST 24
Peak memory 1243396 kb
Host smart-99bc1efd-6780-49ae-a806-df3e942e74ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562704074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.562704074
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.47525255
Short name T554
Test name
Test status
Simulation time 185557389 ps
CPU time 0.98 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:43:51 PM PST 24
Peak memory 203260 kb
Host smart-364c5ee4-0d30-441e-a942-d9f17b8d7a5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47525255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt
.47525255
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.26927839
Short name T881
Test name
Test status
Simulation time 7577565265 ps
CPU time 303.19 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 01:48:42 PM PST 24
Peak memory 944096 kb
Host smart-9b9d49de-87fd-4f0a-81fc-b1fe189a186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26927839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.26927839
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.4149479444
Short name T732
Test name
Test status
Simulation time 16614919762 ps
CPU time 72.47 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:44:49 PM PST 24
Peak memory 318616 kb
Host smart-580b7165-cc9d-4fa7-a478-5ee50123f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149479444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.4149479444
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_rx_oversample.325338225
Short name T805
Test name
Test status
Simulation time 18217999220 ps
CPU time 152.17 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:46:10 PM PST 24
Peak memory 276792 kb
Host smart-31d3b0ec-78b5-4b82-b4f3-4db9e7a9805e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325338225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_rx_oversample.
325338225
Directory /workspace/10.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3353293355
Short name T126
Test name
Test status
Simulation time 10894637248 ps
CPU time 926.36 seconds
Started Jan 07 01:43:32 PM PST 24
Finished Jan 07 01:59:18 PM PST 24
Peak memory 1239568 kb
Host smart-14f482e4-9bb9-4183-a429-823478b0361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353293355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3353293355
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2760814448
Short name T221
Test name
Test status
Simulation time 5271903191 ps
CPU time 44.23 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:44:17 PM PST 24
Peak memory 211508 kb
Host smart-7dde387c-9839-466c-9950-1230f11af0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760814448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2760814448
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3840143260
Short name T1108
Test name
Test status
Simulation time 1273639463 ps
CPU time 1.88 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:43:49 PM PST 24
Peak memory 203408 kb
Host smart-6f6ab797-a6c1-42ad-ab0f-5804d8f25a4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840143260 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3840143260
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.4014368848
Short name T843
Test name
Test status
Simulation time 10464582932 ps
CPU time 17.03 seconds
Started Jan 07 01:43:37 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 339268 kb
Host smart-945197df-aa7f-4cde-8a23-459abe584fb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014368848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.4014368848
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.347676128
Short name T1316
Test name
Test status
Simulation time 2995997251 ps
CPU time 6.2 seconds
Started Jan 07 01:43:40 PM PST 24
Finished Jan 07 01:44:02 PM PST 24
Peak memory 203344 kb
Host smart-ce123170-7a41-4ae5-84c4-084f38371b7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347676128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.347676128
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1484040954
Short name T1339
Test name
Test status
Simulation time 13860178767 ps
CPU time 139.26 seconds
Started Jan 07 01:43:48 PM PST 24
Finished Jan 07 01:46:19 PM PST 24
Peak memory 1752396 kb
Host smart-86a8e730-bf8a-4ae9-9d40-b59906a2127a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484040954 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1484040954
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.4084851641
Short name T581
Test name
Test status
Simulation time 2516804125 ps
CPU time 4.12 seconds
Started Jan 07 01:43:49 PM PST 24
Finished Jan 07 01:44:04 PM PST 24
Peak memory 203516 kb
Host smart-185c8dea-8b83-4780-b7b4-c568ca9b565a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084851641 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.4084851641
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.3469878791
Short name T1203
Test name
Test status
Simulation time 53288149657 ps
CPU time 3108.82 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 02:35:39 PM PST 24
Peak memory 10203032 kb
Host smart-5b4bbccc-5ddc-42e1-bf5c-deaafeb8d8a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469878791 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.3469878791
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3887901758
Short name T790
Test name
Test status
Simulation time 7170647291 ps
CPU time 26.74 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 203480 kb
Host smart-1aa86629-1c64-4ddf-9761-b6ea036ea96c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887901758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3887901758
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.847230583
Short name T305
Test name
Test status
Simulation time 23401892370 ps
CPU time 655.02 seconds
Started Jan 07 01:43:41 PM PST 24
Finished Jan 07 01:54:51 PM PST 24
Peak memory 4695856 kb
Host smart-b018f0a9-891b-49df-a76a-b8c872ef1e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847230583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_wr.847230583
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2330146678
Short name T1104
Test name
Test status
Simulation time 26636639294 ps
CPU time 243.16 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:47:49 PM PST 24
Peak memory 850992 kb
Host smart-ff75adad-a9bc-4dbf-b9c5-e2d652ca365b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330146678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2330146678
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_tx_ovf.3242200864
Short name T352
Test name
Test status
Simulation time 3057633887 ps
CPU time 150.52 seconds
Started Jan 07 01:43:44 PM PST 24
Finished Jan 07 01:46:29 PM PST 24
Peak memory 447012 kb
Host smart-d52ae944-98c9-46e8-9adb-fd41e07ba37d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242200864 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_tx_ovf.3242200864
Directory /workspace/10.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.3491884253
Short name T935
Test name
Test status
Simulation time 13348056822 ps
CPU time 7.12 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:43:53 PM PST 24
Peak memory 203408 kb
Host smart-92f09961-ab5d-410e-bfcb-528593d377e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491884253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.i2c_target_unexp_stop.3491884253
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.4279735132
Short name T1154
Test name
Test status
Simulation time 133329627 ps
CPU time 0.62 seconds
Started Jan 07 01:43:59 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 202208 kb
Host smart-584a68f6-4d84-44c6-8b96-0424d6b7e521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279735132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.4279735132
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1225988735
Short name T1038
Test name
Test status
Simulation time 142051111 ps
CPU time 1.2 seconds
Started Jan 07 01:43:43 PM PST 24
Finished Jan 07 01:43:59 PM PST 24
Peak memory 211508 kb
Host smart-e520b963-36ae-41a1-a5d6-87b833a22878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225988735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1225988735
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1001576453
Short name T207
Test name
Test status
Simulation time 449679807 ps
CPU time 6.67 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:43:43 PM PST 24
Peak memory 258300 kb
Host smart-229fc7bf-7884-413f-be1a-063309af219c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001576453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1001576453
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2493435715
Short name T690
Test name
Test status
Simulation time 3526762544 ps
CPU time 95.06 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:45:11 PM PST 24
Peak memory 738148 kb
Host smart-72d39890-d593-4803-ab4b-84c107da97eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493435715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2493435715
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1155272688
Short name T764
Test name
Test status
Simulation time 6690111406 ps
CPU time 1003.36 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 02:00:22 PM PST 24
Peak memory 1868296 kb
Host smart-55783fad-a3c5-43f4-8541-775db613e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155272688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1155272688
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2464114820
Short name T477
Test name
Test status
Simulation time 349376908 ps
CPU time 0.89 seconds
Started Jan 07 01:43:32 PM PST 24
Finished Jan 07 01:43:52 PM PST 24
Peak memory 203144 kb
Host smart-95c70955-3ba8-461a-b69d-6bfc466fe89f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464114820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2464114820
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1297735324
Short name T992
Test name
Test status
Simulation time 10529677806 ps
CPU time 560.81 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:52:53 PM PST 24
Peak memory 1545820 kb
Host smart-f9778c16-56f2-450e-9fc0-15e4af486334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297735324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1297735324
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_override.1928178112
Short name T1037
Test name
Test status
Simulation time 19111930 ps
CPU time 0.63 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:33 PM PST 24
Peak memory 202440 kb
Host smart-d6501bec-a81f-45b9-ae25-28a15506625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928178112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1928178112
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_rx_oversample.3559937116
Short name T995
Test name
Test status
Simulation time 3859106375 ps
CPU time 81.51 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:44:57 PM PST 24
Peak memory 302076 kb
Host smart-77fb9441-8fa4-42ca-94ce-fcc29110dd31
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559937116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_rx_oversample
.3559937116
Directory /workspace/11.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3164877231
Short name T1002
Test name
Test status
Simulation time 12982747183 ps
CPU time 83.3 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:44:52 PM PST 24
Peak memory 279752 kb
Host smart-970f9537-8b22-4d8d-a25c-ffea17af78f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164877231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3164877231
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3835286230
Short name T1276
Test name
Test status
Simulation time 19867644906 ps
CPU time 207.01 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:47:38 PM PST 24
Peak memory 220544 kb
Host smart-bed91ed1-033a-4969-a85a-c8f2c092897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835286230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3835286230
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3903701806
Short name T634
Test name
Test status
Simulation time 3350245687 ps
CPU time 11.72 seconds
Started Jan 07 01:43:40 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 219604 kb
Host smart-9b29b880-351c-48a3-afe2-de6baa00db8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903701806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3903701806
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.423309100
Short name T787
Test name
Test status
Simulation time 3322150824 ps
CPU time 3.78 seconds
Started Jan 07 01:43:58 PM PST 24
Finished Jan 07 01:44:10 PM PST 24
Peak memory 203348 kb
Host smart-5c2f56c5-1ca9-438c-b5c7-c8a6531a46ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423309100 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.423309100
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3280364628
Short name T537
Test name
Test status
Simulation time 10264665819 ps
CPU time 11.81 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:44:02 PM PST 24
Peak memory 285736 kb
Host smart-12df9273-b099-4103-80f1-7d560c24771a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280364628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3280364628
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3870446097
Short name T1230
Test name
Test status
Simulation time 10046084827 ps
CPU time 89.52 seconds
Started Jan 07 01:43:51 PM PST 24
Finished Jan 07 01:45:32 PM PST 24
Peak memory 711040 kb
Host smart-eb41ab74-28de-4973-9526-c15d050ab178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870446097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3870446097
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1258798776
Short name T153
Test name
Test status
Simulation time 647301027 ps
CPU time 3.29 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 203244 kb
Host smart-b2be2e2d-0509-45ab-a751-25e73dcdcae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258798776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1258798776
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3334909120
Short name T61
Test name
Test status
Simulation time 25166513416 ps
CPU time 166.23 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:46:31 PM PST 24
Peak memory 1629812 kb
Host smart-7b5279f7-5f28-4be1-8a59-dfe5bb48ace4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334909120 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3334909120
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.2777818096
Short name T957
Test name
Test status
Simulation time 3712296834 ps
CPU time 5.61 seconds
Started Jan 07 01:44:38 PM PST 24
Finished Jan 07 01:44:44 PM PST 24
Peak memory 206884 kb
Host smart-1faba062-4927-43dd-adc7-3908c66c68a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777818096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.2777818096
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.4237901236
Short name T1150
Test name
Test status
Simulation time 1054867527 ps
CPU time 21.26 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:44:33 PM PST 24
Peak memory 203308 kb
Host smart-2e7c9530-9c6e-4b07-aa37-2642f79837df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237901236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.4237901236
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3194789150
Short name T564
Test name
Test status
Simulation time 4738052462 ps
CPU time 8.39 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:44:14 PM PST 24
Peak memory 204004 kb
Host smart-ec89569b-6517-4bb7-a6a3-411578c12fbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194789150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3194789150
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.4248620283
Short name T894
Test name
Test status
Simulation time 12286912591 ps
CPU time 8.96 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:43:46 PM PST 24
Peak memory 209368 kb
Host smart-6cab4897-c265-4224-904c-83ca036a7ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248620283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.4248620283
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.119534576
Short name T276
Test name
Test status
Simulation time 6094494995 ps
CPU time 5.73 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:43:53 PM PST 24
Peak memory 206488 kb
Host smart-90eaa439-14a9-41a7-b74d-e82c60b893ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119534576 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_unexp_stop.119534576
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.4129040796
Short name T808
Test name
Test status
Simulation time 40033369 ps
CPU time 0.61 seconds
Started Jan 07 01:44:41 PM PST 24
Finished Jan 07 01:44:44 PM PST 24
Peak memory 203188 kb
Host smart-4c554062-8390-44c6-ad1a-a5fafa6fc712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129040796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.4129040796
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.1735202304
Short name T1250
Test name
Test status
Simulation time 37675836 ps
CPU time 1.48 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:44:06 PM PST 24
Peak memory 203180 kb
Host smart-bc7ee9d1-150d-4141-a58c-71fbd19ccfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735202304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1735202304
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3814445823
Short name T457
Test name
Test status
Simulation time 1749005211 ps
CPU time 20.97 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 268736 kb
Host smart-025f0603-d8cb-4218-9333-b7ca69470bfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814445823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3814445823
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.848396085
Short name T560
Test name
Test status
Simulation time 16657311840 ps
CPU time 183.87 seconds
Started Jan 07 01:43:58 PM PST 24
Finished Jan 07 01:47:10 PM PST 24
Peak memory 1245528 kb
Host smart-11c42ad2-cb1d-468c-a785-cb9e245698c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848396085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.848396085
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.877037071
Short name T169
Test name
Test status
Simulation time 13678412270 ps
CPU time 366.09 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:49:50 PM PST 24
Peak memory 1051148 kb
Host smart-d0cf368d-9f1a-489d-9b72-fe60f8f76bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877037071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.877037071
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1202909680
Short name T890
Test name
Test status
Simulation time 380825478 ps
CPU time 0.84 seconds
Started Jan 07 01:43:47 PM PST 24
Finished Jan 07 01:44:00 PM PST 24
Peak memory 203164 kb
Host smart-fb520448-cf6a-41d1-85b2-f2b2cfd37f55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202909680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1202909680
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1956185004
Short name T122
Test name
Test status
Simulation time 38891636373 ps
CPU time 382.67 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:50:09 PM PST 24
Peak memory 1886188 kb
Host smart-ba73de46-2b69-408c-acae-481fa208b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956185004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1956185004
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.79642507
Short name T267
Test name
Test status
Simulation time 1508486732 ps
CPU time 84.68 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:45:38 PM PST 24
Peak memory 247532 kb
Host smart-684f0697-0609-462d-869b-c7bf46c94fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79642507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.79642507
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.4006186758
Short name T429
Test name
Test status
Simulation time 17028072 ps
CPU time 0.63 seconds
Started Jan 07 01:43:57 PM PST 24
Finished Jan 07 01:44:07 PM PST 24
Peak memory 202456 kb
Host smart-c8b7b7dc-3283-4246-b82f-e8fbe79fbdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006186758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4006186758
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.4155656061
Short name T156
Test name
Test status
Simulation time 9173290281 ps
CPU time 70.42 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:45:00 PM PST 24
Peak memory 328684 kb
Host smart-b295eb5a-ed4b-471b-80dc-90fc06956018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155656061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.4155656061
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.4176157199
Short name T1105
Test name
Test status
Simulation time 54674963905 ps
CPU time 1062.57 seconds
Started Jan 07 01:44:20 PM PST 24
Finished Jan 07 02:02:04 PM PST 24
Peak memory 1637904 kb
Host smart-d1cbc9de-6ec9-4512-9dbf-6dac4727b0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176157199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.4176157199
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2842644031
Short name T1050
Test name
Test status
Simulation time 1766901580 ps
CPU time 15.77 seconds
Started Jan 07 01:43:58 PM PST 24
Finished Jan 07 01:44:23 PM PST 24
Peak memory 215840 kb
Host smart-a039c972-b7a7-4359-9e47-58c54e0a3c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842644031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2842644031
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.961528881
Short name T290
Test name
Test status
Simulation time 10099169566 ps
CPU time 72.3 seconds
Started Jan 07 01:43:54 PM PST 24
Finished Jan 07 01:45:16 PM PST 24
Peak memory 539252 kb
Host smart-472d0854-c76c-4143-8b81-c39cbee03570
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961528881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.961528881
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1712761047
Short name T209
Test name
Test status
Simulation time 10051264416 ps
CPU time 23.43 seconds
Started Jan 07 01:43:53 PM PST 24
Finished Jan 07 01:44:27 PM PST 24
Peak memory 350356 kb
Host smart-1bbfe1d1-51f1-45e2-b787-ff17764114e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712761047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1712761047
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3190259261
Short name T738
Test name
Test status
Simulation time 4720217520 ps
CPU time 2.6 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 203380 kb
Host smart-84845b68-1685-41f8-8392-39f2c673b15b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190259261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3190259261
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.4216331463
Short name T795
Test name
Test status
Simulation time 1588692379 ps
CPU time 6.5 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:44:20 PM PST 24
Peak memory 205552 kb
Host smart-54cf1a7c-53b4-4756-9357-e5b702132a65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216331463 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.4216331463
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1567844993
Short name T449
Test name
Test status
Simulation time 23520641982 ps
CPU time 1170.96 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 02:03:21 PM PST 24
Peak memory 5728020 kb
Host smart-8d658a8d-ce37-4a0a-85c3-55f80519996a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567844993 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1567844993
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.3701884899
Short name T965
Test name
Test status
Simulation time 515550682 ps
CPU time 2.97 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 204000 kb
Host smart-c5036acc-8ca0-4be0-b2e7-0d0517924b04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701884899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.3701884899
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2456070188
Short name T1298
Test name
Test status
Simulation time 992671307 ps
CPU time 25.12 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:45:30 PM PST 24
Peak memory 203284 kb
Host smart-698c155c-1d53-47b5-9d52-af5ead32d6af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456070188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2456070188
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.4117077336
Short name T888
Test name
Test status
Simulation time 87412916379 ps
CPU time 3515.44 seconds
Started Jan 07 01:43:50 PM PST 24
Finished Jan 07 02:42:37 PM PST 24
Peak memory 2790504 kb
Host smart-950f3053-9dea-4139-96ff-90ebb5711869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117077336 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.4117077336
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2948608809
Short name T919
Test name
Test status
Simulation time 1063636287 ps
CPU time 20.96 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:59 PM PST 24
Peak memory 203308 kb
Host smart-eb44492e-a0c2-40fc-8f68-81db7e3ca770
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948608809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2948608809
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1002379384
Short name T1096
Test name
Test status
Simulation time 41323870148 ps
CPU time 585.33 seconds
Started Jan 07 01:43:53 PM PST 24
Finished Jan 07 01:53:49 PM PST 24
Peak memory 4378596 kb
Host smart-44bbca69-2acd-4acc-bb34-3cc7e6e4a186
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002379384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1002379384
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1711746383
Short name T604
Test name
Test status
Simulation time 1529690420 ps
CPU time 6.86 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:44:17 PM PST 24
Peak memory 216904 kb
Host smart-82e4da39-f3f2-41e8-9024-10d50f977ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711746383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1711746383
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_ovf.612025182
Short name T1302
Test name
Test status
Simulation time 5937549635 ps
CPU time 101.71 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 332796 kb
Host smart-75ae2dd5-fdf0-4eb5-bddb-3349d7cbd333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612025182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_tx_ovf.612025182
Directory /workspace/12.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.1355894938
Short name T578
Test name
Test status
Simulation time 5890123278 ps
CPU time 7.87 seconds
Started Jan 07 01:43:50 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 211196 kb
Host smart-b8dbda3e-69b6-4fca-8a3a-f2baa18b868d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355894938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.1355894938
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3699291197
Short name T68
Test name
Test status
Simulation time 17732047 ps
CPU time 0.61 seconds
Started Jan 07 01:44:39 PM PST 24
Finished Jan 07 01:44:41 PM PST 24
Peak memory 203184 kb
Host smart-b4c60d71-04d0-4d33-8896-ee3c61c3514e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699291197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3699291197
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1665106403
Short name T106
Test name
Test status
Simulation time 33788449 ps
CPU time 1.21 seconds
Started Jan 07 01:44:19 PM PST 24
Finished Jan 07 01:44:22 PM PST 24
Peak memory 212900 kb
Host smart-c63cf474-1faf-488c-9304-ac97e9eaa263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665106403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1665106403
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1564937389
Short name T496
Test name
Test status
Simulation time 1369574549 ps
CPU time 18.54 seconds
Started Jan 07 01:43:57 PM PST 24
Finished Jan 07 01:44:24 PM PST 24
Peak memory 278772 kb
Host smart-4551b13c-5900-409a-9d46-8bbe1243e16d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564937389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1564937389
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3300547835
Short name T625
Test name
Test status
Simulation time 2405469358 ps
CPU time 102.78 seconds
Started Jan 07 01:44:11 PM PST 24
Finished Jan 07 01:45:58 PM PST 24
Peak memory 802132 kb
Host smart-c5163ed0-feec-450f-a76f-ac5e1c010f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300547835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3300547835
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2488570121
Short name T520
Test name
Test status
Simulation time 7574251216 ps
CPU time 192.66 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:47:02 PM PST 24
Peak memory 1074152 kb
Host smart-c28abc9c-6ac8-4faf-a4c8-894daa6f41e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488570121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2488570121
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2932722644
Short name T725
Test name
Test status
Simulation time 553894924 ps
CPU time 1.03 seconds
Started Jan 07 01:43:53 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 203348 kb
Host smart-27bffc8f-4edb-4e88-8181-6aae93beb1ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932722644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2932722644
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.378265372
Short name T749
Test name
Test status
Simulation time 936173622 ps
CPU time 11.61 seconds
Started Jan 07 01:44:08 PM PST 24
Finished Jan 07 01:44:26 PM PST 24
Peak memory 203180 kb
Host smart-a93701a0-2314-4a26-8693-46d69a12b09a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378265372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
378265372
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.4057075898
Short name T125
Test name
Test status
Simulation time 3636256415 ps
CPU time 152.42 seconds
Started Jan 07 01:44:01 PM PST 24
Finished Jan 07 01:46:41 PM PST 24
Peak memory 1111200 kb
Host smart-7748d6dd-edb6-4e41-a4ba-c7c22b5addba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057075898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.4057075898
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2840533815
Short name T36
Test name
Test status
Simulation time 6416412107 ps
CPU time 325.67 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:49:39 PM PST 24
Peak memory 203528 kb
Host smart-5fa86b73-55d4-4ac1-9afb-fc16e8c997f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840533815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2840533815
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_rx_oversample.189889172
Short name T402
Test name
Test status
Simulation time 6230187892 ps
CPU time 102.91 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 260088 kb
Host smart-fbf1c57f-da13-44d8-b031-429e610f6621
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189889172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_rx_oversample.
189889172
Directory /workspace/13.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3289728713
Short name T696
Test name
Test status
Simulation time 2851509417 ps
CPU time 82.6 seconds
Started Jan 07 01:44:56 PM PST 24
Finished Jan 07 01:46:23 PM PST 24
Peak memory 340964 kb
Host smart-5f1d24dd-13d5-4939-8357-45d7ead35452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289728713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3289728713
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3244959391
Short name T1042
Test name
Test status
Simulation time 24883596308 ps
CPU time 2880.15 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 02:32:14 PM PST 24
Peak memory 2776740 kb
Host smart-38c697b7-9382-4660-bc1d-7cde8ec93cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244959391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3244959391
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.638560398
Short name T1366
Test name
Test status
Simulation time 2270340444 ps
CPU time 16.96 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:44:30 PM PST 24
Peak memory 218572 kb
Host smart-7bc0db58-0a93-4734-9dc4-7d966eef032e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638560398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.638560398
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.675657142
Short name T791
Test name
Test status
Simulation time 10034649497 ps
CPU time 69.15 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:45:22 PM PST 24
Peak memory 595332 kb
Host smart-26c888d0-d7f9-4dbf-8c7c-98a1a5f19ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675657142 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.675657142
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2430890491
Short name T838
Test name
Test status
Simulation time 10118453836 ps
CPU time 67.27 seconds
Started Jan 07 01:43:57 PM PST 24
Finished Jan 07 01:45:13 PM PST 24
Peak memory 652376 kb
Host smart-cac691cf-bf67-4080-a6b1-26f44a2c7f8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430890491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2430890491
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.77187744
Short name T986
Test name
Test status
Simulation time 993016837 ps
CPU time 2.34 seconds
Started Jan 07 01:44:40 PM PST 24
Finished Jan 07 01:44:44 PM PST 24
Peak memory 203284 kb
Host smart-ef15eb59-6d62-417f-ac4d-7af6aa29da96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77187744 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.i2c_target_hrst.77187744
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2314073941
Short name T1077
Test name
Test status
Simulation time 2826156684 ps
CPU time 5.59 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:14 PM PST 24
Peak memory 203348 kb
Host smart-a1551365-64db-4312-a929-17a7b4739d14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314073941 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2314073941
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2462632834
Short name T1197
Test name
Test status
Simulation time 14863303737 ps
CPU time 158.93 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:47:54 PM PST 24
Peak memory 1864520 kb
Host smart-b39dcd5d-5233-428e-a51e-186b46a345e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462632834 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2462632834
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.417997380
Short name T203
Test name
Test status
Simulation time 1968624480 ps
CPU time 23.82 seconds
Started Jan 07 01:44:40 PM PST 24
Finished Jan 07 01:45:05 PM PST 24
Peak memory 203248 kb
Host smart-97f348ce-f763-47ed-a944-a5844383d3da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417997380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.417997380
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.4136675119
Short name T698
Test name
Test status
Simulation time 15402248827 ps
CPU time 53.62 seconds
Started Jan 07 01:43:54 PM PST 24
Finished Jan 07 01:44:57 PM PST 24
Peak memory 228664 kb
Host smart-219efef0-ebe8-4120-99ca-6afc3faa3f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136675119 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.4136675119
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.14504815
Short name T679
Test name
Test status
Simulation time 1376475241 ps
CPU time 21.44 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:28 PM PST 24
Peak memory 216412 kb
Host smart-91cbc6d4-c3b5-43b1-b918-c4d0e47fc8ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14504815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stress_rd.14504815
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.63013583
Short name T699
Test name
Test status
Simulation time 15388047461 ps
CPU time 33.86 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:44:47 PM PST 24
Peak memory 857708 kb
Host smart-a9b65c37-afe0-43bd-a9e3-888fa9e6b869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63013583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stress_wr.63013583
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3784003114
Short name T2
Test name
Test status
Simulation time 39793615607 ps
CPU time 98.59 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:45:51 PM PST 24
Peak memory 407176 kb
Host smart-f0ab10d0-8425-43c7-85f9-fbfc45cb76a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784003114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3784003114
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1291741699
Short name T350
Test name
Test status
Simulation time 2488578983 ps
CPU time 6.17 seconds
Started Jan 07 01:44:08 PM PST 24
Finished Jan 07 01:44:20 PM PST 24
Peak memory 203396 kb
Host smart-412ba2bf-1575-4917-9532-0719fdf473e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291741699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1291741699
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_ovf.3320447640
Short name T495
Test name
Test status
Simulation time 2793807989 ps
CPU time 102.94 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:45:55 PM PST 24
Peak memory 329356 kb
Host smart-6f3b51fc-52d4-4fdb-bbce-c7608df6e498
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320447640 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_tx_ovf.3320447640
Directory /workspace/13.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.41025194
Short name T309
Test name
Test status
Simulation time 3105613123 ps
CPU time 7.24 seconds
Started Jan 07 01:44:55 PM PST 24
Finished Jan 07 01:45:05 PM PST 24
Peak memory 203372 kb
Host smart-584ba8f3-4dc2-4cbd-9e5f-5a28f9ca807f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025194 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_unexp_stop.41025194
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.1040468652
Short name T921
Test name
Test status
Simulation time 56356390 ps
CPU time 0.59 seconds
Started Jan 07 01:43:53 PM PST 24
Finished Jan 07 01:44:04 PM PST 24
Peak memory 202232 kb
Host smart-6a784a69-f2e7-46cb-8770-165e62f4c9b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040468652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1040468652
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.436857284
Short name T1309
Test name
Test status
Simulation time 91944764 ps
CPU time 1.48 seconds
Started Jan 07 01:44:38 PM PST 24
Finished Jan 07 01:44:41 PM PST 24
Peak memory 211468 kb
Host smart-585323b3-820e-43a3-89d5-ad5324fa4e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436857284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.436857284
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1949234104
Short name T389
Test name
Test status
Simulation time 4093174417 ps
CPU time 6.74 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:12 PM PST 24
Peak memory 282792 kb
Host smart-c6fba79f-c83d-4c0e-aa22-053827cb3980
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949234104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1949234104
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2793049725
Short name T1006
Test name
Test status
Simulation time 9384536270 ps
CPU time 71.82 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:45:16 PM PST 24
Peak memory 726228 kb
Host smart-24c040e4-8a99-4ff8-9013-82bd8eb658f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793049725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2793049725
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3345947572
Short name T1047
Test name
Test status
Simulation time 7467033986 ps
CPU time 206.15 seconds
Started Jan 07 01:43:49 PM PST 24
Finished Jan 07 01:47:27 PM PST 24
Peak memory 1056792 kb
Host smart-d2eaa1b5-3297-4517-8500-c68a7841eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345947572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3345947572
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.547029704
Short name T640
Test name
Test status
Simulation time 189867652 ps
CPU time 1.04 seconds
Started Jan 07 01:44:39 PM PST 24
Finished Jan 07 01:44:42 PM PST 24
Peak memory 203300 kb
Host smart-add11953-4747-4e0e-a77f-09bf0daf897b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547029704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fm
t.547029704
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1644788577
Short name T1210
Test name
Test status
Simulation time 21597185538 ps
CPU time 296.84 seconds
Started Jan 07 01:43:49 PM PST 24
Finished Jan 07 01:48:58 PM PST 24
Peak memory 1582612 kb
Host smart-61be2d17-6c1e-4166-929c-5c028fa69af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644788577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1644788577
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_override.4282875923
Short name T596
Test name
Test status
Simulation time 49159113 ps
CPU time 0.6 seconds
Started Jan 07 01:44:39 PM PST 24
Finished Jan 07 01:44:41 PM PST 24
Peak memory 202460 kb
Host smart-9109b2ad-ccc6-44be-82a3-ee19646b6377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282875923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.4282875923
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.292981168
Short name T476
Test name
Test status
Simulation time 5723253942 ps
CPU time 53.63 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:45:07 PM PST 24
Peak memory 307824 kb
Host smart-bdd5e369-6687-48b6-8ae7-c2459f8bc513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292981168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.292981168
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3001359845
Short name T771
Test name
Test status
Simulation time 3170343679 ps
CPU time 22.27 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:31 PM PST 24
Peak memory 245220 kb
Host smart-994f9d0d-149a-439c-8364-1430b150780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001359845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3001359845
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3808139038
Short name T1361
Test name
Test status
Simulation time 1119703050 ps
CPU time 19.77 seconds
Started Jan 07 01:44:38 PM PST 24
Finished Jan 07 01:44:59 PM PST 24
Peak memory 219716 kb
Host smart-249b4771-67e2-4b79-ac55-d171717a14d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808139038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3808139038
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1998699733
Short name T768
Test name
Test status
Simulation time 1395120924 ps
CPU time 5.05 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 204700 kb
Host smart-b3d4cefd-fe6f-46fa-a25b-39f851feee61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998699733 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1998699733
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.3300531132
Short name T190
Test name
Test status
Simulation time 10155846484 ps
CPU time 41.72 seconds
Started Jan 07 01:43:59 PM PST 24
Finished Jan 07 01:44:49 PM PST 24
Peak memory 420004 kb
Host smart-ca9ec43f-86e6-45c3-baea-a25659754a21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300531132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.3300531132
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2898272742
Short name T302
Test name
Test status
Simulation time 10121567721 ps
CPU time 79.03 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:45:32 PM PST 24
Peak memory 593212 kb
Host smart-72c54410-9961-4771-842b-54675110fcc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898272742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2898272742
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2649821400
Short name T1200
Test name
Test status
Simulation time 748016152 ps
CPU time 2.28 seconds
Started Jan 07 01:44:19 PM PST 24
Finished Jan 07 01:44:23 PM PST 24
Peak memory 203236 kb
Host smart-88d68a6b-8b87-4ea5-8f06-ae7a5b5fa043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649821400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2649821400
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2745936521
Short name T1165
Test name
Test status
Simulation time 2087208833 ps
CPU time 8.64 seconds
Started Jan 07 01:43:58 PM PST 24
Finished Jan 07 01:44:16 PM PST 24
Peak memory 209328 kb
Host smart-f803902c-e6b4-4aae-be28-8296a389b085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745936521 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2745936521
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_perf.1450275784
Short name T601
Test name
Test status
Simulation time 653834142 ps
CPU time 3.89 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 203368 kb
Host smart-6cfa1285-3120-4d76-8e61-7387ca7188a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450275784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.1450275784
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1859004098
Short name T934
Test name
Test status
Simulation time 2335310699 ps
CPU time 28.34 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:44:39 PM PST 24
Peak memory 203324 kb
Host smart-6c85d494-da50-405f-8645-03e0b87e1985
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859004098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1859004098
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.148415606
Short name T158
Test name
Test status
Simulation time 56970604734 ps
CPU time 1958.68 seconds
Started Jan 07 01:44:41 PM PST 24
Finished Jan 07 02:17:22 PM PST 24
Peak memory 3247040 kb
Host smart-7bbc62b0-0ac7-4b17-99b4-de835de53071
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148415606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.i2c_target_stress_all.148415606
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3420046129
Short name T321
Test name
Test status
Simulation time 417428540 ps
CPU time 5.89 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 203216 kb
Host smart-8378809a-7be7-4eb2-9b0b-f0289c422e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420046129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3420046129
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1997623655
Short name T708
Test name
Test status
Simulation time 57966668088 ps
CPU time 184.36 seconds
Started Jan 07 01:44:02 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 1907292 kb
Host smart-2e1061db-1810-4205-a0ee-489bea023e04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997623655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1997623655
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.311068130
Short name T445
Test name
Test status
Simulation time 18020371064 ps
CPU time 614.88 seconds
Started Jan 07 01:44:01 PM PST 24
Finished Jan 07 01:54:24 PM PST 24
Peak memory 3192720 kb
Host smart-b799cc40-56d2-4356-9709-6427bd8964f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311068130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.311068130
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.4178237541
Short name T937
Test name
Test status
Simulation time 1828654356 ps
CPU time 6.88 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 203208 kb
Host smart-ad271df1-931e-4fe3-bf5e-e18929946218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178237541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.4178237541
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_ovf.2026110122
Short name T1198
Test name
Test status
Simulation time 2894143466 ps
CPU time 184.57 seconds
Started Jan 07 01:43:50 PM PST 24
Finished Jan 07 01:47:06 PM PST 24
Peak memory 466664 kb
Host smart-780fdf1b-d473-4a63-a0b2-649cd3c24717
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026110122 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_tx_ovf.2026110122
Directory /workspace/14.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.3689279553
Short name T693
Test name
Test status
Simulation time 10176702768 ps
CPU time 3.94 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 203268 kb
Host smart-56c90645-b72a-409c-8805-a5189dbc728c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689279553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.i2c_target_unexp_stop.3689279553
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1033735368
Short name T369
Test name
Test status
Simulation time 35209823 ps
CPU time 0.59 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:27 PM PST 24
Peak memory 203224 kb
Host smart-fc0e7116-272f-4c65-ba2c-336e837e660b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033735368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1033735368
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3541860864
Short name T204
Test name
Test status
Simulation time 54909302 ps
CPU time 1.32 seconds
Started Jan 07 01:43:54 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 211508 kb
Host smart-001f0d56-4b29-4fc3-8da4-5cc129ed56ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541860864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3541860864
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.492667288
Short name T463
Test name
Test status
Simulation time 350482588 ps
CPU time 17.32 seconds
Started Jan 07 01:44:07 PM PST 24
Finished Jan 07 01:44:31 PM PST 24
Peak memory 271548 kb
Host smart-ed65c871-b170-426e-9f8e-b5ebe046d438
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492667288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.492667288
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.4183077729
Short name T1176
Test name
Test status
Simulation time 26469758350 ps
CPU time 481.1 seconds
Started Jan 07 01:44:12 PM PST 24
Finished Jan 07 01:52:17 PM PST 24
Peak memory 1836896 kb
Host smart-adfcbb26-7cfb-4230-940c-97e0c87a729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183077729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.4183077729
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.4248037006
Short name T58
Test name
Test status
Simulation time 392718645 ps
CPU time 0.94 seconds
Started Jan 07 01:44:35 PM PST 24
Finished Jan 07 01:44:37 PM PST 24
Peak memory 203264 kb
Host smart-4e8cdb57-832e-4aa4-86d2-0b797062a50f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248037006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.4248037006
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3842826866
Short name T145
Test name
Test status
Simulation time 552114036 ps
CPU time 4.23 seconds
Started Jan 07 01:44:01 PM PST 24
Finished Jan 07 01:44:13 PM PST 24
Peak memory 227796 kb
Host smart-a68889fb-ad61-4b51-963a-666c4977e592
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842826866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3842826866
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.590227241
Short name T661
Test name
Test status
Simulation time 5067145790 ps
CPU time 494.23 seconds
Started Jan 07 01:43:59 PM PST 24
Finished Jan 07 01:52:22 PM PST 24
Peak memory 1369808 kb
Host smart-97dd29b0-4783-4159-8ed5-af011b84b9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590227241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.590227241
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1934698967
Short name T39
Test name
Test status
Simulation time 2130002618 ps
CPU time 57.96 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:46:10 PM PST 24
Peak memory 272344 kb
Host smart-5ab489d2-4502-470a-96a1-3c77ed591439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934698967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1934698967
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.2169110606
Short name T608
Test name
Test status
Simulation time 59863590 ps
CPU time 0.6 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:44:14 PM PST 24
Peak memory 202496 kb
Host smart-2eaee13e-6094-4e0c-b7ec-3ff272d5ebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169110606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2169110606
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1205897074
Short name T135
Test name
Test status
Simulation time 1368225942 ps
CPU time 19.3 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:45:24 PM PST 24
Peak memory 231952 kb
Host smart-f336477c-c870-4240-90d2-83ae22d16cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205897074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1205897074
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_rx_oversample.3454696525
Short name T1308
Test name
Test status
Simulation time 8844164413 ps
CPU time 73.7 seconds
Started Jan 07 01:43:54 PM PST 24
Finished Jan 07 01:45:18 PM PST 24
Peak memory 280932 kb
Host smart-f42a3367-423b-4801-8f68-b8c3f46a6ea6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454696525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_rx_oversample
.3454696525
Directory /workspace/15.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.238106273
Short name T1237
Test name
Test status
Simulation time 2603893898 ps
CPU time 154.7 seconds
Started Jan 07 01:43:50 PM PST 24
Finished Jan 07 01:46:37 PM PST 24
Peak memory 253652 kb
Host smart-78d8380f-d052-498a-a9b2-f1ba9b0eaffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238106273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.238106273
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.930919038
Short name T522
Test name
Test status
Simulation time 6629786006 ps
CPU time 18.53 seconds
Started Jan 07 01:44:09 PM PST 24
Finished Jan 07 01:44:33 PM PST 24
Peak memory 219696 kb
Host smart-f2466ed5-36a0-42dc-a07b-53b2248704cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930919038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.930919038
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.659692486
Short name T830
Test name
Test status
Simulation time 616224949 ps
CPU time 2.73 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:44:47 PM PST 24
Peak memory 203320 kb
Host smart-7848cb6e-8f6e-4f60-9781-7f4bd2de7093
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659692486 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.659692486
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2358667095
Short name T1359
Test name
Test status
Simulation time 10067350370 ps
CPU time 59.95 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 489296 kb
Host smart-d966734b-f88c-4cd1-acf8-cbef04104c65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358667095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2358667095
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1397683048
Short name T971
Test name
Test status
Simulation time 530104334 ps
CPU time 2.45 seconds
Started Jan 07 01:44:45 PM PST 24
Finished Jan 07 01:44:49 PM PST 24
Peak memory 203396 kb
Host smart-79608b99-e6fe-4c71-99cd-a277ada561d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397683048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1397683048
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1513334844
Short name T1095
Test name
Test status
Simulation time 4565534758 ps
CPU time 5.32 seconds
Started Jan 07 01:43:49 PM PST 24
Finished Jan 07 01:44:06 PM PST 24
Peak memory 205268 kb
Host smart-3cdafb20-5457-4fa5-933c-238529e67281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513334844 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1513334844
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.4002366244
Short name T1178
Test name
Test status
Simulation time 20061270480 ps
CPU time 778.38 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:57:04 PM PST 24
Peak memory 4723344 kb
Host smart-d81297be-e058-40fa-94f5-53afe420acf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002366244 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.4002366244
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.3821965633
Short name T508
Test name
Test status
Simulation time 1808939183 ps
CPU time 4.74 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:23 PM PST 24
Peak memory 208400 kb
Host smart-6829d7ae-364b-47ba-9967-f49bb25e9d75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821965633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.3821965633
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.2793801291
Short name T1102
Test name
Test status
Simulation time 116660059759 ps
CPU time 1205.19 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 02:05:38 PM PST 24
Peak memory 743344 kb
Host smart-0112660d-b8f5-4664-8b92-58625be8c125
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793801291 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.2793801291
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1492032114
Short name T1310
Test name
Test status
Simulation time 2030359666 ps
CPU time 14.63 seconds
Started Jan 07 01:43:52 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 208604 kb
Host smart-f9a7efe4-5a88-4792-920b-20846884d6b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492032114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1492032114
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3548442557
Short name T1063
Test name
Test status
Simulation time 49974752421 ps
CPU time 2901.05 seconds
Started Jan 07 01:44:01 PM PST 24
Finished Jan 07 02:32:31 PM PST 24
Peak memory 10469456 kb
Host smart-6541dcf3-93ce-468f-bbe7-341146422522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548442557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3548442557
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3907178977
Short name T828
Test name
Test status
Simulation time 12676710691 ps
CPU time 235.22 seconds
Started Jan 07 01:44:41 PM PST 24
Finished Jan 07 01:48:38 PM PST 24
Peak memory 1591652 kb
Host smart-682f76af-3250-4ea8-9ff6-d70e3a141eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907178977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3907178977
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2918524923
Short name T258
Test name
Test status
Simulation time 6779466988 ps
CPU time 7.03 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:44:51 PM PST 24
Peak memory 212708 kb
Host smart-4eb61698-addd-4d80-bb28-f7a9b95671b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918524923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2918524923
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_ovf.1160020960
Short name T594
Test name
Test status
Simulation time 16240848767 ps
CPU time 202.88 seconds
Started Jan 07 01:44:56 PM PST 24
Finished Jan 07 01:48:24 PM PST 24
Peak memory 435124 kb
Host smart-8a479f84-855c-4226-a14f-96b753796ad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160020960 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_tx_ovf.1160020960
Directory /workspace/15.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.3968449271
Short name T630
Test name
Test status
Simulation time 1028037867 ps
CPU time 5.31 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:19 PM PST 24
Peak memory 203284 kb
Host smart-83202788-b613-4798-8ef0-42e72a3a030a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968449271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.3968449271
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2990113853
Short name T820
Test name
Test status
Simulation time 37880679 ps
CPU time 0.58 seconds
Started Jan 07 01:44:34 PM PST 24
Finished Jan 07 01:44:36 PM PST 24
Peak memory 202200 kb
Host smart-2e8582d0-5f25-41f4-af83-5c93a8574e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990113853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2990113853
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.317068796
Short name T958
Test name
Test status
Simulation time 58618157 ps
CPU time 1 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:45:49 PM PST 24
Peak memory 212644 kb
Host smart-84087e8b-5082-4156-82ac-e2ffc3c30d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317068796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.317068796
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3691400986
Short name T733
Test name
Test status
Simulation time 714791078 ps
CPU time 17.51 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:41 PM PST 24
Peak memory 274040 kb
Host smart-f08137c5-a74f-478d-981d-5cfa4815b01e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691400986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3691400986
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1478104668
Short name T1244
Test name
Test status
Simulation time 11469240235 ps
CPU time 232.93 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:49:32 PM PST 24
Peak memory 887624 kb
Host smart-6c65736c-d6b8-4094-b4c0-8134d3aa34fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478104668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1478104668
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2620000053
Short name T1193
Test name
Test status
Simulation time 22922136362 ps
CPU time 377.39 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:52:03 PM PST 24
Peak memory 1607964 kb
Host smart-28f13076-8ac7-4249-97b6-10e4d2ed1f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620000053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2620000053
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.38995857
Short name T339
Test name
Test status
Simulation time 113548006 ps
CPU time 0.94 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:07 PM PST 24
Peak memory 203120 kb
Host smart-5d1c31ae-27b2-40a6-828e-266f5cedc9db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt
.38995857
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.54795653
Short name T507
Test name
Test status
Simulation time 828873572 ps
CPU time 12.93 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:25 PM PST 24
Peak memory 245884 kb
Host smart-cf918b89-47de-49f2-be1e-04c35a0827cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54795653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.54795653
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.877234345
Short name T718
Test name
Test status
Simulation time 16316675210 ps
CPU time 380.46 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:51:46 PM PST 24
Peak memory 1135764 kb
Host smart-da2e0719-12a9-4865-8868-3fdd50839e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877234345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.877234345
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1647108596
Short name T1075
Test name
Test status
Simulation time 4037861687 ps
CPU time 38.05 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:46 PM PST 24
Peak memory 258820 kb
Host smart-700b4c42-a582-469b-8309-57230e489b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647108596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1647108596
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.2522637102
Short name T760
Test name
Test status
Simulation time 17614724 ps
CPU time 0.63 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:45:46 PM PST 24
Peak memory 202352 kb
Host smart-b617b89d-956c-42de-b19c-4d2ea5a02056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522637102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2522637102
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3687124611
Short name T1158
Test name
Test status
Simulation time 27368160038 ps
CPU time 483.76 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:53:26 PM PST 24
Peak memory 211564 kb
Host smart-8a7e7fdc-a914-4ffe-be7c-d537fc65a229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687124611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3687124611
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_rx_oversample.789864079
Short name T653
Test name
Test status
Simulation time 5337940860 ps
CPU time 78.4 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:47:13 PM PST 24
Peak memory 270968 kb
Host smart-c2b04b36-7216-48b4-b09a-7022e4a440f7
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789864079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_rx_oversample.
789864079
Directory /workspace/16.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.798618712
Short name T938
Test name
Test status
Simulation time 939614991 ps
CPU time 3.82 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 203192 kb
Host smart-7edf5532-9eee-47ee-9d63-b8cc9bbf99d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798618712 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.798618712
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1701177994
Short name T1140
Test name
Test status
Simulation time 10294576915 ps
CPU time 8.75 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 244344 kb
Host smart-57bfb84a-b687-4ac2-b66f-5bd014bfacc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701177994 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1701177994
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.3771491513
Short name T252
Test name
Test status
Simulation time 10143736996 ps
CPU time 75.67 seconds
Started Jan 07 01:45:43 PM PST 24
Finished Jan 07 01:47:38 PM PST 24
Peak memory 611824 kb
Host smart-cf64e700-b024-4dd4-b10a-3485abbd6204
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771491513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.3771491513
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2032929023
Short name T1268
Test name
Test status
Simulation time 606954250 ps
CPU time 2.86 seconds
Started Jan 07 01:44:43 PM PST 24
Finished Jan 07 01:44:48 PM PST 24
Peak memory 203296 kb
Host smart-61d145bc-8b16-4c7b-bd1f-794b3cdcd597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032929023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2032929023
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2360620292
Short name T884
Test name
Test status
Simulation time 5604901244 ps
CPU time 5.55 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:13 PM PST 24
Peak memory 203224 kb
Host smart-5365aa77-b584-4831-a405-08a7508a178a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360620292 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2360620292
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.720523640
Short name T371
Test name
Test status
Simulation time 10928311246 ps
CPU time 4.07 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:46:10 PM PST 24
Peak memory 208084 kb
Host smart-986591e2-9529-4389-b35e-d4adb47b89b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720523640 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.720523640
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.2778442849
Short name T1356
Test name
Test status
Simulation time 4068207357 ps
CPU time 4.55 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:46:00 PM PST 24
Peak memory 203328 kb
Host smart-56356a80-d173-42ba-9cd1-24e625097054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778442849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.2778442849
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.1499754014
Short name T739
Test name
Test status
Simulation time 61701686028 ps
CPU time 144.19 seconds
Started Jan 07 01:43:52 PM PST 24
Finished Jan 07 01:46:28 PM PST 24
Peak memory 1278788 kb
Host smart-4de1abe3-f9d2-4a8e-9283-892b4f98aece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499754014 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.1499754014
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.892449059
Short name T1065
Test name
Test status
Simulation time 17455766360 ps
CPU time 20.68 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:46:15 PM PST 24
Peak memory 212084 kb
Host smart-6e351c8d-ac99-4a81-8878-a76872b6370b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892449059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.892449059
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.105779405
Short name T519
Test name
Test status
Simulation time 28038104328 ps
CPU time 967.98 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 02:01:59 PM PST 24
Peak memory 6164192 kb
Host smart-f5f72cb7-8d10-4ec4-ba3f-d7fc5275ca8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105779405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_wr.105779405
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.65287710
Short name T1014
Test name
Test status
Simulation time 17350985863 ps
CPU time 835.61 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:59:49 PM PST 24
Peak memory 3484804 kb
Host smart-4c209ccb-e6d6-4ae7-a2cd-e1b0f14c8303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65287710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_stretch.65287710
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1914570910
Short name T394
Test name
Test status
Simulation time 9406858006 ps
CPU time 6.78 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:45:46 PM PST 24
Peak memory 208012 kb
Host smart-08674f03-3172-44cf-8e50-58c2dbc56700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914570910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1914570910
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_ovf.3679098430
Short name T654
Test name
Test status
Simulation time 6180721603 ps
CPU time 158.53 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:48:22 PM PST 24
Peak memory 469920 kb
Host smart-239e0c75-9dcb-4199-8c8f-54c2c341814d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679098430 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_tx_ovf.3679098430
Directory /workspace/16.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.3826217594
Short name T1330
Test name
Test status
Simulation time 5014636267 ps
CPU time 5.1 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:04 PM PST 24
Peak memory 203332 kb
Host smart-ac905b5e-94aa-48b4-bccb-e7a44ff998aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826217594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.i2c_target_unexp_stop.3826217594
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.95882654
Short name T673
Test name
Test status
Simulation time 54312559 ps
CPU time 0.6 seconds
Started Jan 07 01:44:02 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 202232 kb
Host smart-bd755b73-56c2-40f2-b223-715c0c895dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95882654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.95882654
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.4286537926
Short name T150
Test name
Test status
Simulation time 132541331 ps
CPU time 1.67 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:44:14 PM PST 24
Peak memory 211384 kb
Host smart-9d58d597-ebf4-440d-a711-9024ada9b617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286537926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.4286537926
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.4099431505
Short name T363
Test name
Test status
Simulation time 1413609553 ps
CPU time 14.67 seconds
Started Jan 07 01:44:12 PM PST 24
Finished Jan 07 01:44:31 PM PST 24
Peak memory 341036 kb
Host smart-4bae394d-3cef-4b71-bbaa-63e5fca71ee3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099431505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.4099431505
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.226499343
Short name T988
Test name
Test status
Simulation time 2783085196 ps
CPU time 112.85 seconds
Started Jan 07 01:44:39 PM PST 24
Finished Jan 07 01:46:33 PM PST 24
Peak memory 876212 kb
Host smart-d281fb5c-78e0-4834-b89e-275dd75c7085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226499343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.226499343
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.99749755
Short name T13
Test name
Test status
Simulation time 3820696463 ps
CPU time 190.76 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:48:25 PM PST 24
Peak memory 1014284 kb
Host smart-711bb459-e4a5-4dce-a480-449b02f2320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99749755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.99749755
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3248254804
Short name T195
Test name
Test status
Simulation time 142190465 ps
CPU time 1.09 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:06 PM PST 24
Peak memory 203192 kb
Host smart-002e468a-43d8-4e80-9fd1-6be829de0d61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248254804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3248254804
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3062892244
Short name T907
Test name
Test status
Simulation time 569744662 ps
CPU time 3.34 seconds
Started Jan 07 01:44:20 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 203412 kb
Host smart-468ef05b-b713-4a91-a731-07d374be4c4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062892244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3062892244
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1978256365
Short name T1148
Test name
Test status
Simulation time 10879154440 ps
CPU time 472.67 seconds
Started Jan 07 01:44:02 PM PST 24
Finished Jan 07 01:52:02 PM PST 24
Peak memory 1223168 kb
Host smart-a9c88fbd-bf58-4c12-b03b-ab766bf5784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978256365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1978256365
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3186665085
Short name T148
Test name
Test status
Simulation time 9101202035 ps
CPU time 128.9 seconds
Started Jan 07 01:44:01 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 265804 kb
Host smart-f85230a3-5e3b-47eb-9e22-0fbd669dd010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186665085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3186665085
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.5693316
Short name T1032
Test name
Test status
Simulation time 43210380 ps
CPU time 0.64 seconds
Started Jan 07 01:44:12 PM PST 24
Finished Jan 07 01:44:17 PM PST 24
Peak memory 202352 kb
Host smart-374498d6-1bdf-46c5-94fb-e6ff1411d29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5693316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.5693316
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2545267584
Short name T1109
Test name
Test status
Simulation time 7153837130 ps
CPU time 391.77 seconds
Started Jan 07 01:43:58 PM PST 24
Finished Jan 07 01:50:39 PM PST 24
Peak memory 263776 kb
Host smart-7424833d-7ea5-409f-a5a0-8ef83d432191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545267584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2545267584
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_rx_oversample.4256840403
Short name T181
Test name
Test status
Simulation time 33925015980 ps
CPU time 158.66 seconds
Started Jan 07 01:44:02 PM PST 24
Finished Jan 07 01:46:48 PM PST 24
Peak memory 350088 kb
Host smart-2e0c1b6a-80b9-4153-a07c-8844e2a53174
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256840403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_rx_oversample
.4256840403
Directory /workspace/17.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.709840544
Short name T709
Test name
Test status
Simulation time 4936738657 ps
CPU time 76.67 seconds
Started Jan 07 01:44:24 PM PST 24
Finished Jan 07 01:45:43 PM PST 24
Peak memory 342848 kb
Host smart-859fa179-f125-4b0c-bfa5-1492cead2362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709840544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.709840544
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.331221273
Short name T1271
Test name
Test status
Simulation time 1107952468 ps
CPU time 19.67 seconds
Started Jan 07 01:44:09 PM PST 24
Finished Jan 07 01:44:34 PM PST 24
Peak memory 219216 kb
Host smart-ab9e2477-f51c-43f6-b88b-46bf4b084c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331221273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.331221273
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1743153877
Short name T1338
Test name
Test status
Simulation time 7015866168 ps
CPU time 3.74 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:44:17 PM PST 24
Peak memory 203508 kb
Host smart-5d589faa-878e-4b6d-bf60-67653db48652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743153877 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1743153877
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3907317813
Short name T218
Test name
Test status
Simulation time 10101723731 ps
CPU time 11.65 seconds
Started Jan 07 01:43:59 PM PST 24
Finished Jan 07 01:44:19 PM PST 24
Peak memory 267720 kb
Host smart-846c1b58-1f80-4954-b0c7-12b13a144643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907317813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3907317813
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.718553205
Short name T547
Test name
Test status
Simulation time 10029960645 ps
CPU time 62.41 seconds
Started Jan 07 01:44:18 PM PST 24
Finished Jan 07 01:45:22 PM PST 24
Peak memory 545548 kb
Host smart-903dbae2-76b9-4ee5-95a5-8d161ebe96ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718553205 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.718553205
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.2793021103
Short name T155
Test name
Test status
Simulation time 1277445558 ps
CPU time 2.69 seconds
Started Jan 07 01:43:57 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 203292 kb
Host smart-b3dee290-43a4-4cb3-8645-fa1264f89505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793021103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.2793021103
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.4057505100
Short name T1286
Test name
Test status
Simulation time 16696694201 ps
CPU time 5.96 seconds
Started Jan 07 01:44:21 PM PST 24
Finished Jan 07 01:44:29 PM PST 24
Peak memory 205876 kb
Host smart-2610b1c8-adac-45fb-8a73-931b12d1597b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057505100 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.4057505100
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1748949537
Short name T683
Test name
Test status
Simulation time 5756096901 ps
CPU time 21.53 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:44:34 PM PST 24
Peak memory 637180 kb
Host smart-260628b9-923d-4dbc-a999-6d04d15c97b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748949537 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1748949537
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.3614911269
Short name T1304
Test name
Test status
Simulation time 14720212755 ps
CPU time 4.43 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:44:16 PM PST 24
Peak memory 203364 kb
Host smart-6d3ababb-eec7-4c4f-b102-1a91d65b3730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614911269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.3614911269
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2583789771
Short name T686
Test name
Test status
Simulation time 2075545770 ps
CPU time 45.57 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:44:51 PM PST 24
Peak memory 203340 kb
Host smart-33eca74c-7fab-496c-8dd3-6dc676c89324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583789771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2583789771
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.2648544201
Short name T1370
Test name
Test status
Simulation time 12631547937 ps
CPU time 467.75 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:51:59 PM PST 24
Peak memory 560208 kb
Host smart-e25edbd9-eafc-4e10-a286-ba8bc2cc3b3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648544201 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.2648544201
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3564276362
Short name T824
Test name
Test status
Simulation time 384214422 ps
CPU time 6.63 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:27 PM PST 24
Peak memory 203288 kb
Host smart-6c0de287-5688-4afb-97ea-db369e00cfce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564276362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3564276362
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2383815534
Short name T1363
Test name
Test status
Simulation time 48233897435 ps
CPU time 3459.53 seconds
Started Jan 07 01:44:18 PM PST 24
Finished Jan 07 02:42:00 PM PST 24
Peak memory 10844044 kb
Host smart-820064e9-a9af-410b-bea5-438f7439d914
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383815534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2383815534
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3426933040
Short name T241
Test name
Test status
Simulation time 17717952487 ps
CPU time 6.14 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:15 PM PST 24
Peak memory 208996 kb
Host smart-05a77032-b65c-4df5-b9e8-d6d35e7e82a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426933040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3426933040
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_ovf.2452583596
Short name T1119
Test name
Test status
Simulation time 5553933481 ps
CPU time 109.29 seconds
Started Jan 07 01:43:59 PM PST 24
Finished Jan 07 01:45:57 PM PST 24
Peak memory 331556 kb
Host smart-5be9a560-9e71-4f7a-8000-1dba5341d8dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452583596 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_tx_ovf.2452583596
Directory /workspace/17.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.3690125411
Short name T763
Test name
Test status
Simulation time 1866864559 ps
CPU time 8.56 seconds
Started Jan 07 01:44:20 PM PST 24
Finished Jan 07 01:44:31 PM PST 24
Peak memory 210784 kb
Host smart-6ee36b6c-fd63-4f2b-87e6-29e7818db593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690125411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.3690125411
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2094151472
Short name T1369
Test name
Test status
Simulation time 103755387 ps
CPU time 1.48 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:44:15 PM PST 24
Peak memory 211500 kb
Host smart-5b81bbff-a486-44fc-ab71-e7d916f4276b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094151472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2094151472
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1673765716
Short name T440
Test name
Test status
Simulation time 568418910 ps
CPU time 28 seconds
Started Jan 07 01:44:11 PM PST 24
Finished Jan 07 01:44:43 PM PST 24
Peak memory 322252 kb
Host smart-8af4cae3-35a8-4aed-90a5-837b65075f5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673765716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1673765716
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1368621579
Short name T809
Test name
Test status
Simulation time 25900985487 ps
CPU time 140.02 seconds
Started Jan 07 01:44:17 PM PST 24
Finished Jan 07 01:46:39 PM PST 24
Peak memory 675968 kb
Host smart-d874c76f-d8ab-460c-8e87-f4a0c73120ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368621579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1368621579
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2589818479
Short name T592
Test name
Test status
Simulation time 15079619670 ps
CPU time 309.55 seconds
Started Jan 07 01:44:12 PM PST 24
Finished Jan 07 01:49:25 PM PST 24
Peak memory 921760 kb
Host smart-a39a9851-ec56-45d8-97ea-d7004d8eb188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589818479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2589818479
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3860620211
Short name T93
Test name
Test status
Simulation time 75921531 ps
CPU time 0.71 seconds
Started Jan 07 01:44:02 PM PST 24
Finished Jan 07 01:44:10 PM PST 24
Peak memory 203136 kb
Host smart-128ae5a6-2992-46f5-8335-9ad5d4e5a08d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860620211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3860620211
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3786209944
Short name T916
Test name
Test status
Simulation time 477306257 ps
CPU time 3.5 seconds
Started Jan 07 01:44:07 PM PST 24
Finished Jan 07 01:44:17 PM PST 24
Peak memory 223004 kb
Host smart-bb7fc8d4-c571-4292-b23c-08eb9b10aa03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786209944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3786209944
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_override.891858879
Short name T1208
Test name
Test status
Simulation time 18430985 ps
CPU time 0.64 seconds
Started Jan 07 01:43:59 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 202308 kb
Host smart-b7df2f18-f6dc-4b4d-aa04-3c6ef51f418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891858879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.891858879
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3434379746
Short name T137
Test name
Test status
Simulation time 51245682863 ps
CPU time 313.48 seconds
Started Jan 07 01:44:12 PM PST 24
Finished Jan 07 01:49:29 PM PST 24
Peak memory 402004 kb
Host smart-40eff341-7e45-4c9e-8bb4-036f65b1be18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434379746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3434379746
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_rx_oversample.168235633
Short name T927
Test name
Test status
Simulation time 2294201230 ps
CPU time 49.44 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:45:03 PM PST 24
Peak memory 267136 kb
Host smart-fe9b8ecf-1422-4e56-9041-fd12bfe9963d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168235633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_rx_oversample.
168235633
Directory /workspace/18.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2129061803
Short name T199
Test name
Test status
Simulation time 1446157459 ps
CPU time 29.93 seconds
Started Jan 07 01:44:37 PM PST 24
Finished Jan 07 01:45:08 PM PST 24
Peak memory 260356 kb
Host smart-8f9a5e09-b029-4042-9cbb-f1ee7e9eb04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129061803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2129061803
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all_with_rand_reset.1229916501
Short name T101
Test name
Test status
Simulation time 11833007402 ps
CPU time 779.8 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:58:07 PM PST 24
Peak memory 938360 kb
Host smart-c2331330-fbae-4506-af7f-55881799e3f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229916501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.i2c_host_stress_all_with_rand_reset.1229916501
Directory /workspace/18.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.261260273
Short name T481
Test name
Test status
Simulation time 731610410 ps
CPU time 31.22 seconds
Started Jan 07 01:44:41 PM PST 24
Finished Jan 07 01:45:15 PM PST 24
Peak memory 211484 kb
Host smart-4d493f4d-db53-459b-92e6-06bda4efc253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261260273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.261260273
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1671818585
Short name T1251
Test name
Test status
Simulation time 11500874484 ps
CPU time 3.55 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:44:15 PM PST 24
Peak memory 222120 kb
Host smart-7b3d9637-d533-43c7-9290-b346e1e46719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671818585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1671818585
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2951400500
Short name T20
Test name
Test status
Simulation time 11574884552 ps
CPU time 3.43 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:24 PM PST 24
Peak memory 224196 kb
Host smart-74ba81be-646d-47bc-9a9d-f56e184e4e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951400500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2951400500
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1493626193
Short name T289
Test name
Test status
Simulation time 529033396 ps
CPU time 2.81 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:07 PM PST 24
Peak memory 203272 kb
Host smart-fffcf311-756c-4528-82fe-505085c67dfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493626193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1493626193
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1354925119
Short name T1017
Test name
Test status
Simulation time 3649340305 ps
CPU time 3.91 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 203284 kb
Host smart-3773791b-410e-41a0-92a1-97cd959fcf7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354925119 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1354925119
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.1314704640
Short name T512
Test name
Test status
Simulation time 16357830523 ps
CPU time 457.76 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:51:51 PM PST 24
Peak memory 3658716 kb
Host smart-03214c38-4821-42ce-b4e8-f7696c011e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314704640 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.1314704640
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.3414412022
Short name T1069
Test name
Test status
Simulation time 3797052517 ps
CPU time 4.73 seconds
Started Jan 07 01:44:05 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 209360 kb
Host smart-7adfd497-a6d7-4b72-b8dd-95323b5ad91b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414412022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.3414412022
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2410462827
Short name T913
Test name
Test status
Simulation time 957515489 ps
CPU time 11.6 seconds
Started Jan 07 01:44:06 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 203312 kb
Host smart-cf02fc29-3d65-4ca1-8370-c805dbb2317c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410462827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2410462827
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2640628005
Short name T246
Test name
Test status
Simulation time 1150432204 ps
CPU time 45.55 seconds
Started Jan 07 01:44:38 PM PST 24
Finished Jan 07 01:45:25 PM PST 24
Peak memory 203348 kb
Host smart-c0a3765f-fd70-4ade-a34a-1a8d4de44f86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640628005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2640628005
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.804957422
Short name T293
Test name
Test status
Simulation time 27010128039 ps
CPU time 101.9 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:45:53 PM PST 24
Peak memory 1603592 kb
Host smart-0e5b3246-b275-425e-8d0f-be2f9ecef89f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804957422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.804957422
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2166370705
Short name T1324
Test name
Test status
Simulation time 7465543775 ps
CPU time 30.48 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:48 PM PST 24
Peak memory 578636 kb
Host smart-d8c39f63-4825-4fa2-9c12-31e599b8c446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166370705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2166370705
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.2789954262
Short name T242
Test name
Test status
Simulation time 1400697831 ps
CPU time 6.49 seconds
Started Jan 07 01:44:41 PM PST 24
Finished Jan 07 01:44:50 PM PST 24
Peak memory 203320 kb
Host smart-36398979-db21-4ba5-a29b-b30405914736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789954262 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.2789954262
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_ovf.2262116143
Short name T1357
Test name
Test status
Simulation time 4752622710 ps
CPU time 60.28 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:45:11 PM PST 24
Peak memory 233140 kb
Host smart-b399e818-6999-4d76-b6f9-54764418de7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262116143 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_tx_ovf.2262116143
Directory /workspace/18.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.265477490
Short name T896
Test name
Test status
Simulation time 1560400427 ps
CPU time 6.69 seconds
Started Jan 07 01:44:03 PM PST 24
Finished Jan 07 01:44:17 PM PST 24
Peak memory 208668 kb
Host smart-42dc0207-7288-4fb9-b712-346512393789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265477490 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_unexp_stop.265477490
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1490849035
Short name T1110
Test name
Test status
Simulation time 62497841 ps
CPU time 0.63 seconds
Started Jan 07 01:44:21 PM PST 24
Finished Jan 07 01:44:23 PM PST 24
Peak memory 202208 kb
Host smart-8c6f9dd7-252e-419d-b3dd-12c6fc22adfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490849035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1490849035
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3305491205
Short name T54
Test name
Test status
Simulation time 198016469 ps
CPU time 1.52 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:21 PM PST 24
Peak memory 211452 kb
Host smart-e4f600e8-243b-4b05-911f-eee52d92c5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305491205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3305491205
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3654743684
Short name T1305
Test name
Test status
Simulation time 514049579 ps
CPU time 24.82 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:42 PM PST 24
Peak memory 293692 kb
Host smart-a6337bb7-f619-46e3-bb1c-00282ed64858
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654743684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3654743684
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2447359848
Short name T472
Test name
Test status
Simulation time 12733452544 ps
CPU time 132.18 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:47:32 PM PST 24
Peak memory 966492 kb
Host smart-2efc5fa8-8591-4d27-a10e-7ec2aa9e4c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447359848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2447359848
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1955232452
Short name T775
Test name
Test status
Simulation time 4602654153 ps
CPU time 507.76 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:54:10 PM PST 24
Peak memory 1231764 kb
Host smart-2a676ff8-9cba-4653-9a31-06a26a94755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955232452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1955232452
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.4086531578
Short name T866
Test name
Test status
Simulation time 1209050465 ps
CPU time 0.98 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:08 PM PST 24
Peak memory 203220 kb
Host smart-228db0c0-0942-483a-b93b-44ea97118986
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086531578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.4086531578
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3561458773
Short name T1179
Test name
Test status
Simulation time 287882757 ps
CPU time 8.39 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 01:45:47 PM PST 24
Peak memory 263220 kb
Host smart-ae0e2bc2-6ff6-46ad-a404-e6d69970e5f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561458773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3561458773
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2997509891
Short name T1100
Test name
Test status
Simulation time 4065623133 ps
CPU time 182.8 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:48:14 PM PST 24
Peak memory 1176032 kb
Host smart-e23a8e9c-23f7-406e-9997-6c750521b7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997509891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2997509891
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1069036474
Short name T1273
Test name
Test status
Simulation time 2523786186 ps
CPU time 74.57 seconds
Started Jan 07 01:44:25 PM PST 24
Finished Jan 07 01:45:42 PM PST 24
Peak memory 332864 kb
Host smart-28bb8088-0394-47d9-b3fb-afac0cd59c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069036474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1069036474
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3235815893
Short name T5
Test name
Test status
Simulation time 21269901 ps
CPU time 0.65 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:43 PM PST 24
Peak memory 202588 kb
Host smart-5e9e93fd-85a4-4561-bcfd-12d73ee46405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235815893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3235815893
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2812860897
Short name T133
Test name
Test status
Simulation time 507504142 ps
CPU time 3.14 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:45:50 PM PST 24
Peak memory 226428 kb
Host smart-64246f7c-a81b-45d2-b7b3-b1c15c21ee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812860897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2812860897
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_rx_oversample.4125283069
Short name T172
Test name
Test status
Simulation time 8442065676 ps
CPU time 80.56 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:46:54 PM PST 24
Peak memory 305660 kb
Host smart-2b951c5d-2072-479f-9616-f9b9ec0b8337
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125283069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_rx_oversample
.4125283069
Directory /workspace/19.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.665292035
Short name T1114
Test name
Test status
Simulation time 5158803279 ps
CPU time 78.16 seconds
Started Jan 07 01:44:43 PM PST 24
Finished Jan 07 01:46:03 PM PST 24
Peak memory 321800 kb
Host smart-80dfe054-33f6-44f0-bd5a-d37c4e52c94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665292035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.665292035
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1443231473
Short name T263
Test name
Test status
Simulation time 2270554623 ps
CPU time 51.73 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:46:11 PM PST 24
Peak memory 218680 kb
Host smart-de59c628-179e-4dcf-ae3e-cf9b5a7d0a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443231473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1443231473
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.297522109
Short name T687
Test name
Test status
Simulation time 10312735058 ps
CPU time 11.36 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:33 PM PST 24
Peak memory 260660 kb
Host smart-3b7f1400-1531-49ed-9a5f-050092e9f277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297522109 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.297522109
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3825698566
Short name T299
Test name
Test status
Simulation time 10574693587 ps
CPU time 13.86 seconds
Started Jan 07 01:44:16 PM PST 24
Finished Jan 07 01:44:31 PM PST 24
Peak memory 327708 kb
Host smart-c4c98d90-0731-420f-9dc3-f09900d6769e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825698566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3825698566
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1353782237
Short name T163
Test name
Test status
Simulation time 903978791 ps
CPU time 2.91 seconds
Started Jan 07 01:44:22 PM PST 24
Finished Jan 07 01:44:27 PM PST 24
Peak memory 203348 kb
Host smart-9e6bbea4-ad30-4a95-a151-d7756dbb7856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353782237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1353782237
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2376540790
Short name T874
Test name
Test status
Simulation time 6205863841 ps
CPU time 4.98 seconds
Started Jan 07 01:44:18 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 203432 kb
Host smart-787f76a0-95a5-4e95-b07c-b1c52d8c63f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376540790 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2376540790
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.540510164
Short name T1240
Test name
Test status
Simulation time 22868821524 ps
CPU time 370.86 seconds
Started Jan 07 01:44:17 PM PST 24
Finished Jan 07 01:50:30 PM PST 24
Peak memory 2835404 kb
Host smart-261790de-a125-4a29-a5c2-a40a379c100b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540510164 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.540510164
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.1266999946
Short name T100
Test name
Test status
Simulation time 678126847 ps
CPU time 3.81 seconds
Started Jan 07 01:44:23 PM PST 24
Finished Jan 07 01:44:30 PM PST 24
Peak memory 203380 kb
Host smart-5999350e-3580-4a41-9320-65336fea1e7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266999946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.1266999946
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1116226713
Short name T224
Test name
Test status
Simulation time 2452531549 ps
CPU time 21.94 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:46:02 PM PST 24
Peak memory 203360 kb
Host smart-82bea8db-88da-400c-ba01-647a47d34342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116226713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1116226713
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.2175146273
Short name T1170
Test name
Test status
Simulation time 45300872645 ps
CPU time 1798.57 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 02:15:26 PM PST 24
Peak memory 7337712 kb
Host smart-aab4aba8-c8c8-4086-87f9-792cec7529aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175146273 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.2175146273
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1523060729
Short name T67
Test name
Test status
Simulation time 8820732303 ps
CPU time 30.85 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:46:11 PM PST 24
Peak memory 223640 kb
Host smart-9ccc801d-e8c9-4ae2-b8b2-abf8b296bc8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523060729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1523060729
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3429599795
Short name T484
Test name
Test status
Simulation time 46007704995 ps
CPU time 3174.81 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 02:38:02 PM PST 24
Peak memory 10433712 kb
Host smart-3547db01-0ef8-45af-b6ef-71b25f94e417
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429599795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3429599795
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3953757121
Short name T804
Test name
Test status
Simulation time 6930517583 ps
CPU time 602.87 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:56:00 PM PST 24
Peak memory 1788772 kb
Host smart-cff35ef9-5af0-4e69-b60d-449a39934a3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953757121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3953757121
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2441309899
Short name T825
Test name
Test status
Simulation time 2203876549 ps
CPU time 7.28 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:33 PM PST 24
Peak memory 203272 kb
Host smart-cbaec01d-32f7-41d6-a70a-31b4f5f316dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441309899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2441309899
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_ovf.785659328
Short name T852
Test name
Test status
Simulation time 9159227357 ps
CPU time 33.43 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:58 PM PST 24
Peak memory 219808 kb
Host smart-10236fd1-db2d-4b35-87d6-3a3bde0e54a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785659328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_tx_ovf.785659328
Directory /workspace/19.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.925508846
Short name T1223
Test name
Test status
Simulation time 4995439902 ps
CPU time 9.64 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:29 PM PST 24
Peak memory 206256 kb
Host smart-8e6b1e20-2f75-48bf-a8cb-167ae18ab5a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925508846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_unexp_stop.925508846
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1777055103
Short name T1270
Test name
Test status
Simulation time 16342234 ps
CPU time 0.6 seconds
Started Jan 07 01:42:44 PM PST 24
Finished Jan 07 01:43:04 PM PST 24
Peak memory 202136 kb
Host smart-428cac47-abff-407a-af2c-819cf71fd109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777055103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1777055103
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2247589957
Short name T275
Test name
Test status
Simulation time 65248235 ps
CPU time 1.71 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 01:43:28 PM PST 24
Peak memory 211544 kb
Host smart-2ef5d004-aa73-4a0c-ae14-fe25f77df302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247589957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2247589957
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1600232900
Short name T1294
Test name
Test status
Simulation time 913892293 ps
CPU time 10.11 seconds
Started Jan 07 01:43:09 PM PST 24
Finished Jan 07 01:43:30 PM PST 24
Peak memory 289756 kb
Host smart-95f1f822-9363-48f4-8903-256385dfeb97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600232900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1600232900
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3506684658
Short name T1068
Test name
Test status
Simulation time 4998386973 ps
CPU time 64.16 seconds
Started Jan 07 01:43:09 PM PST 24
Finished Jan 07 01:44:24 PM PST 24
Peak memory 665224 kb
Host smart-126f317e-0471-443d-ab36-15d3df39d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506684658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3506684658
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.4019273651
Short name T590
Test name
Test status
Simulation time 15499355931 ps
CPU time 165.86 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:46:14 PM PST 24
Peak memory 1009132 kb
Host smart-0aafc863-b311-4d9b-af32-067397d09e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019273651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.4019273651
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.601187020
Short name T786
Test name
Test status
Simulation time 376384035 ps
CPU time 0.99 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 203292 kb
Host smart-83ea7178-f24e-41a5-b680-72c4b68b278c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601187020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.601187020
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3813786733
Short name T755
Test name
Test status
Simulation time 5656549686 ps
CPU time 636.69 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 01:54:16 PM PST 24
Peak memory 1615508 kb
Host smart-338c968f-46a8-452e-8d96-23e0cc7c46f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813786733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3813786733
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_override.3433480529
Short name T735
Test name
Test status
Simulation time 20639951 ps
CPU time 0.6 seconds
Started Jan 07 01:42:50 PM PST 24
Finished Jan 07 01:43:10 PM PST 24
Peak memory 202324 kb
Host smart-f9134eb0-fed8-4847-a982-443693a90350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433480529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3433480529
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.961118269
Short name T1160
Test name
Test status
Simulation time 28823504142 ps
CPU time 448.23 seconds
Started Jan 07 01:42:47 PM PST 24
Finished Jan 07 01:50:35 PM PST 24
Peak memory 203316 kb
Host smart-1647598e-af29-4ed4-a985-b88da7d7deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961118269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.961118269
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2246804337
Short name T410
Test name
Test status
Simulation time 2337598032 ps
CPU time 140.18 seconds
Started Jan 07 01:42:59 PM PST 24
Finished Jan 07 01:45:35 PM PST 24
Peak memory 276584 kb
Host smart-f30a1b91-11c3-44e3-b486-8d001ae93b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246804337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2246804337
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.89854895
Short name T182
Test name
Test status
Simulation time 71060312191 ps
CPU time 3027.06 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 02:34:04 PM PST 24
Peak memory 2948364 kb
Host smart-1f2b794c-940d-4e45-9b73-f843c5cec457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89854895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.89854895
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3610622699
Short name T645
Test name
Test status
Simulation time 3001945729 ps
CPU time 11.31 seconds
Started Jan 07 01:43:10 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 211600 kb
Host smart-24a850ff-1150-492c-b0d7-c4739d00d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610622699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3610622699
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3663561475
Short name T79
Test name
Test status
Simulation time 61983061 ps
CPU time 0.94 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:43:37 PM PST 24
Peak memory 219636 kb
Host smart-5b5b0add-fc61-4f56-8020-67c21e1bb134
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663561475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3663561475
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1853119636
Short name T72
Test name
Test status
Simulation time 10477225854 ps
CPU time 11.97 seconds
Started Jan 07 01:42:57 PM PST 24
Finished Jan 07 01:43:25 PM PST 24
Peak memory 269248 kb
Host smart-f354f773-94bb-4a36-9824-0b598362a231
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853119636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1853119636
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2430350819
Short name T766
Test name
Test status
Simulation time 10115542877 ps
CPU time 61.47 seconds
Started Jan 07 01:42:50 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 585176 kb
Host smart-78b54e38-7711-46b5-b2fc-d86c3144db39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430350819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2430350819
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.736910963
Short name T588
Test name
Test status
Simulation time 1538694280 ps
CPU time 2.31 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 203208 kb
Host smart-c0185932-a608-408c-bb64-59ec5ae8e78e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736910963 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.736910963
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1759734577
Short name T1186
Test name
Test status
Simulation time 3033120622 ps
CPU time 6.99 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:43:35 PM PST 24
Peak memory 206296 kb
Host smart-769b8d61-1276-4a30-816d-7b65a638ac35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759734577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1759734577
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.153049004
Short name T1296
Test name
Test status
Simulation time 48254686300 ps
CPU time 3340.49 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 02:39:31 PM PST 24
Peak memory 10722744 kb
Host smart-acefce60-a811-4f6c-8d78-509d16ee0dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153049004 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.153049004
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3091313954
Short name T639
Test name
Test status
Simulation time 2360506593 ps
CPU time 14.47 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:43:47 PM PST 24
Peak memory 203304 kb
Host smart-ba6cdd50-4be2-4218-860e-d92b3f3e8864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091313954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3091313954
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.259023944
Short name T695
Test name
Test status
Simulation time 8792914837 ps
CPU time 73.17 seconds
Started Jan 07 01:42:45 PM PST 24
Finished Jan 07 01:44:23 PM PST 24
Peak memory 215440 kb
Host smart-cab464f1-b4c9-4e71-9cab-9f9260f54fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259023944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_target_stress_all.259023944
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3661405351
Short name T404
Test name
Test status
Simulation time 2124534625 ps
CPU time 37.24 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:44:11 PM PST 24
Peak memory 223228 kb
Host smart-77a4b4d7-80a0-4ace-86e0-9abd0a410a84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661405351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3661405351
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.819053314
Short name T945
Test name
Test status
Simulation time 18440626828 ps
CPU time 140.65 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 1893608 kb
Host smart-e6ddec41-f0c0-43e8-9b56-bf021ad7a895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819053314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.819053314
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.41654259
Short name T317
Test name
Test status
Simulation time 10334396737 ps
CPU time 401.7 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:50:35 PM PST 24
Peak memory 1295592 kb
Host smart-97dc2320-3434-4eb0-b800-4df4225e33ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41654259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_stretch.41654259
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2225410590
Short name T911
Test name
Test status
Simulation time 8607095011 ps
CPU time 7.78 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 203408 kb
Host smart-f74e25f4-b154-4708-95a1-dedc54779551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225410590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2225410590
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_ovf.910386637
Short name T576
Test name
Test status
Simulation time 36125626982 ps
CPU time 38.17 seconds
Started Jan 07 01:43:39 PM PST 24
Finished Jan 07 01:44:33 PM PST 24
Peak memory 226480 kb
Host smart-9b54db09-1943-4fad-8d67-add88a7ecaf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910386637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_tx_ovf.910386637
Directory /workspace/2.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.817422538
Short name T614
Test name
Test status
Simulation time 1449167502 ps
CPU time 4.97 seconds
Started Jan 07 01:42:58 PM PST 24
Finished Jan 07 01:43:19 PM PST 24
Peak memory 203360 kb
Host smart-16a301cf-f8cd-4e08-a5a4-bcda52057332
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817422538 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_unexp_stop.817422538
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2099995376
Short name T926
Test name
Test status
Simulation time 18135468 ps
CPU time 0.62 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:45:29 PM PST 24
Peak memory 202152 kb
Host smart-bb80a596-39b5-4bbc-88cb-3e04c2bbea43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099995376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2099995376
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3381045345
Short name T1258
Test name
Test status
Simulation time 35988939 ps
CPU time 1.53 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:28 PM PST 24
Peak memory 211456 kb
Host smart-a0f6d9a5-8015-4bf2-8b91-408173a8a937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381045345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3381045345
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.936039722
Short name T1206
Test name
Test status
Simulation time 288574159 ps
CPU time 5.28 seconds
Started Jan 07 01:44:25 PM PST 24
Finished Jan 07 01:44:33 PM PST 24
Peak memory 257348 kb
Host smart-8ae2327e-e2e0-4732-8bf4-8b24a75126d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936039722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.936039722
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.682836970
Short name T944
Test name
Test status
Simulation time 19584118406 ps
CPU time 113.88 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:47:27 PM PST 24
Peak memory 455904 kb
Host smart-1e383e33-0783-4b8a-8173-6aef9395a0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682836970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.682836970
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2291628655
Short name T573
Test name
Test status
Simulation time 25318740665 ps
CPU time 911.01 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 02:00:31 PM PST 24
Peak memory 1665212 kb
Host smart-5a77482d-1a19-4f10-bb11-6e31f37e1f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291628655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2291628655
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.4214909292
Short name T606
Test name
Test status
Simulation time 125089460 ps
CPU time 0.98 seconds
Started Jan 07 01:44:19 PM PST 24
Finished Jan 07 01:44:21 PM PST 24
Peak memory 203220 kb
Host smart-b70f1f28-337f-4a3b-a1b9-254047aa6fb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214909292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.4214909292
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.683513862
Short name T144
Test name
Test status
Simulation time 2451622658 ps
CPU time 4.78 seconds
Started Jan 07 01:44:18 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 237072 kb
Host smart-0df3116e-1eb7-453c-bed1-98a93f99edb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683513862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
683513862
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2734122533
Short name T124
Test name
Test status
Simulation time 23260869098 ps
CPU time 264.72 seconds
Started Jan 07 01:44:04 PM PST 24
Finished Jan 07 01:48:36 PM PST 24
Peak memory 1542508 kb
Host smart-654687b6-a4fe-4264-9142-8fe2bd64e396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734122533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2734122533
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3560237180
Short name T1059
Test name
Test status
Simulation time 4309699317 ps
CPU time 85.11 seconds
Started Jan 07 01:44:21 PM PST 24
Finished Jan 07 01:45:48 PM PST 24
Peak memory 336068 kb
Host smart-14ebe6f5-f77b-4f1a-841c-3936050ed784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560237180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3560237180
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.1517283579
Short name T846
Test name
Test status
Simulation time 22928040 ps
CPU time 0.63 seconds
Started Jan 07 01:44:18 PM PST 24
Finished Jan 07 01:44:20 PM PST 24
Peak memory 202208 kb
Host smart-10bf01ea-55d0-4660-b7fb-b8a2c9599521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517283579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1517283579
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.4006042359
Short name T897
Test name
Test status
Simulation time 10224702996 ps
CPU time 183 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:48:29 PM PST 24
Peak memory 490048 kb
Host smart-6c1fe529-660e-49e3-89f9-209c9d62b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006042359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.4006042359
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1308835664
Short name T700
Test name
Test status
Simulation time 8374449445 ps
CPU time 32.84 seconds
Started Jan 07 01:44:22 PM PST 24
Finished Jan 07 01:44:57 PM PST 24
Peak memory 211572 kb
Host smart-5b8c2f83-0c38-4774-82da-9844c2a55c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308835664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1308835664
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2466136162
Short name T1060
Test name
Test status
Simulation time 10106416521 ps
CPU time 61.65 seconds
Started Jan 07 01:44:20 PM PST 24
Finished Jan 07 01:45:23 PM PST 24
Peak memory 592008 kb
Host smart-eebbb02b-1873-41fa-9ecb-a75ce5b90d5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466136162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2466136162
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2965603111
Short name T840
Test name
Test status
Simulation time 10102618082 ps
CPU time 24.35 seconds
Started Jan 07 01:44:19 PM PST 24
Finished Jan 07 01:44:45 PM PST 24
Peak memory 351476 kb
Host smart-e1bdabad-3ff4-41ea-a9df-0ec620dd70ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965603111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2965603111
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1706050105
Short name T256
Test name
Test status
Simulation time 557346578 ps
CPU time 2.55 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:33 PM PST 24
Peak memory 203336 kb
Host smart-d5e4f356-f626-49db-8778-abee0e1ba211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706050105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1706050105
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3860768627
Short name T201
Test name
Test status
Simulation time 2277216913 ps
CPU time 5.13 seconds
Started Jan 07 01:44:17 PM PST 24
Finished Jan 07 01:44:24 PM PST 24
Peak memory 203308 kb
Host smart-f9dc81c2-9ba3-418a-b701-cd07934b85ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860768627 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3860768627
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.1486801363
Short name T493
Test name
Test status
Simulation time 19651597361 ps
CPU time 746.5 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:57:46 PM PST 24
Peak memory 4457972 kb
Host smart-f41addde-eb3a-4a85-93d2-bd64fb3ae8a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486801363 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.1486801363
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.2631705625
Short name T635
Test name
Test status
Simulation time 1221165705 ps
CPU time 3.6 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:33 PM PST 24
Peak memory 203268 kb
Host smart-36bf8e1e-7973-4521-99cf-3ea3adeb5572
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631705625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.2631705625
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.4206584316
Short name T245
Test name
Test status
Simulation time 2265741268 ps
CPU time 14.77 seconds
Started Jan 07 01:44:18 PM PST 24
Finished Jan 07 01:44:34 PM PST 24
Peak memory 203384 kb
Host smart-d30094c2-97d9-46e2-85de-b129d800692c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206584316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.4206584316
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.3020009804
Short name T1351
Test name
Test status
Simulation time 9938735932 ps
CPU time 200.78 seconds
Started Jan 07 01:44:43 PM PST 24
Finished Jan 07 01:48:06 PM PST 24
Peak memory 405076 kb
Host smart-ebf1497e-81ae-495c-a106-66f7a3b00dd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020009804 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.3020009804
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3132577453
Short name T312
Test name
Test status
Simulation time 1602955246 ps
CPU time 26.13 seconds
Started Jan 07 01:44:24 PM PST 24
Finished Jan 07 01:44:53 PM PST 24
Peak memory 220232 kb
Host smart-fb03b39b-6b63-4a2c-8d67-2c07a76d622e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132577453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3132577453
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2618483391
Short name T1078
Test name
Test status
Simulation time 13642536545 ps
CPU time 365.13 seconds
Started Jan 07 01:44:25 PM PST 24
Finished Jan 07 01:50:33 PM PST 24
Peak memory 1363700 kb
Host smart-0fc17d13-f16b-438e-8f43-0a92bcffc1e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618483391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2618483391
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2052202111
Short name T1315
Test name
Test status
Simulation time 1344143449 ps
CPU time 6.93 seconds
Started Jan 07 01:44:25 PM PST 24
Finished Jan 07 01:44:34 PM PST 24
Peak memory 211620 kb
Host smart-7da93646-319e-4adc-946a-9cdb3eca28ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052202111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2052202111
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_ovf.2947043922
Short name T260
Test name
Test status
Simulation time 4395755305 ps
CPU time 43.1 seconds
Started Jan 07 01:44:28 PM PST 24
Finished Jan 07 01:45:13 PM PST 24
Peak memory 223044 kb
Host smart-ae036b6a-2466-4fab-92d0-657892543779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947043922 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_tx_ovf.2947043922
Directory /workspace/20.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.1406408799
Short name T1300
Test name
Test status
Simulation time 2588129657 ps
CPU time 6.28 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:25 PM PST 24
Peak memory 204420 kb
Host smart-ab78b875-9c7d-48d7-aa53-40e78bbf5168
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406408799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.1406408799
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.86669809
Short name T423
Test name
Test status
Simulation time 19798209 ps
CPU time 0.61 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:45:29 PM PST 24
Peak memory 202220 kb
Host smart-cce69716-3d91-4613-95ea-3363a384eb47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86669809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.86669809
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3064505612
Short name T612
Test name
Test status
Simulation time 37440554 ps
CPU time 1.45 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:45:57 PM PST 24
Peak memory 203344 kb
Host smart-91bc08b8-74a9-4e36-b486-0de26785fce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064505612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3064505612
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3939351248
Short name T647
Test name
Test status
Simulation time 6354480244 ps
CPU time 24.33 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:50 PM PST 24
Peak memory 304500 kb
Host smart-ae246f2e-2d8d-4e3d-bdcf-1482b3dac409
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939351248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3939351248
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1659670405
Short name T318
Test name
Test status
Simulation time 5482557077 ps
CPU time 105.79 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 407692 kb
Host smart-2748089c-a493-4f0f-a7fd-6fcb494aae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659670405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1659670405
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1536484289
Short name T655
Test name
Test status
Simulation time 22472480135 ps
CPU time 221.9 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:49:15 PM PST 24
Peak memory 1215436 kb
Host smart-e3db5d14-5b68-48a7-826c-9f668d0292e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536484289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1536484289
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1616200467
Short name T1139
Test name
Test status
Simulation time 391019039 ps
CPU time 0.95 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 203352 kb
Host smart-a1b97e81-4be1-43a8-858d-374de2c2174e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616200467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1616200467
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.626486281
Short name T1174
Test name
Test status
Simulation time 1297818433 ps
CPU time 4.62 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:47 PM PST 24
Peak memory 203336 kb
Host smart-c988d864-97b9-4a32-8016-0f2327845640
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626486281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
626486281
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2305675424
Short name T684
Test name
Test status
Simulation time 3699297451 ps
CPU time 174.65 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:48:12 PM PST 24
Peak memory 1125964 kb
Host smart-864d958b-8da0-4559-98c7-0400846b004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305675424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2305675424
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.1613039759
Short name T313
Test name
Test status
Simulation time 7317673044 ps
CPU time 49.29 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:46:46 PM PST 24
Peak memory 274564 kb
Host smart-ddd41c65-d8a0-4ccd-82cf-24d94026a556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613039759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1613039759
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.335554256
Short name T368
Test name
Test status
Simulation time 23494057 ps
CPU time 0.62 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:44:45 PM PST 24
Peak memory 202280 kb
Host smart-cac27f79-0b52-4970-9d96-b43cf2a71e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335554256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.335554256
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2206621442
Short name T1373
Test name
Test status
Simulation time 51564811084 ps
CPU time 914.52 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 02:00:38 PM PST 24
Peak memory 203408 kb
Host smart-cf3b3164-e22c-4765-80d8-66bdaa5a897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206621442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2206621442
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_rx_oversample.426483104
Short name T185
Test name
Test status
Simulation time 3005586931 ps
CPU time 185.5 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 01:48:44 PM PST 24
Peak memory 370568 kb
Host smart-5d883e21-f0f4-4cfc-9948-c2d6021467cd
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426483104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_rx_oversample.
426483104
Directory /workspace/21.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.615133949
Short name T200
Test name
Test status
Simulation time 12184798057 ps
CPU time 154.56 seconds
Started Jan 07 01:44:23 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 276800 kb
Host smart-f3ac23e0-bf82-4f5c-9a10-4c468148e9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615133949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.615133949
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1979726030
Short name T1288
Test name
Test status
Simulation time 20449594885 ps
CPU time 1949.71 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 02:18:42 PM PST 24
Peak memory 1661456 kb
Host smart-a2e78fdc-96b6-4b32-abe1-2dceb53bbb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979726030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1979726030
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.4123149660
Short name T439
Test name
Test status
Simulation time 1269544007 ps
CPU time 27.42 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:46:07 PM PST 24
Peak memory 211508 kb
Host smart-62c8c3b9-ca2c-4fe3-8c21-59db99811078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123149660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.4123149660
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2813672921
Short name T288
Test name
Test status
Simulation time 1703385459 ps
CPU time 3.27 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:46:06 PM PST 24
Peak memory 203284 kb
Host smart-123706e5-65b6-4dd5-befd-fa5fc2cb1d10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813672921 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2813672921
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.2162946022
Short name T558
Test name
Test status
Simulation time 10054765538 ps
CPU time 62.05 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:47:08 PM PST 24
Peak memory 504104 kb
Host smart-99e278b5-0758-4202-918d-e292fb1eed01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162946022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.2162946022
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.761973792
Short name T855
Test name
Test status
Simulation time 3427415500 ps
CPU time 2.59 seconds
Started Jan 07 01:45:40 PM PST 24
Finished Jan 07 01:46:23 PM PST 24
Peak memory 203404 kb
Host smart-d42ee495-ae06-4cab-919b-78d9117007b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761973792 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.761973792
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.61504128
Short name T1070
Test name
Test status
Simulation time 1669777484 ps
CPU time 4.14 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:45:53 PM PST 24
Peak memory 203224 kb
Host smart-5da3c693-49fc-42f9-8884-9d79521d127a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61504128 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.61504128
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3996306118
Short name T1073
Test name
Test status
Simulation time 4134558575 ps
CPU time 33.77 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 800540 kb
Host smart-84466851-1afb-47dd-88cf-2b9a8ee951f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996306118 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3996306118
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.3362942955
Short name T1349
Test name
Test status
Simulation time 836109808 ps
CPU time 4.52 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:46:10 PM PST 24
Peak memory 203216 kb
Host smart-8c932ddb-6f51-424b-a9d5-822cc6b6fdf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362942955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.3362942955
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3035100153
Short name T517
Test name
Test status
Simulation time 1781759389 ps
CPU time 19.82 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:19 PM PST 24
Peak memory 203276 kb
Host smart-1a999112-7249-4270-8326-a51251294345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035100153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3035100153
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.1274507631
Short name T568
Test name
Test status
Simulation time 70803857007 ps
CPU time 2773.64 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 02:32:09 PM PST 24
Peak memory 1127256 kb
Host smart-c391ac23-9ac7-41b4-a056-e7629cdcc796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274507631 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.1274507631
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.4269350231
Short name T873
Test name
Test status
Simulation time 3937240426 ps
CPU time 11.42 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 203248 kb
Host smart-36beac7c-1e4f-4940-9e87-829d0ae60d1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269350231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.4269350231
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2750409319
Short name T762
Test name
Test status
Simulation time 3593265527 ps
CPU time 7.24 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:06 PM PST 24
Peak memory 208740 kb
Host smart-531062c6-f1a3-4f89-bc95-2a69be046461
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750409319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2750409319
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_ovf.567858578
Short name T902
Test name
Test status
Simulation time 13586335348 ps
CPU time 45.34 seconds
Started Jan 07 01:45:12 PM PST 24
Finished Jan 07 01:46:26 PM PST 24
Peak memory 222716 kb
Host smart-8bec8ff3-0cf6-45eb-93a0-fceaaceeda09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567858578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_tx_ovf.567858578
Directory /workspace/21.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.496402916
Short name T322
Test name
Test status
Simulation time 1346312406 ps
CPU time 5.28 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:46:02 PM PST 24
Peak memory 205000 kb
Host smart-9077758f-09a1-4bca-80e9-44ebab10285f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496402916 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_unexp_stop.496402916
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3367262423
Short name T822
Test name
Test status
Simulation time 17845584 ps
CPU time 0.62 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:43 PM PST 24
Peak memory 202248 kb
Host smart-ec38e178-0522-4fc3-9a7b-2ade6243eddf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367262423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3367262423
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.320443834
Short name T552
Test name
Test status
Simulation time 111918486 ps
CPU time 1.57 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:24 PM PST 24
Peak memory 211556 kb
Host smart-1c34b31e-94fb-44a0-9ce4-2e468e76a52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320443834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.320443834
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.275826976
Short name T638
Test name
Test status
Simulation time 728696406 ps
CPU time 16.3 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:42 PM PST 24
Peak memory 266920 kb
Host smart-fa23c3e5-fe85-47e5-bc09-4a33c0b95d70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275826976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.275826976
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3061240469
Short name T1260
Test name
Test status
Simulation time 161006999 ps
CPU time 4.69 seconds
Started Jan 07 01:44:19 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 230628 kb
Host smart-4c92dbb7-a95e-4327-9004-7bdc38a6e8e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061240469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3061240469
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2744660727
Short name T648
Test name
Test status
Simulation time 5653563068 ps
CPU time 270.58 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:50:03 PM PST 24
Peak memory 1587992 kb
Host smart-c6ff511b-3010-4339-8e42-ebbe186eabbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744660727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2744660727
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_override.1575657764
Short name T1285
Test name
Test status
Simulation time 90403473 ps
CPU time 0.61 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:25 PM PST 24
Peak memory 202308 kb
Host smart-3c04523b-8d14-447f-a03f-6a34bf1aed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575657764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1575657764
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2669106465
Short name T37
Test name
Test status
Simulation time 3004862500 ps
CPU time 159.47 seconds
Started Jan 07 01:44:24 PM PST 24
Finished Jan 07 01:47:06 PM PST 24
Peak memory 260120 kb
Host smart-60b63c2a-3f60-4cf8-9ca7-7be520c7bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669106465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2669106465
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_rx_oversample.828688502
Short name T55
Test name
Test status
Simulation time 3828125962 ps
CPU time 147.75 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:47:56 PM PST 24
Peak memory 279952 kb
Host smart-05139e95-e2c1-4ae2-a46c-13c9e607511e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828688502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_rx_oversample.
828688502
Directory /workspace/22.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.393935332
Short name T1278
Test name
Test status
Simulation time 1910969294 ps
CPU time 41.58 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:46:11 PM PST 24
Peak memory 280028 kb
Host smart-9812f38b-f7de-4013-ab8e-4406e9d8ab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393935332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.393935332
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.2405739407
Short name T967
Test name
Test status
Simulation time 66086132421 ps
CPU time 1896.2 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 02:17:07 PM PST 24
Peak memory 3552776 kb
Host smart-799bd798-8c28-43c6-81cb-6e2a8eba3492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405739407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2405739407
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2449598870
Short name T851
Test name
Test status
Simulation time 937628385 ps
CPU time 12.54 seconds
Started Jan 07 01:44:20 PM PST 24
Finished Jan 07 01:44:35 PM PST 24
Peak memory 219732 kb
Host smart-15c0d4b6-ca56-41a9-a68e-b466f005236c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449598870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2449598870
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.741095216
Short name T328
Test name
Test status
Simulation time 1026319684 ps
CPU time 4.21 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:47 PM PST 24
Peak memory 203356 kb
Host smart-ad51b1de-b0ca-40cc-9392-90d95dfe8596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741095216 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.741095216
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2236025409
Short name T222
Test name
Test status
Simulation time 10149739555 ps
CPU time 42.36 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:46:14 PM PST 24
Peak memory 484976 kb
Host smart-6b3f12d5-d747-45bf-b25a-0aadc0f817d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236025409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2236025409
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.500962720
Short name T441
Test name
Test status
Simulation time 2150582013 ps
CPU time 2.58 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:03 PM PST 24
Peak memory 203392 kb
Host smart-477294d9-47f3-4f35-b221-9b115bad691e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500962720 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.500962720
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.291236850
Short name T212
Test name
Test status
Simulation time 1695909837 ps
CPU time 5.47 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 203180 kb
Host smart-9582896b-5438-4fb8-8620-d2d2e7d31fe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291236850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.291236850
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2342375529
Short name T585
Test name
Test status
Simulation time 16115110254 ps
CPU time 61.86 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:46:34 PM PST 24
Peak memory 904032 kb
Host smart-1dc596c6-ea05-4c95-8ab7-4a2d522dfd13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342375529 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2342375529
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.1293542932
Short name T731
Test name
Test status
Simulation time 1998203313 ps
CPU time 3.23 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:45:58 PM PST 24
Peak memory 203284 kb
Host smart-87bb3bca-3a17-4766-aafa-47e27114a3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293542932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.1293542932
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.930070126
Short name T1043
Test name
Test status
Simulation time 747994126 ps
CPU time 18.78 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:45:48 PM PST 24
Peak memory 203312 kb
Host smart-f355391b-3d27-4e77-8603-9192e09153dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930070126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.930070126
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2944229400
Short name T605
Test name
Test status
Simulation time 57735856671 ps
CPU time 289.65 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:50:54 PM PST 24
Peak memory 1569032 kb
Host smart-7726a6ae-ba9d-463f-b2d7-040365989d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944229400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2944229400
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2152296320
Short name T340
Test name
Test status
Simulation time 6360525392 ps
CPU time 60.89 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:46:46 PM PST 24
Peak memory 203248 kb
Host smart-3c390635-cea8-4ed2-8ebd-65bc20041644
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152296320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2152296320
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.4119603558
Short name T1019
Test name
Test status
Simulation time 40888857607 ps
CPU time 139.41 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:47:48 PM PST 24
Peak memory 1614640 kb
Host smart-535fc5e0-6000-46b5-a387-a65382f4e4ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119603558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.4119603558
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3789900985
Short name T356
Test name
Test status
Simulation time 20537593283 ps
CPU time 123.02 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:48:11 PM PST 24
Peak memory 1070100 kb
Host smart-0b3cd579-2a71-4260-954d-2e3a529e0698
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789900985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3789900985
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.3903293373
Short name T1125
Test name
Test status
Simulation time 7018889753 ps
CPU time 8.11 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:46:06 PM PST 24
Peak memory 212688 kb
Host smart-be55b463-8e4a-4f50-825c-27ec2f69265c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903293373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_target_unexp_stop.3903293373
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2528154026
Short name T827
Test name
Test status
Simulation time 47667342 ps
CPU time 0.62 seconds
Started Jan 07 01:44:25 PM PST 24
Finished Jan 07 01:44:28 PM PST 24
Peak memory 203188 kb
Host smart-903be3a7-d769-42fe-b475-def5177ecaf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528154026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2528154026
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1401889440
Short name T1233
Test name
Test status
Simulation time 72899033 ps
CPU time 1.45 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 211484 kb
Host smart-89f724a3-6ba3-47e9-ab71-f7278e5250e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401889440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1401889440
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.8786252
Short name T346
Test name
Test status
Simulation time 1069003991 ps
CPU time 11.24 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:46:27 PM PST 24
Peak memory 241492 kb
Host smart-e9562118-4a24-40d1-8349-814ff6566cfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8786252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.8786252
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2044453435
Short name T1149
Test name
Test status
Simulation time 19973314734 ps
CPU time 66.49 seconds
Started Jan 07 01:45:38 PM PST 24
Finished Jan 07 01:47:25 PM PST 24
Peak memory 626084 kb
Host smart-1de14615-e1b3-4911-a789-09cbfe4b65d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044453435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2044453435
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3285891239
Short name T177
Test name
Test status
Simulation time 4304979357 ps
CPU time 325.91 seconds
Started Jan 07 01:45:38 PM PST 24
Finished Jan 07 01:51:44 PM PST 24
Peak memory 905616 kb
Host smart-a912ee50-eba1-4d35-8f99-ca385fe5f8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285891239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3285891239
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1079042040
Short name T1144
Test name
Test status
Simulation time 103632782 ps
CPU time 0.82 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:03 PM PST 24
Peak memory 202404 kb
Host smart-5312a5b8-f9cf-4ab3-9361-c1c246e0fc40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079042040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1079042040
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1208456805
Short name T901
Test name
Test status
Simulation time 509755365 ps
CPU time 2.89 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 203432 kb
Host smart-7fc3290f-7d15-4075-a8b3-86d65d60e5f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208456805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1208456805
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1694783567
Short name T704
Test name
Test status
Simulation time 6127950205 ps
CPU time 333.52 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:51:23 PM PST 24
Peak memory 1701636 kb
Host smart-89bd1276-48bf-4fb3-8358-4824006a21b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694783567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1694783567
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1616170247
Short name T1153
Test name
Test status
Simulation time 2152533190 ps
CPU time 105.3 seconds
Started Jan 07 01:44:38 PM PST 24
Finished Jan 07 01:46:25 PM PST 24
Peak memory 235956 kb
Host smart-2e5ae088-3788-43df-815b-312399ad2a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616170247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1616170247
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.130132626
Short name T1015
Test name
Test status
Simulation time 19325444 ps
CPU time 0.61 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 202404 kb
Host smart-3abf9e28-6889-4716-b010-4c05fb043c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130132626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.130132626
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1427861280
Short name T417
Test name
Test status
Simulation time 2992740029 ps
CPU time 26.42 seconds
Started Jan 07 01:45:32 PM PST 24
Finished Jan 07 01:46:37 PM PST 24
Peak memory 211512 kb
Host smart-f5c076be-0f09-48f8-a132-130057a131de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427861280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1427861280
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_rx_oversample.3745856523
Short name T631
Test name
Test status
Simulation time 10990992600 ps
CPU time 135.12 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:48:31 PM PST 24
Peak memory 374864 kb
Host smart-46af5232-ca0b-4d3a-a7ae-6f57b56c8fcb
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745856523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_rx_oversample
.3745856523
Directory /workspace/23.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3927757302
Short name T701
Test name
Test status
Simulation time 11180814248 ps
CPU time 87.01 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:47:19 PM PST 24
Peak memory 324292 kb
Host smart-29b19c17-7863-4b62-9826-99f63e83e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927757302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3927757302
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1000801494
Short name T1347
Test name
Test status
Simulation time 3384294517 ps
CPU time 14.12 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:46:30 PM PST 24
Peak memory 211584 kb
Host smart-b02a8448-a4a6-40bf-87ba-421284cd8046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000801494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1000801494
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1625018762
Short name T1328
Test name
Test status
Simulation time 2095434654 ps
CPU time 3.87 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:28 PM PST 24
Peak memory 203388 kb
Host smart-88b59e10-91c6-4534-a886-49a57a05225d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625018762 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1625018762
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.1430654104
Short name T1207
Test name
Test status
Simulation time 10963406677 ps
CPU time 3.31 seconds
Started Jan 07 01:44:22 PM PST 24
Finished Jan 07 01:44:27 PM PST 24
Peak memory 210024 kb
Host smart-f599a77c-cde9-4084-a725-6509451b59b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430654104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.1430654104
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3681909707
Short name T287
Test name
Test status
Simulation time 10281073784 ps
CPU time 30.29 seconds
Started Jan 07 01:44:23 PM PST 24
Finished Jan 07 01:44:56 PM PST 24
Peak memory 453572 kb
Host smart-29e118a9-137c-44cf-9a84-06e50f3ba622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681909707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3681909707
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3528862695
Short name T777
Test name
Test status
Simulation time 2118745751 ps
CPU time 2.42 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:26 PM PST 24
Peak memory 203392 kb
Host smart-5e29203f-e7bd-4cf8-935d-1b730da47bd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528862695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3528862695
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3896926991
Short name T821
Test name
Test status
Simulation time 7943783967 ps
CPU time 6.03 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 212076 kb
Host smart-47fe6ce3-9198-44f7-b05e-dfa6a0e4702d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896926991 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3896926991
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2268300211
Short name T1266
Test name
Test status
Simulation time 9375920971 ps
CPU time 27.15 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:30 PM PST 24
Peak memory 633540 kb
Host smart-feeef405-704d-4415-a311-60245545a685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268300211 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2268300211
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3459628004
Short name T214
Test name
Test status
Simulation time 767023732 ps
CPU time 4.07 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:34 PM PST 24
Peak memory 202672 kb
Host smart-367de5d0-8a25-4c09-9d90-206abf29ff23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459628004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3459628004
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1128114385
Short name T501
Test name
Test status
Simulation time 909868949 ps
CPU time 8.91 seconds
Started Jan 07 01:45:32 PM PST 24
Finished Jan 07 01:46:19 PM PST 24
Peak memory 203272 kb
Host smart-860a8691-cd32-4c2b-bdb1-d0448bbd4a79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128114385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1128114385
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.2644990514
Short name T244
Test name
Test status
Simulation time 37299914305 ps
CPU time 1657.68 seconds
Started Jan 07 01:44:22 PM PST 24
Finished Jan 07 02:12:02 PM PST 24
Peak memory 1224280 kb
Host smart-66eddccf-30ff-4014-8819-28d468c5c21e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644990514 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.2644990514
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.822196620
Short name T1225
Test name
Test status
Simulation time 1108066224 ps
CPU time 15.54 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 214072 kb
Host smart-ced8f39a-6984-462c-81be-2832a0dd7043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822196620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_rd.822196620
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1017602650
Short name T319
Test name
Test status
Simulation time 7352814850 ps
CPU time 34.26 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:46:50 PM PST 24
Peak memory 810380 kb
Host smart-bb4672e6-4894-4bc8-9cd2-02e642f76dea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017602650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1017602650
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2879043159
Short name T63
Test name
Test status
Simulation time 17669712436 ps
CPU time 91.93 seconds
Started Jan 07 01:45:48 PM PST 24
Finished Jan 07 01:48:01 PM PST 24
Peak memory 1049360 kb
Host smart-945ec56a-fdf6-473f-b7fc-16e11362318d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879043159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2879043159
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3992615849
Short name T716
Test name
Test status
Simulation time 1811299787 ps
CPU time 7.14 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:33 PM PST 24
Peak memory 211440 kb
Host smart-31370d32-8d50-4ee9-aefa-2b45ee771b38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992615849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3992615849
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_ovf.3455752776
Short name T268
Test name
Test status
Simulation time 2974292248 ps
CPU time 42.34 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:45 PM PST 24
Peak memory 223028 kb
Host smart-54c39800-6177-41de-b0ed-821633490bc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455752776 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_tx_ovf.3455752776
Directory /workspace/23.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.3071009508
Short name T46
Test name
Test status
Simulation time 1517244172 ps
CPU time 5.42 seconds
Started Jan 07 01:44:22 PM PST 24
Finished Jan 07 01:44:30 PM PST 24
Peak memory 208752 kb
Host smart-cb375e27-cd09-4de4-b982-563f77920ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071009508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.3071009508
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.901931088
Short name T910
Test name
Test status
Simulation time 80809635 ps
CPU time 0.6 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:00 PM PST 24
Peak memory 203148 kb
Host smart-0cb3f54d-19ee-4f2c-b6c1-909c7244fe46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901931088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.901931088
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3140419535
Short name T459
Test name
Test status
Simulation time 152320615 ps
CPU time 1.38 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 211512 kb
Host smart-f2933278-e272-4e55-81f4-181dd62dbfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140419535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3140419535
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.741333147
Short name T1155
Test name
Test status
Simulation time 1161956818 ps
CPU time 14.76 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:46:12 PM PST 24
Peak memory 261544 kb
Host smart-dcda8c35-a325-4e4e-b3a0-ec37407c27c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741333147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.741333147
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1874576933
Short name T793
Test name
Test status
Simulation time 30066750945 ps
CPU time 538.49 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:54:24 PM PST 24
Peak memory 1961808 kb
Host smart-890fb4d5-ec2a-4845-abc9-9b7612c5eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874576933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1874576933
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2691657034
Short name T364
Test name
Test status
Simulation time 462094414 ps
CPU time 1.09 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:31 PM PST 24
Peak memory 203320 kb
Host smart-d8d8ac72-21bd-4b57-b29e-1c391ee1527a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691657034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2691657034
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2740081943
Short name T217
Test name
Test status
Simulation time 1346679442 ps
CPU time 5.06 seconds
Started Jan 07 01:44:20 PM PST 24
Finished Jan 07 01:44:27 PM PST 24
Peak memory 203280 kb
Host smart-340c5913-5dae-4b51-b434-f4e2d088c012
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740081943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2740081943
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3560946731
Short name T999
Test name
Test status
Simulation time 18594862798 ps
CPU time 228.99 seconds
Started Jan 07 01:44:28 PM PST 24
Finished Jan 07 01:48:19 PM PST 24
Peak memory 1315204 kb
Host smart-c5adba43-3f6c-40b3-986e-06605f45a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560946731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3560946731
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2457746666
Short name T386
Test name
Test status
Simulation time 1404046183 ps
CPU time 32.17 seconds
Started Jan 07 01:45:32 PM PST 24
Finished Jan 07 01:46:43 PM PST 24
Peak memory 262120 kb
Host smart-8321bb9f-646a-4d67-8f57-8855d586da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457746666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2457746666
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1099613108
Short name T1118
Test name
Test status
Simulation time 18117556 ps
CPU time 0.63 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:32 PM PST 24
Peak memory 203132 kb
Host smart-f658d05e-622e-475a-b1bc-b91ae217b298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099613108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1099613108
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3081895423
Short name T136
Test name
Test status
Simulation time 6927512855 ps
CPU time 27.42 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 203388 kb
Host smart-3ea8a16d-3fe0-43b7-b577-60c75f75fd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081895423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3081895423
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_rx_oversample.2153619823
Short name T282
Test name
Test status
Simulation time 6969359937 ps
CPU time 50.64 seconds
Started Jan 07 01:44:20 PM PST 24
Finished Jan 07 01:45:12 PM PST 24
Peak memory 271932 kb
Host smart-6a3fa96e-39d5-49ab-9a4b-5473eb8b63fd
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153619823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_rx_oversample
.2153619823
Directory /workspace/24.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3678778093
Short name T844
Test name
Test status
Simulation time 10100501661 ps
CPU time 161.12 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:48:14 PM PST 24
Peak memory 276680 kb
Host smart-434002e3-31db-41ca-9b7e-0d6554594d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678778093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3678778093
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.663704514
Short name T829
Test name
Test status
Simulation time 1387795629 ps
CPU time 9.6 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:45:59 PM PST 24
Peak memory 219632 kb
Host smart-507bdfac-5f69-48d9-992d-b8cd0cf163ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663704514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.663704514
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1816250172
Short name T637
Test name
Test status
Simulation time 4927902846 ps
CPU time 4.42 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:46:00 PM PST 24
Peak memory 203376 kb
Host smart-4c659ded-6a65-4a54-b9b6-f10f829aaf05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816250172 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1816250172
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.4058083648
Short name T674
Test name
Test status
Simulation time 10073285658 ps
CPU time 59.6 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:46:53 PM PST 24
Peak memory 546740 kb
Host smart-ffd8df93-cf1f-4977-bb9a-07638b6aaf6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058083648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.4058083648
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3713864429
Short name T583
Test name
Test status
Simulation time 10097500295 ps
CPU time 81.9 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:47:26 PM PST 24
Peak memory 650752 kb
Host smart-f80cf79f-a902-49bc-a927-6d4fda5d3669
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713864429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3713864429
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2722274484
Short name T1180
Test name
Test status
Simulation time 1840599550 ps
CPU time 2.14 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 203184 kb
Host smart-eb41658e-e14a-46d3-ab4f-d9e881ef7295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722274484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2722274484
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.4125587732
Short name T516
Test name
Test status
Simulation time 1171933314 ps
CPU time 4.87 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:45:44 PM PST 24
Peak memory 203264 kb
Host smart-7b3d9627-2876-4fd1-878f-484854e17d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125587732 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.4125587732
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.3941381308
Short name T1235
Test name
Test status
Simulation time 20778742940 ps
CPU time 53.94 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:47:00 PM PST 24
Peak memory 736260 kb
Host smart-dfe7e822-3f5c-4dfe-a37d-c232a4f575bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941381308 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3941381308
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.3944997576
Short name T1172
Test name
Test status
Simulation time 4219822772 ps
CPU time 5.03 seconds
Started Jan 07 01:45:41 PM PST 24
Finished Jan 07 01:46:26 PM PST 24
Peak memory 203340 kb
Host smart-52d28b96-0756-4337-ae7b-c6f405c6f8d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944997576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.3944997576
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.595842727
Short name T452
Test name
Test status
Simulation time 57913319547 ps
CPU time 240.99 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:50:06 PM PST 24
Peak memory 2141328 kb
Host smart-f2ba2db8-d8f8-46cf-9607-c24fb5aa8f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595842727 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.i2c_target_stress_all.595842727
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3532503336
Short name T1086
Test name
Test status
Simulation time 886692597 ps
CPU time 33.67 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:46:47 PM PST 24
Peak memory 203292 kb
Host smart-1dbc30a8-190d-4259-99eb-92670aac2f12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532503336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3532503336
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.775528911
Short name T1277
Test name
Test status
Simulation time 17152519628 ps
CPU time 39.82 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:46:09 PM PST 24
Peak memory 904060 kb
Host smart-69f137ca-64f5-48f1-8ec3-9ddc0d11c5a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775528911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.775528911
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3404944053
Short name T993
Test name
Test status
Simulation time 8148775306 ps
CPU time 272.13 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:50:30 PM PST 24
Peak memory 1076812 kb
Host smart-96c71e8a-8570-4be3-be6c-9d9e4830878c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404944053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3404944053
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2630768124
Short name T719
Test name
Test status
Simulation time 7058662069 ps
CPU time 6.61 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:37 PM PST 24
Peak memory 207744 kb
Host smart-ee1b8bff-3d5e-46a1-8387-94c006013ec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630768124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2630768124
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_ovf.3356273692
Short name T1151
Test name
Test status
Simulation time 24187651677 ps
CPU time 81.99 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:46:56 PM PST 24
Peak memory 290848 kb
Host smart-0ce7f3d4-8de3-43a8-b2e7-76fed8b68998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356273692 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_tx_ovf.3356273692
Directory /workspace/24.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.2085532408
Short name T861
Test name
Test status
Simulation time 2306034668 ps
CPU time 5.65 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 206508 kb
Host smart-481c4d68-decd-4c09-9510-fbe9287f5656
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085532408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.i2c_target_unexp_stop.2085532408
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.4125731288
Short name T414
Test name
Test status
Simulation time 49767716 ps
CPU time 0.59 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 01:45:39 PM PST 24
Peak memory 202064 kb
Host smart-a55b3aca-c32b-4114-bfaf-0f2b229acda1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125731288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.4125731288
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1450554794
Short name T1097
Test name
Test status
Simulation time 43117524 ps
CPU time 1.31 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:45:45 PM PST 24
Peak memory 211536 kb
Host smart-cf6d47c9-1779-4988-892c-7f3b9776ce65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450554794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1450554794
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3804584257
Short name T981
Test name
Test status
Simulation time 1066514373 ps
CPU time 5.15 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:45:38 PM PST 24
Peak memory 256240 kb
Host smart-45660e7a-6365-4397-b615-46b8f41c2731
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804584257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3804584257
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3126456670
Short name T1181
Test name
Test status
Simulation time 12626316431 ps
CPU time 114.17 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:47:27 PM PST 24
Peak memory 961072 kb
Host smart-7da7b1fb-c218-4a48-85a2-7afe3032b0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126456670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3126456670
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1102522136
Short name T1204
Test name
Test status
Simulation time 18980540698 ps
CPU time 585.49 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 01:55:54 PM PST 24
Peak memory 1340180 kb
Host smart-4acfb703-a20f-41e6-900f-c47e8f06de2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102522136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1102522136
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1324445990
Short name T56
Test name
Test status
Simulation time 102667388 ps
CPU time 0.85 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 01:46:10 PM PST 24
Peak memory 203088 kb
Host smart-37a3ad07-28e3-49d2-b42b-f77aad1d52cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324445990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1324445990
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1970227415
Short name T1183
Test name
Test status
Simulation time 227294720 ps
CPU time 5.1 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:45:38 PM PST 24
Peak memory 203316 kb
Host smart-d284c7e1-52bc-4194-9bd0-42d19796031c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970227415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1970227415
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1202140646
Short name T1081
Test name
Test status
Simulation time 23869281195 ps
CPU time 313.88 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:51:21 PM PST 24
Peak memory 1665512 kb
Host smart-d2a75625-791f-4f75-aea1-a88d6b48860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202140646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1202140646
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3515212341
Short name T398
Test name
Test status
Simulation time 2807571732 ps
CPU time 217.04 seconds
Started Jan 07 01:44:41 PM PST 24
Finished Jan 07 01:48:20 PM PST 24
Peak memory 353924 kb
Host smart-dd7add66-c184-459f-8653-f01433077de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515212341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3515212341
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.72097493
Short name T959
Test name
Test status
Simulation time 29794945 ps
CPU time 0.62 seconds
Started Jan 07 01:45:40 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 202352 kb
Host smart-e7e873c1-dfe1-4d75-8aad-5ede098f4727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72097493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.72097493
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.707359813
Short name T485
Test name
Test status
Simulation time 1453544709 ps
CPU time 18.08 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:45:51 PM PST 24
Peak memory 214036 kb
Host smart-36c35158-f64e-408c-9df4-d47d29393d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707359813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.707359813
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_rx_oversample.3438884018
Short name T1009
Test name
Test status
Simulation time 2864362891 ps
CPU time 110.95 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:47:56 PM PST 24
Peak memory 258776 kb
Host smart-7ca540a0-6ae0-4492-b87c-0c4b7b2216d8
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438884018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_rx_oversample
.3438884018
Directory /workspace/25.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1888374597
Short name T1290
Test name
Test status
Simulation time 76035559889 ps
CPU time 843.3 seconds
Started Jan 07 01:44:41 PM PST 24
Finished Jan 07 01:58:46 PM PST 24
Peak memory 1554984 kb
Host smart-7ab01140-a2bb-40eb-ac2d-fd26b3c80e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888374597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1888374597
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2724604793
Short name T1064
Test name
Test status
Simulation time 658587894 ps
CPU time 10.25 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:45:42 PM PST 24
Peak memory 218940 kb
Host smart-4e44901b-8e90-4ede-be04-82c899a5834d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724604793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2724604793
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2009681620
Short name T373
Test name
Test status
Simulation time 826337481 ps
CPU time 3.04 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:45:05 PM PST 24
Peak memory 203308 kb
Host smart-1d501dcd-c3ab-4645-8102-fe89b5150ba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009681620 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2009681620
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.428623562
Short name T1173
Test name
Test status
Simulation time 10135705637 ps
CPU time 55.56 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:45:39 PM PST 24
Peak memory 506880 kb
Host smart-dacf243e-f718-425d-8ceb-ad8320664e73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428623562 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.428623562
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3249732081
Short name T849
Test name
Test status
Simulation time 10038563935 ps
CPU time 33.39 seconds
Started Jan 07 01:44:43 PM PST 24
Finished Jan 07 01:45:18 PM PST 24
Peak memory 441836 kb
Host smart-c45b859e-eb4d-4b3a-930f-3cfe0f05fe54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249732081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3249732081
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.3425131614
Short name T1259
Test name
Test status
Simulation time 855078502 ps
CPU time 2.15 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:45:35 PM PST 24
Peak memory 203288 kb
Host smart-8ca03a9e-467b-418b-94ff-0253c51f512a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425131614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.3425131614
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3922668326
Short name T626
Test name
Test status
Simulation time 1414916257 ps
CPU time 6.68 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:45:39 PM PST 24
Peak memory 207744 kb
Host smart-bc10cf95-1d40-466d-853f-24e193e3f0c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922668326 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3922668326
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1445755869
Short name T225
Test name
Test status
Simulation time 15233583362 ps
CPU time 47.57 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:45:32 PM PST 24
Peak memory 728836 kb
Host smart-64377127-fbde-454e-944a-27b63525b893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445755869 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1445755869
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.3580940674
Short name T454
Test name
Test status
Simulation time 1809683078 ps
CPU time 4.91 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 01:45:44 PM PST 24
Peak memory 203200 kb
Host smart-6a8277d8-0815-4f13-ba7a-371192b141aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580940674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.3580940674
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2276603177
Short name T694
Test name
Test status
Simulation time 3968631166 ps
CPU time 17.21 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 203900 kb
Host smart-db5a7257-049b-4c14-809d-1cb011120b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276603177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2276603177
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3770080562
Short name T461
Test name
Test status
Simulation time 17009936776 ps
CPU time 22.54 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 351972 kb
Host smart-ddaf647e-60ef-48c1-aeed-22a0dc67f9a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770080562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3770080562
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.1327248276
Short name T283
Test name
Test status
Simulation time 2122601812 ps
CPU time 8.65 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:29 PM PST 24
Peak memory 214724 kb
Host smart-3661bada-5cf0-4942-ab05-a20845f5e3a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327248276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.1327248276
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_ovf.3812420076
Short name T270
Test name
Test status
Simulation time 10046699199 ps
CPU time 45.62 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:46:16 PM PST 24
Peak memory 230424 kb
Host smart-c1ff6a11-07cd-4bbe-8ecf-5740956e8f5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812420076 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_tx_ovf.3812420076
Directory /workspace/25.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.2833057088
Short name T320
Test name
Test status
Simulation time 1747392413 ps
CPU time 7.4 seconds
Started Jan 07 01:44:44 PM PST 24
Finished Jan 07 01:44:53 PM PST 24
Peak memory 206508 kb
Host smart-c49fd871-0d20-4950-8208-f4de1eb7f00f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833057088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.2833057088
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3194807282
Short name T565
Test name
Test status
Simulation time 47766791 ps
CPU time 0.59 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:45:46 PM PST 24
Peak memory 202136 kb
Host smart-1689c8a1-6c2f-4999-bd77-2989a909d79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194807282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3194807282
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1596636181
Short name T442
Test name
Test status
Simulation time 95606137 ps
CPU time 1.99 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 211520 kb
Host smart-7b9be03f-7088-4926-90e4-c8e7f0c914d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596636181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1596636181
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2604159168
Short name T479
Test name
Test status
Simulation time 268099663 ps
CPU time 13.39 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 255168 kb
Host smart-3301555c-cb6e-4efe-8cfb-d9d7500ca724
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604159168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2604159168
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1340626091
Short name T1291
Test name
Test status
Simulation time 3252543867 ps
CPU time 280.37 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 01:50:30 PM PST 24
Peak memory 979424 kb
Host smart-e0a28c7e-7e98-424c-89ec-bdd69b6bc46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340626091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1340626091
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3789048257
Short name T294
Test name
Test status
Simulation time 54383701873 ps
CPU time 1073.86 seconds
Started Jan 07 01:44:56 PM PST 24
Finished Jan 07 02:02:55 PM PST 24
Peak memory 1862460 kb
Host smart-031c95a6-0287-421e-a7ff-53af5270a90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789048257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3789048257
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2776823667
Short name T545
Test name
Test status
Simulation time 163934632 ps
CPU time 1.07 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:13 PM PST 24
Peak memory 203352 kb
Host smart-18b1d88f-145c-4a25-a73f-dd995e265668
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776823667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2776823667
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2985406568
Short name T1157
Test name
Test status
Simulation time 173429899 ps
CPU time 10.18 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:17 PM PST 24
Peak memory 234828 kb
Host smart-4e82f497-652b-44ec-8801-1ffd75e06f3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985406568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2985406568
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1718383546
Short name T1004
Test name
Test status
Simulation time 2157328273 ps
CPU time 72.2 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 342024 kb
Host smart-33866d93-21fb-4317-b60c-85fd5cf87768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718383546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1718383546
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.1485612641
Short name T380
Test name
Test status
Simulation time 142640927 ps
CPU time 0.64 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:16 PM PST 24
Peak memory 202460 kb
Host smart-5dcd0f60-8f48-4539-8235-166ddab23826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485612641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1485612641
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_rx_oversample.1036545062
Short name T176
Test name
Test status
Simulation time 16234220863 ps
CPU time 226.07 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:48:53 PM PST 24
Peak memory 295468 kb
Host smart-c3c60914-417a-4541-af79-bc9aadf73371
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036545062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_rx_oversample
.1036545062
Directory /workspace/26.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3753599211
Short name T758
Test name
Test status
Simulation time 15290928909 ps
CPU time 75.15 seconds
Started Jan 07 01:44:56 PM PST 24
Finished Jan 07 01:46:15 PM PST 24
Peak memory 311936 kb
Host smart-93536856-b8c5-4a6b-9bd2-59ba89abd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753599211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3753599211
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2905681936
Short name T138
Test name
Test status
Simulation time 200322434479 ps
CPU time 1992.05 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 02:18:17 PM PST 24
Peak memory 734524 kb
Host smart-68d610dc-61df-4734-b0c3-009c51f97991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905681936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2905681936
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all_with_rand_reset.1660948020
Short name T35
Test name
Test status
Simulation time 9843360353 ps
CPU time 229.48 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 01:49:40 PM PST 24
Peak memory 460980 kb
Host smart-37720295-a06f-4689-b904-095f88465d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660948020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.i2c_host_stress_all_with_rand_reset.1660948020
Directory /workspace/26.i2c_host_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3765783029
Short name T1352
Test name
Test status
Simulation time 2479060316 ps
CPU time 8.94 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:26 PM PST 24
Peak memory 219732 kb
Host smart-f8f66ad7-a88a-4838-83df-c052a10558fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765783029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3765783029
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3641417563
Short name T1121
Test name
Test status
Simulation time 4551165030 ps
CPU time 4.23 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:04 PM PST 24
Peak memory 203436 kb
Host smart-867d182a-3a00-4ecb-a6f8-dbcb84fe9ce0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641417563 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3641417563
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1389706463
Short name T503
Test name
Test status
Simulation time 10107639006 ps
CPU time 9.5 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:45:53 PM PST 24
Peak memory 242968 kb
Host smart-c609f10b-fdff-41eb-b32c-b03b48fb2e08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389706463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1389706463
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.2051883105
Short name T994
Test name
Test status
Simulation time 10033201741 ps
CPU time 61.69 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:47:07 PM PST 24
Peak memory 578628 kb
Host smart-97cc2690-37e2-47f6-8670-a2b05e0a8bbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051883105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.2051883105
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3453095221
Short name T589
Test name
Test status
Simulation time 604096640 ps
CPU time 2.83 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:45:57 PM PST 24
Peak memory 203320 kb
Host smart-8d47e7b2-9d5f-44b8-88d5-61c5f41ccfb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453095221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3453095221
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1462628725
Short name T703
Test name
Test status
Simulation time 1606537586 ps
CPU time 4.01 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:36 PM PST 24
Peak memory 203348 kb
Host smart-b8d9cf68-ef01-483a-a419-e90d77d3e37e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462628725 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1462628725
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3917091060
Short name T1163
Test name
Test status
Simulation time 22208891739 ps
CPU time 373.13 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:52:28 PM PST 24
Peak memory 2696884 kb
Host smart-fd71fc0b-dcaf-4ea5-91c1-03090b64708b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917091060 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3917091060
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.4157110495
Short name T202
Test name
Test status
Simulation time 626246196 ps
CPU time 3.68 seconds
Started Jan 07 01:45:45 PM PST 24
Finished Jan 07 01:46:28 PM PST 24
Peak memory 203324 kb
Host smart-544a6b1e-d71b-45f5-9e45-1e073b389d40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157110495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.4157110495
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4082465939
Short name T857
Test name
Test status
Simulation time 1014814160 ps
CPU time 12.55 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:25 PM PST 24
Peak memory 203288 kb
Host smart-f15f84ab-a0d4-4b48-8d91-ed8d5c92be77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082465939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4082465939
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.1774490692
Short name T998
Test name
Test status
Simulation time 62474140145 ps
CPU time 24.74 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 219720 kb
Host smart-29046f4d-e5b2-4b2a-a3dc-94e49705721c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774490692 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.1774490692
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2307846722
Short name T492
Test name
Test status
Simulation time 3230463143 ps
CPU time 25.03 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 213260 kb
Host smart-2c922eaa-6447-4453-b01d-1bc029b69462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307846722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2307846722
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.19176798
Short name T538
Test name
Test status
Simulation time 26506762909 ps
CPU time 99.68 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:46:58 PM PST 24
Peak memory 1493568 kb
Host smart-285030b5-2d4f-4ded-9d31-14d2393bebef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19176798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stress_wr.19176798
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2249799729
Short name T1365
Test name
Test status
Simulation time 3679950169 ps
CPU time 6.98 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:45:43 PM PST 24
Peak memory 203304 kb
Host smart-b6f21905-4790-415f-9c49-7e2566d8d688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249799729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2249799729
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_ovf.3938999801
Short name T1092
Test name
Test status
Simulation time 2419122166 ps
CPU time 38.56 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:46:25 PM PST 24
Peak memory 220536 kb
Host smart-67d849f3-de67-4c75-ad4e-42041f7f8169
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938999801 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_tx_ovf.3938999801
Directory /workspace/26.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.3978819542
Short name T1343
Test name
Test status
Simulation time 2782082751 ps
CPU time 6.17 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:48 PM PST 24
Peak memory 203416 kb
Host smart-dcfcb6da-8a17-49ca-8004-1d4dd929ca0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978819542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.3978819542
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.679020134
Short name T1003
Test name
Test status
Simulation time 60456263 ps
CPU time 0.6 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:41 PM PST 24
Peak memory 202268 kb
Host smart-a110bcbb-7708-4e83-a077-08ef7e406094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679020134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.679020134
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.4173105154
Short name T806
Test name
Test status
Simulation time 33120212 ps
CPU time 1.19 seconds
Started Jan 07 01:44:49 PM PST 24
Finished Jan 07 01:44:52 PM PST 24
Peak memory 213624 kb
Host smart-616bdece-44a3-4502-afc7-b606fc2dd6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173105154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.4173105154
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.242461026
Short name T1143
Test name
Test status
Simulation time 1635926393 ps
CPU time 9.03 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:46:15 PM PST 24
Peak memory 289228 kb
Host smart-28ebbb40-f103-40b9-8848-c48213e2e67a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242461026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empt
y.242461026
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.2776451974
Short name T1336
Test name
Test status
Simulation time 12192085128 ps
CPU time 120.8 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:47:59 PM PST 24
Peak memory 523896 kb
Host smart-d9db9314-7ac8-40de-ba3e-b22abd1ac9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776451974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2776451974
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1865397034
Short name T307
Test name
Test status
Simulation time 114111694 ps
CPU time 0.94 seconds
Started Jan 07 01:45:38 PM PST 24
Finished Jan 07 01:46:19 PM PST 24
Peak memory 203188 kb
Host smart-d49a5ab5-7eba-4466-bd6a-aaab855ad608
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865397034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1865397034
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.713796128
Short name T1229
Test name
Test status
Simulation time 245260893 ps
CPU time 5.9 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:45:44 PM PST 24
Peak memory 203340 kb
Host smart-545054ec-8538-419e-9de7-8cafbfc64bf1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713796128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
713796128
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.3293821926
Short name T1224
Test name
Test status
Simulation time 2456795357 ps
CPU time 72.07 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 309336 kb
Host smart-4156c315-368a-4cfd-bcb3-c3abe5be0757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293821926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.3293821926
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1497248794
Short name T151
Test name
Test status
Simulation time 20610580 ps
CPU time 0.64 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:45:45 PM PST 24
Peak memory 202404 kb
Host smart-94cd0f86-97f7-464c-8518-ba82ec1e734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497248794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1497248794
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2687644354
Short name T8
Test name
Test status
Simulation time 5634246770 ps
CPU time 101.24 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:46:25 PM PST 24
Peak memory 229876 kb
Host smart-9a2c044a-3b11-4553-8958-500b504cbfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687644354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2687644354
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_rx_oversample.613053268
Short name T569
Test name
Test status
Simulation time 4912711956 ps
CPU time 60.29 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:46:45 PM PST 24
Peak memory 283304 kb
Host smart-069c57e7-72dc-4521-8cd3-82959fca88e5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613053268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_rx_oversample.
613053268
Directory /workspace/27.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3535693510
Short name T780
Test name
Test status
Simulation time 11805153410 ps
CPU time 92.16 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:47:46 PM PST 24
Peak memory 250640 kb
Host smart-f85dbd38-a5e9-4cf3-9595-0a5058877826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535693510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3535693510
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1180597576
Short name T814
Test name
Test status
Simulation time 1130822655 ps
CPU time 19.2 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 01:45:58 PM PST 24
Peak memory 214080 kb
Host smart-2e5fb559-69a4-4c02-aecc-bc37b3d5e300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180597576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1180597576
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2499931618
Short name T747
Test name
Test status
Simulation time 6085436535 ps
CPU time 4.82 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:45:45 PM PST 24
Peak memory 203424 kb
Host smart-11ee634d-c1c4-496c-b680-7846ab9a0eae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499931618 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2499931618
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1290063618
Short name T1145
Test name
Test status
Simulation time 10709938512 ps
CPU time 11.78 seconds
Started Jan 07 01:44:56 PM PST 24
Finished Jan 07 01:45:11 PM PST 24
Peak memory 257692 kb
Host smart-8d5a77a4-1f5f-46f0-bace-6a9cdd34899c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290063618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1290063618
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.712622880
Short name T1318
Test name
Test status
Simulation time 526534303 ps
CPU time 2.62 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:45:41 PM PST 24
Peak memory 203240 kb
Host smart-4320df2d-be66-414d-9111-d9e7255498f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712622880 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_hrst.712622880
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.1522820746
Short name T1142
Test name
Test status
Simulation time 2626079666 ps
CPU time 5.29 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:36 PM PST 24
Peak memory 203284 kb
Host smart-acbcb684-41d6-423b-9474-e2bbf66e99c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522820746 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.1522820746
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1945405731
Short name T619
Test name
Test status
Simulation time 15633853823 ps
CPU time 169.25 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:48:03 PM PST 24
Peak memory 1833436 kb
Host smart-b9c540ab-1f9f-404e-a15c-dbd4d62f39a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945405731 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1945405731
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.292235388
Short name T1242
Test name
Test status
Simulation time 10978424473 ps
CPU time 4.25 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:45:44 PM PST 24
Peak memory 203400 kb
Host smart-4d78d6a2-344e-4c43-a61a-0349af2afd9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292235388 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_perf.292235388
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3307064832
Short name T238
Test name
Test status
Simulation time 752224596 ps
CPU time 19.02 seconds
Started Jan 07 01:44:43 PM PST 24
Finished Jan 07 01:45:05 PM PST 24
Peak memory 203364 kb
Host smart-c7f2f79d-d5e3-4493-a591-741f31242597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307064832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3307064832
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.521787599
Short name T399
Test name
Test status
Simulation time 60439021731 ps
CPU time 283.71 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:49:56 PM PST 24
Peak memory 473352 kb
Host smart-4ce62d93-d82c-432a-a351-e7af8650b798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521787599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_target_stress_all.521787599
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1607739499
Short name T561
Test name
Test status
Simulation time 2233203639 ps
CPU time 19.26 seconds
Started Jan 07 01:44:44 PM PST 24
Finished Jan 07 01:45:05 PM PST 24
Peak memory 211396 kb
Host smart-f9fde738-ca1e-4c2b-b2ec-0dc40fe76ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607739499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1607739499
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3802849828
Short name T96
Test name
Test status
Simulation time 2169492713 ps
CPU time 7.9 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:46:04 PM PST 24
Peak memory 203388 kb
Host smart-a1eaf5d2-8d5d-4225-895f-a7dcd55c3dbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802849828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3802849828
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_ovf.4133301105
Short name T1220
Test name
Test status
Simulation time 15194706244 ps
CPU time 338 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:51:20 PM PST 24
Peak memory 548300 kb
Host smart-8fc3cb0a-0b5d-4bca-9557-59b7d1fdf0a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133301105 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_tx_ovf.4133301105
Directory /workspace/27.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3086410251
Short name T1374
Test name
Test status
Simulation time 121965285 ps
CPU time 0.6 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:44:45 PM PST 24
Peak memory 202216 kb
Host smart-652c87c8-93ab-412a-b95e-66c160a3d5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086410251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3086410251
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3358330063
Short name T595
Test name
Test status
Simulation time 314291454 ps
CPU time 1.12 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 211500 kb
Host smart-bbb2a9a2-8a5a-457b-a379-f462a8b06a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358330063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3358330063
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.495315351
Short name T233
Test name
Test status
Simulation time 9203090853 ps
CPU time 186 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:49:10 PM PST 24
Peak memory 777444 kb
Host smart-c2525342-166a-4cb5-8bc8-39d85a505b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495315351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.495315351
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.416372781
Short name T453
Test name
Test status
Simulation time 55867043365 ps
CPU time 392.81 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:52:11 PM PST 24
Peak memory 1630964 kb
Host smart-f7f7ca47-a776-4bd1-ac00-48435642d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416372781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.416372781
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.794344332
Short name T1167
Test name
Test status
Simulation time 748188054 ps
CPU time 0.78 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:45:55 PM PST 24
Peak memory 202996 kb
Host smart-06c41f5b-5ae4-41a5-9b7f-d1f426365348
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794344332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.794344332
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.4136321851
Short name T1131
Test name
Test status
Simulation time 733613560 ps
CPU time 10.93 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 203348 kb
Host smart-a04a78e6-64b3-4d24-99df-f4bfdc0ec216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136321851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.4136321851
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3700991736
Short name T391
Test name
Test status
Simulation time 15031936837 ps
CPU time 792.66 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:59:15 PM PST 24
Peak memory 1808744 kb
Host smart-375b417a-2fef-4fe4-bb21-0bab33248bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700991736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3700991736
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.575281078
Short name T1099
Test name
Test status
Simulation time 12037451342 ps
CPU time 123.55 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:47:08 PM PST 24
Peak memory 444084 kb
Host smart-24b61881-7f43-4c08-a8f9-1aa28d7184c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575281078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.575281078
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.4124854864
Short name T128
Test name
Test status
Simulation time 50707441 ps
CPU time 0.67 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:45:59 PM PST 24
Peak memory 202304 kb
Host smart-2ee05948-5cd2-44f4-a9cc-475f4473d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124854864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.4124854864
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.4063650783
Short name T1146
Test name
Test status
Simulation time 25827183803 ps
CPU time 217 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:49:23 PM PST 24
Peak memory 246112 kb
Host smart-8bb8ab4d-c3a1-4d04-8d3d-839924c30a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063650783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4063650783
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_rx_oversample.3357583298
Short name T400
Test name
Test status
Simulation time 1612575252 ps
CPU time 102.08 seconds
Started Jan 07 01:45:22 PM PST 24
Finished Jan 07 01:47:38 PM PST 24
Peak memory 249980 kb
Host smart-191ab951-3512-43f8-b21f-da07d74165e1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357583298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_rx_oversample
.3357583298
Directory /workspace/28.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.4269028892
Short name T713
Test name
Test status
Simulation time 2349813992 ps
CPU time 125.24 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 01:47:44 PM PST 24
Peak memory 235960 kb
Host smart-6ac3826a-eba6-454b-84d2-450b8ea0dcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269028892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.4269028892
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3320719601
Short name T711
Test name
Test status
Simulation time 69853208656 ps
CPU time 1673.08 seconds
Started Jan 07 01:45:40 PM PST 24
Finished Jan 07 02:14:14 PM PST 24
Peak memory 2840344 kb
Host smart-26a56ef5-ff1e-4770-bcf3-bdcc40e427aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320719601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3320719601
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.4062097137
Short name T1195
Test name
Test status
Simulation time 490606555 ps
CPU time 21.54 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 211468 kb
Host smart-adebd136-d30a-4acb-9bf5-5690120ed7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062097137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.4062097137
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.567931539
Short name T524
Test name
Test status
Simulation time 1292704369 ps
CPU time 2.62 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:45:35 PM PST 24
Peak memory 203380 kb
Host smart-e8fe95c8-611c-4e6b-a1f4-e227b64d3e09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567931539 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.567931539
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2118233040
Short name T559
Test name
Test status
Simulation time 10273263974 ps
CPU time 27.44 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:46:11 PM PST 24
Peak memory 374852 kb
Host smart-cac1544a-c1b8-4b04-b84e-71c9f0f17bd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118233040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2118233040
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2598774152
Short name T1372
Test name
Test status
Simulation time 272438278 ps
CPU time 1.63 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:45:40 PM PST 24
Peak memory 203344 kb
Host smart-004b94a8-0bc0-4136-8db8-3854afccfcc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598774152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2598774152
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2589461645
Short name T1040
Test name
Test status
Simulation time 9372473817 ps
CPU time 6.14 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 01:46:16 PM PST 24
Peak memory 203376 kb
Host smart-fd9b05a3-533a-44ae-a36f-f5bd77abb0ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589461645 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2589461645
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1907283050
Short name T1292
Test name
Test status
Simulation time 10968368310 ps
CPU time 31.46 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:46:37 PM PST 24
Peak memory 692728 kb
Host smart-3ab495a1-f6da-45d9-9afd-037bce3394e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907283050 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1907283050
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.3280701609
Short name T724
Test name
Test status
Simulation time 5329816539 ps
CPU time 4.67 seconds
Started Jan 07 01:45:41 PM PST 24
Finished Jan 07 01:46:26 PM PST 24
Peak memory 203644 kb
Host smart-313c4293-34c0-461e-8d28-af8c77c4a941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280701609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.3280701609
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2948691052
Short name T889
Test name
Test status
Simulation time 1544334234 ps
CPU time 40.12 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 01:46:48 PM PST 24
Peak memory 203196 kb
Host smart-27d3a71f-413d-46d3-837c-40a7ddd24e66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948691052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2948691052
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2951284012
Short name T437
Test name
Test status
Simulation time 4507158251 ps
CPU time 18.61 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 208876 kb
Host smart-cf196ecc-069c-4bad-83f2-fc499767fe8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951284012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2951284012
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2682199001
Short name T973
Test name
Test status
Simulation time 33757940049 ps
CPU time 1484.11 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 02:10:47 PM PST 24
Peak memory 7177716 kb
Host smart-22e80056-a0d4-4bde-9c43-8b832c03221d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682199001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2682199001
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1880810960
Short name T377
Test name
Test status
Simulation time 7705094746 ps
CPU time 7.62 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:15 PM PST 24
Peak memory 215376 kb
Host smart-81d654bd-cba1-4118-83b6-1d4032053b25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880810960 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1880810960
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_ovf.118885598
Short name T621
Test name
Test status
Simulation time 8739539319 ps
CPU time 116.89 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:47:57 PM PST 24
Peak memory 369664 kb
Host smart-3ed25385-92ca-4bd0-9cce-8ceb969ce8c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118885598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_tx_ovf.118885598
Directory /workspace/28.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.388739653
Short name T1010
Test name
Test status
Simulation time 10287478303 ps
CPU time 6.65 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 212820 kb
Host smart-f7168bc4-b51b-4722-8e18-d4dadcc970ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388739653 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_unexp_stop.388739653
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.195330035
Short name T1367
Test name
Test status
Simulation time 14959268 ps
CPU time 0.61 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:21 PM PST 24
Peak memory 202112 kb
Host smart-bed6ce0e-f011-4aa4-aed9-0d9ec8a2754b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195330035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.195330035
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2298095606
Short name T1013
Test name
Test status
Simulation time 50040230 ps
CPU time 1.42 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:45:40 PM PST 24
Peak memory 211536 kb
Host smart-3bd44b99-2054-48fe-824c-fb3e10755d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298095606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2298095606
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1848233435
Short name T657
Test name
Test status
Simulation time 1913665922 ps
CPU time 12.24 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:23 PM PST 24
Peak memory 317720 kb
Host smart-726a2613-d823-443c-b1f8-112e85ea64d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848233435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1848233435
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1708893411
Short name T341
Test name
Test status
Simulation time 2814560620 ps
CPU time 109.11 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:47:10 PM PST 24
Peak memory 850736 kb
Host smart-b0164cf7-428c-43e1-ac93-d5b43f78dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708893411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1708893411
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.4138330058
Short name T1274
Test name
Test status
Simulation time 45752684157 ps
CPU time 444.68 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:52:30 PM PST 24
Peak memory 1685916 kb
Host smart-b8fc29fc-3893-4017-9e43-64e67be36065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138330058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.4138330058
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1901384054
Short name T878
Test name
Test status
Simulation time 397956474 ps
CPU time 0.86 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:45:30 PM PST 24
Peak memory 203184 kb
Host smart-600fa189-9249-418b-bc6a-6161db6c3933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901384054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1901384054
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.1643548352
Short name T1067
Test name
Test status
Simulation time 361980571 ps
CPU time 4.26 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:45:47 PM PST 24
Peak memory 233444 kb
Host smart-cb15d9bd-8e8b-4a37-832e-1fba477a8601
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643548352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.1643548352
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1116290144
Short name T1048
Test name
Test status
Simulation time 12656975612 ps
CPU time 727.33 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:57:46 PM PST 24
Peak memory 1705928 kb
Host smart-b3c9f2f5-f5f8-489e-b727-2fa3affc43fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116290144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1116290144
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1572715640
Short name T480
Test name
Test status
Simulation time 3555554875 ps
CPU time 36.97 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:46:15 PM PST 24
Peak memory 274408 kb
Host smart-13c4cbc4-57b6-4477-ba42-3c2b082eb5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572715640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1572715640
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3412514248
Short name T599
Test name
Test status
Simulation time 24904970 ps
CPU time 0.64 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:45:33 PM PST 24
Peak memory 202480 kb
Host smart-f09cfd2d-1e35-4a06-840d-bc77b6bc2832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412514248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3412514248
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.936004109
Short name T1194
Test name
Test status
Simulation time 50194588174 ps
CPU time 262 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:50:16 PM PST 24
Peak memory 331948 kb
Host smart-0d3d4aac-3c73-40ef-b64b-8d6f68700fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936004109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.936004109
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_rx_oversample.71231999
Short name T175
Test name
Test status
Simulation time 4801384379 ps
CPU time 147.93 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 01:48:08 PM PST 24
Peak memory 253004 kb
Host smart-bbac0ced-656a-4310-a279-ccf29c15d9bf
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71231999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_rx_oversample.71231999
Directory /workspace/29.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1907948625
Short name T582
Test name
Test status
Simulation time 7720777523 ps
CPU time 110.93 seconds
Started Jan 07 01:44:42 PM PST 24
Finished Jan 07 01:46:34 PM PST 24
Peak memory 244248 kb
Host smart-f432d77d-c972-4943-902f-807aea329425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907948625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1907948625
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.1284810662
Short name T184
Test name
Test status
Simulation time 67829126667 ps
CPU time 2332.66 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 02:24:07 PM PST 24
Peak memory 2431960 kb
Host smart-a49afed9-5402-434a-b37c-1af3cb4a914e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284810662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1284810662
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3675470828
Short name T1332
Test name
Test status
Simulation time 616303710 ps
CPU time 26.54 seconds
Started Jan 07 01:45:12 PM PST 24
Finished Jan 07 01:46:07 PM PST 24
Peak memory 211480 kb
Host smart-d947b22a-3a12-4d72-b5f8-7a7c105e6ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675470828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3675470828
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2850503223
Short name T970
Test name
Test status
Simulation time 3946776535 ps
CPU time 3.84 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:30 PM PST 24
Peak memory 203472 kb
Host smart-d568d863-87b4-4ff8-9d38-d55e90486ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850503223 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2850503223
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.676405097
Short name T210
Test name
Test status
Simulation time 10166323275 ps
CPU time 12.66 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:25 PM PST 24
Peak memory 287232 kb
Host smart-52e0faf7-4a04-4dca-900d-601e233e7976
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676405097 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.676405097
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3752801531
Short name T468
Test name
Test status
Simulation time 10314180896 ps
CPU time 12.03 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 299072 kb
Host smart-803eb295-514e-4b1b-9113-e529100eafe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752801531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3752801531
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2707951279
Short name T1234
Test name
Test status
Simulation time 11834387554 ps
CPU time 4.77 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:35 PM PST 24
Peak memory 203336 kb
Host smart-61a3fd00-0e3c-4885-9a98-e9c719ab3350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707951279 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2707951279
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2228326408
Short name T734
Test name
Test status
Simulation time 4371399316 ps
CPU time 15.48 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 500620 kb
Host smart-197f21aa-0548-40d2-bcc9-b679efc402e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228326408 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2228326408
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.3535342025
Short name T1337
Test name
Test status
Simulation time 879355493 ps
CPU time 2.76 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:45:36 PM PST 24
Peak memory 203320 kb
Host smart-d5c856d6-7fcd-4940-9288-e94d0e308bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535342025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.3535342025
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.64019761
Short name T1327
Test name
Test status
Simulation time 1045387616 ps
CPU time 11.57 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:45:14 PM PST 24
Peak memory 203332 kb
Host smart-ac9d630c-bda3-46d3-8611-2a6107920c8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64019761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_targ
et_smoke.64019761
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.3429470345
Short name T362
Test name
Test status
Simulation time 45466482849 ps
CPU time 2284.33 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 02:23:07 PM PST 24
Peak memory 8081236 kb
Host smart-4f8f3918-9336-48cd-b42b-8846e9f9cf1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429470345 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.3429470345
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.2271116922
Short name T531
Test name
Test status
Simulation time 18410454675 ps
CPU time 97.54 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:46:56 PM PST 24
Peak memory 1168516 kb
Host smart-549b553c-09cc-4a2e-acbe-275abf72bc49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271116922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.2271116922
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.4168078967
Short name T521
Test name
Test status
Simulation time 1853258712 ps
CPU time 7.41 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:45:46 PM PST 24
Peak memory 214740 kb
Host smart-6d478647-d2cc-42dc-8cce-60daf6872ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168078967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.4168078967
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1203008169
Short name T358
Test name
Test status
Simulation time 42762844 ps
CPU time 0.58 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:43:32 PM PST 24
Peak memory 202172 kb
Host smart-f97e3d9d-245b-43ff-95c1-0cf8486047ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203008169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1203008169
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.2841548003
Short name T105
Test name
Test status
Simulation time 155065659 ps
CPU time 1.29 seconds
Started Jan 07 01:42:48 PM PST 24
Finished Jan 07 01:43:10 PM PST 24
Peak memory 203316 kb
Host smart-beee81fb-9c91-49c6-81c5-d1c698d4274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841548003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2841548003
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2052754935
Short name T411
Test name
Test status
Simulation time 2121513756 ps
CPU time 9.23 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 300956 kb
Host smart-92a48934-b2a8-4dba-9c54-a288ff4ceac3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052754935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2052754935
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2489989624
Short name T250
Test name
Test status
Simulation time 4936855320 ps
CPU time 315.94 seconds
Started Jan 07 01:43:11 PM PST 24
Finished Jan 07 01:48:40 PM PST 24
Peak memory 1041840 kb
Host smart-5c414fa7-2908-4502-b1d8-3adbe4ec157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489989624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2489989624
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2960663358
Short name T381
Test name
Test status
Simulation time 22001520356 ps
CPU time 162.93 seconds
Started Jan 07 01:42:53 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 1084064 kb
Host smart-c49f4624-6066-420a-82f2-3754ce6fc4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960663358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2960663358
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3620573759
Short name T539
Test name
Test status
Simulation time 1062736522 ps
CPU time 0.92 seconds
Started Jan 07 01:43:06 PM PST 24
Finished Jan 07 01:43:19 PM PST 24
Peak memory 203200 kb
Host smart-b02c8b86-2085-4dc3-bf45-3a61d32687e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620573759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3620573759
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2645560011
Short name T1222
Test name
Test status
Simulation time 7633666838 ps
CPU time 378.62 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:50:04 PM PST 24
Peak memory 1154468 kb
Host smart-3cc403b7-1d07-41c9-9759-a68d09cfe371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645560011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2645560011
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3137655601
Short name T899
Test name
Test status
Simulation time 21936280851 ps
CPU time 75.33 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:44:53 PM PST 24
Peak memory 310228 kb
Host smart-afcec75a-4733-4645-a43b-048fbae51de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137655601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3137655601
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.1595718768
Short name T131
Test name
Test status
Simulation time 52379408 ps
CPU time 0.62 seconds
Started Jan 07 01:42:46 PM PST 24
Finished Jan 07 01:43:07 PM PST 24
Peak memory 202376 kb
Host smart-d9cafc01-e5ad-489a-8156-46477f061a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595718768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1595718768
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2368111307
Short name T848
Test name
Test status
Simulation time 53052908783 ps
CPU time 733.97 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:55:50 PM PST 24
Peak memory 495320 kb
Host smart-fcd1f65f-e976-4cac-8b81-656e7b7ecc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368111307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2368111307
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_rx_oversample.3238658274
Short name T1056
Test name
Test status
Simulation time 13649051860 ps
CPU time 262.47 seconds
Started Jan 07 01:42:52 PM PST 24
Finished Jan 07 01:47:32 PM PST 24
Peak memory 280804 kb
Host smart-96b4d4cb-f159-4f1a-ad8d-86d26428fda7
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238658274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_rx_oversample.
3238658274
Directory /workspace/3.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.526288325
Short name T550
Test name
Test status
Simulation time 2061242404 ps
CPU time 117.21 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:45:36 PM PST 24
Peak memory 268448 kb
Host smart-c605c71b-effe-470c-b33a-9c47dd27c597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526288325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.526288325
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.2574799145
Short name T149
Test name
Test status
Simulation time 84911607334 ps
CPU time 2422.7 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 02:23:48 PM PST 24
Peak memory 4432608 kb
Host smart-baa4103d-8d71-49b2-97a7-9c47661a52df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574799145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.2574799145
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.363445250
Short name T254
Test name
Test status
Simulation time 1595000124 ps
CPU time 5.47 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:43:50 PM PST 24
Peak memory 211456 kb
Host smart-a8d4314b-4e6d-4f21-bded-b81dc83c5cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363445250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.363445250
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1145967
Short name T78
Test name
Test status
Simulation time 73484262 ps
CPU time 0.83 seconds
Started Jan 07 01:43:00 PM PST 24
Finished Jan 07 01:43:16 PM PST 24
Peak memory 219920 kb
Host smart-728bb9a3-cb9b-4b3d-963d-ce4f7faf751b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1145967
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.8965187
Short name T535
Test name
Test status
Simulation time 6784830603 ps
CPU time 5.97 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:39 PM PST 24
Peak memory 203872 kb
Host smart-46523805-1dcb-4990-83d3-5dbab859ca7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8965187 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_bad_addr.8965187
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1293841497
Short name T682
Test name
Test status
Simulation time 10457066915 ps
CPU time 10.66 seconds
Started Jan 07 01:42:40 PM PST 24
Finished Jan 07 01:43:12 PM PST 24
Peak memory 276468 kb
Host smart-c3c2ce42-c34f-4024-9da9-7fd8e3629188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293841497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1293841497
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3043149943
Short name T324
Test name
Test status
Simulation time 10346593076 ps
CPU time 16.15 seconds
Started Jan 07 01:42:47 PM PST 24
Finished Jan 07 01:43:23 PM PST 24
Peak memory 311972 kb
Host smart-305e5eb4-0788-46a6-9eaa-2e59cfab7a7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043149943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3043149943
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2912171851
Short name T882
Test name
Test status
Simulation time 3572285420 ps
CPU time 2.65 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 203444 kb
Host smart-20c82902-2452-4bb8-a6e1-03bc9f716ac5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912171851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2912171851
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2005554140
Short name T1025
Test name
Test status
Simulation time 3750589967 ps
CPU time 3.98 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:43:33 PM PST 24
Peak memory 203388 kb
Host smart-48cd4505-a08e-427c-bfc2-0375e9a9b74d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005554140 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2005554140
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2179580564
Short name T1098
Test name
Test status
Simulation time 8353777638 ps
CPU time 146.54 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:45:57 PM PST 24
Peak memory 1802084 kb
Host smart-5751de15-c14d-4802-ba11-46d80f24c16f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179580564 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2179580564
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.2297063712
Short name T1106
Test name
Test status
Simulation time 1421681901 ps
CPU time 4.41 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 01:43:43 PM PST 24
Peak memory 203104 kb
Host smart-d0a6d05f-6efa-48a9-8e27-c56d886c0d08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297063712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.2297063712
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3345252673
Short name T265
Test name
Test status
Simulation time 1344393602 ps
CPU time 17.11 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 203268 kb
Host smart-55f7a314-f249-4360-af94-243711069d86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345252673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3345252673
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.3586188051
Short name T1012
Test name
Test status
Simulation time 82681519843 ps
CPU time 286.85 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 01:48:12 PM PST 24
Peak memory 368640 kb
Host smart-d2c142c0-1bed-4629-81b0-7055d6843b41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586188051 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.3586188051
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.527008533
Short name T750
Test name
Test status
Simulation time 3839784022 ps
CPU time 66.1 seconds
Started Jan 07 01:43:06 PM PST 24
Finished Jan 07 01:44:24 PM PST 24
Peak memory 203892 kb
Host smart-95861c0d-6fec-42a8-a0f2-d8f393ad662a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527008533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.527008533
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1297331168
Short name T862
Test name
Test status
Simulation time 46113233528 ps
CPU time 303.3 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:48:40 PM PST 24
Peak memory 2783844 kb
Host smart-2d61b2b4-c917-4401-9af2-fdf497b6000d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297331168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1297331168
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1459438614
Short name T876
Test name
Test status
Simulation time 25383360183 ps
CPU time 2130.35 seconds
Started Jan 07 01:42:58 PM PST 24
Finished Jan 07 02:18:45 PM PST 24
Peak memory 6253308 kb
Host smart-1a50d5b8-7818-4bb4-b7b3-d97894258cbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459438614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1459438614
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.892661281
Short name T532
Test name
Test status
Simulation time 4809778489 ps
CPU time 6.75 seconds
Started Jan 07 01:42:56 PM PST 24
Finished Jan 07 01:43:19 PM PST 24
Peak memory 203364 kb
Host smart-66d05179-be1d-4de2-bcf5-cf8375848e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892661281 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.892661281
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_ovf.1259132373
Short name T1192
Test name
Test status
Simulation time 16042537782 ps
CPU time 45.92 seconds
Started Jan 07 01:42:47 PM PST 24
Finished Jan 07 01:43:54 PM PST 24
Peak memory 258224 kb
Host smart-1738cc79-d3ee-4e87-8825-5cff6f73daab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259132373 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_tx_ovf.1259132373
Directory /workspace/3.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/30.i2c_alert_test.90330871
Short name T311
Test name
Test status
Simulation time 41117481 ps
CPU time 0.62 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:07 PM PST 24
Peak memory 202168 kb
Host smart-087e20b5-ca01-48a0-ad38-5b742136cb8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90330871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.90330871
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2159034907
Short name T776
Test name
Test status
Simulation time 39134184 ps
CPU time 1.08 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:18 PM PST 24
Peak memory 214924 kb
Host smart-a593ea01-4106-4921-ac99-22ba5fb6f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159034907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2159034907
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2014627346
Short name T751
Test name
Test status
Simulation time 1374766245 ps
CPU time 8.37 seconds
Started Jan 07 01:44:56 PM PST 24
Finished Jan 07 01:45:08 PM PST 24
Peak memory 286540 kb
Host smart-0dfb00e6-1295-445c-99dc-c7dadd3b4725
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014627346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2014627346
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.3031064293
Short name T1358
Test name
Test status
Simulation time 3466956581 ps
CPU time 215.78 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:49:16 PM PST 24
Peak memory 829252 kb
Host smart-bdb53f35-c936-4693-9bc8-585d5b3ae6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031064293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3031064293
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3155701073
Short name T1312
Test name
Test status
Simulation time 10061848644 ps
CPU time 646.87 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:56:13 PM PST 24
Peak memory 1511756 kb
Host smart-cb205422-069a-4f4c-bd6f-6442fd53beeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155701073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3155701073
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3672160957
Short name T1123
Test name
Test status
Simulation time 143518708 ps
CPU time 0.77 seconds
Started Jan 07 01:44:55 PM PST 24
Finished Jan 07 01:44:57 PM PST 24
Peak memory 203088 kb
Host smart-b9607761-4fcd-4e5c-b63c-ea6bfbac272d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672160957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3672160957
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3972661117
Short name T1354
Test name
Test status
Simulation time 468464012 ps
CPU time 5.94 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:13 PM PST 24
Peak memory 250256 kb
Host smart-26187e0d-d319-497e-a2b8-0a0914aeddf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972661117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3972661117
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.4078423813
Short name T483
Test name
Test status
Simulation time 9853843551 ps
CPU time 566.98 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:54:31 PM PST 24
Peak memory 1461700 kb
Host smart-620fb530-7ff9-43ed-a538-2ce688775bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078423813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.4078423813
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1930585063
Short name T548
Test name
Test status
Simulation time 12974077289 ps
CPU time 55.62 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 267528 kb
Host smart-8b7f3b70-9aa8-43fc-bea4-3c5b938ba813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930585063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1930585063
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.145587865
Short name T584
Test name
Test status
Simulation time 26281272 ps
CPU time 0.62 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:43 PM PST 24
Peak memory 202408 kb
Host smart-57d63da9-24d7-4c3c-ae41-bd67cab26e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145587865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.145587865
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1648396720
Short name T291
Test name
Test status
Simulation time 6562790654 ps
CPU time 106.2 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:47:25 PM PST 24
Peak memory 203408 kb
Host smart-0eae68e7-3591-4727-b374-f7df5fc29c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648396720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1648396720
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_rx_oversample.2074516957
Short name T557
Test name
Test status
Simulation time 2049186593 ps
CPU time 188.55 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:49:03 PM PST 24
Peak memory 305176 kb
Host smart-e765e2c2-6cbe-4e61-8936-7486bd4406f6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074516957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_rx_oversample
.2074516957
Directory /workspace/30.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3123963868
Short name T618
Test name
Test status
Simulation time 5761435990 ps
CPU time 71.17 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:46:42 PM PST 24
Peak memory 230220 kb
Host smart-01aff7c6-e788-419e-b150-646d68bdb99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123963868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3123963868
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3323526309
Short name T45
Test name
Test status
Simulation time 999895006 ps
CPU time 4.11 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:45:35 PM PST 24
Peak memory 203376 kb
Host smart-8c3448cf-2f57-4ad1-af72-d0e0746a1127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323526309 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3323526309
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.4248519585
Short name T562
Test name
Test status
Simulation time 10083856153 ps
CPU time 52.21 seconds
Started Jan 07 01:45:12 PM PST 24
Finished Jan 07 01:46:33 PM PST 24
Peak memory 483348 kb
Host smart-3e824540-6ebc-46b9-99d5-eb06dd7eaf21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248519585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.4248519585
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.823100628
Short name T1249
Test name
Test status
Simulation time 10079753599 ps
CPU time 27.37 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:45:59 PM PST 24
Peak memory 370844 kb
Host smart-e1a008e3-f753-4337-99e7-e8c3e827ef9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823100628 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.823100628
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.293401590
Short name T572
Test name
Test status
Simulation time 643244424 ps
CPU time 3.12 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:45:07 PM PST 24
Peak memory 203348 kb
Host smart-06181860-f9ba-4288-8753-0ff82ce981b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293401590 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.293401590
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1209027
Short name T1378
Test name
Test status
Simulation time 1926560354 ps
CPU time 4.34 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:45:48 PM PST 24
Peak memory 206244 kb
Host smart-584ecb90-d0f2-496c-84ed-d302c8bbf35a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209027 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_intr_smoke.1209027
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.968604971
Short name T955
Test name
Test status
Simulation time 7667417475 ps
CPU time 104.89 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:47:12 PM PST 24
Peak memory 1626972 kb
Host smart-58265247-8769-4489-bdfc-0ffd59d9144a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968604971 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.968604971
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.3578163605
Short name T1320
Test name
Test status
Simulation time 2914271049 ps
CPU time 4.77 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:45:58 PM PST 24
Peak memory 207372 kb
Host smart-b41c625e-30c1-43a6-b4cf-11a6af7e35ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578163605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.3578163605
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.4213614261
Short name T643
Test name
Test status
Simulation time 2496066165 ps
CPU time 28.7 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:46:12 PM PST 24
Peak memory 203284 kb
Host smart-f368661f-e9e8-4066-82bc-104728312174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213614261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.4213614261
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.1774226955
Short name T1137
Test name
Test status
Simulation time 54776235274 ps
CPU time 698.82 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:57:30 PM PST 24
Peak memory 4846356 kb
Host smart-d3d78688-4114-4486-a7ec-664fd044f50d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774226955 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.1774226955
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3498707317
Short name T823
Test name
Test status
Simulation time 9174890506 ps
CPU time 47.98 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:46:23 PM PST 24
Peak memory 203400 kb
Host smart-87a96343-5633-4a1c-99f8-b5c1d71288a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498707317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3498707317
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1039274721
Short name T403
Test name
Test status
Simulation time 22002513653 ps
CPU time 361.93 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:51:35 PM PST 24
Peak memory 3391548 kb
Host smart-6bdeb757-df91-4cb9-ae6e-4b73f0972b95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039274721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1039274721
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2980302696
Short name T230
Test name
Test status
Simulation time 6896972745 ps
CPU time 89.47 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:46:46 PM PST 24
Peak memory 548692 kb
Host smart-6145774f-9bf4-42ad-b27b-7c419102963a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980302696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2980302696
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.489682249
Short name T280
Test name
Test status
Simulation time 5695866573 ps
CPU time 5.92 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:45:44 PM PST 24
Peak memory 211896 kb
Host smart-a7806dec-372f-4477-9c69-fc962c397364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489682249 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.489682249
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.2499938909
Short name T462
Test name
Test status
Simulation time 917296282 ps
CPU time 3.97 seconds
Started Jan 07 01:45:06 PM PST 24
Finished Jan 07 01:45:38 PM PST 24
Peak memory 203316 kb
Host smart-6b5a43f0-e518-434a-9d63-3c574f58694e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499938909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.2499938909
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3232475561
Short name T598
Test name
Test status
Simulation time 63695295 ps
CPU time 0.6 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:45:54 PM PST 24
Peak memory 202152 kb
Host smart-4a294acb-8792-4c16-a28e-fc1a74bf1c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232475561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3232475561
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1558834467
Short name T206
Test name
Test status
Simulation time 59549349 ps
CPU time 1.53 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:45:38 PM PST 24
Peak memory 211508 kb
Host smart-c5f4ef60-9d81-4e7a-b242-1f931a1acc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558834467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1558834467
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.766541978
Short name T677
Test name
Test status
Simulation time 1405141585 ps
CPU time 8.15 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:27 PM PST 24
Peak memory 275856 kb
Host smart-ecdda6a6-b4d0-42ce-816d-fbb0e22aa766
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766541978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.766541978
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.566396840
Short name T741
Test name
Test status
Simulation time 21900696434 ps
CPU time 195.81 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:48:30 PM PST 24
Peak memory 1157620 kb
Host smart-c06dca63-7af9-41ac-b79d-92a3238a3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566396840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.566396840
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.471261686
Short name T577
Test name
Test status
Simulation time 267791039 ps
CPU time 3.51 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:45:58 PM PST 24
Peak memory 225884 kb
Host smart-1d0ae38e-d50a-4a81-b06c-89d8773c90b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471261686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
471261686
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1248184967
Short name T879
Test name
Test status
Simulation time 48392195996 ps
CPU time 191.28 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:48:17 PM PST 24
Peak memory 1171496 kb
Host smart-d29006ff-eae0-44ec-8c0d-62fcbfbf7d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248184967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1248184967
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2499185560
Short name T425
Test name
Test status
Simulation time 6415058987 ps
CPU time 50.47 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:46:46 PM PST 24
Peak memory 328968 kb
Host smart-60dd16f7-e6c5-46ab-a8f4-dfa15d335ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499185560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2499185560
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.3755938292
Short name T127
Test name
Test status
Simulation time 20716263 ps
CPU time 0.62 seconds
Started Jan 07 01:45:08 PM PST 24
Finished Jan 07 01:45:39 PM PST 24
Peak memory 202456 kb
Host smart-be57f526-b24c-493e-adf1-1527e27b38e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755938292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3755938292
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3420888172
Short name T1241
Test name
Test status
Simulation time 365411719 ps
CPU time 17.11 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 220784 kb
Host smart-482cbf2f-e7e0-4669-a9cd-29931c7ceb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420888172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3420888172
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_rx_oversample.3372761677
Short name T179
Test name
Test status
Simulation time 2986141851 ps
CPU time 136.34 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:48:09 PM PST 24
Peak memory 333360 kb
Host smart-7360c71a-69a2-4fef-8298-d935cae22740
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372761677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_rx_oversample
.3372761677
Directory /workspace/31.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1677382352
Short name T1267
Test name
Test status
Simulation time 4511472842 ps
CPU time 92.99 seconds
Started Jan 07 01:45:05 PM PST 24
Finished Jan 07 01:47:05 PM PST 24
Peak memory 234848 kb
Host smart-e3b3c100-20d6-4445-bfd6-1452e439c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677382352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1677382352
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.289085834
Short name T422
Test name
Test status
Simulation time 930775040 ps
CPU time 40.88 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:46:34 PM PST 24
Peak memory 211456 kb
Host smart-ef8ea669-4a74-43eb-a802-8fb160667071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289085834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.289085834
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1883537136
Short name T1152
Test name
Test status
Simulation time 4772966586 ps
CPU time 4.53 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:46:09 PM PST 24
Peak memory 203368 kb
Host smart-20d4b85f-7140-48d6-b874-317c308cfd52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883537136 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1883537136
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2580514059
Short name T1265
Test name
Test status
Simulation time 10378572333 ps
CPU time 12.58 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:13 PM PST 24
Peak memory 290420 kb
Host smart-1bd519e9-d4f0-4fce-a440-eb0314d047c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580514059 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2580514059
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.967663748
Short name T1344
Test name
Test status
Simulation time 10423769696 ps
CPU time 13.95 seconds
Started Jan 07 01:45:07 PM PST 24
Finished Jan 07 01:45:49 PM PST 24
Peak memory 309028 kb
Host smart-33a1bc16-08ee-4bc0-baa5-984a246cbfe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967663748 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.967663748
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.948865346
Short name T1280
Test name
Test status
Simulation time 7838960450 ps
CPU time 3.33 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:02 PM PST 24
Peak memory 203800 kb
Host smart-77a0b7f9-4c5a-4ca7-98e4-3e0f393cb610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948865346 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.948865346
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1157035655
Short name T95
Test name
Test status
Simulation time 2352972955 ps
CPU time 9.46 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 219752 kb
Host smart-d7eeff44-2bb9-4573-922b-da6cb42d3e1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157035655 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1157035655
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3713253485
Short name T141
Test name
Test status
Simulation time 22194604248 ps
CPU time 899.06 seconds
Started Jan 07 01:45:09 PM PST 24
Finished Jan 07 02:00:38 PM PST 24
Peak memory 5280148 kb
Host smart-868eac0a-03a2-423e-9b80-063616a75d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713253485 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3713253485
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.2224487371
Short name T947
Test name
Test status
Simulation time 2902305587 ps
CPU time 5.02 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:45:48 PM PST 24
Peak memory 212956 kb
Host smart-320d6077-31db-40c2-8b77-e97b440160cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224487371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.2224487371
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1243325529
Short name T396
Test name
Test status
Simulation time 1457802798 ps
CPU time 37.31 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 203344 kb
Host smart-93f58c2a-526c-4b79-aab1-a18f960b533d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243325529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1243325529
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.126513503
Short name T1026
Test name
Test status
Simulation time 2061823830 ps
CPU time 79.06 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:47:26 PM PST 24
Peak memory 203088 kb
Host smart-50dd1478-de93-46b4-ada6-716c395e70c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126513503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.126513503
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3728732670
Short name T1345
Test name
Test status
Simulation time 19674029157 ps
CPU time 429.25 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:53:11 PM PST 24
Peak memory 3947736 kb
Host smart-c62aa140-49d3-493c-a0b9-7c95b71570fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728732670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3728732670
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.672893460
Short name T366
Test name
Test status
Simulation time 1953098082 ps
CPU time 8.02 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 213300 kb
Host smart-e82b70ab-3fe6-442f-a6af-f134ae1ce4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672893460 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.672893460
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_ovf.2340460217
Short name T769
Test name
Test status
Simulation time 5007168289 ps
CPU time 35.12 seconds
Started Jan 07 01:45:17 PM PST 24
Finished Jan 07 01:46:24 PM PST 24
Peak memory 219672 kb
Host smart-49fb8f98-ee26-4cab-87b3-bba52cb1c7ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340460217 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_tx_ovf.2340460217
Directory /workspace/31.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.415068065
Short name T833
Test name
Test status
Simulation time 1663603743 ps
CPU time 7.93 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:45:55 PM PST 24
Peak memory 203092 kb
Host smart-4ff7a82e-ac40-40d4-9a06-9807aa1d2761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415068065 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_unexp_stop.415068065
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3542415458
Short name T1058
Test name
Test status
Simulation time 24179636 ps
CPU time 0.58 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:46:05 PM PST 24
Peak memory 201868 kb
Host smart-92f9d87a-6a2f-49f2-a6e9-3f881ebae660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542415458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3542415458
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2897940215
Short name T646
Test name
Test status
Simulation time 45221206 ps
CPU time 1.29 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:09 PM PST 24
Peak memory 211520 kb
Host smart-9e57d9ce-3f71-4812-853d-afce419f93af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897940215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2897940215
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2907942316
Short name T706
Test name
Test status
Simulation time 1459943768 ps
CPU time 8.59 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:46:16 PM PST 24
Peak memory 284980 kb
Host smart-8669344a-6e52-49b7-a1d3-ab931f8db6b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907942316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2907942316
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2939304280
Short name T1055
Test name
Test status
Simulation time 2315667776 ps
CPU time 166.9 seconds
Started Jan 07 01:45:10 PM PST 24
Finished Jan 07 01:48:26 PM PST 24
Peak memory 778492 kb
Host smart-72e32198-e47b-41b7-8377-7e87e0a89816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939304280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2939304280
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1325901616
Short name T14
Test name
Test status
Simulation time 5910572537 ps
CPU time 366.27 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:52:23 PM PST 24
Peak memory 1560580 kb
Host smart-7699cf85-1f74-4e87-a3ce-6eb1485d79a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325901616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1325901616
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3830362908
Short name T887
Test name
Test status
Simulation time 341051521 ps
CPU time 0.96 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 203120 kb
Host smart-09b3806c-a39d-4049-9215-3c4cff9a4c65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830362908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3830362908
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1325033239
Short name T979
Test name
Test status
Simulation time 702591084 ps
CPU time 9.19 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 203244 kb
Host smart-5992a6e2-539e-4727-9e5c-310ad0971670
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325033239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1325033239
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.375891509
Short name T237
Test name
Test status
Simulation time 3686690813 ps
CPU time 354.88 seconds
Started Jan 07 01:45:49 PM PST 24
Finished Jan 07 01:52:24 PM PST 24
Peak memory 1084396 kb
Host smart-0dfc26b0-9e10-4931-8fab-27701ffb68fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375891509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.375891509
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.726985428
Short name T38
Test name
Test status
Simulation time 2095721274 ps
CPU time 55.77 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:46:54 PM PST 24
Peak memory 313908 kb
Host smart-a425c9fc-7b0a-43e6-aead-234b2c8b7673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726985428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.726985428
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3921987711
Short name T954
Test name
Test status
Simulation time 16150785 ps
CPU time 0.61 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 202420 kb
Host smart-9b0e8f2a-ca40-49e3-bc6b-2f44a155613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921987711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3921987711
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1582080692
Short name T869
Test name
Test status
Simulation time 3520454125 ps
CPU time 14.43 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:19 PM PST 24
Peak memory 222684 kb
Host smart-12c73cdd-fcb2-4293-ba3b-b42e3dfe5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582080692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1582080692
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_rx_oversample.2316270290
Short name T788
Test name
Test status
Simulation time 2223937317 ps
CPU time 192.4 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:49:11 PM PST 24
Peak memory 300588 kb
Host smart-0bed479e-11a2-4380-8528-78430eed8b73
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316270290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_rx_oversample
.2316270290
Directory /workspace/32.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3642627235
Short name T754
Test name
Test status
Simulation time 9900577979 ps
CPU time 100.52 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:47:41 PM PST 24
Peak memory 249120 kb
Host smart-0640f15c-66fd-46c1-960d-9cfc3246ca23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642627235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3642627235
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1220565464
Short name T672
Test name
Test status
Simulation time 7717619526 ps
CPU time 34 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:39 PM PST 24
Peak memory 211408 kb
Host smart-03ec004c-1472-4ef0-b6ff-c3df5505f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220565464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1220565464
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2436881972
Short name T928
Test name
Test status
Simulation time 1313722598 ps
CPU time 4.34 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:22 PM PST 24
Peak memory 203252 kb
Host smart-27e359be-ed36-431d-8935-c10d957f9021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436881972 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2436881972
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3690549566
Short name T357
Test name
Test status
Simulation time 10434268903 ps
CPU time 13.27 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:45:40 PM PST 24
Peak memory 262696 kb
Host smart-15815719-16cc-4b95-bc74-e521a4c6f278
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690549566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3690549566
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.584471304
Short name T466
Test name
Test status
Simulation time 10202772492 ps
CPU time 13.53 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:45:25 PM PST 24
Peak memory 292708 kb
Host smart-51ddcc06-4044-481d-ba66-205f47c5a01f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584471304 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_tx.584471304
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.652612826
Short name T1289
Test name
Test status
Simulation time 700858742 ps
CPU time 2.01 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:19 PM PST 24
Peak memory 203324 kb
Host smart-eadc9d41-4649-402d-90ec-d70a3a3447b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652612826 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.652612826
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.498492462
Short name T908
Test name
Test status
Simulation time 1682915349 ps
CPU time 6.88 seconds
Started Jan 07 01:45:00 PM PST 24
Finished Jan 07 01:45:21 PM PST 24
Peak memory 212324 kb
Host smart-b77022af-dbd0-477b-a238-f7dce026d1a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498492462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.498492462
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1721475658
Short name T1134
Test name
Test status
Simulation time 20387260345 ps
CPU time 870.62 seconds
Started Jan 07 01:45:03 PM PST 24
Finished Jan 07 01:59:58 PM PST 24
Peak memory 4682068 kb
Host smart-1034e6fa-3624-4d6c-8f5f-7b04d5b8dffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721475658 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1721475658
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.4235669870
Short name T819
Test name
Test status
Simulation time 616334274 ps
CPU time 3.58 seconds
Started Jan 07 01:44:58 PM PST 24
Finished Jan 07 01:45:08 PM PST 24
Peak memory 203328 kb
Host smart-d398f543-8fcf-4b7b-b0ce-9b04e25be4fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235669870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.4235669870
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2577221551
Short name T781
Test name
Test status
Simulation time 1346447057 ps
CPU time 16.82 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:46:00 PM PST 24
Peak memory 203332 kb
Host smart-be23b91b-7cca-45aa-b8d6-59e56ac352d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577221551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2577221551
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.2893565586
Short name T1269
Test name
Test status
Simulation time 9562760861 ps
CPU time 43.85 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:46:28 PM PST 24
Peak memory 268540 kb
Host smart-190efdb6-c92c-4512-a8c4-f10df48ea976
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893565586 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.2893565586
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.631490973
Short name T948
Test name
Test status
Simulation time 2443157631 ps
CPU time 22.51 seconds
Started Jan 07 01:44:57 PM PST 24
Finished Jan 07 01:45:27 PM PST 24
Peak memory 218296 kb
Host smart-b7889e2b-8782-48a5-851d-ea1adbf0741c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631490973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.631490973
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1593898049
Short name T1052
Test name
Test status
Simulation time 21516585940 ps
CPU time 478.43 seconds
Started Jan 07 01:45:02 PM PST 24
Finished Jan 07 01:53:25 PM PST 24
Peak memory 4283488 kb
Host smart-8b950483-b033-4861-8fe3-4f645df19ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593898049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1593898049
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3988596563
Short name T515
Test name
Test status
Simulation time 23173029066 ps
CPU time 131.89 seconds
Started Jan 07 01:45:04 PM PST 24
Finished Jan 07 01:47:42 PM PST 24
Peak memory 1244420 kb
Host smart-9c89f0e4-f85f-47c0-a7fa-d4556c582ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988596563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3988596563
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_tx_ovf.125297035
Short name T397
Test name
Test status
Simulation time 3079196767 ps
CPU time 64.55 seconds
Started Jan 07 01:44:59 PM PST 24
Finished Jan 07 01:46:17 PM PST 24
Peak memory 300856 kb
Host smart-fca3e8d4-ee39-4053-9c62-a15c3a33859e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125297035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_tx_ovf.125297035
Directory /workspace/32.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.3794618776
Short name T1124
Test name
Test status
Simulation time 4311387190 ps
CPU time 5.76 seconds
Started Jan 07 01:45:01 PM PST 24
Finished Jan 07 01:45:26 PM PST 24
Peak memory 203320 kb
Host smart-7d1c1a24-a164-4a81-aeee-511986d2609b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794618776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.3794618776
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3886951177
Short name T446
Test name
Test status
Simulation time 40970509 ps
CPU time 0.59 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:45:55 PM PST 24
Peak memory 202120 kb
Host smart-17d53488-5c21-4c34-bbc2-4b0131799b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886951177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3886951177
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3618268496
Short name T1209
Test name
Test status
Simulation time 72469561 ps
CPU time 1.66 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:09 PM PST 24
Peak memory 213664 kb
Host smart-c5612661-971d-47b2-96ba-49084e42f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618268496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3618268496
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3875188117
Short name T602
Test name
Test status
Simulation time 6487815120 ps
CPU time 32.36 seconds
Started Jan 07 01:45:21 PM PST 24
Finished Jan 07 01:46:27 PM PST 24
Peak memory 339932 kb
Host smart-f61a4573-54c4-49e5-b880-ab8957dd89d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875188117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3875188117
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.748419814
Short name T1218
Test name
Test status
Simulation time 11292733150 ps
CPU time 191.49 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:49:25 PM PST 24
Peak memory 800324 kb
Host smart-d9a36ee6-2a3e-4a0e-94eb-a30ee0975e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748419814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.748419814
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2682516461
Short name T332
Test name
Test status
Simulation time 247801741 ps
CPU time 12.11 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 01:46:03 PM PST 24
Peak memory 203404 kb
Host smart-72a4eb9b-da87-4a9b-bd89-060444babc85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682516461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2682516461
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3134958797
Short name T257
Test name
Test status
Simulation time 4197048726 ps
CPU time 202.25 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:49:37 PM PST 24
Peak memory 1166760 kb
Host smart-852adc09-a895-406d-8e4b-89187bf48749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134958797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3134958797
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.2627924643
Short name T932
Test name
Test status
Simulation time 2738917386 ps
CPU time 131.02 seconds
Started Jan 07 01:45:42 PM PST 24
Finished Jan 07 01:48:33 PM PST 24
Peak memory 235204 kb
Host smart-cc209ce8-263f-47ae-ab6c-2b605c2db231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627924643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.2627924643
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.1827791358
Short name T152
Test name
Test status
Simulation time 18827777 ps
CPU time 0.63 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 202404 kb
Host smart-9414b88b-d809-45e5-9629-548a2826ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827791358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.1827791358
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.4210286379
Short name T1046
Test name
Test status
Simulation time 30186717562 ps
CPU time 1295.94 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 02:07:42 PM PST 24
Peak memory 203408 kb
Host smart-fa631655-0e5f-434b-aaae-a4936b7a1e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210286379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.4210286379
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_rx_oversample.1754665053
Short name T863
Test name
Test status
Simulation time 2027399061 ps
CPU time 163.81 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:48:38 PM PST 24
Peak memory 288120 kb
Host smart-8c3d57e0-af0f-4094-af4a-c17e217a4220
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754665053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_rx_oversample
.1754665053
Directory /workspace/33.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2159495721
Short name T553
Test name
Test status
Simulation time 1618175876 ps
CPU time 41.57 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 284600 kb
Host smart-8a16eac2-ff5f-4cff-bef2-079b9897486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159495721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2159495721
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.189461598
Short name T789
Test name
Test status
Simulation time 25663681628 ps
CPU time 997.07 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 02:02:45 PM PST 24
Peak memory 1115788 kb
Host smart-bddea7e8-daef-4f93-a455-2a953b311b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189461598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.189461598
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2782100623
Short name T208
Test name
Test status
Simulation time 3137300519 ps
CPU time 41.28 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:46:28 PM PST 24
Peak memory 211508 kb
Host smart-e231d59e-d791-4ce4-aa04-2aa58994db55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782100623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2782100623
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.4152314629
Short name T1275
Test name
Test status
Simulation time 2968825004 ps
CPU time 3.04 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 203332 kb
Host smart-28ab4dde-1448-4dc6-9139-adbd0aa1bdfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152314629 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.4152314629
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.54419568
Short name T692
Test name
Test status
Simulation time 10133899562 ps
CPU time 69.38 seconds
Started Jan 07 01:45:22 PM PST 24
Finished Jan 07 01:47:06 PM PST 24
Peak memory 516384 kb
Host smart-9456c1a3-922b-48f8-a7b4-b38da8e4aed0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54419568 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_acq.54419568
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3638613411
Short name T1245
Test name
Test status
Simulation time 10047715717 ps
CPU time 75.96 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:47:32 PM PST 24
Peak memory 654148 kb
Host smart-de665fd5-a0bc-497b-bcfd-c49001878e02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638613411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3638613411
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2190139631
Short name T434
Test name
Test status
Simulation time 1430426606 ps
CPU time 2.37 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:46:10 PM PST 24
Peak memory 203268 kb
Host smart-0294fabe-587e-4605-b218-bba9e01e0309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190139631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2190139631
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.4003401806
Short name T3
Test name
Test status
Simulation time 3958545207 ps
CPU time 4.84 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:13 PM PST 24
Peak memory 203380 kb
Host smart-5995c6e6-ae47-4a7f-b384-7df4a2690101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003401806 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.4003401806
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1509357711
Short name T1083
Test name
Test status
Simulation time 42738920419 ps
CPU time 2473.2 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 02:27:23 PM PST 24
Peak memory 9412524 kb
Host smart-b62f68b3-5398-4c14-afcf-0d97c677b4fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509357711 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1509357711
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3069044328
Short name T1239
Test name
Test status
Simulation time 5333887153 ps
CPU time 3.6 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:46:02 PM PST 24
Peak memory 203368 kb
Host smart-a5e674d0-43e3-4637-baf5-21dd7b40aa18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069044328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3069044328
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3462868809
Short name T213
Test name
Test status
Simulation time 3924444211 ps
CPU time 27.36 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 203292 kb
Host smart-0b08dee7-3a66-4602-ac98-1b6fe54ec8dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462868809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3462868809
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.3903205993
Short name T382
Test name
Test status
Simulation time 50978604583 ps
CPU time 147.38 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:48:35 PM PST 24
Peak memory 412984 kb
Host smart-68a1590c-580f-491d-87b5-ac7827e81707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903205993 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.3903205993
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.994021707
Short name T627
Test name
Test status
Simulation time 51810256797 ps
CPU time 1151.11 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 02:05:29 PM PST 24
Peak memory 6062084 kb
Host smart-18d1de81-fe34-42d6-a1b3-b773fd16e873
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994021707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_wr.994021707
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.71824362
Short name T571
Test name
Test status
Simulation time 9361276936 ps
CPU time 352.78 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:51:57 PM PST 24
Peak memory 1214556 kb
Host smart-b46bc90e-77f7-4e8e-80bf-1fddb9316f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71824362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_stretch.71824362
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2103911447
Short name T331
Test name
Test status
Simulation time 10984104619 ps
CPU time 6.87 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:46:24 PM PST 24
Peak memory 218672 kb
Host smart-97fa6e95-8e42-4af6-ae9e-58b2046cea9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103911447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2103911447
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_ovf.3816219583
Short name T1325
Test name
Test status
Simulation time 10801234037 ps
CPU time 35.81 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:46:49 PM PST 24
Peak memory 213316 kb
Host smart-d1fab6b3-9118-4964-8030-be1161655369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816219583 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_tx_ovf.3816219583
Directory /workspace/33.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.601551804
Short name T858
Test name
Test status
Simulation time 1971154573 ps
CPU time 6.23 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 203200 kb
Host smart-a64896b3-675c-4a35-b2fe-f4e2e8ed4ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601551804 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_unexp_stop.601551804
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3026588046
Short name T525
Test name
Test status
Simulation time 37964562 ps
CPU time 0.59 seconds
Started Jan 07 01:45:51 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 202192 kb
Host smart-9af9a13a-73c1-433f-aa3c-13d2128b2aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026588046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3026588046
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.582050008
Short name T872
Test name
Test status
Simulation time 90596125 ps
CPU time 1.13 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:46:00 PM PST 24
Peak memory 203388 kb
Host smart-7f7dc1c9-4de3-44d1-a0e8-2f2e143ce3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582050008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.582050008
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2358081180
Short name T870
Test name
Test status
Simulation time 3088985227 ps
CPU time 106.16 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:48:01 PM PST 24
Peak memory 942144 kb
Host smart-cdc3300a-7dc8-4a3d-b9bf-bad564664450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358081180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2358081180
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2280158715
Short name T1031
Test name
Test status
Simulation time 4189117220 ps
CPU time 417.7 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:53:12 PM PST 24
Peak memory 1164476 kb
Host smart-853b5b41-91d6-425c-a935-4f8c6d50e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280158715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2280158715
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.149975222
Short name T663
Test name
Test status
Simulation time 446837682 ps
CPU time 0.99 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 01:46:12 PM PST 24
Peak memory 203236 kb
Host smart-2b8aa36f-5859-47aa-9b68-1a14bc18ec74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149975222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.149975222
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2860563499
Short name T924
Test name
Test status
Simulation time 709351353 ps
CPU time 4.68 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 203352 kb
Host smart-a567db02-a019-4ff9-99bb-cd8fab59e5b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860563499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2860563499
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2843406452
Short name T600
Test name
Test status
Simulation time 3214359710 ps
CPU time 269.28 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:50:37 PM PST 24
Peak memory 1003020 kb
Host smart-fef43e58-4beb-4651-81b1-35ae9c15913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843406452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2843406452
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2745116581
Short name T1001
Test name
Test status
Simulation time 7946109492 ps
CPU time 163.48 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:48:38 PM PST 24
Peak memory 491724 kb
Host smart-03d9cb28-c8c5-4462-9a5a-36a759e84390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745116581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2745116581
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.4242522624
Short name T1164
Test name
Test status
Simulation time 44266739 ps
CPU time 0.61 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:45:59 PM PST 24
Peak memory 202352 kb
Host smart-0deea0c5-648a-4e28-a43b-47b7f94abbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242522624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.4242522624
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3044017107
Short name T1135
Test name
Test status
Simulation time 52328861901 ps
CPU time 105.48 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:48:03 PM PST 24
Peak memory 212464 kb
Host smart-9f435854-d278-485c-90b3-8088abcc74a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044017107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3044017107
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_rx_oversample.4284527790
Short name T651
Test name
Test status
Simulation time 22694228284 ps
CPU time 128.59 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:48:07 PM PST 24
Peak memory 261576 kb
Host smart-29020858-bf34-412d-a0cf-b594ec42ea45
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284527790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_rx_oversample
.4284527790
Directory /workspace/34.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.498807888
Short name T714
Test name
Test status
Simulation time 5508565659 ps
CPU time 132.02 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:48:09 PM PST 24
Peak memory 376324 kb
Host smart-0135b259-afab-4340-9a21-3f1178c26d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498807888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.498807888
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2341688720
Short name T451
Test name
Test status
Simulation time 2254108191 ps
CPU time 47.96 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 01:46:58 PM PST 24
Peak memory 211564 kb
Host smart-b1b540c5-60a5-4133-96b1-9626693f916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341688720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2341688720
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2515907575
Short name T984
Test name
Test status
Simulation time 10025123854 ps
CPU time 65.08 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:47:22 PM PST 24
Peak memory 555144 kb
Host smart-0928929f-cd6b-4db6-bac4-4c6d16862494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515907575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2515907575
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1836513147
Short name T474
Test name
Test status
Simulation time 10136751687 ps
CPU time 29.85 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:46:47 PM PST 24
Peak memory 382544 kb
Host smart-99ac0c5f-4c1c-4015-bc21-c0dfd2b40054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836513147 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1836513147
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1100621443
Short name T778
Test name
Test status
Simulation time 2316843463 ps
CPU time 4.75 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:46:19 PM PST 24
Peak memory 204240 kb
Host smart-822a4345-e353-4a54-8390-2877bb67a8f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100621443 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1100621443
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2235105672
Short name T1111
Test name
Test status
Simulation time 17166129015 ps
CPU time 274.17 seconds
Started Jan 07 01:45:32 PM PST 24
Finished Jan 07 01:50:45 PM PST 24
Peak memory 2672752 kb
Host smart-b4aba016-be5f-4b59-aff7-5e5b789c67dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235105672 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2235105672
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.83974574
Short name T818
Test name
Test status
Simulation time 2642074584 ps
CPU time 3.73 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 01:46:16 PM PST 24
Peak memory 203428 kb
Host smart-35480dcb-88ea-4c5d-a9bb-f68eb5282762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83974574 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 34.i2c_target_perf.83974574
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2600860824
Short name T191
Test name
Test status
Simulation time 8212662324 ps
CPU time 37.49 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:40 PM PST 24
Peak memory 203312 kb
Host smart-bf2fa41d-60c7-424b-a8fa-a97c106b5e05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600860824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2600860824
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.1347539892
Short name T34
Test name
Test status
Simulation time 60027597512 ps
CPU time 570.94 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:55:50 PM PST 24
Peak memory 1823792 kb
Host smart-c5009e07-a85b-4796-8789-b886e2f9d4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347539892 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.1347539892
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2955685243
Short name T337
Test name
Test status
Simulation time 44117707120 ps
CPU time 329.48 seconds
Started Jan 07 01:45:46 PM PST 24
Finished Jan 07 01:51:55 PM PST 24
Peak memory 2550088 kb
Host smart-03f66e92-4908-4c55-a561-d1dc0f714e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955685243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2955685243
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.305532804
Short name T418
Test name
Test status
Simulation time 4399001165 ps
CPU time 284.82 seconds
Started Jan 07 01:45:53 PM PST 24
Finished Jan 07 01:51:18 PM PST 24
Peak memory 1147004 kb
Host smart-0b51eaf7-df5d-455f-84c4-8098bbca0bb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305532804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.305532804
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.3844442282
Short name T1313
Test name
Test status
Simulation time 7788237101 ps
CPU time 7.9 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 208784 kb
Host smart-52c3e333-acb1-45be-9ce8-6f0152c54e8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844442282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.3844442282
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_ovf.2791526387
Short name T142
Test name
Test status
Simulation time 3626177532 ps
CPU time 277.35 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:50:36 PM PST 24
Peak memory 531608 kb
Host smart-73a7f602-bf21-470d-a2bd-c4e321c522d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791526387 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_tx_ovf.2791526387
Directory /workspace/34.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.4038854757
Short name T797
Test name
Test status
Simulation time 3469258269 ps
CPU time 4.62 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 203184 kb
Host smart-9d92fdf1-98db-4ee7-8a9d-7c83b1ebf30b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038854757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.4038854757
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3512122215
Short name T886
Test name
Test status
Simulation time 139106831 ps
CPU time 0.56 seconds
Started Jan 07 01:45:41 PM PST 24
Finished Jan 07 01:46:23 PM PST 24
Peak memory 202088 kb
Host smart-f041f064-8563-4d7c-850d-580e6d0ec238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512122215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3512122215
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2025386164
Short name T549
Test name
Test status
Simulation time 131893292 ps
CPU time 1.35 seconds
Started Jan 07 01:46:14 PM PST 24
Finished Jan 07 01:46:55 PM PST 24
Peak memory 211556 kb
Host smart-8a3f12ee-bec2-4569-be64-2837ad27cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025386164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2025386164
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.659009565
Short name T1362
Test name
Test status
Simulation time 989858824 ps
CPU time 4.96 seconds
Started Jan 07 01:45:50 PM PST 24
Finished Jan 07 01:46:36 PM PST 24
Peak memory 252652 kb
Host smart-41e45400-9507-4c9f-9acd-3e47f53c248b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659009565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empt
y.659009565
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2918479563
Short name T1061
Test name
Test status
Simulation time 2458542580 ps
CPU time 86.06 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:47:46 PM PST 24
Peak memory 815660 kb
Host smart-416add06-2042-420d-a3f7-bd10d049f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918479563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2918479563
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.356045659
Short name T900
Test name
Test status
Simulation time 7103110099 ps
CPU time 655.05 seconds
Started Jan 07 01:46:06 PM PST 24
Finished Jan 07 01:57:40 PM PST 24
Peak memory 1577508 kb
Host smart-ef4fa3ff-7195-4c04-ac08-7fa54668de5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356045659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.356045659
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3463005417
Short name T730
Test name
Test status
Simulation time 309462865 ps
CPU time 1.04 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 01:46:41 PM PST 24
Peak memory 203280 kb
Host smart-d7671a09-9995-482f-a896-f1990bf6c3d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463005417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3463005417
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3223171292
Short name T736
Test name
Test status
Simulation time 238224405 ps
CPU time 5.23 seconds
Started Jan 07 01:46:04 PM PST 24
Finished Jan 07 01:46:48 PM PST 24
Peak memory 203188 kb
Host smart-1dfc1777-e5de-4f31-81fa-4e2c36812b74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223171292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3223171292
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.577542729
Short name T658
Test name
Test status
Simulation time 5614957786 ps
CPU time 504.84 seconds
Started Jan 07 01:46:04 PM PST 24
Finished Jan 07 01:55:07 PM PST 24
Peak memory 1406344 kb
Host smart-8d9a1a85-ef5e-4fec-86bb-4be23afbd756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577542729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.577542729
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1455633697
Short name T342
Test name
Test status
Simulation time 5833428123 ps
CPU time 275.1 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:50:35 PM PST 24
Peak memory 426328 kb
Host smart-b6fe0ac3-e850-49e8-aaf9-bfec8aff830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455633697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1455633697
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3301052621
Short name T761
Test name
Test status
Simulation time 18347719 ps
CPU time 0.64 seconds
Started Jan 07 01:45:46 PM PST 24
Finished Jan 07 01:46:26 PM PST 24
Peak memory 202400 kb
Host smart-75c7e34a-09b8-4ac2-aaa6-a19d1b87c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301052621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3301052621
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1315170740
Short name T1182
Test name
Test status
Simulation time 6983690709 ps
CPU time 65.08 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:48:10 PM PST 24
Peak memory 211604 kb
Host smart-67beec49-6dba-4a6e-84a9-2abe2e771a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315170740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1315170740
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_rx_oversample.873383215
Short name T871
Test name
Test status
Simulation time 2386219413 ps
CPU time 152.43 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:49:37 PM PST 24
Peak memory 260592 kb
Host smart-8a1123f4-7dcc-43e7-948a-39e9d1f94ca7
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873383215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_rx_oversample.
873383215
Directory /workspace/35.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1517081106
Short name T375
Test name
Test status
Simulation time 2501017432 ps
CPU time 158.16 seconds
Started Jan 07 01:45:44 PM PST 24
Finished Jan 07 01:49:03 PM PST 24
Peak memory 281844 kb
Host smart-076a6127-6a48-4f3e-b295-1251c2d431d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517081106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1517081106
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1868833533
Short name T845
Test name
Test status
Simulation time 121458874072 ps
CPU time 955.34 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 02:03:09 PM PST 24
Peak memory 2055740 kb
Host smart-488f6c00-2e6f-4949-b325-526a1ca24e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868833533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1868833533
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1841838986
Short name T75
Test name
Test status
Simulation time 628070227 ps
CPU time 12.14 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:28 PM PST 24
Peak memory 219648 kb
Host smart-b59f9743-af08-4586-9b33-03646f99b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841838986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1841838986
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3964421341
Short name T723
Test name
Test status
Simulation time 4859136932 ps
CPU time 4.71 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 203332 kb
Host smart-4938789d-c915-4537-9d8c-b7d89355c697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964421341 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3964421341
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3478940414
Short name T166
Test name
Test status
Simulation time 10143857969 ps
CPU time 52.23 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:55 PM PST 24
Peak memory 500148 kb
Host smart-16f0b60b-fae6-4cc6-9bd1-c0da4324c0b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478940414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3478940414
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.934656139
Short name T1044
Test name
Test status
Simulation time 10134042072 ps
CPU time 61.64 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:47:06 PM PST 24
Peak memory 509688 kb
Host smart-c3b6e10c-7266-4053-9c4e-4732c8c66377
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934656139 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.934656139
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.637612726
Short name T147
Test name
Test status
Simulation time 3144994731 ps
CPU time 3.34 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:46:09 PM PST 24
Peak memory 203384 kb
Host smart-32445810-0ab4-4de5-ac95-4dfcf821de3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637612726 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.637612726
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1546663359
Short name T922
Test name
Test status
Simulation time 1353624183 ps
CPU time 6.17 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:11 PM PST 24
Peak memory 205420 kb
Host smart-df026723-bc26-431b-b396-1d3afc7a6212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546663359 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1546663359
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_perf.3571904733
Short name T667
Test name
Test status
Simulation time 1830653307 ps
CPU time 3.04 seconds
Started Jan 07 01:45:28 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 203316 kb
Host smart-62d2daa5-5825-4002-aa69-ada12b40ec39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571904733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.3571904733
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2192523652
Short name T1103
Test name
Test status
Simulation time 9487860829 ps
CPU time 21.87 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:37 PM PST 24
Peak memory 203388 kb
Host smart-d942176b-0bd4-49ad-99b3-7db9a8389948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192523652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2192523652
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.1410270674
Short name T1162
Test name
Test status
Simulation time 74357900811 ps
CPU time 523.86 seconds
Started Jan 07 01:45:27 PM PST 24
Finished Jan 07 01:54:47 PM PST 24
Peak memory 3400320 kb
Host smart-4c56437e-d84b-4189-809e-931b3ff5da65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410270674 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.1410270674
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.888247270
Short name T277
Test name
Test status
Simulation time 1740160494 ps
CPU time 7.61 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:13 PM PST 24
Peak memory 203140 kb
Host smart-be3551b2-1d15-49f8-9367-19c47fa874e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888247270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.888247270
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.3307512027
Short name T509
Test name
Test status
Simulation time 37872994240 ps
CPU time 186.59 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:50:18 PM PST 24
Peak memory 2099324 kb
Host smart-2b603233-7e5c-4d3c-bddb-c18be0030495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307512027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.3307512027
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.487133290
Short name T1062
Test name
Test status
Simulation time 27446515298 ps
CPU time 260.85 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:51:38 PM PST 24
Peak memory 880632 kb
Host smart-be72c1eb-d4e9-494b-9e91-60e4eb32217d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487133290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.487133290
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.4206918457
Short name T1281
Test name
Test status
Simulation time 6678025817 ps
CPU time 7.64 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 214940 kb
Host smart-f9217ef8-bd79-49c2-9be5-f3ca14339568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206918457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.4206918457
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_ovf.3939229393
Short name T295
Test name
Test status
Simulation time 4063437953 ps
CPU time 105.26 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:49:00 PM PST 24
Peak memory 366972 kb
Host smart-455bffc2-bc3b-4ea7-9824-48999aceb5fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939229393 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_tx_ovf.3939229393
Directory /workspace/35.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.712786301
Short name T499
Test name
Test status
Simulation time 4027375860 ps
CPU time 5.78 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:13 PM PST 24
Peak memory 203348 kb
Host smart-db5d98bb-2778-4b0e-877c-610e5b982d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712786301 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_unexp_stop.712786301
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3026791559
Short name T231
Test name
Test status
Simulation time 1100557374 ps
CPU time 10.69 seconds
Started Jan 07 01:45:23 PM PST 24
Finished Jan 07 01:46:08 PM PST 24
Peak memory 324024 kb
Host smart-ccccd468-1c5e-4238-9c48-e7964c64bc29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026791559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3026791559
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.651759789
Short name T447
Test name
Test status
Simulation time 3626483288 ps
CPU time 69.53 seconds
Started Jan 07 01:45:15 PM PST 24
Finished Jan 07 01:46:54 PM PST 24
Peak memory 494664 kb
Host smart-e5bec642-e6f6-4f37-afce-47ca71a3f72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651759789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.651759789
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2035267004
Short name T1084
Test name
Test status
Simulation time 7058226865 ps
CPU time 315.04 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:51:22 PM PST 24
Peak memory 1621440 kb
Host smart-7f47f12a-e6a6-4bd3-b849-fd168c84009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035267004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2035267004
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3318825297
Short name T197
Test name
Test status
Simulation time 407571712 ps
CPU time 0.9 seconds
Started Jan 07 01:45:20 PM PST 24
Finished Jan 07 01:45:55 PM PST 24
Peak memory 203140 kb
Host smart-7fa7907d-9f4b-4ad8-a5bc-1544380b0407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318825297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3318825297
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.1123460828
Short name T946
Test name
Test status
Simulation time 838550115 ps
CPU time 10.96 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:13 PM PST 24
Peak memory 203412 kb
Host smart-e53b3557-72f2-4bab-9e78-fd8fb59d2ba0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123460828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.1123460828
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.941999759
Short name T737
Test name
Test status
Simulation time 5754287674 ps
CPU time 621.85 seconds
Started Jan 07 01:45:11 PM PST 24
Finished Jan 07 01:56:02 PM PST 24
Peak memory 1550004 kb
Host smart-0f0b5414-2b40-47a5-b530-7608d6ee6f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941999759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.941999759
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3596688485
Short name T351
Test name
Test status
Simulation time 2032321504 ps
CPU time 52.23 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:56 PM PST 24
Peak memory 291740 kb
Host smart-b5d77c83-fada-4e8e-97ce-27b3e2e86f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596688485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3596688485
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.862609026
Short name T347
Test name
Test status
Simulation time 26284550 ps
CPU time 0.63 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 203024 kb
Host smart-3eb8a510-2ec7-4a13-856f-e14659ad4c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862609026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.862609026
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_rx_oversample.3174852510
Short name T41
Test name
Test status
Simulation time 8889761421 ps
CPU time 135.09 seconds
Started Jan 07 01:45:31 PM PST 24
Finished Jan 07 01:48:24 PM PST 24
Peak memory 248424 kb
Host smart-673278d2-12c2-442e-97f1-1f94ca105249
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174852510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_rx_oversample
.3174852510
Directory /workspace/36.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3659822434
Short name T642
Test name
Test status
Simulation time 2683039284 ps
CPU time 30.24 seconds
Started Jan 07 01:45:45 PM PST 24
Finished Jan 07 01:46:55 PM PST 24
Peak memory 251404 kb
Host smart-721003bd-8e7f-4074-a272-170e746d071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659822434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3659822434
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1246594147
Short name T556
Test name
Test status
Simulation time 7140022653 ps
CPU time 53.39 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:54 PM PST 24
Peak memory 212716 kb
Host smart-6062a171-427e-4697-b118-5cf4301a9071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246594147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1246594147
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1614062576
Short name T43
Test name
Test status
Simulation time 1840390402 ps
CPU time 4.03 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:46:23 PM PST 24
Peak memory 203220 kb
Host smart-3dce9978-43a4-452f-94b2-5584a9b4a9ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614062576 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1614062576
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2438499933
Short name T1377
Test name
Test status
Simulation time 10405053795 ps
CPU time 4.23 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:46:11 PM PST 24
Peak memory 210452 kb
Host smart-ac179ed4-b2b5-42ac-8fbf-0f25a633a07d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438499933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2438499933
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1083604893
Short name T1317
Test name
Test status
Simulation time 10135642825 ps
CPU time 78.07 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:47:34 PM PST 24
Peak memory 580464 kb
Host smart-6b14210b-264c-4f8c-9b3c-407534961de8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083604893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1083604893
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.884050846
Short name T486
Test name
Test status
Simulation time 553770429 ps
CPU time 2.45 seconds
Started Jan 07 01:45:44 PM PST 24
Finished Jan 07 01:46:26 PM PST 24
Peak memory 203276 kb
Host smart-fdfe96bf-bf6b-4713-bad5-a5bed908955c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884050846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.884050846
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2183690920
Short name T21
Test name
Test status
Simulation time 1006190128 ps
CPU time 4.33 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 01:46:16 PM PST 24
Peak memory 203336 kb
Host smart-9b8551bd-0603-48a7-a9b9-e8ca59cfa533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183690920 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2183690920
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.112726350
Short name T1117
Test name
Test status
Simulation time 16930853044 ps
CPU time 14.76 seconds
Started Jan 07 01:45:41 PM PST 24
Finished Jan 07 01:46:37 PM PST 24
Peak memory 400004 kb
Host smart-1f13d10f-ffb0-4182-8466-51fcae89590d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112726350 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.112726350
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.554615597
Short name T1071
Test name
Test status
Simulation time 696164697 ps
CPU time 4.12 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 203376 kb
Host smart-e1f3de83-1ac7-476f-905b-8ae3b1584726
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554615597 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_perf.554615597
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1133934806
Short name T518
Test name
Test status
Simulation time 9462622819 ps
CPU time 10.33 seconds
Started Jan 07 01:45:16 PM PST 24
Finished Jan 07 01:45:57 PM PST 24
Peak memory 203460 kb
Host smart-67e7490c-1474-4097-9666-797ec38b6de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133934806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1133934806
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3130934427
Short name T1074
Test name
Test status
Simulation time 6395030932 ps
CPU time 22.51 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:46:38 PM PST 24
Peak memory 225844 kb
Host smart-027d2604-e86b-4f5e-9ef8-a7942195b721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130934427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3130934427
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2620225803
Short name T586
Test name
Test status
Simulation time 36637206774 ps
CPU time 130.88 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:48:30 PM PST 24
Peak memory 1707128 kb
Host smart-96ad9f05-8a94-4f5f-9f1d-13e05e101868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620225803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2620225803
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1769454170
Short name T678
Test name
Test status
Simulation time 11457963724 ps
CPU time 1272.33 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 02:07:32 PM PST 24
Peak memory 2711272 kb
Host smart-ce69ae8c-4e15-4a40-b432-69bf9358e6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769454170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1769454170
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1194588261
Short name T435
Test name
Test status
Simulation time 5263126469 ps
CPU time 8.69 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:46:23 PM PST 24
Peak memory 214536 kb
Host smart-8f1ddb77-92e1-4af7-b3e0-c8da42738844
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194588261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1194588261
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_ovf.733750987
Short name T343
Test name
Test status
Simulation time 39837256890 ps
CPU time 60.99 seconds
Started Jan 07 01:45:29 PM PST 24
Finished Jan 07 01:47:07 PM PST 24
Peak memory 292588 kb
Host smart-cd358505-9eca-4a47-8e98-3abb93e10363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733750987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_tx_ovf.733750987
Directory /workspace/36.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.3334949235
Short name T236
Test name
Test status
Simulation time 5136164990 ps
CPU time 6.17 seconds
Started Jan 07 01:45:43 PM PST 24
Finished Jan 07 01:46:29 PM PST 24
Peak memory 203372 kb
Host smart-7e59debb-7a1e-4925-9608-c51f7b4b5834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334949235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.3334949235
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.223368120
Short name T1008
Test name
Test status
Simulation time 48134232 ps
CPU time 0.6 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 202092 kb
Host smart-d5935e89-fff5-4a16-942c-1e60b19abcf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223368120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.223368120
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.4292078298
Short name T544
Test name
Test status
Simulation time 75173570 ps
CPU time 1.19 seconds
Started Jan 07 01:45:25 PM PST 24
Finished Jan 07 01:46:01 PM PST 24
Peak memory 211480 kb
Host smart-c73b1e24-1b15-4eb7-9def-37eda2c004a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292078298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.4292078298
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.2068612407
Short name T1219
Test name
Test status
Simulation time 3372212567 ps
CPU time 11.26 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:16 PM PST 24
Peak memory 319900 kb
Host smart-d237951b-980e-43d1-a53b-2148bbc6ff02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068612407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.2068612407
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2206102836
Short name T796
Test name
Test status
Simulation time 3055962001 ps
CPU time 62.04 seconds
Started Jan 07 01:45:38 PM PST 24
Finished Jan 07 01:47:20 PM PST 24
Peak memory 427040 kb
Host smart-35e8381b-462b-4618-86c1-831e1049fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206102836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2206102836
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1801698913
Short name T629
Test name
Test status
Simulation time 11137943994 ps
CPU time 662.63 seconds
Started Jan 07 01:46:04 PM PST 24
Finished Jan 07 01:57:46 PM PST 24
Peak memory 1543180 kb
Host smart-914d5923-43dc-45ca-b36f-39fdd2db9aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801698913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1801698913
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.117628121
Short name T1076
Test name
Test status
Simulation time 132564991 ps
CPU time 0.83 seconds
Started Jan 07 01:46:11 PM PST 24
Finished Jan 07 01:46:52 PM PST 24
Peak memory 203184 kb
Host smart-5debecd4-6c42-456a-9d3c-aaaa61258192
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117628121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.117628121
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3901282525
Short name T837
Test name
Test status
Simulation time 1756860334 ps
CPU time 5.29 seconds
Started Jan 07 01:45:18 PM PST 24
Finished Jan 07 01:45:56 PM PST 24
Peak memory 203244 kb
Host smart-6754c981-d499-4129-9a69-32754edf2550
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901282525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3901282525
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1021843447
Short name T192
Test name
Test status
Simulation time 3235124703 ps
CPU time 274.5 seconds
Started Jan 07 01:45:40 PM PST 24
Finished Jan 07 01:50:55 PM PST 24
Peak memory 1000492 kb
Host smart-beffc930-2bb8-438b-94ee-97bb6cf0a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021843447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1021843447
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1533653004
Short name T597
Test name
Test status
Simulation time 4935431086 ps
CPU time 157.14 seconds
Started Jan 07 01:45:45 PM PST 24
Finished Jan 07 01:49:02 PM PST 24
Peak memory 324952 kb
Host smart-0087f2ad-4753-42ce-a380-5450307f8a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533653004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1533653004
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2046367816
Short name T783
Test name
Test status
Simulation time 21858975 ps
CPU time 0.7 seconds
Started Jan 07 01:45:47 PM PST 24
Finished Jan 07 01:46:28 PM PST 24
Peak memory 202340 kb
Host smart-6901ba45-bace-4be3-920e-3cbbafddba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046367816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2046367816
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_rx_oversample.736040402
Short name T186
Test name
Test status
Simulation time 1230281481 ps
CPU time 76.08 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 01:47:58 PM PST 24
Peak memory 251608 kb
Host smart-5648f429-a401-432f-b356-4c27e83f32b0
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736040402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_rx_oversample.
736040402
Directory /workspace/37.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1116413561
Short name T1364
Test name
Test status
Simulation time 10779736849 ps
CPU time 92.28 seconds
Started Jan 07 01:45:59 PM PST 24
Finished Jan 07 01:48:10 PM PST 24
Peak memory 325228 kb
Host smart-98d4f8a2-b208-4d83-9144-e98637997759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116413561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1116413561
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.678856110
Short name T421
Test name
Test status
Simulation time 3856495915 ps
CPU time 42.23 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:50 PM PST 24
Peak memory 211556 kb
Host smart-6a794a6a-7d1b-4a15-a28b-bb4e96fdf8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678856110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.678856110
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2651232203
Short name T1016
Test name
Test status
Simulation time 10489249430 ps
CPU time 10.26 seconds
Started Jan 07 01:45:30 PM PST 24
Finished Jan 07 01:46:18 PM PST 24
Peak memory 280728 kb
Host smart-5a051232-f8c1-4104-ad9b-293493e21aaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651232203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2651232203
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3750309567
Short name T1213
Test name
Test status
Simulation time 2326433832 ps
CPU time 2.94 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:46:17 PM PST 24
Peak memory 203376 kb
Host smart-680c491e-f791-4b8a-800b-25bef12cb1eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750309567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3750309567
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3231262777
Short name T859
Test name
Test status
Simulation time 5367627078 ps
CPU time 5.21 seconds
Started Jan 07 01:45:12 PM PST 24
Finished Jan 07 01:45:46 PM PST 24
Peak memory 203292 kb
Host smart-ba8c73e9-36ce-413d-8b2a-4d3e5b7bf2f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231262777 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3231262777
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2497932032
Short name T727
Test name
Test status
Simulation time 23723616707 ps
CPU time 64.28 seconds
Started Jan 07 01:45:24 PM PST 24
Finished Jan 07 01:47:03 PM PST 24
Peak memory 873224 kb
Host smart-a23c45ae-b3d0-4dd4-a5fc-02a07a3b5b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497932032 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2497932032
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.785279038
Short name T914
Test name
Test status
Simulation time 519205927 ps
CPU time 3.23 seconds
Started Jan 07 01:45:14 PM PST 24
Finished Jan 07 01:45:46 PM PST 24
Peak memory 203340 kb
Host smart-4c2e1ab2-81e2-4427-b091-cb3961383da6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785279038 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_perf.785279038
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3869176127
Short name T284
Test name
Test status
Simulation time 610915524 ps
CPU time 6.62 seconds
Started Jan 07 01:45:26 PM PST 24
Finished Jan 07 01:46:09 PM PST 24
Peak memory 203248 kb
Host smart-80a46ec1-6ec2-4ccf-b1fa-2d1949903924
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869176127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3869176127
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.2736973294
Short name T1321
Test name
Test status
Simulation time 123232095321 ps
CPU time 1742.84 seconds
Started Jan 07 01:45:43 PM PST 24
Finished Jan 07 02:15:25 PM PST 24
Peak memory 3322908 kb
Host smart-03d4bb0c-7b2d-4f52-b0b4-f371a2b6cc78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736973294 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.2736973294
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.205727292
Short name T964
Test name
Test status
Simulation time 7090336928 ps
CPU time 24.3 seconds
Started Jan 07 01:45:32 PM PST 24
Finished Jan 07 01:46:35 PM PST 24
Peak memory 227156 kb
Host smart-32a5d3c7-8f2d-4141-8bf6-f974789af258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205727292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.205727292
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4086818900
Short name T540
Test name
Test status
Simulation time 21238984668 ps
CPU time 452.51 seconds
Started Jan 07 01:45:19 PM PST 24
Finished Jan 07 01:53:25 PM PST 24
Peak memory 4249904 kb
Host smart-0db5492a-9cdc-4425-a0f1-73dacf652036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086818900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4086818900
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.322068623
Short name T960
Test name
Test status
Simulation time 7437720488 ps
CPU time 8.29 seconds
Started Jan 07 01:45:13 PM PST 24
Finished Jan 07 01:45:51 PM PST 24
Peak memory 203356 kb
Host smart-a605cd36-38ae-470d-85a9-79aa42d9e2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322068623 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_unexp_stop.322068623
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2410504595
Short name T473
Test name
Test status
Simulation time 15601501 ps
CPU time 0.61 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:46:16 PM PST 24
Peak memory 202244 kb
Host smart-6a40d5da-7178-4900-acfc-5c89b996650c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410504595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2410504595
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3173636335
Short name T1169
Test name
Test status
Simulation time 78731165 ps
CPU time 1.86 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 219628 kb
Host smart-44eb4b08-0a8e-43ae-bdce-413145d34542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173636335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3173636335
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2595523190
Short name T615
Test name
Test status
Simulation time 926219108 ps
CPU time 8.98 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:46:23 PM PST 24
Peak memory 304300 kb
Host smart-3bbe183a-89df-4245-ba67-5dac10313f39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595523190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2595523190
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2781444009
Short name T1039
Test name
Test status
Simulation time 5842101202 ps
CPU time 95.85 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:47:53 PM PST 24
Peak memory 819420 kb
Host smart-b1f3d72a-5648-4ff8-b3c3-eee9874e1d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781444009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2781444009
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2757387345
Short name T989
Test name
Test status
Simulation time 5494902402 ps
CPU time 639.1 seconds
Started Jan 07 01:45:35 PM PST 24
Finished Jan 07 01:56:53 PM PST 24
Peak memory 1462024 kb
Host smart-d15c5d28-d0a9-4a5d-90ab-4d5e30284623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757387345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2757387345
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3952280480
Short name T1350
Test name
Test status
Simulation time 96228400 ps
CPU time 0.9 seconds
Started Jan 07 01:45:51 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 203372 kb
Host smart-0f907a84-65b6-43ed-90cb-b2229e9d2298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952280480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3952280480
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2431057109
Short name T691
Test name
Test status
Simulation time 1024379155 ps
CPU time 11.29 seconds
Started Jan 07 01:45:43 PM PST 24
Finished Jan 07 01:46:34 PM PST 24
Peak memory 203380 kb
Host smart-ce92cc37-6dbc-44dc-991c-c6ad9ca134b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431057109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.2431057109
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.4201451906
Short name T194
Test name
Test status
Simulation time 30311748340 ps
CPU time 481.69 seconds
Started Jan 07 01:46:02 PM PST 24
Finished Jan 07 01:54:43 PM PST 24
Peak memory 1338560 kb
Host smart-2f41e545-7048-4214-ba73-b7cd06d8f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201451906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.4201451906
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.464705871
Short name T941
Test name
Test status
Simulation time 6707653082 ps
CPU time 98.48 seconds
Started Jan 07 01:45:58 PM PST 24
Finished Jan 07 01:48:16 PM PST 24
Peak memory 380860 kb
Host smart-5cf2415f-fa7b-4284-b006-d5d6563573f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464705871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.464705871
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.4077627818
Short name T4
Test name
Test status
Simulation time 19145526 ps
CPU time 0.66 seconds
Started Jan 07 01:45:48 PM PST 24
Finished Jan 07 01:46:29 PM PST 24
Peak memory 202488 kb
Host smart-7b3cb0e4-7f3b-4665-9245-886e9abadea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077627818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.4077627818
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.4213757184
Short name T689
Test name
Test status
Simulation time 1415675967 ps
CPU time 12.84 seconds
Started Jan 07 01:45:56 PM PST 24
Finished Jan 07 01:46:48 PM PST 24
Peak memory 211420 kb
Host smart-28e5d4d8-2c54-4bee-8e0d-698861fa97b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213757184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.4213757184
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_rx_oversample.2856527437
Short name T354
Test name
Test status
Simulation time 3559350450 ps
CPU time 200.69 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:49:40 PM PST 24
Peak memory 414648 kb
Host smart-cd60272e-59f0-40e9-a50f-108b6823efa7
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856527437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_rx_oversample
.2856527437
Directory /workspace/38.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.683332427
Short name T644
Test name
Test status
Simulation time 130464315163 ps
CPU time 981.57 seconds
Started Jan 07 01:45:38 PM PST 24
Finished Jan 07 02:02:40 PM PST 24
Peak memory 627224 kb
Host smart-4b7d04bb-a3c1-42fb-b6d6-7427f72b2fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683332427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.683332427
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2147148831
Short name T487
Test name
Test status
Simulation time 888034144 ps
CPU time 37.13 seconds
Started Jan 07 01:46:31 PM PST 24
Finished Jan 07 01:47:40 PM PST 24
Peak memory 211444 kb
Host smart-565198a1-f8cf-4ad8-82c9-f00576ab7c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147148831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2147148831
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2030000509
Short name T745
Test name
Test status
Simulation time 10386824732 ps
CPU time 6.58 seconds
Started Jan 07 01:45:40 PM PST 24
Finished Jan 07 01:46:26 PM PST 24
Peak memory 245512 kb
Host smart-c4cd4027-0f1c-49a9-bc90-6baa2ff0e75f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030000509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2030000509
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1857009743
Short name T753
Test name
Test status
Simulation time 10083651361 ps
CPU time 31.42 seconds
Started Jan 07 01:45:32 PM PST 24
Finished Jan 07 01:46:42 PM PST 24
Peak memory 458484 kb
Host smart-99f0099b-b4d4-403b-bdfa-3736924e79fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857009743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1857009743
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.14117895
Short name T982
Test name
Test status
Simulation time 489588662 ps
CPU time 2.49 seconds
Started Jan 07 01:45:51 PM PST 24
Finished Jan 07 01:46:34 PM PST 24
Peak memory 203316 kb
Host smart-7bd82319-68f0-4a18-af06-78370c5aec0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14117895 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.i2c_target_hrst.14117895
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.914106234
Short name T854
Test name
Test status
Simulation time 6672848565 ps
CPU time 7.27 seconds
Started Jan 07 01:45:34 PM PST 24
Finished Jan 07 01:46:21 PM PST 24
Peak memory 209568 kb
Host smart-50d9098e-eec7-4f92-aba0-feac04ce4000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914106234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.914106234
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.676341425
Short name T489
Test name
Test status
Simulation time 18260297439 ps
CPU time 41.29 seconds
Started Jan 07 01:45:56 PM PST 24
Finished Jan 07 01:47:17 PM PST 24
Peak memory 672844 kb
Host smart-ebfe55b2-4460-45d9-bfed-40d295eea7be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676341425 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.676341425
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.251850781
Short name T298
Test name
Test status
Simulation time 764254919 ps
CPU time 4.32 seconds
Started Jan 07 01:45:54 PM PST 24
Finished Jan 07 01:46:38 PM PST 24
Peak memory 203296 kb
Host smart-e8829a4f-1890-4fc2-87f4-e5d2b16cd479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251850781 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_perf.251850781
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2175571993
Short name T681
Test name
Test status
Simulation time 1558233010 ps
CPU time 39.28 seconds
Started Jan 07 01:45:40 PM PST 24
Finished Jan 07 01:47:00 PM PST 24
Peak memory 203176 kb
Host smart-f50d42ec-05bd-49bd-b072-c6088d37a4d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175571993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2175571993
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3972522882
Short name T1322
Test name
Test status
Simulation time 1514138597 ps
CPU time 54.1 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:47:10 PM PST 24
Peak memory 203204 kb
Host smart-9831d3a0-edb1-4378-8c9e-97a334087d6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972522882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3972522882
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.337071373
Short name T920
Test name
Test status
Simulation time 58149275896 ps
CPU time 350.19 seconds
Started Jan 07 01:46:01 PM PST 24
Finished Jan 07 01:52:31 PM PST 24
Peak memory 2860452 kb
Host smart-94069e68-0db6-42cc-8a0f-a8afde743f34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337071373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.337071373
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.4265836957
Short name T62
Test name
Test status
Simulation time 14916137690 ps
CPU time 57.26 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 01:47:10 PM PST 24
Peak memory 815256 kb
Host smart-7989dac4-3966-4329-ad65-b0d94fe7a647
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265836957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.4265836957
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1289600541
Short name T659
Test name
Test status
Simulation time 5155611629 ps
CPU time 7.59 seconds
Started Jan 07 01:45:53 PM PST 24
Finished Jan 07 01:46:40 PM PST 24
Peak memory 206836 kb
Host smart-fe7f3638-6183-4cd7-81cc-704eabcfccdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289600541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1289600541
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_ovf.3134058408
Short name T773
Test name
Test status
Simulation time 29328449877 ps
CPU time 76.49 seconds
Started Jan 07 01:45:54 PM PST 24
Finished Jan 07 01:47:50 PM PST 24
Peak memory 325744 kb
Host smart-4b781797-82f4-4665-a396-d6dfd5b44b2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134058408 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_tx_ovf.3134058408
Directory /workspace/38.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.903456232
Short name T616
Test name
Test status
Simulation time 1671110690 ps
CPU time 5.67 seconds
Started Jan 07 01:45:59 PM PST 24
Finished Jan 07 01:46:44 PM PST 24
Peak memory 203260 kb
Host smart-7329aba3-d269-44b1-9407-673d915bd47b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903456232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_unexp_stop.903456232
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.4262854330
Short name T1129
Test name
Test status
Simulation time 43498127 ps
CPU time 0.58 seconds
Started Jan 07 01:46:04 PM PST 24
Finished Jan 07 01:46:44 PM PST 24
Peak memory 202020 kb
Host smart-fd91ddf4-f8e5-4d70-9cd1-3294e220a4ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262854330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.4262854330
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.388612399
Short name T665
Test name
Test status
Simulation time 75890399 ps
CPU time 1.25 seconds
Started Jan 07 01:45:51 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 219688 kb
Host smart-1e153c12-5fd2-4d4f-9c1f-5a1dff498189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388612399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.388612399
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.4106598539
Short name T802
Test name
Test status
Simulation time 1401063567 ps
CPU time 17.84 seconds
Started Jan 07 01:45:56 PM PST 24
Finished Jan 07 01:46:53 PM PST 24
Peak memory 279436 kb
Host smart-19b094c1-9c02-4d65-81c6-56e4cd376456
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106598539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.4106598539
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3909836964
Short name T613
Test name
Test status
Simulation time 926538700 ps
CPU time 0.76 seconds
Started Jan 07 01:45:50 PM PST 24
Finished Jan 07 01:46:31 PM PST 24
Peak memory 202524 kb
Host smart-5ace85d3-4129-439c-85c7-b67be7cdbca8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909836964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3909836964
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1828862892
Short name T877
Test name
Test status
Simulation time 1006060119 ps
CPU time 5.47 seconds
Started Jan 07 01:45:38 PM PST 24
Finished Jan 07 01:46:24 PM PST 24
Peak memory 203376 kb
Host smart-7cf6c66e-36fa-4f60-aa1a-78b6d3f4ed7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828862892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1828862892
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3268762039
Short name T193
Test name
Test status
Simulation time 19796746208 ps
CPU time 610.97 seconds
Started Jan 07 01:45:36 PM PST 24
Finished Jan 07 01:56:28 PM PST 24
Peak memory 1481584 kb
Host smart-1eaf9de8-5e14-49bc-84ae-18e1be06582d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268762039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3268762039
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1463477680
Short name T359
Test name
Test status
Simulation time 8363579675 ps
CPU time 92.35 seconds
Started Jan 07 01:45:59 PM PST 24
Finished Jan 07 01:48:11 PM PST 24
Peak memory 326300 kb
Host smart-ba6ad5cf-aaab-481a-bc41-2983f00f57a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463477680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1463477680
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.450080135
Short name T323
Test name
Test status
Simulation time 16125127 ps
CPU time 0.62 seconds
Started Jan 07 01:45:41 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 203020 kb
Host smart-74a72490-0a32-4d11-a526-6b7038305073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450080135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.450080135
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1379056508
Short name T1254
Test name
Test status
Simulation time 7532402519 ps
CPU time 75.54 seconds
Started Jan 07 01:45:56 PM PST 24
Finished Jan 07 01:47:51 PM PST 24
Peak memory 203340 kb
Host smart-ce3da71b-8e04-4fa0-871a-712056c8d982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379056508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1379056508
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_rx_oversample.1376962988
Short name T1136
Test name
Test status
Simulation time 3461525495 ps
CPU time 271.82 seconds
Started Jan 07 01:45:37 PM PST 24
Finished Jan 07 01:50:49 PM PST 24
Peak memory 295332 kb
Host smart-7027c613-e0e9-4b3a-8508-ed2a3f2f6015
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376962988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_rx_oversample
.1376962988
Directory /workspace/39.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2203083208
Short name T1303
Test name
Test status
Simulation time 5925898601 ps
CPU time 32.11 seconds
Started Jan 07 01:45:55 PM PST 24
Finished Jan 07 01:47:07 PM PST 24
Peak memory 247460 kb
Host smart-eaf7ecb8-c832-4ed6-bef8-9aba4b546670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203083208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2203083208
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.196584657
Short name T656
Test name
Test status
Simulation time 2151725703 ps
CPU time 39.15 seconds
Started Jan 07 01:45:39 PM PST 24
Finished Jan 07 01:46:58 PM PST 24
Peak memory 219724 kb
Host smart-525e79c0-b967-414d-9d97-e8d28e69a7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196584657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.196584657
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.4091843109
Short name T44
Test name
Test status
Simulation time 1042166989 ps
CPU time 3.07 seconds
Started Jan 07 01:45:53 PM PST 24
Finished Jan 07 01:46:36 PM PST 24
Peak memory 203348 kb
Host smart-4ab9067d-74e7-41f8-b31c-3a8733ee3350
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091843109 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.4091843109
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1619582866
Short name T432
Test name
Test status
Simulation time 10109504462 ps
CPU time 53.41 seconds
Started Jan 07 01:46:08 PM PST 24
Finished Jan 07 01:47:40 PM PST 24
Peak memory 494812 kb
Host smart-d0e71c03-ae16-4018-bf55-e6e2a22afa41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619582866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1619582866
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2879286172
Short name T269
Test name
Test status
Simulation time 888836945 ps
CPU time 2.3 seconds
Started Jan 07 01:46:28 PM PST 24
Finished Jan 07 01:47:03 PM PST 24
Peak memory 203376 kb
Host smart-c64dd4be-f4dd-4077-a5dd-5f5430ec3417
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879286172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2879286172
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1696497982
Short name T273
Test name
Test status
Simulation time 3334948179 ps
CPU time 3.67 seconds
Started Jan 07 01:45:48 PM PST 24
Finished Jan 07 01:46:32 PM PST 24
Peak memory 204488 kb
Host smart-6a0a72d0-361f-4eed-9fdd-d90e58f29370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696497982 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1696497982
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.620325682
Short name T530
Test name
Test status
Simulation time 20372879554 ps
CPU time 945.85 seconds
Started Jan 07 01:45:49 PM PST 24
Finished Jan 07 02:02:15 PM PST 24
Peak memory 4879340 kb
Host smart-ff910425-0e7c-4fc3-84eb-0fb0917c94fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620325682 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.620325682
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.2625906753
Short name T898
Test name
Test status
Simulation time 669026205 ps
CPU time 3.95 seconds
Started Jan 07 01:45:54 PM PST 24
Finished Jan 07 01:46:38 PM PST 24
Peak memory 207644 kb
Host smart-6c056880-6568-4ad1-9fb2-02c05ee7bd86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625906753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_perf.2625906753
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3094314688
Short name T1215
Test name
Test status
Simulation time 2156978274 ps
CPU time 13.78 seconds
Started Jan 07 01:45:45 PM PST 24
Finished Jan 07 01:46:38 PM PST 24
Peak memory 203288 kb
Host smart-b69f1e16-43a8-49df-89a7-d1356e4ccbe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094314688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3094314688
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.886877360
Short name T285
Test name
Test status
Simulation time 50238967054 ps
CPU time 1959.03 seconds
Started Jan 07 01:45:58 PM PST 24
Finished Jan 07 02:19:16 PM PST 24
Peak memory 1615560 kb
Host smart-705f09ac-750f-45dc-ae35-9bce58bb30e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886877360 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.i2c_target_stress_all.886877360
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.4187350736
Short name T475
Test name
Test status
Simulation time 1631838715 ps
CPU time 66.2 seconds
Started Jan 07 01:45:38 PM PST 24
Finished Jan 07 01:47:25 PM PST 24
Peak memory 203288 kb
Host smart-fb9ae924-64d6-4535-95c7-06fe868bf09c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187350736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.4187350736
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3843590354
Short name T1
Test name
Test status
Simulation time 12301170429 ps
CPU time 125.7 seconds
Started Jan 07 01:45:59 PM PST 24
Finished Jan 07 01:48:44 PM PST 24
Peak memory 2109956 kb
Host smart-961ebb6e-7882-411a-aece-854af492bcea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843590354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3843590354
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3261022522
Short name T1257
Test name
Test status
Simulation time 40158727640 ps
CPU time 1211.58 seconds
Started Jan 07 01:45:56 PM PST 24
Finished Jan 07 02:06:47 PM PST 24
Peak memory 4016384 kb
Host smart-0584aded-d84d-40f0-950c-13a58598565f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261022522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3261022522
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3188887583
Short name T1128
Test name
Test status
Simulation time 6436882430 ps
CPU time 6.72 seconds
Started Jan 07 01:46:04 PM PST 24
Finished Jan 07 01:46:49 PM PST 24
Peak memory 203380 kb
Host smart-38d0d217-4006-4139-b58f-4abd5e350700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188887583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3188887583
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_ovf.3062845311
Short name T1156
Test name
Test status
Simulation time 13711021183 ps
CPU time 107.29 seconds
Started Jan 07 01:45:40 PM PST 24
Finished Jan 07 01:48:08 PM PST 24
Peak memory 351296 kb
Host smart-90508faf-2629-4c6e-a885-aa7e82fe44a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062845311 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_tx_ovf.3062845311
Directory /workspace/39.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.680647785
Short name T792
Test name
Test status
Simulation time 1648867284 ps
CPU time 7.54 seconds
Started Jan 07 01:45:33 PM PST 24
Finished Jan 07 01:46:20 PM PST 24
Peak memory 203248 kb
Host smart-3637b09e-3491-495d-a724-1e0df0144564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680647785 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_unexp_stop.680647785
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3780543852
Short name T1342
Test name
Test status
Simulation time 59459467 ps
CPU time 0.6 seconds
Started Jan 07 01:43:41 PM PST 24
Finished Jan 07 01:43:57 PM PST 24
Peak memory 202144 kb
Host smart-3c6df70b-c54b-40c4-8cdb-165a2cdf729c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780543852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3780543852
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3660065841
Short name T301
Test name
Test status
Simulation time 83235042 ps
CPU time 1.27 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 01:43:28 PM PST 24
Peak memory 213512 kb
Host smart-6370ca31-617f-4520-adcf-d1469d0ad080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660065841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3660065841
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1717873667
Short name T266
Test name
Test status
Simulation time 2099001388 ps
CPU time 27.88 seconds
Started Jan 07 01:42:56 PM PST 24
Finished Jan 07 01:43:41 PM PST 24
Peak memory 319900 kb
Host smart-08da953f-f67d-4e5d-b273-a11bdc27809e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717873667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1717873667
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1906279179
Short name T500
Test name
Test status
Simulation time 11826196638 ps
CPU time 78.3 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:44:51 PM PST 24
Peak memory 624636 kb
Host smart-15bd4d30-63df-41b0-950d-f2e15b2436b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906279179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1906279179
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.599717490
Short name T798
Test name
Test status
Simulation time 10684148370 ps
CPU time 307.08 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 01:48:33 PM PST 24
Peak memory 1501420 kb
Host smart-b00522a1-31b1-47c0-b7ce-07ec5ac86a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599717490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.599717490
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1928500273
Short name T1022
Test name
Test status
Simulation time 638769247 ps
CPU time 0.89 seconds
Started Jan 07 01:42:54 PM PST 24
Finished Jan 07 01:43:12 PM PST 24
Peak memory 203188 kb
Host smart-8340f7ef-a530-4a1f-9a45-463748933c91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928500273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1928500273
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2031886063
Short name T511
Test name
Test status
Simulation time 2131916924 ps
CPU time 117.1 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:45:43 PM PST 24
Peak memory 250428 kb
Host smart-ff034b5d-1d8f-4561-8f5a-e67a4f9c0a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031886063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2031886063
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.945423002
Short name T1214
Test name
Test status
Simulation time 15406444 ps
CPU time 0.65 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 01:43:28 PM PST 24
Peak memory 202400 kb
Host smart-41992b78-8c6d-4035-a756-8078fb101480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945423002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.945423002
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1391027457
Short name T1082
Test name
Test status
Simulation time 51145619787 ps
CPU time 822.5 seconds
Started Jan 07 01:42:57 PM PST 24
Finished Jan 07 01:56:56 PM PST 24
Peak memory 367576 kb
Host smart-8713b89d-6936-4315-88ca-1323d41743ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391027457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1391027457
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_rx_oversample.4111603906
Short name T624
Test name
Test status
Simulation time 2810469508 ps
CPU time 102.54 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:45:20 PM PST 24
Peak memory 252352 kb
Host smart-6680da3c-d41d-4abd-a8c6-96ce755185e2
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111603906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_rx_oversample.
4111603906
Directory /workspace/4.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2900503275
Short name T529
Test name
Test status
Simulation time 1569384657 ps
CPU time 81.03 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:44:53 PM PST 24
Peak memory 233076 kb
Host smart-57ce09f9-2448-49f9-8222-f578fa0919b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900503275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2900503275
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.549587248
Short name T344
Test name
Test status
Simulation time 58177645734 ps
CPU time 2264.42 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 02:21:24 PM PST 24
Peak memory 2708500 kb
Host smart-a33e44a4-68a4-4e94-b6c9-307ec0ac2fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549587248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.549587248
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2681993145
Short name T743
Test name
Test status
Simulation time 1947382456 ps
CPU time 17.18 seconds
Started Jan 07 01:42:59 PM PST 24
Finished Jan 07 01:43:32 PM PST 24
Peak memory 219644 kb
Host smart-71831859-beb9-4288-b870-4cb0d3a49a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681993145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2681993145
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1057227887
Short name T702
Test name
Test status
Simulation time 5395705753 ps
CPU time 5.04 seconds
Started Jan 07 01:43:40 PM PST 24
Finished Jan 07 01:44:01 PM PST 24
Peak memory 203384 kb
Host smart-e849c03f-effb-48da-9a08-634242245a45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057227887 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1057227887
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3691300322
Short name T835
Test name
Test status
Simulation time 10041816581 ps
CPU time 57.21 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:44:43 PM PST 24
Peak memory 469864 kb
Host smart-e6325045-63e5-4452-924a-2f7070bdabd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691300322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3691300322
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.381523569
Short name T16
Test name
Test status
Simulation time 10199568353 ps
CPU time 12.79 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:21 PM PST 24
Peak memory 287548 kb
Host smart-8a352120-0cfb-4824-a6f1-fbfa8fd3ec14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381523569 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.381523569
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1052398337
Short name T379
Test name
Test status
Simulation time 1058548356 ps
CPU time 2.55 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 01:43:41 PM PST 24
Peak memory 203180 kb
Host smart-09644879-c740-476f-b335-66ee08840e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052398337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1052398337
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.508345631
Short name T611
Test name
Test status
Simulation time 1971928250 ps
CPU time 4.66 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:43:54 PM PST 24
Peak memory 203256 kb
Host smart-df2c335f-f6b6-49ba-8cef-256822e127b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508345631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.508345631
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2239931834
Short name T406
Test name
Test status
Simulation time 18239115384 ps
CPU time 700.4 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:55:24 PM PST 24
Peak memory 4260224 kb
Host smart-ddd6ad42-1173-4a46-bed5-ca178bc0ae07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239931834 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2239931834
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.1550832726
Short name T977
Test name
Test status
Simulation time 531364512 ps
CPU time 3.29 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:43:54 PM PST 24
Peak memory 203204 kb
Host smart-3bd8fc19-c8da-4c02-9903-c11334db76a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550832726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.1550832726
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3081477154
Short name T259
Test name
Test status
Simulation time 1492112862 ps
CPU time 9.43 seconds
Started Jan 07 01:42:49 PM PST 24
Finished Jan 07 01:43:18 PM PST 24
Peak memory 203240 kb
Host smart-d9fbe984-3f8b-4bee-9839-924db21e579e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081477154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3081477154
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.427062596
Short name T666
Test name
Test status
Simulation time 31566463566 ps
CPU time 691.56 seconds
Started Jan 07 01:43:42 PM PST 24
Finished Jan 07 01:55:29 PM PST 24
Peak memory 3922332 kb
Host smart-c9e6b35d-a4da-4fdd-a177-fb6d62a4f2c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427062596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.i2c_target_stress_all.427062596
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.414812000
Short name T401
Test name
Test status
Simulation time 9115272239 ps
CPU time 92.97 seconds
Started Jan 07 01:43:11 PM PST 24
Finished Jan 07 01:44:57 PM PST 24
Peak memory 205032 kb
Host smart-bd0cf085-9a51-43ac-8d93-222198427c44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414812000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.414812000
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.671262194
Short name T444
Test name
Test status
Simulation time 55608826661 ps
CPU time 715.33 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:55:33 PM PST 24
Peak memory 2937212 kb
Host smart-aa0e5626-f11f-4f41-a734-a85be0d35039
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671262194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.671262194
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1390239273
Short name T407
Test name
Test status
Simulation time 3668744812 ps
CPU time 7.2 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:43:37 PM PST 24
Peak memory 212288 kb
Host smart-fc3d8350-2c75-4ec5-b445-a163f2087757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390239273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1390239273
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.1737713952
Short name T1175
Test name
Test status
Simulation time 5554496253 ps
CPU time 6.61 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:44 PM PST 24
Peak memory 204132 kb
Host smart-32ab8d12-9340-4d96-a207-f3c1e1cdac2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737713952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.1737713952
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3452840188
Short name T603
Test name
Test status
Simulation time 16352254 ps
CPU time 0.61 seconds
Started Jan 07 01:45:50 PM PST 24
Finished Jan 07 01:46:31 PM PST 24
Peak memory 203232 kb
Host smart-b82aa755-49d1-4d7f-ab61-c8602214fbb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452840188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3452840188
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3039729863
Short name T211
Test name
Test status
Simulation time 166863252 ps
CPU time 1.66 seconds
Started Jan 07 01:46:11 PM PST 24
Finished Jan 07 01:46:53 PM PST 24
Peak memory 203228 kb
Host smart-97475943-da81-49fa-904d-beae99e5fa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039729863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3039729863
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1348373376
Short name T660
Test name
Test status
Simulation time 460400821 ps
CPU time 8.35 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 301336 kb
Host smart-b73971eb-5245-4706-864f-ecfc52d43a22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348373376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1348373376
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3894654716
Short name T491
Test name
Test status
Simulation time 8761503087 ps
CPU time 163.08 seconds
Started Jan 07 01:46:16 PM PST 24
Finished Jan 07 01:49:37 PM PST 24
Peak memory 727324 kb
Host smart-52c3ad74-cac9-43b3-88ec-2cf8b316ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894654716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3894654716
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2054585965
Short name T1283
Test name
Test status
Simulation time 5939469196 ps
CPU time 396.84 seconds
Started Jan 07 01:46:11 PM PST 24
Finished Jan 07 01:53:28 PM PST 24
Peak memory 1656196 kb
Host smart-9c83c71e-1aad-4468-94c3-1774557062a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054585965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2054585965
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.926711453
Short name T1018
Test name
Test status
Simulation time 165591754 ps
CPU time 1.14 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:14 PM PST 24
Peak memory 203252 kb
Host smart-2a2d928d-61db-42a4-bdd0-e4a8941efc03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926711453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.926711453
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2453914538
Short name T1021
Test name
Test status
Simulation time 227746685 ps
CPU time 4.64 seconds
Started Jan 07 01:46:17 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 203292 kb
Host smart-148cb7ed-d455-4689-b803-9db755d1970f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453914538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2453914538
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.4059912392
Short name T1007
Test name
Test status
Simulation time 20882638364 ps
CPU time 269.47 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 01:51:08 PM PST 24
Peak memory 1538688 kb
Host smart-c9d44614-2da6-4cf2-9efb-9d3c242e2b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059912392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.4059912392
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1585823791
Short name T961
Test name
Test status
Simulation time 2609336515 ps
CPU time 147.48 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:49:33 PM PST 24
Peak memory 260072 kb
Host smart-7453a8a2-7625-41a5-9985-40568f1a524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585823791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1585823791
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3479567538
Short name T817
Test name
Test status
Simulation time 51449546 ps
CPU time 0.62 seconds
Started Jan 07 01:46:01 PM PST 24
Finished Jan 07 01:46:41 PM PST 24
Peak memory 202460 kb
Host smart-231e99f0-cf05-4876-9c56-8e6f0b202a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479567538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3479567538
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3476964276
Short name T1353
Test name
Test status
Simulation time 404950917 ps
CPU time 2.28 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:47:07 PM PST 24
Peak memory 211540 kb
Host smart-2f5def94-d99d-471f-a441-de26c9d7bbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476964276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3476964276
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_rx_oversample.2978730712
Short name T847
Test name
Test status
Simulation time 9359345613 ps
CPU time 139.45 seconds
Started Jan 07 01:46:14 PM PST 24
Finished Jan 07 01:49:13 PM PST 24
Peak memory 276592 kb
Host smart-ab27b9aa-3e43-4df1-84ac-18bfbd482733
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978730712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_rx_oversample
.2978730712
Directory /workspace/40.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2834469569
Short name T1199
Test name
Test status
Simulation time 15883009981 ps
CPU time 60.86 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 01:47:43 PM PST 24
Peak memory 342356 kb
Host smart-1f52d477-fa22-40b8-b250-41c617fc4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834469569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2834469569
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2944013693
Short name T1326
Test name
Test status
Simulation time 113603170551 ps
CPU time 3236.82 seconds
Started Jan 07 01:46:12 PM PST 24
Finished Jan 07 02:40:49 PM PST 24
Peak memory 1593032 kb
Host smart-8467c187-09a0-425c-8683-e1083db87bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944013693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2944013693
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2584259431
Short name T1299
Test name
Test status
Simulation time 1730660558 ps
CPU time 13.56 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:47:28 PM PST 24
Peak memory 216384 kb
Host smart-8dc3d4c7-92f9-4376-aeba-5b1ac128ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584259431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2584259431
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1314144034
Short name T1376
Test name
Test status
Simulation time 3782680905 ps
CPU time 3.35 seconds
Started Jan 07 01:46:02 PM PST 24
Finished Jan 07 01:46:44 PM PST 24
Peak memory 203416 kb
Host smart-764e72df-2193-44d1-90cb-9e779ce07af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314144034 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1314144034
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2369568417
Short name T99
Test name
Test status
Simulation time 10472514728 ps
CPU time 12.23 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:16 PM PST 24
Peak memory 255620 kb
Host smart-e61d5304-52d1-46ff-9f1a-f87c72988346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369568417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2369568417
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.680702573
Short name T707
Test name
Test status
Simulation time 11831952777 ps
CPU time 4.52 seconds
Started Jan 07 01:46:05 PM PST 24
Finished Jan 07 01:46:48 PM PST 24
Peak memory 224412 kb
Host smart-5b56a8ef-e70d-46a0-b348-43a56f5a1842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680702573 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.680702573
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1998284813
Short name T949
Test name
Test status
Simulation time 2053762708 ps
CPU time 2.55 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 203252 kb
Host smart-b7f7df79-3547-4f88-9feb-3e2b299cf9d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998284813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1998284813
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.616444430
Short name T264
Test name
Test status
Simulation time 9967693771 ps
CPU time 3.55 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:09 PM PST 24
Peak memory 203204 kb
Host smart-28ac478d-71ed-46f4-9390-ef740f75132e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616444430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.616444430
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.625750468
Short name T551
Test name
Test status
Simulation time 4938222471 ps
CPU time 41.52 seconds
Started Jan 07 01:45:48 PM PST 24
Finished Jan 07 01:47:10 PM PST 24
Peak memory 1015272 kb
Host smart-0a74a3c1-573c-4388-9c54-3bfe49f1aa3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625750468 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.625750468
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.749198283
Short name T803
Test name
Test status
Simulation time 2064208764 ps
CPU time 3.15 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:13 PM PST 24
Peak memory 203276 kb
Host smart-27f81b2b-ff4d-463a-8c47-9656e23716c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749198283 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_perf.749198283
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2004253466
Short name T1115
Test name
Test status
Simulation time 6042918306 ps
CPU time 17.63 seconds
Started Jan 07 01:46:05 PM PST 24
Finished Jan 07 01:47:02 PM PST 24
Peak memory 203252 kb
Host smart-69ce8631-af81-42c3-8965-17b4e811735b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004253466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2004253466
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.2619622203
Short name T936
Test name
Test status
Simulation time 37923502522 ps
CPU time 1273.81 seconds
Started Jan 07 01:46:28 PM PST 24
Finished Jan 07 02:08:15 PM PST 24
Peak memory 6541360 kb
Host smart-266e5663-6b23-409b-bc98-d85c2c23405a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619622203 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.2619622203
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2040336370
Short name T304
Test name
Test status
Simulation time 889166487 ps
CPU time 5.53 seconds
Started Jan 07 01:45:59 PM PST 24
Finished Jan 07 01:46:44 PM PST 24
Peak memory 203148 kb
Host smart-4b907b49-9ac0-4c0f-80d6-f9a398583662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040336370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2040336370
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3910535888
Short name T853
Test name
Test status
Simulation time 18431934703 ps
CPU time 1142.16 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 02:05:44 PM PST 24
Peak memory 4280108 kb
Host smart-09a31732-9ac4-4b47-9000-26a5428813c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910535888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3910535888
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.2153991490
Short name T300
Test name
Test status
Simulation time 1272496773 ps
CPU time 5.72 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:11 PM PST 24
Peak memory 203312 kb
Host smart-1c839c12-4c69-4039-9705-4215024da238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153991490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.2153991490
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.3808667873
Short name T506
Test name
Test status
Simulation time 5639570147 ps
CPU time 10.49 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 01:46:50 PM PST 24
Peak memory 210552 kb
Host smart-dc9750e6-c39f-4798-83b3-bf3c3dba73c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808667873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.i2c_target_unexp_stop.3808667873
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.4117448391
Short name T308
Test name
Test status
Simulation time 15969906 ps
CPU time 0.6 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 01:46:40 PM PST 24
Peak memory 202132 kb
Host smart-4d74789e-78dd-4785-aeff-de6158fc3847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117448391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.4117448391
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1532526896
Short name T1319
Test name
Test status
Simulation time 117702369 ps
CPU time 1.11 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:47:07 PM PST 24
Peak memory 211564 kb
Host smart-6588c1a6-842d-4a30-b686-24535981c530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532526896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1532526896
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.4182283170
Short name T464
Test name
Test status
Simulation time 904935132 ps
CPU time 5.1 seconds
Started Jan 07 01:46:11 PM PST 24
Finished Jan 07 01:46:56 PM PST 24
Peak memory 244240 kb
Host smart-8de49ca8-85dd-44a9-b05b-b19a7d294d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182283170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.4182283170
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3830986673
Short name T488
Test name
Test status
Simulation time 14020620618 ps
CPU time 155.97 seconds
Started Jan 07 01:45:53 PM PST 24
Finished Jan 07 01:49:09 PM PST 24
Peak memory 1079964 kb
Host smart-a864b6eb-1319-4111-95fa-d7609b12e1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830986673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3830986673
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.4198859589
Short name T799
Test name
Test status
Simulation time 10274860558 ps
CPU time 610.14 seconds
Started Jan 07 01:45:57 PM PST 24
Finished Jan 07 01:56:47 PM PST 24
Peak memory 1462316 kb
Host smart-2ea89652-13e8-4516-998b-da02b6b5fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198859589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.4198859589
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.332707251
Short name T1101
Test name
Test status
Simulation time 396493851 ps
CPU time 0.85 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:04 PM PST 24
Peak memory 203064 kb
Host smart-70af26ec-0b66-4a2d-83e5-de444758df6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332707251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.332707251
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3123731170
Short name T1311
Test name
Test status
Simulation time 524823005 ps
CPU time 2.85 seconds
Started Jan 07 01:45:54 PM PST 24
Finished Jan 07 01:46:37 PM PST 24
Peak memory 203328 kb
Host smart-996f2a2e-b0ce-4be2-8baf-0e92bc03b4aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123731170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3123731170
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2491577983
Short name T722
Test name
Test status
Simulation time 68049568262 ps
CPU time 196.02 seconds
Started Jan 07 01:46:30 PM PST 24
Finished Jan 07 01:50:18 PM PST 24
Peak memory 1178168 kb
Host smart-8d77065f-9eeb-436d-a26b-ce3f8c303086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491577983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2491577983
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2603197667
Short name T40
Test name
Test status
Simulation time 2682513601 ps
CPU time 54.63 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 01:47:34 PM PST 24
Peak memory 280252 kb
Host smart-2c583c19-898b-4ff9-aca5-7eedfcd546e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603197667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2603197667
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.290309224
Short name T705
Test name
Test status
Simulation time 24775435 ps
CPU time 0.62 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 01:46:50 PM PST 24
Peak memory 202356 kb
Host smart-6196f624-62f6-429d-8e18-30b91f4cdb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290309224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.290309224
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2964498380
Short name T443
Test name
Test status
Simulation time 547884163 ps
CPU time 5.9 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 01:46:56 PM PST 24
Peak memory 211468 kb
Host smart-59a9ac4c-7798-489b-93f9-0fc36211945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964498380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2964498380
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_rx_oversample.2153458658
Short name T794
Test name
Test status
Simulation time 2640882993 ps
CPU time 92.63 seconds
Started Jan 07 01:46:13 PM PST 24
Finished Jan 07 01:48:25 PM PST 24
Peak memory 309076 kb
Host smart-a1679d42-63be-45ad-9546-14c023ea346f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153458658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_rx_oversample
.2153458658
Directory /workspace/41.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3393643984
Short name T1090
Test name
Test status
Simulation time 1542109895 ps
CPU time 41.46 seconds
Started Jan 07 01:45:51 PM PST 24
Finished Jan 07 01:47:13 PM PST 24
Peak memory 251240 kb
Host smart-cbd2bcf0-eefc-45c9-93ce-d3a6964b3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393643984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3393643984
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.1998398743
Short name T183
Test name
Test status
Simulation time 61383394190 ps
CPU time 2433.48 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 02:27:13 PM PST 24
Peak memory 2153036 kb
Host smart-89d69091-1799-4588-9282-3c63496c3951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998398743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.1998398743
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3290123669
Short name T297
Test name
Test status
Simulation time 2727132635 ps
CPU time 27.16 seconds
Started Jan 07 01:46:02 PM PST 24
Finished Jan 07 01:47:08 PM PST 24
Peak memory 211584 kb
Host smart-0121ce89-0c5e-47ec-bea5-a0a91a46a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290123669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3290123669
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2364122438
Short name T893
Test name
Test status
Simulation time 8664088599 ps
CPU time 3.93 seconds
Started Jan 07 01:46:14 PM PST 24
Finished Jan 07 01:46:57 PM PST 24
Peak memory 203328 kb
Host smart-b542bfc8-c645-42e4-8b2c-e475f138d600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364122438 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2364122438
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3107907101
Short name T345
Test name
Test status
Simulation time 10066200782 ps
CPU time 61.32 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:48:18 PM PST 24
Peak memory 515628 kb
Host smart-61bfd468-5c87-434b-a2ab-6c753f82fa19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107907101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3107907101
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.4023512704
Short name T770
Test name
Test status
Simulation time 10174838536 ps
CPU time 27.35 seconds
Started Jan 07 01:46:09 PM PST 24
Finished Jan 07 01:47:16 PM PST 24
Peak memory 383624 kb
Host smart-74e7f5d6-24fc-40c8-830b-03e4ed59f57e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023512704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.4023512704
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.402081666
Short name T154
Test name
Test status
Simulation time 6290730116 ps
CPU time 3.16 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 203356 kb
Host smart-6fcc3c86-8124-4160-b9f6-2fb0d82050de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402081666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_hrst.402081666
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.299432379
Short name T953
Test name
Test status
Simulation time 10687619975 ps
CPU time 30.34 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:47:43 PM PST 24
Peak memory 685024 kb
Host smart-a60597cb-6b1f-4165-a7f3-ff82c12fca18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299432379 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.299432379
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.2549520152
Short name T1262
Test name
Test status
Simulation time 2187106200 ps
CPU time 3.51 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:19 PM PST 24
Peak memory 203460 kb
Host smart-fd49707f-dade-45a2-ad73-78ddaf6bd714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549520152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.2549520152
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3359208330
Short name T883
Test name
Test status
Simulation time 3022486726 ps
CPU time 14.57 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 01:46:56 PM PST 24
Peak memory 203380 kb
Host smart-eb2b573a-6114-4e29-a104-4d998cf68164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359208330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3359208330
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.3142059650
Short name T728
Test name
Test status
Simulation time 4762110807 ps
CPU time 22.22 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 01:47:13 PM PST 24
Peak memory 210464 kb
Host smart-1fa360f7-7709-4f28-a4a0-6c5310470ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142059650 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.3142059650
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2500242475
Short name T930
Test name
Test status
Simulation time 304408517 ps
CPU time 11.51 seconds
Started Jan 07 01:46:04 PM PST 24
Finished Jan 07 01:46:55 PM PST 24
Peak memory 203196 kb
Host smart-2963ec33-e711-42ad-bb0c-63070f8f6cdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500242475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2500242475
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.97269232
Short name T534
Test name
Test status
Simulation time 26581824000 ps
CPU time 516.01 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:55:40 PM PST 24
Peak memory 2485952 kb
Host smart-e75cee06-9920-47c2-ad37-91ed3ab35278
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97269232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_stretch.97269232
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.182134962
Short name T272
Test name
Test status
Simulation time 1792496246 ps
CPU time 7.24 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 01:46:57 PM PST 24
Peak memory 203300 kb
Host smart-58a21aaa-1f7c-4055-a4c0-296753072791
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182134962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_timeout.182134962
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_ovf.2833516988
Short name T18
Test name
Test status
Simulation time 17228824564 ps
CPU time 76.1 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:48:32 PM PST 24
Peak memory 317448 kb
Host smart-550c4fd7-bb1e-4438-9654-6e89ff64df0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833516988 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_tx_ovf.2833516988
Directory /workspace/41.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.2869745729
Short name T1185
Test name
Test status
Simulation time 1642812472 ps
CPU time 5.05 seconds
Started Jan 07 01:46:15 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 203272 kb
Host smart-00cbfdca-8e0a-4480-8bd4-9c8d895a0232
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869745729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_target_unexp_stop.2869745729
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.960045889
Short name T968
Test name
Test status
Simulation time 72190136 ps
CPU time 0.62 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:06 PM PST 24
Peak memory 202856 kb
Host smart-1cb9b50f-6fb5-402d-b8e8-838a80d30124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960045889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.960045889
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.858459761
Short name T336
Test name
Test status
Simulation time 1062572524 ps
CPU time 12.41 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 01:46:51 PM PST 24
Peak memory 326156 kb
Host smart-74df191f-63a2-4817-b058-c4849a423316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858459761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.858459761
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.152152776
Short name T74
Test name
Test status
Simulation time 5800944394 ps
CPU time 106.16 seconds
Started Jan 07 01:45:56 PM PST 24
Finished Jan 07 01:48:21 PM PST 24
Peak memory 897680 kb
Host smart-30f961cc-8291-4ba2-aa0d-d118dbda118e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152152776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.152152776
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3687067303
Short name T15
Test name
Test status
Simulation time 6364583557 ps
CPU time 294.11 seconds
Started Jan 07 01:46:01 PM PST 24
Finished Jan 07 01:51:36 PM PST 24
Peak memory 952208 kb
Host smart-ebb30104-5bd7-4839-bcc8-900343be3582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687067303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3687067303
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2344655921
Short name T1057
Test name
Test status
Simulation time 886746282 ps
CPU time 0.94 seconds
Started Jan 07 01:46:06 PM PST 24
Finished Jan 07 01:46:46 PM PST 24
Peak memory 203220 kb
Host smart-fc9cf3e5-1f3a-4002-b1ab-f5304f03f81c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344655921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2344655921
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3627907209
Short name T1306
Test name
Test status
Simulation time 1090964948 ps
CPU time 9.55 seconds
Started Jan 07 01:45:50 PM PST 24
Finished Jan 07 01:46:40 PM PST 24
Peak memory 232264 kb
Host smart-018e0e99-ce0a-4bd4-85a2-e23c0086c1e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627907209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3627907209
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2476641378
Short name T1177
Test name
Test status
Simulation time 6723797612 ps
CPU time 388.69 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 01:53:10 PM PST 24
Peak memory 1867944 kb
Host smart-56bff242-3569-43f0-b6be-153581edbbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476641378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2476641378
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3260833384
Short name T785
Test name
Test status
Simulation time 6354921044 ps
CPU time 177.8 seconds
Started Jan 07 01:46:31 PM PST 24
Finished Jan 07 01:50:01 PM PST 24
Peak memory 267156 kb
Host smart-a3d6de7a-12b9-4c80-9163-bf93b13c261e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260833384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3260833384
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.903688879
Short name T335
Test name
Test status
Simulation time 51809975 ps
CPU time 0.64 seconds
Started Jan 07 01:45:57 PM PST 24
Finished Jan 07 01:46:37 PM PST 24
Peak memory 202496 kb
Host smart-dc0b5d5c-2931-4283-b562-13e6d926ef90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903688879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.903688879
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.408466456
Short name T752
Test name
Test status
Simulation time 20882670619 ps
CPU time 178.93 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:50:11 PM PST 24
Peak memory 345412 kb
Host smart-928ad7f8-30b9-46d2-98e2-0413cac10110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408466456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.408466456
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_rx_oversample.3746925281
Short name T167
Test name
Test status
Simulation time 3780577758 ps
CPU time 140.6 seconds
Started Jan 07 01:46:02 PM PST 24
Finished Jan 07 01:49:02 PM PST 24
Peak memory 350328 kb
Host smart-12008da4-9e1b-4c36-a774-d19c87c67583
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746925281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_rx_oversample
.3746925281
Directory /workspace/42.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1753379294
Short name T1190
Test name
Test status
Simulation time 31033663886 ps
CPU time 90.7 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:48:41 PM PST 24
Peak memory 346568 kb
Host smart-6d99efbc-aafd-4177-a41b-d211ea59c249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753379294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1753379294
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.1197351973
Short name T49
Test name
Test status
Simulation time 26537655700 ps
CPU time 719.09 seconds
Started Jan 07 01:45:59 PM PST 24
Finished Jan 07 01:58:37 PM PST 24
Peak memory 1824192 kb
Host smart-63b79485-c433-48ba-9186-78f37b0ac357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197351973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1197351973
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1676410089
Short name T671
Test name
Test status
Simulation time 3662141006 ps
CPU time 12.89 seconds
Started Jan 07 01:46:11 PM PST 24
Finished Jan 07 01:47:04 PM PST 24
Peak memory 214788 kb
Host smart-d3724320-53e0-4372-9041-05b9855c24e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676410089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1676410089
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3077938342
Short name T253
Test name
Test status
Simulation time 666032257 ps
CPU time 3.03 seconds
Started Jan 07 01:45:58 PM PST 24
Finished Jan 07 01:46:40 PM PST 24
Peak memory 203348 kb
Host smart-3aa69107-268b-43a4-8293-67206bc03bc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077938342 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3077938342
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.4058055683
Short name T71
Test name
Test status
Simulation time 10088233959 ps
CPU time 55.98 seconds
Started Jan 07 01:45:56 PM PST 24
Finished Jan 07 01:47:31 PM PST 24
Peak memory 496052 kb
Host smart-d71d4f5c-d140-4e6b-a0a0-1503650c2d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058055683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.4058055683
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.892442411
Short name T292
Test name
Test status
Simulation time 10134419776 ps
CPU time 12.51 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:24 PM PST 24
Peak memory 302064 kb
Host smart-1080e6b7-e27b-45d8-8719-ea11c3ef118d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892442411 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.892442411
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3740625354
Short name T782
Test name
Test status
Simulation time 1057492243 ps
CPU time 2.48 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 203232 kb
Host smart-5e5fe751-ccbf-43db-a1bd-825dce0a1585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740625354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3740625354
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.680584494
Short name T310
Test name
Test status
Simulation time 6142210942 ps
CPU time 6.05 seconds
Started Jan 07 01:46:30 PM PST 24
Finished Jan 07 01:47:08 PM PST 24
Peak memory 203384 kb
Host smart-20d1fcad-b12a-4368-afd1-1e6128ebd468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680584494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.680584494
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3061201156
Short name T1138
Test name
Test status
Simulation time 19329763776 ps
CPU time 700.46 seconds
Started Jan 07 01:45:58 PM PST 24
Finished Jan 07 01:58:18 PM PST 24
Peak memory 4335920 kb
Host smart-78066894-ef01-4270-9105-445c68478ddc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061201156 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3061201156
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.4034893675
Short name T933
Test name
Test status
Simulation time 1337332609 ps
CPU time 3.57 seconds
Started Jan 07 01:46:01 PM PST 24
Finished Jan 07 01:46:44 PM PST 24
Peak memory 205040 kb
Host smart-080ea424-85a6-4362-80d0-175d41215e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034893675 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.4034893675
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3353880245
Short name T216
Test name
Test status
Simulation time 1057732856 ps
CPU time 27.03 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:31 PM PST 24
Peak memory 203368 kb
Host smart-a91fd472-a427-46b7-98e2-66ae5f1ab513
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353880245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3353880245
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.2678032222
Short name T966
Test name
Test status
Simulation time 77177248797 ps
CPU time 1517.4 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 02:12:08 PM PST 24
Peak memory 7355808 kb
Host smart-b5743dcd-a315-4e35-a532-e72c3690a9ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678032222 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.2678032222
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.3179664547
Short name T729
Test name
Test status
Simulation time 1467472446 ps
CPU time 5.83 seconds
Started Jan 07 01:45:59 PM PST 24
Finished Jan 07 01:46:44 PM PST 24
Peak memory 203256 kb
Host smart-dd3ae554-3d46-4577-823f-160e14d55859
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179664547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.3179664547
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.923067278
Short name T1116
Test name
Test status
Simulation time 25396839439 ps
CPU time 818.35 seconds
Started Jan 07 01:46:31 PM PST 24
Finished Jan 07 02:00:42 PM PST 24
Peak memory 5223908 kb
Host smart-bba87b11-508c-4e7a-99c3-cb2dccfc414c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923067278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.923067278
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3138336302
Short name T455
Test name
Test status
Simulation time 6680210665 ps
CPU time 7.1 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 01:46:49 PM PST 24
Peak memory 206352 kb
Host smart-dc0c6ce8-594e-437e-8adb-0a463cb62a12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138336302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3138336302
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_ovf.3740898467
Short name T1334
Test name
Test status
Simulation time 5466868991 ps
CPU time 162.09 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:49:57 PM PST 24
Peak memory 425172 kb
Host smart-ea3df45d-1097-44d3-8f02-8beb9b4bd9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740898467 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_tx_ovf.3740898467
Directory /workspace/42.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.1819443785
Short name T610
Test name
Test status
Simulation time 3698884234 ps
CPU time 8.14 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 01:46:49 PM PST 24
Peak memory 208504 kb
Host smart-14908d78-3c80-4863-b85b-019ad1548d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819443785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.1819443785
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2976341633
Short name T875
Test name
Test status
Simulation time 43462143 ps
CPU time 0.58 seconds
Started Jan 07 01:46:22 PM PST 24
Finished Jan 07 01:46:58 PM PST 24
Peak memory 202188 kb
Host smart-5b5cc910-8909-4f16-a4aa-7f8c9d81cf84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976341633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2976341633
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1786969844
Short name T220
Test name
Test status
Simulation time 30915277 ps
CPU time 1.33 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:14 PM PST 24
Peak memory 211432 kb
Host smart-4747e43f-717b-4795-bf2e-89ebea4ae5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786969844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1786969844
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3971479131
Short name T865
Test name
Test status
Simulation time 636005694 ps
CPU time 7.31 seconds
Started Jan 07 01:46:07 PM PST 24
Finished Jan 07 01:46:53 PM PST 24
Peak memory 269824 kb
Host smart-65c86ae4-bbc6-4b70-bab2-7bd5bd2afe4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971479131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3971479131
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2064225588
Short name T950
Test name
Test status
Simulation time 6721354734 ps
CPU time 1075.26 seconds
Started Jan 07 01:46:00 PM PST 24
Finished Jan 07 02:04:35 PM PST 24
Peak memory 1892404 kb
Host smart-960c0eff-9234-40bc-ba67-3e2ef8dd1ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064225588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2064225588
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.1299939091
Short name T1045
Test name
Test status
Simulation time 111380958 ps
CPU time 0.91 seconds
Started Jan 07 01:46:03 PM PST 24
Finished Jan 07 01:46:43 PM PST 24
Peak memory 203208 kb
Host smart-63612dd3-3ac5-496d-9636-0e38f9d2a4fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299939091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.1299939091
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2430220588
Short name T205
Test name
Test status
Simulation time 1101085596 ps
CPU time 7.01 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:22 PM PST 24
Peak memory 258596 kb
Host smart-aab598cf-1008-45da-9b50-f554248f6f29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430220588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2430220588
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1464752503
Short name T1333
Test name
Test status
Simulation time 6659552355 ps
CPU time 463.19 seconds
Started Jan 07 01:46:12 PM PST 24
Finished Jan 07 01:54:35 PM PST 24
Peak memory 1880452 kb
Host smart-4d7ecf8f-1025-4d5a-b9da-d6073fd7ed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464752503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1464752503
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.225672010
Short name T1028
Test name
Test status
Simulation time 11950546731 ps
CPU time 140.45 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:49:33 PM PST 24
Peak memory 244072 kb
Host smart-7fe37315-97e9-424a-84c3-7159865a81f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225672010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.225672010
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.121146262
Short name T1011
Test name
Test status
Simulation time 21612558 ps
CPU time 0.66 seconds
Started Jan 07 01:45:50 PM PST 24
Finished Jan 07 01:46:31 PM PST 24
Peak memory 202484 kb
Host smart-e8f5159b-9f72-4368-bdaa-001e568f15a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121146262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.121146262
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.3159029554
Short name T239
Test name
Test status
Simulation time 578797394 ps
CPU time 10.85 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:27 PM PST 24
Peak memory 225984 kb
Host smart-a0e467b5-afe1-46ab-b22a-a5cb33f7b1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159029554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.3159029554
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_rx_oversample.2579018267
Short name T987
Test name
Test status
Simulation time 2821021416 ps
CPU time 225.95 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 01:50:36 PM PST 24
Peak memory 280668 kb
Host smart-ad7fbfee-c86f-44dc-bc5b-bbd914ca7f73
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579018267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_rx_oversample
.2579018267
Directory /workspace/43.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3460401959
Short name T940
Test name
Test status
Simulation time 13201060295 ps
CPU time 75.82 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:48:19 PM PST 24
Peak memory 234728 kb
Host smart-9a72712d-c971-4ffd-a2d8-f532ca94ac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460401959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3460401959
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1679703756
Short name T338
Test name
Test status
Simulation time 2327257620 ps
CPU time 23.79 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:36 PM PST 24
Peak memory 211628 kb
Host smart-27ce97ec-834a-45f6-bbef-b4d4cb9a7fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679703756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1679703756
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2306782842
Short name T1331
Test name
Test status
Simulation time 1423333719 ps
CPU time 5.59 seconds
Started Jan 07 01:46:13 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 203604 kb
Host smart-6e1057c8-83b6-4ac9-8b8b-a031337c13bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306782842 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2306782842
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2267725972
Short name T523
Test name
Test status
Simulation time 10194606449 ps
CPU time 26.84 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 01:47:16 PM PST 24
Peak memory 337888 kb
Host smart-b9ebcb51-d810-4c9f-975c-8006e8fd0c93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267725972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2267725972
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1534797192
Short name T1297
Test name
Test status
Simulation time 10027492743 ps
CPU time 64.94 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:48:15 PM PST 24
Peak memory 563892 kb
Host smart-39143600-9f55-43c8-8683-16704940a710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534797192 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1534797192
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3443818787
Short name T162
Test name
Test status
Simulation time 1235554749 ps
CPU time 2.99 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:07 PM PST 24
Peak memory 203404 kb
Host smart-5fe0c75e-7e9a-4a45-8957-f52a8d801393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443818787 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3443818787
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3454123525
Short name T1226
Test name
Test status
Simulation time 3324666971 ps
CPU time 7.08 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:20 PM PST 24
Peak memory 206628 kb
Host smart-2dbe88f6-5e8c-4bb9-864e-94f7e86d6a45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454123525 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3454123525
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_perf.774346518
Short name T240
Test name
Test status
Simulation time 19681254889 ps
CPU time 5.85 seconds
Started Jan 07 01:46:11 PM PST 24
Finished Jan 07 01:46:57 PM PST 24
Peak memory 213608 kb
Host smart-ae91818e-dae0-40c9-873a-36a085a279b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774346518 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_perf.774346518
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2761809399
Short name T860
Test name
Test status
Simulation time 1229481824 ps
CPU time 12.48 seconds
Started Jan 07 01:46:13 PM PST 24
Finished Jan 07 01:47:06 PM PST 24
Peak memory 203292 kb
Host smart-298eb0a4-ee93-46b5-9daa-459c9128984e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761809399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2761809399
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.2987885794
Short name T740
Test name
Test status
Simulation time 45250984664 ps
CPU time 36.78 seconds
Started Jan 07 01:46:13 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 435148 kb
Host smart-d2425c57-aeb7-4f97-99e0-1c3d6395832e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987885794 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.2987885794
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.4264348977
Short name T281
Test name
Test status
Simulation time 653627975 ps
CPU time 11.72 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:23 PM PST 24
Peak memory 204852 kb
Host smart-831fdb59-b948-4aa3-b650-4bdd24fd9b94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264348977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.4264348977
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1724256982
Short name T620
Test name
Test status
Simulation time 10980923383 ps
CPU time 100.82 seconds
Started Jan 07 01:46:13 PM PST 24
Finished Jan 07 01:48:33 PM PST 24
Peak memory 1805872 kb
Host smart-99f7efea-8e4a-451c-95af-adb62bc8adfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724256982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1724256982
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.495249027
Short name T962
Test name
Test status
Simulation time 6096557930 ps
CPU time 297.02 seconds
Started Jan 07 01:46:13 PM PST 24
Finished Jan 07 01:51:50 PM PST 24
Peak memory 1061808 kb
Host smart-907bea9b-b453-4638-bb26-bbff587c1046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495249027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_t
arget_stretch.495249027
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1537160888
Short name T467
Test name
Test status
Simulation time 8487134756 ps
CPU time 8.06 seconds
Started Jan 07 01:46:10 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 209860 kb
Host smart-be8df4ef-dca1-45f8-91d5-6b75fab64041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537160888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1537160888
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_ovf.4223670335
Short name T513
Test name
Test status
Simulation time 3637493076 ps
CPU time 167.69 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:50:05 PM PST 24
Peak memory 466860 kb
Host smart-0e1690bf-ee5e-4f63-8f86-9e76f6347538
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223670335 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_tx_ovf.4223670335
Directory /workspace/43.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.2513487692
Short name T227
Test name
Test status
Simulation time 1024104324 ps
CPU time 4.79 seconds
Started Jan 07 01:46:16 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 203256 kb
Host smart-b97d2167-98dc-4cc8-b5c1-d7a8592723b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513487692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.i2c_target_unexp_stop.2513487692
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.4044733373
Short name T813
Test name
Test status
Simulation time 51816103 ps
CPU time 0.61 seconds
Started Jan 07 01:46:45 PM PST 24
Finished Jan 07 01:47:23 PM PST 24
Peak memory 203064 kb
Host smart-9069d0fd-a74f-4b1c-9e17-46a2f3be7df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044733373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.4044733373
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.798737471
Short name T219
Test name
Test status
Simulation time 64101387 ps
CPU time 1.48 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:47:17 PM PST 24
Peak memory 211496 kb
Host smart-7064de4f-4797-438d-a764-c23d0d3039f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798737471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.798737471
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3014064561
Short name T1085
Test name
Test status
Simulation time 5846515061 ps
CPU time 10.89 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:23 PM PST 24
Peak memory 311832 kb
Host smart-2c00920e-cd5b-4d9f-9187-1bb05bdd9b41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014064561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3014064561
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3741654218
Short name T1122
Test name
Test status
Simulation time 6428242601 ps
CPU time 124.19 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:49:20 PM PST 24
Peak memory 952784 kb
Host smart-fde514b2-7719-4b67-8e34-63b58627fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741654218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3741654218
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2336762356
Short name T1033
Test name
Test status
Simulation time 8718442680 ps
CPU time 229.86 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:51:03 PM PST 24
Peak memory 1147464 kb
Host smart-23b33bc4-cb61-4882-a1ae-a810baaf1693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336762356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2336762356
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3135693266
Short name T430
Test name
Test status
Simulation time 105160058 ps
CPU time 0.99 seconds
Started Jan 07 01:46:30 PM PST 24
Finished Jan 07 01:47:03 PM PST 24
Peak memory 203156 kb
Host smart-79a089ec-b8ea-49e9-ad25-0b794545805c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135693266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3135693266
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3779568842
Short name T1335
Test name
Test status
Simulation time 1161664954 ps
CPU time 5.59 seconds
Started Jan 07 01:46:13 PM PST 24
Finished Jan 07 01:46:59 PM PST 24
Peak memory 203384 kb
Host smart-34126c4f-701e-43dd-9835-b757ffaa0d4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779568842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3779568842
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.3405503260
Short name T816
Test name
Test status
Simulation time 5817069115 ps
CPU time 641.67 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:57:52 PM PST 24
Peak memory 1542372 kb
Host smart-630ed114-7c17-4347-a240-1fbcc38ac353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405503260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3405503260
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.756889519
Short name T1216
Test name
Test status
Simulation time 5733512776 ps
CPU time 189.3 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:50:24 PM PST 24
Peak memory 299676 kb
Host smart-3f54be7b-d815-4c17-9461-de047c942511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756889519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.756889519
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2632478745
Short name T812
Test name
Test status
Simulation time 77602716 ps
CPU time 0.61 seconds
Started Jan 07 01:46:14 PM PST 24
Finished Jan 07 01:46:54 PM PST 24
Peak memory 202444 kb
Host smart-c92411f3-9668-48d6-b01f-eb682c1302f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632478745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2632478745
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2315207806
Short name T1036
Test name
Test status
Simulation time 28463433748 ps
CPU time 33.25 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:38 PM PST 24
Peak memory 211644 kb
Host smart-131ecf64-b825-47e4-89bb-c7b95fd59f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315207806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2315207806
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_rx_oversample.2734970279
Short name T348
Test name
Test status
Simulation time 22085934191 ps
CPU time 232.69 seconds
Started Jan 07 01:46:21 PM PST 24
Finished Jan 07 01:50:49 PM PST 24
Peak memory 309868 kb
Host smart-c9150858-c9e0-4173-88ef-0191726304cc
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734970279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_rx_oversample
.2734970279
Directory /workspace/44.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2642456137
Short name T497
Test name
Test status
Simulation time 7926253787 ps
CPU time 61.07 seconds
Started Jan 07 01:46:12 PM PST 24
Finished Jan 07 01:47:53 PM PST 24
Peak memory 300504 kb
Host smart-23d2d5b0-c5e5-4aa0-aad7-0efa672787b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642456137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2642456137
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.3527292321
Short name T868
Test name
Test status
Simulation time 5776394777 ps
CPU time 21.84 seconds
Started Jan 07 01:46:20 PM PST 24
Finished Jan 07 01:47:19 PM PST 24
Peak memory 227968 kb
Host smart-179d1cac-d84a-4ad5-af62-50b8a283bb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527292321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3527292321
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.773056168
Short name T471
Test name
Test status
Simulation time 6331015601 ps
CPU time 5.46 seconds
Started Jan 07 01:46:45 PM PST 24
Finished Jan 07 01:47:28 PM PST 24
Peak memory 203360 kb
Host smart-afd22922-5fb5-4493-bde9-c0b933a98f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773056168 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.773056168
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.127169305
Short name T188
Test name
Test status
Simulation time 10208004885 ps
CPU time 12.48 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:25 PM PST 24
Peak memory 269444 kb
Host smart-0acf7855-ff55-4e2f-beb9-b208f27da7a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127169305 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.127169305
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2266398641
Short name T811
Test name
Test status
Simulation time 10116850354 ps
CPU time 11.69 seconds
Started Jan 07 01:46:45 PM PST 24
Finished Jan 07 01:47:34 PM PST 24
Peak memory 298468 kb
Host smart-cfb36987-8dbb-43ac-bee7-ffeb171e9f59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266398641 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2266398641
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3195304640
Short name T985
Test name
Test status
Simulation time 380446962 ps
CPU time 2.19 seconds
Started Jan 07 01:46:45 PM PST 24
Finished Jan 07 01:47:25 PM PST 24
Peak memory 203160 kb
Host smart-e9f7c31e-8ef3-4682-a9c3-e32d2e49936d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195304640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3195304640
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.86839232
Short name T990
Test name
Test status
Simulation time 1855637055 ps
CPU time 6.62 seconds
Started Jan 07 01:46:11 PM PST 24
Finished Jan 07 01:46:58 PM PST 24
Peak memory 203292 kb
Host smart-d2496189-7c93-4db0-b3a6-ade47868cc3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86839232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.86839232
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1197462176
Short name T296
Test name
Test status
Simulation time 19912369508 ps
CPU time 111.39 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:49:01 PM PST 24
Peak memory 1207856 kb
Host smart-84dcfea6-53f9-423d-8525-3c5b87dfcb19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197462176 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1197462176
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.2079759985
Short name T779
Test name
Test status
Simulation time 278303740 ps
CPU time 1.91 seconds
Started Jan 07 01:46:41 PM PST 24
Finished Jan 07 01:47:22 PM PST 24
Peak memory 203252 kb
Host smart-671bff41-58ca-47dd-b32e-93ab06f9df7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079759985 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.2079759985
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1223556568
Short name T767
Test name
Test status
Simulation time 2864489153 ps
CPU time 13.38 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 203376 kb
Host smart-3c6fa6c0-5f62-4a14-990f-4b50b9a8449b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223556568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1223556568
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.1829672238
Short name T1236
Test name
Test status
Simulation time 6390838687 ps
CPU time 30.4 seconds
Started Jan 07 01:46:45 PM PST 24
Finished Jan 07 01:47:53 PM PST 24
Peak memory 263028 kb
Host smart-12ee50d2-4b2b-4017-907f-ba7309363512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829672238 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.i2c_target_stress_all.1829672238
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.94571698
Short name T1120
Test name
Test status
Simulation time 4461278760 ps
CPU time 46.44 seconds
Started Jan 07 01:46:09 PM PST 24
Finished Jan 07 01:47:35 PM PST 24
Peak memory 203492 kb
Host smart-1b0e4bfa-bb6c-47a5-a8f7-e60071bb17e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94571698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stress_rd.94571698
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3820178704
Short name T1141
Test name
Test status
Simulation time 48936235021 ps
CPU time 3501.77 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 02:45:39 PM PST 24
Peak memory 11126008 kb
Host smart-01407aa2-5a74-4fbc-8ba9-f82d0327e81c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820178704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3820178704
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.327073488
Short name T504
Test name
Test status
Simulation time 21396287204 ps
CPU time 449.09 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:54:45 PM PST 24
Peak memory 1289192 kb
Host smart-13cc806e-0d4e-469b-a2f4-3a413834ec91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327073488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.327073488
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3301451114
Short name T409
Test name
Test status
Simulation time 1704969418 ps
CPU time 7.05 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:47:24 PM PST 24
Peak memory 203384 kb
Host smart-e0b6a25c-5646-44e0-afe0-f213ac80afbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301451114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3301451114
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_ovf.1887618917
Short name T143
Test name
Test status
Simulation time 14545762771 ps
CPU time 118.17 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:49:15 PM PST 24
Peak memory 376884 kb
Host smart-f1d9d00f-bc79-450d-83e1-d7fd17484b50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887618917 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_tx_ovf.1887618917
Directory /workspace/44.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.187935965
Short name T47
Test name
Test status
Simulation time 5908216210 ps
CPU time 7.47 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:12 PM PST 24
Peak memory 203372 kb
Host smart-9ae5d589-c14e-4d27-816f-eaa3da3a6ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187935965 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_unexp_stop.187935965
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1953570435
Short name T1189
Test name
Test status
Simulation time 157860427 ps
CPU time 0.59 seconds
Started Jan 07 01:46:43 PM PST 24
Finished Jan 07 01:47:22 PM PST 24
Peak memory 203252 kb
Host smart-e5dc6232-9151-4fa6-913d-15d5c63de850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953570435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1953570435
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3033102715
Short name T831
Test name
Test status
Simulation time 83732368 ps
CPU time 1.14 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 211412 kb
Host smart-eca850ad-9842-4e50-b05f-2f82a311bbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033102715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3033102715
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2358122031
Short name T235
Test name
Test status
Simulation time 330661511 ps
CPU time 6.57 seconds
Started Jan 07 01:46:43 PM PST 24
Finished Jan 07 01:47:28 PM PST 24
Peak memory 251848 kb
Host smart-47d58ad6-c755-4d40-ac27-7ad271b9e2b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358122031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2358122031
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2222374564
Short name T1228
Test name
Test status
Simulation time 3142268539 ps
CPU time 113.8 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:49:07 PM PST 24
Peak memory 955368 kb
Host smart-1fe7ca7d-374a-45f2-b31a-cbb6e4fef08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222374564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2222374564
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1972649042
Short name T652
Test name
Test status
Simulation time 24138403273 ps
CPU time 393.72 seconds
Started Jan 07 01:46:43 PM PST 24
Finished Jan 07 01:53:55 PM PST 24
Peak memory 1700124 kb
Host smart-cd9cba95-df12-476f-a300-0b74d82f2dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972649042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1972649042
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2751950752
Short name T1187
Test name
Test status
Simulation time 230704052 ps
CPU time 0.72 seconds
Started Jan 07 01:46:43 PM PST 24
Finished Jan 07 01:47:22 PM PST 24
Peak memory 202508 kb
Host smart-27041efb-ec01-41de-827e-acaeec7058b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751950752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2751950752
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3401678377
Short name T98
Test name
Test status
Simulation time 203406747 ps
CPU time 5.79 seconds
Started Jan 07 01:46:39 PM PST 24
Finished Jan 07 01:47:23 PM PST 24
Peak memory 240300 kb
Host smart-dc2c53e5-5ef8-4455-91bf-b8063507e887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401678377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3401678377
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2944646946
Short name T123
Test name
Test status
Simulation time 25516503316 ps
CPU time 308.22 seconds
Started Jan 07 01:46:40 PM PST 24
Finished Jan 07 01:52:28 PM PST 24
Peak memory 1633720 kb
Host smart-859e6767-6342-4adf-913b-f02b423557a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944646946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2944646946
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_override.2315555169
Short name T1253
Test name
Test status
Simulation time 32623299 ps
CPU time 0.6 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 202388 kb
Host smart-07ec4f11-3f4f-48fe-aacd-6524f71f15f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315555169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2315555169
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1630117253
Short name T1238
Test name
Test status
Simulation time 51275266332 ps
CPU time 1351.89 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 02:09:54 PM PST 24
Peak memory 347380 kb
Host smart-bbad7b22-f295-4b4f-9f13-dc49955c2e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630117253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1630117253
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_rx_oversample.4221518169
Short name T1255
Test name
Test status
Simulation time 10285773270 ps
CPU time 265.38 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:51:41 PM PST 24
Peak memory 314924 kb
Host smart-2bd96bd3-e476-422b-a278-8acf13afe8e6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221518169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_rx_oversample
.4221518169
Directory /workspace/45.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3107682537
Short name T1256
Test name
Test status
Simulation time 1679485176 ps
CPU time 35.22 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:46 PM PST 24
Peak memory 278164 kb
Host smart-33f423c9-54f5-48c0-b998-21f8dd153c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107682537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3107682537
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1584445806
Short name T623
Test name
Test status
Simulation time 5168094861 ps
CPU time 48.79 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 01:48:11 PM PST 24
Peak memory 219464 kb
Host smart-5689ea0f-1f9b-4819-8675-14b687ce3b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584445806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1584445806
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.235876558
Short name T361
Test name
Test status
Simulation time 1032545541 ps
CPU time 4.28 seconds
Started Jan 07 01:46:57 PM PST 24
Finished Jan 07 01:47:35 PM PST 24
Peak memory 203264 kb
Host smart-391605cb-7332-421d-a6dd-9882c029af21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235876558 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.235876558
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.4251785032
Short name T720
Test name
Test status
Simulation time 10079055902 ps
CPU time 75.58 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 01:48:37 PM PST 24
Peak memory 589956 kb
Host smart-1e9c1c6e-0faf-4ce5-9202-61ac8da09d82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251785032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.4251785032
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3225713399
Short name T413
Test name
Test status
Simulation time 10045668110 ps
CPU time 26.15 seconds
Started Jan 07 01:46:59 PM PST 24
Finished Jan 07 01:47:59 PM PST 24
Peak memory 374172 kb
Host smart-85abfddb-80c5-4613-8dfe-39f6df24c79b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225713399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3225713399
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2464115390
Short name T536
Test name
Test status
Simulation time 1682060556 ps
CPU time 6.95 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 202864 kb
Host smart-fb6fdfca-93bd-4a93-b065-5c064af99d30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464115390 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2464115390
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1932701970
Short name T353
Test name
Test status
Simulation time 8698139732 ps
CPU time 140.09 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 01:49:47 PM PST 24
Peak memory 1888532 kb
Host smart-8ee3d919-232d-4c51-9c12-8d9ef6ef7aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932701970 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1932701970
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.4274047396
Short name T575
Test name
Test status
Simulation time 47397598365 ps
CPU time 313.11 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:52:42 PM PST 24
Peak memory 536532 kb
Host smart-4eaf064f-8dcc-4626-94f1-46b62b7e315f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274047396 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.4274047396
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.1814051932
Short name T609
Test name
Test status
Simulation time 18766246783 ps
CPU time 76.62 seconds
Started Jan 07 01:46:58 PM PST 24
Finished Jan 07 01:48:48 PM PST 24
Peak memory 206416 kb
Host smart-b4a757cc-8ec7-4ae2-9804-0b3609b0917b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814051932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.1814051932
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2094479854
Short name T570
Test name
Test status
Simulation time 16098617167 ps
CPU time 18.37 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:35 PM PST 24
Peak memory 579332 kb
Host smart-6d5e34bf-c3a2-452b-b493-f6d791f3028b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094479854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2094479854
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2162459572
Short name T836
Test name
Test status
Simulation time 38928926643 ps
CPU time 526.59 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 01:56:08 PM PST 24
Peak memory 1607488 kb
Host smart-4b486cdd-f854-46f9-a863-eba20f738d3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162459572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2162459572
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.730424184
Short name T33
Test name
Test status
Simulation time 1919803376 ps
CPU time 7.3 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 01:47:34 PM PST 24
Peak memory 203340 kb
Host smart-278d8730-bb45-4915-8a37-a816044f79f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730424184 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.730424184
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_ovf.235442384
Short name T502
Test name
Test status
Simulation time 12737140296 ps
CPU time 161.01 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 01:50:08 PM PST 24
Peak memory 461812 kb
Host smart-86587bb6-f2d3-4db3-936a-21e813baff85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235442384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_tx_ovf.235442384
Directory /workspace/45.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/46.i2c_alert_test.578947449
Short name T89
Test name
Test status
Simulation time 45689285 ps
CPU time 0.61 seconds
Started Jan 07 01:46:31 PM PST 24
Finished Jan 07 01:47:04 PM PST 24
Peak memory 202156 kb
Host smart-ca4c0579-56c5-42a3-b3bc-08031708715c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578947449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.578947449
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1274963547
Short name T1020
Test name
Test status
Simulation time 34320329 ps
CPU time 1.47 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 211572 kb
Host smart-79b2b2b7-dbd8-42bc-9ddb-063ed03b9944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274963547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1274963547
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3909347167
Short name T232
Test name
Test status
Simulation time 2022506330 ps
CPU time 28.29 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:33 PM PST 24
Peak memory 320092 kb
Host smart-b70c192e-973d-4389-b668-8a00d0ee223e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909347167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3909347167
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1201064779
Short name T349
Test name
Test status
Simulation time 14924645453 ps
CPU time 115.96 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:49:06 PM PST 24
Peak memory 612004 kb
Host smart-0dcac906-2be9-4d75-8cee-5eb9dee7bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201064779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1201064779
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1995088334
Short name T168
Test name
Test status
Simulation time 14332405252 ps
CPU time 193.76 seconds
Started Jan 07 01:46:39 PM PST 24
Finished Jan 07 01:50:31 PM PST 24
Peak memory 1099152 kb
Host smart-9c06b68c-5bc6-4add-938b-5ab35834ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995088334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1995088334
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2181663014
Short name T1030
Test name
Test status
Simulation time 949849274 ps
CPU time 0.91 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 203116 kb
Host smart-b0f2a629-886e-4d85-9384-ae36a0fd7c7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181663014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2181663014
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.4122062885
Short name T923
Test name
Test status
Simulation time 328728491 ps
CPU time 4.55 seconds
Started Jan 07 01:46:31 PM PST 24
Finished Jan 07 01:47:07 PM PST 24
Peak memory 232476 kb
Host smart-c8173343-13ca-4434-959b-609dcb53b3d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122062885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.4122062885
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_override.3410647737
Short name T593
Test name
Test status
Simulation time 52012364 ps
CPU time 0.63 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:04 PM PST 24
Peak memory 202360 kb
Host smart-95166d30-96fa-4632-bdbd-53918e4ce90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410647737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3410647737
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1674830478
Short name T1340
Test name
Test status
Simulation time 7830001736 ps
CPU time 382.02 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:53:27 PM PST 24
Peak memory 219852 kb
Host smart-f94ab4b1-42b6-4a1a-9db8-cd370022ff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674830478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1674830478
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_rx_oversample.160029698
Short name T641
Test name
Test status
Simulation time 4081584637 ps
CPU time 189.2 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:50:25 PM PST 24
Peak memory 405180 kb
Host smart-3399008a-9d6f-4090-b60b-38396cb77d58
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160029698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_rx_oversample.
160029698
Directory /workspace/46.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3404051073
Short name T1000
Test name
Test status
Simulation time 10756467078 ps
CPU time 315.08 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:52:20 PM PST 24
Peak memory 294904 kb
Host smart-cd5925d5-d3d6-4c77-b2b1-34b6a9a9f931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404051073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3404051073
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1347671501
Short name T10
Test name
Test status
Simulation time 1290504203 ps
CPU time 11.79 seconds
Started Jan 07 01:46:43 PM PST 24
Finished Jan 07 01:47:33 PM PST 24
Peak memory 211512 kb
Host smart-7ff8d51d-a4dd-42f8-bf2f-884dc191a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347671501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1347671501
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1218210355
Short name T378
Test name
Test status
Simulation time 1422652963 ps
CPU time 5.61 seconds
Started Jan 07 01:46:39 PM PST 24
Finished Jan 07 01:47:23 PM PST 24
Peak memory 203360 kb
Host smart-5857c96f-7580-40e2-83bf-aad00d1a8ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218210355 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1218210355
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.691253455
Short name T384
Test name
Test status
Simulation time 10224004026 ps
CPU time 12.8 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:47:34 PM PST 24
Peak memory 293280 kb
Host smart-a97f1267-ea9c-41bb-b4a5-c0b8b661d596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691253455 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.691253455
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2887337758
Short name T1323
Test name
Test status
Simulation time 545532742 ps
CPU time 2.63 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:47:16 PM PST 24
Peak memory 203288 kb
Host smart-6bb9fbb3-3201-43f1-b36d-c8ed00be69e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887337758 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2887337758
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1838525450
Short name T834
Test name
Test status
Simulation time 5624745823 ps
CPU time 6.31 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:22 PM PST 24
Peak memory 203332 kb
Host smart-b8172aef-5557-48fa-9e8a-66027c12e472
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838525450 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1838525450
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.73495834
Short name T956
Test name
Test status
Simulation time 22827701576 ps
CPU time 161.91 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:49:46 PM PST 24
Peak memory 1358424 kb
Host smart-5a190d45-6799-4927-ba66-2133b88390fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73495834 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.73495834
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.464171530
Short name T650
Test name
Test status
Simulation time 1925455199 ps
CPU time 3.08 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:08 PM PST 24
Peak memory 203316 kb
Host smart-7c85c6b0-a445-4cc8-a74c-0f2bbd8810c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464171530 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_perf.464171530
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.4170061437
Short name T904
Test name
Test status
Simulation time 7746150820 ps
CPU time 14.95 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:19 PM PST 24
Peak memory 203264 kb
Host smart-93e85dbf-407a-4780-9139-7b380a3955e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170061437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.4170061437
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3219000117
Short name T426
Test name
Test status
Simulation time 734260683 ps
CPU time 12.27 seconds
Started Jan 07 01:46:31 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 204376 kb
Host smart-3308be24-ff28-4053-879b-ed5906311764
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219000117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3219000117
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.787767644
Short name T975
Test name
Test status
Simulation time 9205087047 ps
CPU time 12.22 seconds
Started Jan 07 01:46:39 PM PST 24
Finished Jan 07 01:47:31 PM PST 24
Peak memory 466636 kb
Host smart-757e121d-0ead-4104-9ae3-95fdb3beb5f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787767644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.787767644
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3234213500
Short name T688
Test name
Test status
Simulation time 9394954045 ps
CPU time 771.69 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 02:00:13 PM PST 24
Peak memory 2147544 kb
Host smart-c9dd7f4b-5bc5-481a-b8a5-2294c41ea89f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234213500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3234213500
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.423558645
Short name T533
Test name
Test status
Simulation time 10027172476 ps
CPU time 10.7 seconds
Started Jan 07 01:46:30 PM PST 24
Finished Jan 07 01:47:13 PM PST 24
Peak memory 214436 kb
Host smart-50b1ff82-3af6-4462-9fa6-089d6d05af38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423558645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_unexp_stop.423558645
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.31184644
Short name T633
Test name
Test status
Simulation time 49176874 ps
CPU time 0.59 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:47:11 PM PST 24
Peak memory 202152 kb
Host smart-aceb71ab-6a83-440d-8d1f-b5f2b7428b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31184644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.31184644
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.109799885
Short name T42
Test name
Test status
Simulation time 114492612 ps
CPU time 1.29 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 211496 kb
Host smart-525777bd-4d4c-4e90-b180-cb2026b67e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109799885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.109799885
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1921764563
Short name T478
Test name
Test status
Simulation time 5463294005 ps
CPU time 9.93 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 298476 kb
Host smart-9113738f-c61a-400e-96c6-30df3853879f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921764563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1921764563
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1404021895
Short name T1024
Test name
Test status
Simulation time 8285105137 ps
CPU time 67.93 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:48:12 PM PST 24
Peak memory 720904 kb
Host smart-f6ba0a87-aa52-4972-bc90-908ee2dcbcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404021895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1404021895
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3756963449
Short name T1130
Test name
Test status
Simulation time 25400427482 ps
CPU time 1011.8 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 02:04:06 PM PST 24
Peak memory 1819172 kb
Host smart-3a8902d2-d96e-4107-be21-c716c361caac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756963449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3756963449
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.4188435760
Short name T1191
Test name
Test status
Simulation time 4062615506 ps
CPU time 11.03 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 203348 kb
Host smart-64473eb1-be16-4e09-b2e2-b9509a497e0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188435760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.4188435760
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.18267430
Short name T906
Test name
Test status
Simulation time 3905867381 ps
CPU time 154.84 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:49:39 PM PST 24
Peak memory 1139604 kb
Host smart-d4cadbe8-e11c-418f-9f7a-fc628eb1594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18267430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.18267430
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.4048711822
Short name T510
Test name
Test status
Simulation time 5547611015 ps
CPU time 118.29 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:49:19 PM PST 24
Peak memory 424452 kb
Host smart-cdf2aa9d-067e-443f-8a7b-2e3e2148ebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048711822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.4048711822
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.1083397152
Short name T6
Test name
Test status
Simulation time 16162285 ps
CPU time 0.68 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:05 PM PST 24
Peak memory 202288 kb
Host smart-4ef665de-416d-4311-8ac3-d5e19df87216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083397152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1083397152
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.3922938150
Short name T1113
Test name
Test status
Simulation time 232014448 ps
CPU time 4.58 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:09 PM PST 24
Peak memory 222896 kb
Host smart-f28b9e67-92d7-444c-a663-fb61cb4e6738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922938150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3922938150
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_rx_oversample.4199212409
Short name T228
Test name
Test status
Simulation time 10809239219 ps
CPU time 256.75 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:51:22 PM PST 24
Peak memory 312640 kb
Host smart-77c570d1-8af4-4e84-9801-b07a5b912e61
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199212409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_rx_oversample
.4199212409
Directory /workspace/47.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2255146860
Short name T757
Test name
Test status
Simulation time 11001068900 ps
CPU time 52.71 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:48:06 PM PST 24
Peak memory 288568 kb
Host smart-330b6f6f-ded6-4e28-b02a-52d5d3c5f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255146860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2255146860
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3820999082
Short name T800
Test name
Test status
Simulation time 1516905338 ps
CPU time 6.12 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:11 PM PST 24
Peak memory 203292 kb
Host smart-9a74cae2-1e4b-4137-96b6-2b463684e17d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820999082 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3820999082
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2227750685
Short name T649
Test name
Test status
Simulation time 10043533544 ps
CPU time 74.34 seconds
Started Jan 07 01:46:31 PM PST 24
Finished Jan 07 01:48:18 PM PST 24
Peak memory 572120 kb
Host smart-7da7cc5b-35bf-444a-9cca-a2c4148b3ff6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227750685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2227750685
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.334123295
Short name T215
Test name
Test status
Simulation time 10130611727 ps
CPU time 25.94 seconds
Started Jan 07 01:46:43 PM PST 24
Finished Jan 07 01:47:48 PM PST 24
Peak memory 399740 kb
Host smart-89cb57dd-49b9-4f09-9477-5db05eef845c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334123295 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.334123295
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.2865484080
Short name T668
Test name
Test status
Simulation time 574001747 ps
CPU time 2.74 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:47:24 PM PST 24
Peak memory 203036 kb
Host smart-b148f9df-a1ef-4a76-86ea-3e418b26b8d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865484080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.2865484080
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.3065992868
Short name T261
Test name
Test status
Simulation time 4134894570 ps
CPU time 4.51 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:47:09 PM PST 24
Peak memory 205880 kb
Host smart-e0136ef1-bda2-4a50-bfca-a26ee45519d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065992868 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.3065992868
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1527182266
Short name T1066
Test name
Test status
Simulation time 29566387077 ps
CPU time 417.15 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:54:18 PM PST 24
Peak memory 3296648 kb
Host smart-9b061b31-18a0-4947-8fb0-30b65e6506dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527182266 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1527182266
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.3198640158
Short name T669
Test name
Test status
Simulation time 722428143 ps
CPU time 3.91 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:47:25 PM PST 24
Peak memory 204232 kb
Host smart-1825268c-a780-4265-a9e4-00c980633a69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198640158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.3198640158
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.2716434236
Short name T1041
Test name
Test status
Simulation time 45433386304 ps
CPU time 870.7 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 02:01:48 PM PST 24
Peak memory 3679636 kb
Host smart-3aaba98f-1ef9-42c8-a03b-e40624cb1a4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716434236 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.i2c_target_stress_all.2716434236
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2635454386
Short name T234
Test name
Test status
Simulation time 8624240203 ps
CPU time 37.14 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:47:58 PM PST 24
Peak memory 223044 kb
Host smart-24d14dd8-08c5-4262-853f-553b899b1e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635454386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2635454386
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.798756346
Short name T1212
Test name
Test status
Simulation time 33282646302 ps
CPU time 389.58 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:53:51 PM PST 24
Peak memory 3247928 kb
Host smart-c30d002e-a253-4a38-b084-cbfca98c209a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798756346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.798756346
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2879962604
Short name T1284
Test name
Test status
Simulation time 34021549609 ps
CPU time 90.99 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:48:41 PM PST 24
Peak memory 885300 kb
Host smart-090cf470-8429-418d-a7d2-220d884a89ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879962604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2879962604
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3710538795
Short name T710
Test name
Test status
Simulation time 3117546292 ps
CPU time 6.24 seconds
Started Jan 07 01:46:32 PM PST 24
Finished Jan 07 01:47:11 PM PST 24
Peak memory 203296 kb
Host smart-79145441-3aac-4a41-b967-01d1b74dc8f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710538795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3710538795
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_ovf.3456225042
Short name T607
Test name
Test status
Simulation time 4419781639 ps
CPU time 335.16 seconds
Started Jan 07 01:46:34 PM PST 24
Finished Jan 07 01:52:45 PM PST 24
Peak memory 532072 kb
Host smart-f930259d-cc32-4af9-95ec-24e109c3271a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456225042 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_tx_ovf.3456225042
Directory /workspace/47.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.2436405683
Short name T895
Test name
Test status
Simulation time 1506417421 ps
CPU time 6.09 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:47:27 PM PST 24
Peak memory 203520 kb
Host smart-e280fb06-e44d-4a00-8bba-dd928a7aa1cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436405683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.2436405683
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2928353723
Short name T1051
Test name
Test status
Simulation time 26939494 ps
CPU time 0.62 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 203180 kb
Host smart-b7dcc8a5-ee60-4c21-bf21-c74df356be57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928353723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2928353723
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3538003395
Short name T416
Test name
Test status
Simulation time 157147191 ps
CPU time 1.16 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:47:18 PM PST 24
Peak memory 211520 kb
Host smart-276f21ab-b227-43c3-8532-6dc2010bd043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538003395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3538003395
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3259730152
Short name T367
Test name
Test status
Simulation time 532902773 ps
CPU time 28.57 seconds
Started Jan 07 01:46:39 PM PST 24
Finished Jan 07 01:47:49 PM PST 24
Peak memory 318776 kb
Host smart-d52e0050-3e6c-4013-b74b-af4c063f26fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259730152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3259730152
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.829188901
Short name T980
Test name
Test status
Simulation time 6292575368 ps
CPU time 269.63 seconds
Started Jan 07 01:46:37 PM PST 24
Finished Jan 07 01:51:45 PM PST 24
Peak memory 970376 kb
Host smart-4f59e889-e745-466f-8dd6-90cd7d9066c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829188901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.829188901
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.657224129
Short name T180
Test name
Test status
Simulation time 9676596290 ps
CPU time 399.43 seconds
Started Jan 07 01:46:45 PM PST 24
Finished Jan 07 01:54:02 PM PST 24
Peak memory 1780260 kb
Host smart-20357912-8322-4218-b944-425327e66e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657224129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.657224129
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2185821060
Short name T526
Test name
Test status
Simulation time 552813166 ps
CPU time 0.97 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:47:15 PM PST 24
Peak memory 203148 kb
Host smart-d1e7c81c-dfd9-4752-90bb-90bcf583cf91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185821060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2185821060
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.525998758
Short name T697
Test name
Test status
Simulation time 749344063 ps
CPU time 3.84 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:47:21 PM PST 24
Peak memory 203360 kb
Host smart-b2b1a528-e1b6-4628-aa70-94dc8a0e51aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525998758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
525998758
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4193623032
Short name T867
Test name
Test status
Simulation time 10537110827 ps
CPU time 238.08 seconds
Started Jan 07 01:46:35 PM PST 24
Finished Jan 07 01:51:09 PM PST 24
Peak memory 1336508 kb
Host smart-a405be56-eb26-4d4e-8b12-c4d6e830b9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193623032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4193623032
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_override.4225418666
Short name T490
Test name
Test status
Simulation time 45372801 ps
CPU time 0.62 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:47:21 PM PST 24
Peak memory 202332 kb
Host smart-f3a6854b-a288-4ae6-ac88-2dcc05d38abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225418666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.4225418666
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1293386260
Short name T408
Test name
Test status
Simulation time 1004774052 ps
CPU time 16.2 seconds
Started Jan 07 01:46:38 PM PST 24
Finished Jan 07 01:47:33 PM PST 24
Peak memory 219700 kb
Host smart-2bea19b1-4c26-4613-b01d-b6ca62456604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293386260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1293386260
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_rx_oversample.112695294
Short name T892
Test name
Test status
Simulation time 2702836877 ps
CPU time 157.03 seconds
Started Jan 07 01:46:42 PM PST 24
Finished Jan 07 01:49:57 PM PST 24
Peak memory 351816 kb
Host smart-34f006ef-3b94-4ad1-9e2b-39cfe802e12d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112695294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_rx_oversample.
112695294
Directory /workspace/48.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2047019675
Short name T1034
Test name
Test status
Simulation time 2208148829 ps
CPU time 134.91 seconds
Started Jan 07 01:46:33 PM PST 24
Finished Jan 07 01:49:20 PM PST 24
Peak memory 260956 kb
Host smart-8660dd32-4cf8-4c63-baf0-781a9b2f95c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047019675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2047019675
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2506235703
Short name T229
Test name
Test status
Simulation time 8662360321 ps
CPU time 357.56 seconds
Started Jan 07 01:46:40 PM PST 24
Finished Jan 07 01:53:17 PM PST 24
Peak memory 1145552 kb
Host smart-4efb146e-eb23-4dbf-bb47-9bb9b8792f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506235703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2506235703
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2795861227
Short name T390
Test name
Test status
Simulation time 1365338782 ps
CPU time 23.48 seconds
Started Jan 07 01:46:43 PM PST 24
Finished Jan 07 01:47:45 PM PST 24
Peak memory 219660 kb
Host smart-0e61bbac-aa36-437e-9ddc-6711f49fd3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795861227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2795861227
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1665621662
Short name T1053
Test name
Test status
Simulation time 3344403540 ps
CPU time 3.38 seconds
Started Jan 07 01:46:52 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 203240 kb
Host smart-b5ae27d2-17fe-497c-879f-32d8ac78ac44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665621662 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1665621662
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1442382280
Short name T1087
Test name
Test status
Simulation time 10193492988 ps
CPU time 12.75 seconds
Started Jan 07 01:46:57 PM PST 24
Finished Jan 07 01:47:43 PM PST 24
Peak memory 263704 kb
Host smart-35cea922-42a1-4861-b638-348dabae1001
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442382280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1442382280
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2851726943
Short name T717
Test name
Test status
Simulation time 10109100709 ps
CPU time 79.5 seconds
Started Jan 07 01:46:58 PM PST 24
Finished Jan 07 01:48:52 PM PST 24
Peak memory 683208 kb
Host smart-d89647a7-8a03-40a4-af2e-f019fd0250b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851726943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2851726943
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3713675932
Short name T680
Test name
Test status
Simulation time 546031355 ps
CPU time 2.42 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 203192 kb
Host smart-8a99e5fb-1577-4d32-aa05-61f6dd42f01f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713675932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3713675932
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3082337432
Short name T327
Test name
Test status
Simulation time 4545147520 ps
CPU time 5.58 seconds
Started Jan 07 01:46:57 PM PST 24
Finished Jan 07 01:47:36 PM PST 24
Peak memory 207912 kb
Host smart-f055dc55-264e-4dfb-9784-f90e7315df11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082337432 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3082337432
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2841851524
Short name T1107
Test name
Test status
Simulation time 25892928900 ps
CPU time 1504.86 seconds
Started Jan 07 01:46:58 PM PST 24
Finished Jan 07 02:12:38 PM PST 24
Peak memory 6356308 kb
Host smart-3e8b87ea-3edc-479f-a91b-c069936740d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841851524 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2841851524
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.1769640111
Short name T746
Test name
Test status
Simulation time 891595393 ps
CPU time 2.95 seconds
Started Jan 07 01:46:57 PM PST 24
Finished Jan 07 01:47:33 PM PST 24
Peak memory 203248 kb
Host smart-3ad1afeb-b2b1-467b-aec7-0440b10e642d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769640111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.1769640111
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.1290035632
Short name T1147
Test name
Test status
Simulation time 17072158403 ps
CPU time 343.9 seconds
Started Jan 07 01:46:54 PM PST 24
Finished Jan 07 01:53:11 PM PST 24
Peak memory 487708 kb
Host smart-e2d4617b-e39b-4cd2-8546-3ee9d7b3128a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290035632 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 48.i2c_target_stress_all.1290035632
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.103484937
Short name T470
Test name
Test status
Simulation time 347468547 ps
CPU time 5.91 seconds
Started Jan 07 01:46:39 PM PST 24
Finished Jan 07 01:47:24 PM PST 24
Peak memory 202972 kb
Host smart-c321693e-3435-449e-8e9e-b533c080a875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103484937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.103484937
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2933346588
Short name T715
Test name
Test status
Simulation time 25305756305 ps
CPU time 409.59 seconds
Started Jan 07 01:46:36 PM PST 24
Finished Jan 07 01:54:03 PM PST 24
Peak memory 3823720 kb
Host smart-a4203506-1f10-4c10-b5fa-6e3ef680838b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933346588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2933346588
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2757305864
Short name T1248
Test name
Test status
Simulation time 24471734428 ps
CPU time 1831.43 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 02:17:58 PM PST 24
Peak memory 5029896 kb
Host smart-702c1418-36f0-48a8-b0b8-ea33c8167f16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757305864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2757305864
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2951708933
Short name T774
Test name
Test status
Simulation time 6907004135 ps
CPU time 7.36 seconds
Started Jan 07 01:46:44 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 203200 kb
Host smart-2090cfab-61bb-4c6c-a21a-48564e97077c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951708933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2951708933
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.2010371695
Short name T943
Test name
Test status
Simulation time 1018317203 ps
CPU time 4.86 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:34 PM PST 24
Peak memory 203404 kb
Host smart-65a6983d-b30c-4faa-8303-71a9ef098f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010371695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.2010371695
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4241720410
Short name T90
Test name
Test status
Simulation time 25805753 ps
CPU time 0.62 seconds
Started Jan 07 01:46:59 PM PST 24
Finished Jan 07 01:47:33 PM PST 24
Peak memory 202148 kb
Host smart-ec2142fd-2cdb-447a-84d9-1ff23cf59b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241720410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4241720410
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3942414037
Short name T807
Test name
Test status
Simulation time 44428636 ps
CPU time 1.48 seconds
Started Jan 07 01:46:54 PM PST 24
Finished Jan 07 01:47:28 PM PST 24
Peak memory 211476 kb
Host smart-8b2236d7-e581-45b0-911d-005c156c19fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942414037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3942414037
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1409916329
Short name T247
Test name
Test status
Simulation time 770775574 ps
CPU time 25.59 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:55 PM PST 24
Peak memory 291768 kb
Host smart-f304866d-56bd-473e-8a8f-cf53dd5bc4e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409916329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1409916329
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1104621438
Short name T1246
Test name
Test status
Simulation time 5769510611 ps
CPU time 154.2 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:50:03 PM PST 24
Peak memory 1067296 kb
Host smart-e1d63eee-6c94-43bf-911d-70d4fb12c4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104621438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1104621438
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3608114587
Short name T880
Test name
Test status
Simulation time 16353146918 ps
CPU time 909.3 seconds
Started Jan 07 01:46:58 PM PST 24
Finished Jan 07 02:02:41 PM PST 24
Peak memory 1693752 kb
Host smart-a9bf8c9c-5182-462d-b8b0-ec6689ba26b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608114587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3608114587
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1290382472
Short name T412
Test name
Test status
Simulation time 605347165 ps
CPU time 0.91 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:30 PM PST 24
Peak memory 203204 kb
Host smart-893a363f-cae7-4d94-a7e7-019124d76bad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290382472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1290382472
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1802671356
Short name T546
Test name
Test status
Simulation time 483976633 ps
CPU time 12.43 seconds
Started Jan 07 01:46:58 PM PST 24
Finished Jan 07 01:47:45 PM PST 24
Peak memory 203092 kb
Host smart-f0648cd5-47f9-48bf-b2ee-fd915dd333eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802671356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1802671356
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2726113870
Short name T810
Test name
Test status
Simulation time 5506465315 ps
CPU time 577.03 seconds
Started Jan 07 01:46:57 PM PST 24
Finished Jan 07 01:57:08 PM PST 24
Peak memory 1513488 kb
Host smart-5079b8a2-5bce-490f-9389-fdf5f839db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726113870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2726113870
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.86018941
Short name T1360
Test name
Test status
Simulation time 2615778843 ps
CPU time 167.73 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 01:50:14 PM PST 24
Peak memory 277476 kb
Host smart-efcfb51f-914c-4b66-85f5-20fc4b12bedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86018941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.86018941
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3453461650
Short name T129
Test name
Test status
Simulation time 19692512 ps
CPU time 0.64 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:47:29 PM PST 24
Peak memory 202448 kb
Host smart-77ed87c5-4b0d-4df0-b20c-8939717079b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453461650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3453461650
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1345183263
Short name T469
Test name
Test status
Simulation time 2602659220 ps
CPU time 48.1 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:48:16 PM PST 24
Peak memory 220900 kb
Host smart-d04b8ffa-460b-44f9-be42-a3eee3b46d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345183263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1345183263
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_rx_oversample.1004815405
Short name T393
Test name
Test status
Simulation time 2398664069 ps
CPU time 143.28 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:49:52 PM PST 24
Peak memory 352756 kb
Host smart-af93b351-5c9a-4a0b-a15b-96deaec83ce4
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004815405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_rx_oversample
.1004815405
Directory /workspace/49.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1011091808
Short name T712
Test name
Test status
Simulation time 2516594127 ps
CPU time 24.5 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:54 PM PST 24
Peak memory 247628 kb
Host smart-a0afed15-4215-4364-b387-c59984e67601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011091808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1011091808
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.4148883032
Short name T51
Test name
Test status
Simulation time 30422527747 ps
CPU time 3138.55 seconds
Started Jan 07 01:46:59 PM PST 24
Finished Jan 07 02:39:51 PM PST 24
Peak memory 4941128 kb
Host smart-86fd658d-3b74-4e2c-be44-1182c5543e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148883032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.4148883032
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.4232107192
Short name T1027
Test name
Test status
Simulation time 2696455813 ps
CPU time 30.32 seconds
Started Jan 07 01:46:54 PM PST 24
Finished Jan 07 01:47:58 PM PST 24
Peak memory 211512 kb
Host smart-0cf12e46-0af2-496b-9aa7-6dcaee8c75a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232107192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.4232107192
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1500066364
Short name T1295
Test name
Test status
Simulation time 5934052141 ps
CPU time 5.8 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:35 PM PST 24
Peak memory 203428 kb
Host smart-b9da9a6a-4fdb-4c4b-8e68-a0999e249b27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500066364 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1500066364
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3249440925
Short name T315
Test name
Test status
Simulation time 11852540271 ps
CPU time 4.19 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:47:32 PM PST 24
Peak memory 217988 kb
Host smart-c1f5ebab-9985-41dd-a65e-95de8a474dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249440925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3249440925
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2637752510
Short name T372
Test name
Test status
Simulation time 10514123994 ps
CPU time 12.44 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:42 PM PST 24
Peak memory 284520 kb
Host smart-7eab5f57-e5a8-4a91-b7aa-03bb52047ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637752510 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2637752510
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.723745194
Short name T66
Test name
Test status
Simulation time 389577851 ps
CPU time 2.03 seconds
Started Jan 07 01:46:51 PM PST 24
Finished Jan 07 01:47:27 PM PST 24
Peak memory 203364 kb
Host smart-1cbfa584-3c04-4626-804d-d2835f44bf9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723745194 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.723745194
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.578990033
Short name T97
Test name
Test status
Simulation time 3947325283 ps
CPU time 4.06 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 01:47:30 PM PST 24
Peak memory 203352 kb
Host smart-450975ac-aeca-478f-ac8c-2b2e619280d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578990033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.578990033
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_perf.3833941077
Short name T334
Test name
Test status
Simulation time 723692590 ps
CPU time 4.05 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:34 PM PST 24
Peak memory 203288 kb
Host smart-32b74928-1d8a-4758-a666-1c1829248db4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833941077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.3833941077
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.467119074
Short name T385
Test name
Test status
Simulation time 1726835488 ps
CPU time 47.57 seconds
Started Jan 07 01:46:51 PM PST 24
Finished Jan 07 01:48:13 PM PST 24
Peak memory 203304 kb
Host smart-f45d5ed9-dd9d-4029-9cb9-3aa58b6c9f86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467119074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.467119074
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.476188565
Short name T969
Test name
Test status
Simulation time 76253035267 ps
CPU time 899.73 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 02:02:29 PM PST 24
Peak memory 2862964 kb
Host smart-d59c26f3-4ff4-41ea-af81-12afd8113d48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476188565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_stress_all.476188565
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3826262410
Short name T360
Test name
Test status
Simulation time 5344098636 ps
CPU time 109.84 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:49:18 PM PST 24
Peak memory 205336 kb
Host smart-669adf66-9e85-4e0c-8768-d18d4f71fc42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826262410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3826262410
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2627773904
Short name T636
Test name
Test status
Simulation time 43452709217 ps
CPU time 2687.69 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 02:32:15 PM PST 24
Peak memory 9912768 kb
Host smart-216938c1-537b-46e9-a528-5ca5eda364b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627773904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2627773904
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.3786585128
Short name T374
Test name
Test status
Simulation time 29623103402 ps
CPU time 584.47 seconds
Started Jan 07 01:46:52 PM PST 24
Finished Jan 07 01:57:10 PM PST 24
Peak memory 3319600 kb
Host smart-4cdc4702-1605-4922-bf84-9d80d9d332a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786585128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.3786585128
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.4093487428
Short name T801
Test name
Test status
Simulation time 3985533256 ps
CPU time 7.87 seconds
Started Jan 07 01:46:55 PM PST 24
Finished Jan 07 01:47:36 PM PST 24
Peak memory 203324 kb
Host smart-dff619af-859a-4666-83a7-515ea5bd6559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093487428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.4093487428
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_ovf.4201860864
Short name T1341
Test name
Test status
Simulation time 8631261705 ps
CPU time 37.68 seconds
Started Jan 07 01:46:53 PM PST 24
Finished Jan 07 01:48:04 PM PST 24
Peak memory 220076 kb
Host smart-24078c9d-1ae2-46e4-b29b-3eebfb5a8e99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201860864 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_tx_ovf.4201860864
Directory /workspace/49.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.2562966280
Short name T458
Test name
Test status
Simulation time 1759477358 ps
CPU time 7.5 seconds
Started Jan 07 01:46:56 PM PST 24
Finished Jan 07 01:47:37 PM PST 24
Peak memory 208820 kb
Host smart-5122aad1-fc1b-4470-8a24-4cdc13a003d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562966280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.2562966280
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.25850800
Short name T1231
Test name
Test status
Simulation time 22227986 ps
CPU time 0.59 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:43:33 PM PST 24
Peak memory 202208 kb
Host smart-397dc297-b1da-48f4-947b-e7ae7a9bb49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25850800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.25850800
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2584455373
Short name T12
Test name
Test status
Simulation time 30130554 ps
CPU time 1.23 seconds
Started Jan 07 01:43:59 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 203144 kb
Host smart-475db77e-b292-4695-83d8-c392b5f2e9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584455373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2584455373
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.986546666
Short name T1264
Test name
Test status
Simulation time 484319819 ps
CPU time 11.16 seconds
Started Jan 07 01:43:45 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 308192 kb
Host smart-0689c16b-ddbf-46e0-9721-e817cb302bcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986546666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.986546666
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3134157610
Short name T1159
Test name
Test status
Simulation time 8373714630 ps
CPU time 103.27 seconds
Started Jan 07 01:43:52 PM PST 24
Finished Jan 07 01:45:47 PM PST 24
Peak memory 792736 kb
Host smart-803467eb-14a1-447b-a4d8-8d27dd16e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134157610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3134157610
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.2826868332
Short name T726
Test name
Test status
Simulation time 10428736948 ps
CPU time 296.95 seconds
Started Jan 07 01:43:42 PM PST 24
Finished Jan 07 01:48:54 PM PST 24
Peak memory 1410200 kb
Host smart-4a5e7390-6dad-4fe1-a857-329626013e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826868332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2826868332
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.4099634045
Short name T514
Test name
Test status
Simulation time 110548951 ps
CPU time 0.9 seconds
Started Jan 07 01:43:46 PM PST 24
Finished Jan 07 01:44:00 PM PST 24
Peak memory 203204 kb
Host smart-247659f0-bb4c-41a8-8a74-0c33934911a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099634045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.4099634045
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.220020406
Short name T976
Test name
Test status
Simulation time 218890639 ps
CPU time 5.91 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:44 PM PST 24
Peak memory 243580 kb
Host smart-3e3319e6-bc2a-4199-8f1b-57fd1a8fa1e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220020406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.220020406
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3661456947
Short name T465
Test name
Test status
Simulation time 4628289688 ps
CPU time 199.07 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:46:57 PM PST 24
Peak memory 1310940 kb
Host smart-a5f888ad-60dd-4f74-8f30-5bec19a1aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661456947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3661456947
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.812046381
Short name T978
Test name
Test status
Simulation time 1847647758 ps
CPU time 97.04 seconds
Started Jan 07 01:43:10 PM PST 24
Finished Jan 07 01:45:00 PM PST 24
Peak memory 235908 kb
Host smart-febc42d0-f42b-41f4-a82f-dc07ad35214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812046381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.812046381
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.176281033
Short name T832
Test name
Test status
Simulation time 20437510 ps
CPU time 0.64 seconds
Started Jan 07 01:43:43 PM PST 24
Finished Jan 07 01:43:58 PM PST 24
Peak memory 202412 kb
Host smart-e67c830c-2deb-405c-8afb-085dbe35dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176281033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.176281033
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.209238600
Short name T942
Test name
Test status
Simulation time 6543644483 ps
CPU time 315.12 seconds
Started Jan 07 01:43:39 PM PST 24
Finished Jan 07 01:49:11 PM PST 24
Peak memory 247104 kb
Host smart-9799df7f-4b87-4210-b1d9-2f7ed105a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209238600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.209238600
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_rx_oversample.4123347166
Short name T1329
Test name
Test status
Simulation time 6054634732 ps
CPU time 60.99 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:44:49 PM PST 24
Peak memory 300572 kb
Host smart-c824a6bc-9ede-418f-bbcc-7834125d782f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123347166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_rx_oversample.
4123347166
Directory /workspace/5.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3057255945
Short name T676
Test name
Test status
Simulation time 59994775810 ps
CPU time 55.37 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:44:42 PM PST 24
Peak memory 246980 kb
Host smart-5e2d2520-80ca-4c45-ad28-a4e4f11c35e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057255945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3057255945
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.99032195
Short name T119
Test name
Test status
Simulation time 30398181538 ps
CPU time 698.32 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:55:28 PM PST 24
Peak memory 951408 kb
Host smart-871fbdd5-4779-4b6b-aca4-e42c732c98d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99032195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.99032195
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.18280086
Short name T841
Test name
Test status
Simulation time 10474887951 ps
CPU time 11.3 seconds
Started Jan 07 01:43:43 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 265004 kb
Host smart-18cd9853-fdab-40cd-b140-9e01746563b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280086 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_acq.18280086
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.489888793
Short name T939
Test name
Test status
Simulation time 10062669754 ps
CPU time 27.55 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:44:02 PM PST 24
Peak memory 405504 kb
Host smart-b6326cee-2476-4b25-b79b-6a6f8eaee0e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489888793 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.489888793
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3990626841
Short name T542
Test name
Test status
Simulation time 619657891 ps
CPU time 2.98 seconds
Started Jan 07 01:43:08 PM PST 24
Finished Jan 07 01:43:22 PM PST 24
Peak memory 203324 kb
Host smart-bee8aebd-9943-4716-9e20-5678b4fd5f59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990626841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3990626841
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.4196290191
Short name T388
Test name
Test status
Simulation time 1588665435 ps
CPU time 6.41 seconds
Started Jan 07 01:43:37 PM PST 24
Finished Jan 07 01:44:01 PM PST 24
Peak memory 206692 kb
Host smart-cca40415-89ec-488f-88a2-1580f54b09cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196290191 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.4196290191
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.349886592
Short name T885
Test name
Test status
Simulation time 17017309676 ps
CPU time 507.62 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:51:56 PM PST 24
Peak memory 3908060 kb
Host smart-1f10bedf-c4fb-4ef6-a606-40f7893996bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349886592 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.349886592
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.2947195021
Short name T376
Test name
Test status
Simulation time 1863114551 ps
CPU time 5.05 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 203388 kb
Host smart-4c83cb46-9d6e-4553-9739-26236e11d86e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947195021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.2947195021
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3675965725
Short name T1035
Test name
Test status
Simulation time 1236733860 ps
CPU time 13.78 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 203268 kb
Host smart-1e5bf807-7c85-40d9-8a28-264ab21bb176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675965725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3675965725
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.85076525
Short name T759
Test name
Test status
Simulation time 19427035814 ps
CPU time 72.34 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:44:45 PM PST 24
Peak memory 236664 kb
Host smart-19f3126f-6ee7-4406-9441-e56136603705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85076525 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.i2c_target_stress_all.85076525
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.4141197806
Short name T274
Test name
Test status
Simulation time 3950749244 ps
CPU time 16.13 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:49 PM PST 24
Peak memory 207760 kb
Host smart-3f95dbb2-7763-48e9-a2b6-5dc0e691d409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141197806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.4141197806
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.860712768
Short name T664
Test name
Test status
Simulation time 49600713323 ps
CPU time 394.25 seconds
Started Jan 07 01:43:48 PM PST 24
Finished Jan 07 01:50:34 PM PST 24
Peak memory 2889596 kb
Host smart-8330eaf1-5573-42ab-8594-ca1408b6e8a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860712768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.860712768
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.65951222
Short name T64
Test name
Test status
Simulation time 31484579661 ps
CPU time 1195.13 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 02:03:21 PM PST 24
Peak memory 2277676 kb
Host smart-4ceaf9f5-bbdc-4b6a-8786-34b9bdd61c7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65951222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_stretch.65951222
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.179851229
Short name T392
Test name
Test status
Simulation time 1705067392 ps
CPU time 7.37 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:43:37 PM PST 24
Peak memory 208808 kb
Host smart-efb63ebe-653c-4758-b670-69129dcdddb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179851229 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_timeout.179851229
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_ovf.1502758663
Short name T420
Test name
Test status
Simulation time 2559441170 ps
CPU time 85.82 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:44:58 PM PST 24
Peak memory 336856 kb
Host smart-853afca8-0f3e-4f49-ab0e-e12950f22b79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502758663 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_tx_ovf.1502758663
Directory /workspace/5.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1387359313
Short name T436
Test name
Test status
Simulation time 107593529 ps
CPU time 0.57 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:43:48 PM PST 24
Peak memory 202120 kb
Host smart-048e8938-e5b7-4e47-8cc3-1d436098e7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387359313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1387359313
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2635199247
Short name T983
Test name
Test status
Simulation time 181071143 ps
CPU time 1.42 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:43:49 PM PST 24
Peak memory 211444 kb
Host smart-756ba0d5-6e18-4c12-830c-b858ba3f365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635199247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2635199247
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1929307299
Short name T1166
Test name
Test status
Simulation time 4298291285 ps
CPU time 63.17 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:44:41 PM PST 24
Peak memory 696612 kb
Host smart-6db9d9e6-f012-4dcb-b058-e1c7a640e1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929307299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1929307299
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3132306198
Short name T196
Test name
Test status
Simulation time 607133641 ps
CPU time 0.99 seconds
Started Jan 07 01:43:25 PM PST 24
Finished Jan 07 01:43:44 PM PST 24
Peak memory 203176 kb
Host smart-67249c68-7d60-4c13-ade3-f90ef8495392
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132306198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3132306198
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3415480750
Short name T249
Test name
Test status
Simulation time 192902455 ps
CPU time 4.25 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:43:38 PM PST 24
Peak memory 203288 kb
Host smart-3dc37c43-2aed-4593-b0d0-9268d5aa8879
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415480750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3415480750
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1492768915
Short name T815
Test name
Test status
Simulation time 15661745061 ps
CPU time 140.26 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:45:58 PM PST 24
Peak memory 1048904 kb
Host smart-e3de84a9-9c82-4dab-9c62-4794d0a82578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492768915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1492768915
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2229224457
Short name T1079
Test name
Test status
Simulation time 2035824423 ps
CPU time 66.99 seconds
Started Jan 07 01:43:40 PM PST 24
Finished Jan 07 01:45:03 PM PST 24
Peak memory 330808 kb
Host smart-ee7dbec5-3d46-42a1-b591-60e354c5d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229224457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2229224457
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2405443390
Short name T1232
Test name
Test status
Simulation time 33248858 ps
CPU time 0.6 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 01:43:27 PM PST 24
Peak memory 202340 kb
Host smart-c97697e2-60c4-41c9-b8e9-f8d8a9e54951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405443390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2405443390
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1991792399
Short name T1282
Test name
Test status
Simulation time 26557960073 ps
CPU time 409 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:50:17 PM PST 24
Peak memory 211544 kb
Host smart-fd15cd7b-f139-42d1-8593-0525dea287c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991792399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1991792399
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_rx_oversample.978155200
Short name T1171
Test name
Test status
Simulation time 2313526840 ps
CPU time 86.18 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:44:57 PM PST 24
Peak memory 291368 kb
Host smart-f0ea86f1-07ab-402e-96d8-5a6d1db3793c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978155200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_rx_oversample.978155200
Directory /workspace/6.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3430592324
Short name T223
Test name
Test status
Simulation time 4322042677 ps
CPU time 59.31 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:44:28 PM PST 24
Peak memory 233616 kb
Host smart-4f1ee4b9-28c0-4de3-8eb3-7573192ecd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430592324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3430592324
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2387175995
Short name T772
Test name
Test status
Simulation time 29336146182 ps
CPU time 455.5 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:51:12 PM PST 24
Peak memory 1088720 kb
Host smart-acd65b92-25cc-4506-8007-d739f4e5f210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387175995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2387175995
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3239368431
Short name T574
Test name
Test status
Simulation time 1279490147 ps
CPU time 26.63 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:43:59 PM PST 24
Peak memory 211560 kb
Host smart-5a194769-d663-4b5c-90ca-7435f9a99241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239368431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3239368431
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.3478317432
Short name T744
Test name
Test status
Simulation time 10069125025 ps
CPU time 58.71 seconds
Started Jan 07 01:43:07 PM PST 24
Finished Jan 07 01:44:17 PM PST 24
Peak memory 485420 kb
Host smart-195b579a-0075-41ca-850f-30a6aa70dee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478317432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.3478317432
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2042326127
Short name T864
Test name
Test status
Simulation time 10376247781 ps
CPU time 11.65 seconds
Started Jan 07 01:43:10 PM PST 24
Finished Jan 07 01:43:35 PM PST 24
Peak memory 282212 kb
Host smart-f5065658-4c53-4b40-8f80-804df58944c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042326127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2042326127
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.2224525471
Short name T918
Test name
Test status
Simulation time 2206050235 ps
CPU time 3.15 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:43:54 PM PST 24
Peak memory 203428 kb
Host smart-505854ef-102b-489d-a9e7-544205823cbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224525471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.2224525471
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.948456411
Short name T329
Test name
Test status
Simulation time 741301357 ps
CPU time 3.68 seconds
Started Jan 07 01:43:21 PM PST 24
Finished Jan 07 01:43:40 PM PST 24
Peak memory 203344 kb
Host smart-52b06807-56e3-4a04-8842-6507b85d9072
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948456411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.948456411
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2168997115
Short name T1201
Test name
Test status
Simulation time 3833569505 ps
CPU time 5.67 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:43:36 PM PST 24
Peak memory 290744 kb
Host smart-06c983b7-af29-4d14-a1bd-219887f6ff2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168997115 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2168997115
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.1001044301
Short name T505
Test name
Test status
Simulation time 1955701846 ps
CPU time 2.95 seconds
Started Jan 07 01:43:41 PM PST 24
Finished Jan 07 01:43:59 PM PST 24
Peak memory 203260 kb
Host smart-98e054ab-acb8-4481-a70e-42a2baa8b836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001044301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.1001044301
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2980917774
Short name T1211
Test name
Test status
Simulation time 4493708397 ps
CPU time 25.11 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:43:55 PM PST 24
Peak memory 203384 kb
Host smart-28b5b548-b2d1-4c11-aa2d-dca2d75be39e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980917774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2980917774
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.3976684796
Short name T1161
Test name
Test status
Simulation time 19720814002 ps
CPU time 457.94 seconds
Started Jan 07 01:43:13 PM PST 24
Finished Jan 07 01:51:05 PM PST 24
Peak memory 1926696 kb
Host smart-3ee33bec-0d0d-433d-bb95-0811fb7ec578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976684796 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_stress_all.3976684796
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1740339442
Short name T1261
Test name
Test status
Simulation time 4968597158 ps
CPU time 32.26 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:44:02 PM PST 24
Peak memory 224644 kb
Host smart-ec89b5ef-6b0d-4b1a-9f8d-c83f48f4d89c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740339442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1740339442
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2815870027
Short name T438
Test name
Test status
Simulation time 14320053443 ps
CPU time 94.67 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:45:06 PM PST 24
Peak memory 1661204 kb
Host smart-f5e50ba9-0951-4e8b-b92b-9b54d813b273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815870027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2815870027
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1656330117
Short name T912
Test name
Test status
Simulation time 9993408208 ps
CPU time 30.95 seconds
Started Jan 07 01:43:09 PM PST 24
Finished Jan 07 01:43:52 PM PST 24
Peak memory 548444 kb
Host smart-1cb094dd-7487-49d2-b9d9-d60d1fc5f2d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656330117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1656330117
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2766832239
Short name T632
Test name
Test status
Simulation time 6784263077 ps
CPU time 8.56 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 203304 kb
Host smart-af7f65e3-3904-45f5-9608-746680d9d549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766832239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2766832239
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_ovf.1334443713
Short name T314
Test name
Test status
Simulation time 4439235865 ps
CPU time 169.85 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:46:22 PM PST 24
Peak memory 374956 kb
Host smart-8cecf24b-413c-4176-b053-4c787c37118b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334443713 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_tx_ovf.1334443713
Directory /workspace/6.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.645544841
Short name T1049
Test name
Test status
Simulation time 7110820208 ps
CPU time 5.35 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:43:37 PM PST 24
Peak memory 203252 kb
Host smart-094b6e7d-7d3e-4900-84bc-7278d7d865ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645544841 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_unexp_stop.645544841
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.260617486
Short name T262
Test name
Test status
Simulation time 26265147 ps
CPU time 0.61 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:43:30 PM PST 24
Peak memory 202136 kb
Host smart-aa2806ad-b5c0-4ea0-940c-660b0cbec837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260617486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.260617486
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.97974688
Short name T1112
Test name
Test status
Simulation time 65031431 ps
CPU time 1.57 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:43:49 PM PST 24
Peak memory 211440 kb
Host smart-aaf58a6a-b730-496e-bc46-bf20eb58b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97974688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.97974688
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3714215883
Short name T94
Test name
Test status
Simulation time 4231567494 ps
CPU time 25 seconds
Started Jan 07 01:43:52 PM PST 24
Finished Jan 07 01:44:28 PM PST 24
Peak memory 311436 kb
Host smart-17bf7ff7-790f-4f53-b548-e452f55f72b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714215883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3714215883
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3536519986
Short name T591
Test name
Test status
Simulation time 2769357501 ps
CPU time 216.72 seconds
Started Jan 07 01:43:26 PM PST 24
Finished Jan 07 01:47:22 PM PST 24
Peak memory 864224 kb
Host smart-5283be0e-d56b-453a-9073-c7c1f28b7e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536519986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3536519986
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3538541811
Short name T355
Test name
Test status
Simulation time 18959808593 ps
CPU time 413.36 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:50:42 PM PST 24
Peak memory 1094492 kb
Host smart-59a37914-7a98-462b-bb3a-d57947ecb1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538541811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3538541811
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.898849972
Short name T456
Test name
Test status
Simulation time 356687538 ps
CPU time 0.74 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:39 PM PST 24
Peak memory 202384 kb
Host smart-02f2a7c3-21dc-4824-863d-38a089ffc937
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898849972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.898849972
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3156203183
Short name T839
Test name
Test status
Simulation time 145522890 ps
CPU time 8.5 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 227720 kb
Host smart-440f0214-92d1-4573-810c-45c8e3807075
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156203183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3156203183
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.884395071
Short name T405
Test name
Test status
Simulation time 9400195074 ps
CPU time 321.73 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:48:56 PM PST 24
Peak memory 989364 kb
Host smart-b4ceca15-dcc7-406c-ad0c-78cff2094bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884395071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.884395071
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.406573316
Short name T1293
Test name
Test status
Simulation time 11281222527 ps
CPU time 104.98 seconds
Started Jan 07 01:43:16 PM PST 24
Finished Jan 07 01:45:16 PM PST 24
Peak memory 268072 kb
Host smart-03d7d160-5b4a-4903-b2ae-d28951573202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406573316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.406573316
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.3053508080
Short name T909
Test name
Test status
Simulation time 22059747 ps
CPU time 0.62 seconds
Started Jan 07 01:43:34 PM PST 24
Finished Jan 07 01:43:53 PM PST 24
Peak memory 202356 kb
Host smart-b51a9dc5-d7a0-4839-a3c2-de610ed6f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053508080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.3053508080
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3424780654
Short name T134
Test name
Test status
Simulation time 5576540003 ps
CPU time 51.33 seconds
Started Jan 07 01:43:44 PM PST 24
Finished Jan 07 01:44:49 PM PST 24
Peak memory 203464 kb
Host smart-04db26bd-1e52-47d4-8737-85e7ac0e05aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424780654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3424780654
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.564645758
Short name T1221
Test name
Test status
Simulation time 56748920078 ps
CPU time 1145.03 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 02:02:55 PM PST 24
Peak memory 1727816 kb
Host smart-8f1dcc06-de98-4c06-9592-aa3e2a9eef10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564645758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.564645758
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3319424766
Short name T567
Test name
Test status
Simulation time 1171438614 ps
CPU time 20.39 seconds
Started Jan 07 01:43:52 PM PST 24
Finished Jan 07 01:44:23 PM PST 24
Peak memory 213928 kb
Host smart-a315ea45-e9ad-4b8e-980d-b98062a1c1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319424766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3319424766
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2461145328
Short name T278
Test name
Test status
Simulation time 1134671261 ps
CPU time 4.58 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:43:41 PM PST 24
Peak memory 203288 kb
Host smart-3fc79f6e-e783-47a5-9ce7-3b4ad74bb632
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461145328 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2461145328
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1910585142
Short name T450
Test name
Test status
Simulation time 10025499657 ps
CPU time 73.18 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:45:02 PM PST 24
Peak memory 552012 kb
Host smart-14d5defe-a7d3-4241-99ef-e52549ed2fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910585142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1910585142
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.3282078566
Short name T528
Test name
Test status
Simulation time 384168342 ps
CPU time 2.13 seconds
Started Jan 07 01:43:05 PM PST 24
Finished Jan 07 01:43:20 PM PST 24
Peak memory 203320 kb
Host smart-6e6d4b37-986a-49da-ae42-fe9a11a902fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282078566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.3282078566
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3037826777
Short name T1088
Test name
Test status
Simulation time 2171684467 ps
CPU time 4.71 seconds
Started Jan 07 01:43:51 PM PST 24
Finished Jan 07 01:44:08 PM PST 24
Peak memory 205332 kb
Host smart-5806fa7b-62d5-4219-86df-314afe8f1be7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037826777 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3037826777
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3465164442
Short name T566
Test name
Test status
Simulation time 19597699815 ps
CPU time 6.1 seconds
Started Jan 07 01:43:37 PM PST 24
Finished Jan 07 01:44:00 PM PST 24
Peak memory 203472 kb
Host smart-eeea8349-b3e2-43b9-a804-5f440467c756
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465164442 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3465164442
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.2833369464
Short name T65
Test name
Test status
Simulation time 682119557 ps
CPU time 4.18 seconds
Started Jan 07 01:43:09 PM PST 24
Finished Jan 07 01:43:26 PM PST 24
Peak memory 203328 kb
Host smart-2657fb89-d9e6-4e4d-90e6-81fca44e2907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833369464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_perf.2833369464
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.1741746315
Short name T905
Test name
Test status
Simulation time 32922330327 ps
CPU time 647.42 seconds
Started Jan 07 01:43:46 PM PST 24
Finished Jan 07 01:54:46 PM PST 24
Peak memory 4351732 kb
Host smart-90d029c6-de6f-4bd1-8b74-36a18e7ecd4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741746315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.1741746315
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.200210764
Short name T1132
Test name
Test status
Simulation time 26794934796 ps
CPU time 628.93 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:54:08 PM PST 24
Peak memory 3240592 kb
Host smart-a1d32937-d202-4ca6-8043-2f5cee3013ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200210764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_ta
rget_stretch.200210764
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2125882742
Short name T1093
Test name
Test status
Simulation time 5924744256 ps
CPU time 7.07 seconds
Started Jan 07 01:43:37 PM PST 24
Finished Jan 07 01:44:06 PM PST 24
Peak memory 203512 kb
Host smart-9523d489-d2d9-406d-80ab-799512ce7e42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125882742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2125882742
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_ovf.1202858275
Short name T19
Test name
Test status
Simulation time 2201758299 ps
CPU time 56.63 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:44:47 PM PST 24
Peak memory 237820 kb
Host smart-b3de91b8-368c-4cde-b08b-94d8d797d10e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202858275 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_tx_ovf.1202858275
Directory /workspace/7.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.4014142680
Short name T279
Test name
Test status
Simulation time 2167602322 ps
CPU time 7.35 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:43:58 PM PST 24
Peak memory 203380 kb
Host smart-b4f38edb-fcdf-4183-bbc2-f3dfa122173a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014142680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.i2c_target_unexp_stop.4014142680
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1296500068
Short name T1287
Test name
Test status
Simulation time 16223778 ps
CPU time 0.6 seconds
Started Jan 07 01:43:24 PM PST 24
Finished Jan 07 01:43:41 PM PST 24
Peak memory 203244 kb
Host smart-f97da3ca-5dd6-4cdf-a59a-3f0c1b05e3f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296500068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1296500068
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1659918993
Short name T370
Test name
Test status
Simulation time 39931291 ps
CPU time 1.42 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:43:48 PM PST 24
Peak memory 211612 kb
Host smart-e6207680-15aa-46cc-8616-d19dca1b132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659918993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1659918993
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2242244997
Short name T662
Test name
Test status
Simulation time 1861230505 ps
CPU time 24.38 seconds
Started Jan 07 01:44:00 PM PST 24
Finished Jan 07 01:44:33 PM PST 24
Peak memory 304988 kb
Host smart-61f5ec33-2c01-4d00-99bb-5b6ffcac19c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242244997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2242244997
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3922203688
Short name T721
Test name
Test status
Simulation time 19008326873 ps
CPU time 108.15 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:45:23 PM PST 24
Peak memory 868136 kb
Host smart-c0ffd612-ff23-41de-8050-7df01351a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922203688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3922203688
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.4230682287
Short name T1127
Test name
Test status
Simulation time 4685602613 ps
CPU time 253.41 seconds
Started Jan 07 01:43:18 PM PST 24
Finished Jan 07 01:47:47 PM PST 24
Peak memory 1297132 kb
Host smart-aaf7afca-d025-4164-b18b-f968eb5ec737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230682287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.4230682287
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2831202457
Short name T330
Test name
Test status
Simulation time 426097979 ps
CPU time 15.1 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 256528 kb
Host smart-b3d97cc1-ffc9-477a-ab15-e4bc7c59000a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831202457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2831202457
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.381282234
Short name T929
Test name
Test status
Simulation time 25264536764 ps
CPU time 182.63 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 01:46:42 PM PST 24
Peak memory 1209640 kb
Host smart-0b6b97c6-0c01-4d15-ade4-9e7e9de891d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381282234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.381282234
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1047351728
Short name T587
Test name
Test status
Simulation time 5240977692 ps
CPU time 32.11 seconds
Started Jan 07 01:43:32 PM PST 24
Finished Jan 07 01:44:23 PM PST 24
Peak memory 250236 kb
Host smart-b841e9eb-94af-477a-9458-448f63f77ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047351728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1047351728
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3770974768
Short name T1054
Test name
Test status
Simulation time 7226479565 ps
CPU time 94.87 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 01:45:24 PM PST 24
Peak memory 261016 kb
Host smart-ee3aa074-4c40-4fe3-83a8-aa0d25c6dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770974768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3770974768
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_rx_oversample.214386003
Short name T494
Test name
Test status
Simulation time 7432856696 ps
CPU time 278.89 seconds
Started Jan 07 01:43:42 PM PST 24
Finished Jan 07 01:48:36 PM PST 24
Peak memory 312048 kb
Host smart-d52173f2-35b9-4bc1-97c4-6d18bbf71eb0
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214386003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_rx_oversample.214386003
Directory /workspace/8.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.3921324896
Short name T415
Test name
Test status
Simulation time 9169119353 ps
CPU time 89.12 seconds
Started Jan 07 01:43:15 PM PST 24
Finished Jan 07 01:44:58 PM PST 24
Peak memory 332316 kb
Host smart-fb50d77d-1cd6-4fd9-a649-57b1ec24fd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921324896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3921324896
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1353937618
Short name T118
Test name
Test status
Simulation time 160211206274 ps
CPU time 1047.18 seconds
Started Jan 07 01:43:27 PM PST 24
Finished Jan 07 02:01:14 PM PST 24
Peak memory 1903320 kb
Host smart-c093ea47-f54c-472e-b9f1-11423032ee3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353937618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1353937618
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2313604183
Short name T1196
Test name
Test status
Simulation time 3686608290 ps
CPU time 41.67 seconds
Started Jan 07 01:43:34 PM PST 24
Finished Jan 07 01:44:34 PM PST 24
Peak memory 213404 kb
Host smart-8e25fe29-0284-4ddf-978b-6601f16eb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313604183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2313604183
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.334708384
Short name T856
Test name
Test status
Simulation time 10273343443 ps
CPU time 25.65 seconds
Started Jan 07 01:43:39 PM PST 24
Finished Jan 07 01:44:21 PM PST 24
Peak memory 334876 kb
Host smart-b1b6e8b2-504e-4596-b20e-6c2e16ba8d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334708384 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.334708384
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3668965795
Short name T164
Test name
Test status
Simulation time 949480630 ps
CPU time 2.32 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:43:35 PM PST 24
Peak memory 203308 kb
Host smart-8a95e710-200d-4055-9702-ee28d22e6158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668965795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3668965795
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.836462496
Short name T1371
Test name
Test status
Simulation time 1403014871 ps
CPU time 5.46 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 203404 kb
Host smart-4ecf4e13-5f9e-49a2-988a-fc3976770c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836462496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.836462496
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1993920293
Short name T431
Test name
Test status
Simulation time 14604918419 ps
CPU time 426.91 seconds
Started Jan 07 01:43:56 PM PST 24
Finished Jan 07 01:51:12 PM PST 24
Peak memory 3180148 kb
Host smart-d16d4733-a91e-4791-be99-91351b1012d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993920293 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1993920293
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.4212541056
Short name T617
Test name
Test status
Simulation time 1193850857 ps
CPU time 3.4 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 203196 kb
Host smart-b711f61f-7d36-45ef-9d0c-5ffb49e63dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212541056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.4212541056
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1421520796
Short name T326
Test name
Test status
Simulation time 4404793293 ps
CPU time 9.97 seconds
Started Jan 07 01:43:29 PM PST 24
Finished Jan 07 01:43:59 PM PST 24
Peak memory 203416 kb
Host smart-7a8b666a-fc23-42be-92cf-9fd65801c610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421520796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1421520796
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.2889821594
Short name T991
Test name
Test status
Simulation time 125428003586 ps
CPU time 93.98 seconds
Started Jan 07 01:43:49 PM PST 24
Finished Jan 07 01:45:34 PM PST 24
Peak memory 273280 kb
Host smart-0b33b584-620f-4b7c-816e-c42ab2d64804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889821594 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.2889821594
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.789462393
Short name T1126
Test name
Test status
Simulation time 4147867301 ps
CPU time 18.03 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:44:05 PM PST 24
Peak memory 219004 kb
Host smart-da8e5878-0690-4f63-8c93-f99892138cfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789462393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.789462393
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2942600081
Short name T316
Test name
Test status
Simulation time 29043114948 ps
CPU time 2077.67 seconds
Started Jan 07 01:43:23 PM PST 24
Finished Jan 07 02:18:17 PM PST 24
Peak memory 6577848 kb
Host smart-83105189-4700-4561-8465-05cd5e98f29f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942600081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2942600081
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3489864109
Short name T1202
Test name
Test status
Simulation time 5410526286 ps
CPU time 5.99 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:43:56 PM PST 24
Peak memory 208784 kb
Host smart-4a11a569-0d00-40bb-bdd3-1f632942df47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489864109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3489864109
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_ovf.3289397217
Short name T784
Test name
Test status
Simulation time 3688123707 ps
CPU time 201.5 seconds
Started Jan 07 01:43:48 PM PST 24
Finished Jan 07 01:47:21 PM PST 24
Peak memory 477136 kb
Host smart-fc1fe060-ebe4-4d98-8aab-dc7495d1ee34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289397217 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_tx_ovf.3289397217
Directory /workspace/8.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.3840542542
Short name T628
Test name
Test status
Simulation time 3126511795 ps
CPU time 6.53 seconds
Started Jan 07 01:43:57 PM PST 24
Finished Jan 07 01:44:13 PM PST 24
Peak memory 211492 kb
Host smart-e8795610-34cb-4566-a552-7f6ee183b373
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840542542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.3840542542
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1963146217
Short name T1188
Test name
Test status
Simulation time 42087506 ps
CPU time 0.63 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:38 PM PST 24
Peak memory 202156 kb
Host smart-47047ba9-a376-4217-97ea-6ab9221a5133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963146217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1963146217
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1433496002
Short name T917
Test name
Test status
Simulation time 251607926 ps
CPU time 1.15 seconds
Started Jan 07 01:43:24 PM PST 24
Finished Jan 07 01:43:42 PM PST 24
Peak memory 211612 kb
Host smart-67a89d50-b0d8-4e97-a465-57628bad4613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433496002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1433496002
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1469356733
Short name T1368
Test name
Test status
Simulation time 516273321 ps
CPU time 11.27 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:44:01 PM PST 24
Peak memory 317596 kb
Host smart-1aa10f56-7d4a-4750-a49b-c2d2f1faa752
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469356733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1469356733
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2217323645
Short name T1133
Test name
Test status
Simulation time 200967286 ps
CPU time 1.05 seconds
Started Jan 07 01:43:51 PM PST 24
Finished Jan 07 01:44:03 PM PST 24
Peak memory 203372 kb
Host smart-4b329995-50c4-4270-b67c-fb225f261a09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217323645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2217323645
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2470182216
Short name T543
Test name
Test status
Simulation time 873073942 ps
CPU time 9.4 seconds
Started Jan 07 01:43:12 PM PST 24
Finished Jan 07 01:43:34 PM PST 24
Peak memory 203260 kb
Host smart-ae430104-2690-4896-94d8-3784a948884d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470182216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2470182216
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2840066251
Short name T243
Test name
Test status
Simulation time 4155388706 ps
CPU time 356.22 seconds
Started Jan 07 01:43:48 PM PST 24
Finished Jan 07 01:49:56 PM PST 24
Peak memory 1058176 kb
Host smart-0c69191a-b3ac-483f-8345-f2c74192be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840066251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2840066251
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.180697189
Short name T850
Test name
Test status
Simulation time 10351697407 ps
CPU time 62.65 seconds
Started Jan 07 01:43:08 PM PST 24
Finished Jan 07 01:44:22 PM PST 24
Peak memory 283316 kb
Host smart-04ab1a32-350e-406a-824d-7b86ab3ef137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180697189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.180697189
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3130666237
Short name T903
Test name
Test status
Simulation time 15262854 ps
CPU time 0.67 seconds
Started Jan 07 01:43:45 PM PST 24
Finished Jan 07 01:43:59 PM PST 24
Peak memory 202252 kb
Host smart-d198bc18-f95d-47aa-b44e-4f100e0694bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130666237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3130666237
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3073389634
Short name T139
Test name
Test status
Simulation time 7591257836 ps
CPU time 178.37 seconds
Started Jan 07 01:43:28 PM PST 24
Finished Jan 07 01:46:45 PM PST 24
Peak memory 215836 kb
Host smart-c6266a06-51ff-42af-aea3-c370894a98da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073389634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3073389634
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_rx_oversample.514046207
Short name T174
Test name
Test status
Simulation time 2550824229 ps
CPU time 153.63 seconds
Started Jan 07 01:43:30 PM PST 24
Finished Jan 07 01:46:24 PM PST 24
Peak memory 369916 kb
Host smart-aedffc64-e47f-49e1-948f-30ba51a9fa98
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514046207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_rx_oversample.514046207
Directory /workspace/9.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.770863232
Short name T251
Test name
Test status
Simulation time 2963120865 ps
CPU time 176.75 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:46:48 PM PST 24
Peak memory 293108 kb
Host smart-e5b07ccc-9c27-421d-93bb-995543a636ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770863232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.770863232
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.277926541
Short name T765
Test name
Test status
Simulation time 237233079979 ps
CPU time 2545.89 seconds
Started Jan 07 01:43:09 PM PST 24
Finished Jan 07 02:25:48 PM PST 24
Peak memory 3448048 kb
Host smart-ba5831f2-0f6f-4225-926c-c45ce01a1ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277926541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.277926541
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.899909216
Short name T1023
Test name
Test status
Simulation time 2279160673 ps
CPU time 21.48 seconds
Started Jan 07 01:43:31 PM PST 24
Finished Jan 07 01:44:12 PM PST 24
Peak memory 219816 kb
Host smart-9feef700-a123-4dd4-a090-dd0a286a9800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899909216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.899909216
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2883598210
Short name T541
Test name
Test status
Simulation time 1192925455 ps
CPU time 4.65 seconds
Started Jan 07 01:43:41 PM PST 24
Finished Jan 07 01:44:01 PM PST 24
Peak memory 203220 kb
Host smart-4497b08d-b05a-4a3f-9f12-7dc6aac233aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883598210 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2883598210
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2613180599
Short name T226
Test name
Test status
Simulation time 10103910745 ps
CPU time 51.9 seconds
Started Jan 07 01:43:42 PM PST 24
Finished Jan 07 01:44:48 PM PST 24
Peak memory 452216 kb
Host smart-92407cc4-d5cb-4872-b111-c5433e0b8c07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613180599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2613180599
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.375750394
Short name T395
Test name
Test status
Simulation time 10446854165 ps
CPU time 13.21 seconds
Started Jan 07 01:43:19 PM PST 24
Finished Jan 07 01:43:48 PM PST 24
Peak memory 291756 kb
Host smart-33697a02-bba1-4e10-a8ba-187d620c1010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375750394 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.375750394
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2335883568
Short name T951
Test name
Test status
Simulation time 1087525663 ps
CPU time 1.67 seconds
Started Jan 07 01:43:24 PM PST 24
Finished Jan 07 01:43:43 PM PST 24
Peak memory 203276 kb
Host smart-7e47300a-f5c5-4a6a-82cb-b6ce62a6018b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335883568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2335883568
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1393713033
Short name T996
Test name
Test status
Simulation time 1128305105 ps
CPU time 4.14 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:43:33 PM PST 24
Peak memory 203372 kb
Host smart-5330e76e-a8b9-4df4-8b20-7c01ce34c2dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393713033 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1393713033
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3844984866
Short name T1301
Test name
Test status
Simulation time 5225340212 ps
CPU time 5.9 seconds
Started Jan 07 01:43:10 PM PST 24
Finished Jan 07 01:43:28 PM PST 24
Peak memory 286388 kb
Host smart-64981795-6934-43ee-99d5-92b120e7cbe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844984866 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3844984866
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.3995879137
Short name T1247
Test name
Test status
Simulation time 914819199 ps
CPU time 5 seconds
Started Jan 07 01:43:24 PM PST 24
Finished Jan 07 01:43:46 PM PST 24
Peak memory 203228 kb
Host smart-53b20534-d6cd-42da-81ea-6066dc57bcf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995879137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.3995879137
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3734869404
Short name T622
Test name
Test status
Simulation time 1443821964 ps
CPU time 14.47 seconds
Started Jan 07 01:43:20 PM PST 24
Finished Jan 07 01:43:51 PM PST 24
Peak memory 203360 kb
Host smart-21276810-6cbc-4ad6-a3cb-88bf281d6298
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734869404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3734869404
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.2637593714
Short name T931
Test name
Test status
Simulation time 5401121748 ps
CPU time 21.5 seconds
Started Jan 07 01:43:41 PM PST 24
Finished Jan 07 01:44:18 PM PST 24
Peak memory 215440 kb
Host smart-d6dab85b-faf9-47a9-8dfd-0a8306f415cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637593714 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.2637593714
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2744314953
Short name T383
Test name
Test status
Simulation time 5339848996 ps
CPU time 36.98 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:44:09 PM PST 24
Peak memory 203440 kb
Host smart-7f53fe39-3521-4978-9e9c-a00baf9dbfdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744314953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2744314953
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2412574915
Short name T842
Test name
Test status
Simulation time 5142565753 ps
CPU time 53.22 seconds
Started Jan 07 01:43:17 PM PST 24
Finished Jan 07 01:44:25 PM PST 24
Peak memory 694472 kb
Host smart-ed3a4fee-e869-4948-bbdd-279876ee6d4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412574915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2412574915
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.235722155
Short name T424
Test name
Test status
Simulation time 3429611904 ps
CPU time 7.62 seconds
Started Jan 07 01:43:14 PM PST 24
Finished Jan 07 01:43:35 PM PST 24
Peak memory 211644 kb
Host smart-441a1cdd-12ef-4019-a297-798e48599cf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235722155 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.235722155
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_ovf.698346710
Short name T1205
Test name
Test status
Simulation time 3338127894 ps
CPU time 192.26 seconds
Started Jan 07 01:43:42 PM PST 24
Finished Jan 07 01:47:09 PM PST 24
Peak memory 418180 kb
Host smart-4060e7b7-f80e-44bf-8b8e-48c2107be286
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698346710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_tx_ovf.698346710
Directory /workspace/9.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.786549424
Short name T1263
Test name
Test status
Simulation time 1165008215 ps
CPU time 5.78 seconds
Started Jan 07 01:43:22 PM PST 24
Finished Jan 07 01:43:44 PM PST 24
Peak memory 207232 kb
Host smart-3d752b17-fbbc-4b0c-8129-53bb6e405957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786549424 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_unexp_stop.786549424
Directory /workspace/9.i2c_target_unexp_stop/latest
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