Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	7056960	1			T1	1		T2	23663		T3	11956
all_values[1]	7056960	1			T1	1		T2	23663		T3	11956
all_values[2]	7056960	1			T1	1		T2	23663		T3	11956
all_values[3]	7056960	1			T1	1		T2	23663		T3	11956
all_values[4]	7056960	1			T1	1		T2	23663		T3	11956
all_values[5]	7056960	1			T1	1		T2	23663		T3	11956
all_values[6]	7056960	1			T1	1		T2	23663		T3	11956
all_values[7]	7056960	1			T1	1		T2	23663		T3	11956
all_values[8]	7056960	1			T1	1		T2	23663		T3	11956
all_values[9]	7056960	1			T1	1		T2	23663		T3	11956
all_values[10]	7056960	1			T1	1		T2	23663		T3	11956
all_values[11]	7056960	1			T1	1		T2	23663		T3	11956
all_values[12]	7056960	1			T1	1		T2	23663		T3	11956
all_values[13]	7056960	1			T1	1		T2	23663		T3	11956
all_values[14]	7056960	1			T1	1		T2	23663		T3	11956

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100535790

1

T1

15

T2

240468

T3

172385

auto[1]

5318610

1

T2

114477

T3

6955

T6

1

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

90401525

1

T1

15

T2

354945

T3

179340

auto[1]

15452875

1

T62

216

T63

983389

T64

293

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	5327664	1			T1	1		T2	2751		T3	11911
all_values[0]	auto[0]	auto[1]	906249	1			T62	8		T63	615565		T64	13
all_values[0]	auto[1]	auto[0]	711371	1			T2	20912		T3	45		T9	1
all_values[0]	auto[1]	auto[1]	111676	1			T62	5		T63	40029		T64	7
all_values[1]	auto[0]	auto[0]	5481881	1			T1	1		T2	970		T3	11773
all_values[1]	auto[0]	auto[1]	957095	1			T62	11		T63	620105		T64	15
all_values[1]	auto[1]	auto[0]	528555	1			T2	22693		T3	183		T10	8666
all_values[1]	auto[1]	auto[1]	89429	1			T62	4		T63	35487		T64	5
all_values[2]	auto[0]	auto[0]	6010417	1			T1	1		T2	23663		T3	11956
all_values[2]	auto[0]	auto[1]	1046296	1			T62	10		T63	655582		T64	16
all_values[2]	auto[1]	auto[1]	247	1			T62	5		T63	12		T64	4
all_values[3]	auto[0]	auto[0]	6052068	1			T1	1		T2	23663		T3	11956
all_values[3]	auto[0]	auto[1]	1004617	1			T62	10		T63	655581		T64	15
all_values[3]	auto[1]	auto[1]	275	1			T62	4		T63	13		T64	4
all_values[4]	auto[0]	auto[0]	6010457	1			T1	1		T2	23663		T3	11956
all_values[4]	auto[0]	auto[1]	1046267	1			T62	9		T63	655583		T64	17
all_values[4]	auto[1]	auto[0]	4	1			T37	3		T209	1		-	-
all_values[4]	auto[1]	auto[1]	232	1			T62	5		T63	11		T64	2
all_values[5]	auto[0]	auto[0]	6010427	1			T1	1		T2	23663		T3	11956
all_values[5]	auto[0]	auto[1]	1046291	1			T62	8		T63	655586		T64	13
all_values[5]	auto[1]	auto[1]	242	1			T62	6		T63	7		T64	7
all_values[6]	auto[0]	auto[0]	5244600	1			T1	1		T2	21		T3	11252
all_values[6]	auto[0]	auto[1]	933216	1			T62	7		T63	613769		T64	16
all_values[6]	auto[1]	auto[0]	765825	1			T2	23642		T3	704		T9	1
all_values[6]	auto[1]	auto[1]	113319	1			T62	7		T63	41824		T64	4
all_values[7]	auto[0]	auto[0]	5742876	1			T1	1		T2	23505		T3	9309
all_values[7]	auto[0]	auto[1]	1003841	1			T62	7		T63	655027		T64	14
all_values[7]	auto[1]	auto[0]	301145	1			T2	158		T3	2647		T9	1
all_values[7]	auto[1]	auto[1]	9098	1			T62	8		T63	566		T64	6
all_values[8]	auto[0]	auto[0]	5122035	1			T1	1		T2	68		T3	8690
all_values[8]	auto[0]	auto[1]	874397	1			T62	8		T63	613012		T64	17
all_values[8]	auto[1]	auto[0]	950502	1			T2	23595		T3	3266		T9	1
all_values[8]	auto[1]	auto[1]	110026	1			T62	7		T63	42582		T64	3
all_values[9]	auto[0]	auto[0]	5087601	1			T1	1		T2	186		T3	11846
all_values[9]	auto[0]	auto[1]	934458	1			T62	8		T63	614819		T64	16
all_values[9]	auto[1]	auto[0]	922827	1			T2	23477		T3	110		T6	1
all_values[9]	auto[1]	auto[1]	112074	1			T62	7		T63	40775		T64	4
all_values[10]	auto[0]	auto[0]	5900455	1			T1	1		T2	23663		T3	11956
all_values[10]	auto[0]	auto[1]	1004654	1			T62	11		T63	655585		T64	18
all_values[10]	auto[1]	auto[0]	151659	1			T15	720		T16	1090		T17	2308
all_values[10]	auto[1]	auto[1]	192	1			T62	4		T63	9		T64	1
all_values[11]	auto[0]	auto[0]	5580325	1			T1	1		T2	23663		T3	11956
all_values[11]	auto[0]	auto[1]	1037422	1			T62	12		T63	655579		T64	17
all_values[11]	auto[1]	auto[0]	438966	1			T15	4174		T16	4239		T17	6009
all_values[11]	auto[1]	auto[1]	247	1			T62	2		T63	14		T64	3
all_values[12]	auto[0]	auto[0]	6010435	1			T1	1		T2	23663		T3	11956
all_values[12]	auto[0]	auto[1]	1046319	1			T62	10		T63	655586		T64	15
all_values[12]	auto[1]	auto[1]	206	1			T62	4		T63	7		T64	4
all_values[13]	auto[0]	auto[0]	6038992	1			T1	1		T2	23663		T3	11956
all_values[13]	auto[0]	auto[1]	1017722	1			T62	8		T63	655583		T64	13
all_values[13]	auto[1]	auto[0]	8	1			T210	1		T211	1		T212	1
all_values[13]	auto[1]	auto[1]	238	1			T62	6		T63	8		T64	4
all_values[14]	auto[0]	auto[0]	6010430	1			T1	1		T2	23663		T3	11956
all_values[14]	auto[0]	auto[1]	1046283	1			T62	9		T63	655577		T64	17
all_values[14]	auto[1]	auto[1]	247	1			T62	6		T63	15		T64	3