Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[1]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[2]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[3]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[4]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[5]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[6]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[7]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[8]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[9]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[10]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[11]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[12]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[13]	7056960	1			T1	1		T2	23663		T3	11956
all_pins[14]	7056960	1			T1	1		T2	23663		T3	11956

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	100470070	1			T1	15		T2	240425		T3	172012
values[0x1]	5384330	1			T2	114520		T3	7328		T6	1
transitions[0x0=>0x1]	3633961	1			T2	69732		T3	6150		T6	1
transitions[0x1=>0x0]	3633973	1			T2	69732		T3	6150		T6	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	6233698	1			T1	1		T2	2751		T3	11910
all_pins[0]	values[0x1]	823262	1			T2	20912		T3	46		T9	1
all_pins[0]	transitions[0x0=>0x1]	232951	1			T3	46		T9	1		T21	1
all_pins[0]	transitions[0x1=>0x0]	29943	1			T2	1782		T3	195		T30	53
all_pins[1]	values[0x0]	6436706	1			T1	1		T2	969		T3	11761
all_pins[1]	values[0x1]	620254	1			T2	22694		T3	195		T10	8666
all_pins[1]	transitions[0x0=>0x1]	620214	1			T2	22694		T3	195		T10	8666
all_pins[1]	transitions[0x1=>0x0]	93	1			T62	2		T63	5		T150	2
all_pins[2]	values[0x0]	7056827	1			T1	1		T2	23663		T3	11956
all_pins[2]	values[0x1]	133	1			T62	3		T63	5		T64	2
all_pins[2]	transitions[0x0=>0x1]	95	1			T62	2		T63	5		T64	2
all_pins[2]	transitions[0x1=>0x0]	73	1			T62	1		T63	2		T64	1
all_pins[3]	values[0x0]	7056849	1			T1	1		T2	23663		T3	11956
all_pins[3]	values[0x1]	111	1			T62	2		T63	2		T64	1
all_pins[3]	transitions[0x0=>0x1]	79	1			T62	1		T63	2		T64	1
all_pins[3]	transitions[0x1=>0x0]	84	1			T62	3		T63	4		T64	1
all_pins[4]	values[0x0]	7056844	1			T1	1		T2	23663		T3	11956
all_pins[4]	values[0x1]	116	1			T62	4		T63	4		T64	1
all_pins[4]	transitions[0x0=>0x1]	89	1			T62	4		T63	4		T227	1
all_pins[4]	transitions[0x1=>0x0]	89	1			T62	1		T63	5		T64	3
all_pins[5]	values[0x0]	7056844	1			T1	1		T2	23663		T3	11956
all_pins[5]	values[0x1]	116	1			T62	1		T63	5		T64	4
all_pins[5]	transitions[0x0=>0x1]	90	1			T62	1		T63	5		T64	3
all_pins[5]	transitions[0x1=>0x0]	882489	1			T2	23642		T3	733		T9	1
all_pins[6]	values[0x0]	6174445	1			T1	1		T2	21		T3	11223
all_pins[6]	values[0x1]	882515	1			T2	23642		T3	733		T9	1
all_pins[6]	transitions[0x0=>0x1]	860648	1			T2	23443		T3	548		T10	10627
all_pins[6]	transitions[0x1=>0x0]	323302	1			T3	2595		T30	2428		T31	606
all_pins[7]	values[0x0]	6711791	1			T1	1		T2	23464		T3	9176
all_pins[7]	values[0x1]	345169	1			T2	199		T3	2780		T9	1
all_pins[7]	transitions[0x0=>0x1]	278870	1			T3	1802		T10	1		T30	2071
all_pins[7]	transitions[0x1=>0x0]	1019033	1			T2	23396		T3	2479		T10	10586
all_pins[8]	values[0x0]	5971628	1			T1	1		T2	68		T3	8499
all_pins[8]	values[0x1]	1085332	1			T2	23595		T3	3457		T9	1
all_pins[8]	transitions[0x0=>0x1]	242994	1			T2	117		T3	3442		T10	323
all_pins[8]	transitions[0x1=>0x0]	193454	1			T3	102		T6	1		T20	1
all_pins[9]	values[0x0]	6021168	1			T1	1		T2	185		T3	11839
all_pins[9]	values[0x1]	1035792	1			T2	23478		T3	117		T6	1
all_pins[9]	transitions[0x0=>0x1]	954439	1			T2	23478		T3	117		T6	1
all_pins[9]	transitions[0x1=>0x0]	70710	1			T15	675		T16	977		T17	1088
all_pins[10]	values[0x0]	6904897	1			T1	1		T2	23663		T3	11956
all_pins[10]	values[0x1]	152063	1			T15	722		T16	1091		T17	2311
all_pins[10]	transitions[0x0=>0x1]	4163	1			T15	2		T17	34		T23	182
all_pins[10]	transitions[0x1=>0x0]	291193	1			T15	3454		T16	3148		T17	3732
all_pins[11]	values[0x0]	6617867	1			T1	1		T2	23663		T3	11956
all_pins[11]	values[0x1]	439093	1			T15	4174		T16	4239		T17	6009
all_pins[11]	transitions[0x0=>0x1]	439069	1			T15	4174		T16	4239		T17	6009
all_pins[11]	transitions[0x1=>0x0]	76	1			T62	2		T63	4		T64	2
all_pins[12]	values[0x0]	7056860	1			T1	1		T2	23663		T3	11956
all_pins[12]	values[0x1]	100	1			T62	2		T63	5		T64	3
all_pins[12]	transitions[0x0=>0x1]	80	1			T62	1		T63	5		T64	3
all_pins[12]	transitions[0x1=>0x0]	112	1			T62	2		T63	3		T64	2
all_pins[13]	values[0x0]	7056828	1			T1	1		T2	23663		T3	11956
all_pins[13]	values[0x1]	132	1			T62	3		T63	3		T64	2
all_pins[13]	transitions[0x0=>0x1]	81	1			T62	2		T63	1		T64	2
all_pins[13]	transitions[0x1=>0x0]	91	1			T62	3		T63	7		T64	1
all_pins[14]	values[0x0]	7056818	1			T1	1		T2	23663		T3	11956
all_pins[14]	values[0x1]	142	1			T62	4		T63	9		T64	1
all_pins[14]	transitions[0x0=>0x1]	99	1			T62	4		T63	7		T64	1
all_pins[14]	transitions[0x1=>0x0]	823231	1			T2	20912		T3	46		T9	1