Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	476	1			T62	7		T63	21		T64	7
all_values[1]	476	1			T62	7		T63	21		T64	7
all_values[2]	476	1			T62	7		T63	21		T64	7
all_values[3]	476	1			T62	7		T63	21		T64	7
all_values[4]	476	1			T62	7		T63	21		T64	7
all_values[5]	476	1			T62	7		T63	21		T64	7
all_values[6]	476	1			T62	7		T63	21		T64	7
all_values[7]	476	1			T62	7		T63	21		T64	7
all_values[8]	476	1			T62	7		T63	21		T64	7
all_values[9]	476	1			T62	7		T63	21		T64	7
all_values[10]	476	1			T62	7		T63	21		T64	7
all_values[11]	476	1			T62	7		T63	21		T64	7
all_values[12]	476	1			T62	7		T63	21		T64	7
all_values[13]	476	1			T62	7		T63	21		T64	7
all_values[14]	476	1			T62	7		T63	21		T64	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3753

1

T62

56

T63

160

T64

50

auto[1]

3387

1

T62

49

T63

155

T64

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T62

9

T63

12

T64

7

auto[1]

6050

1

T62

96

T63

303

T64

98

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4165

1

T62

52

T63

174

T64

58

auto[1]

2975

1

T62

53

T63

141

T64

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	59	1			T62	2		T150	1		T227	1
all_values[0]	auto[0]	auto[0]	auto[1]	93	1			T62	1		T63	7		T64	1
all_values[0]	auto[0]	auto[1]	auto[0]	31	1			T228	1		T196	1		T229	1
all_values[0]	auto[0]	auto[1]	auto[1]	107	1			T62	2		T63	4		T64	1
all_values[0]	auto[1]	auto[0]	auto[1]	96	1			T62	2		T63	3		T64	5
all_values[0]	auto[1]	auto[1]	auto[1]	90	1			T63	7		T150	1		T163	4
all_values[1]	auto[0]	auto[0]	auto[0]	42	1			T63	2		T163	2		T227	1
all_values[1]	auto[0]	auto[0]	auto[1]	109	1			T62	1		T63	8		T64	2
all_values[1]	auto[0]	auto[1]	auto[0]	30	1			T227	1		T196	2		T229	1
all_values[1]	auto[0]	auto[1]	auto[1]	107	1			T62	4		T63	2		T64	2
all_values[1]	auto[1]	auto[0]	auto[1]	97	1			T62	1		T63	4		T64	1
all_values[1]	auto[1]	auto[1]	auto[1]	91	1			T62	1		T63	5		T64	2
all_values[2]	auto[0]	auto[0]	auto[0]	38	1			T227	1		T39	1		T230	1
all_values[2]	auto[0]	auto[0]	auto[1]	102	1			T63	5		T64	1		T150	2
all_values[2]	auto[0]	auto[1]	auto[0]	16	1			T228	1		T231	1		T230	1
all_values[2]	auto[0]	auto[1]	auto[1]	118	1			T62	2		T63	7		T64	2
all_values[2]	auto[1]	auto[0]	auto[1]	107	1			T62	3		T63	8		T64	1
all_values[2]	auto[1]	auto[1]	auto[1]	95	1			T62	2		T63	1		T64	3
all_values[3]	auto[0]	auto[0]	auto[0]	26	1			T62	1		T163	1		T39	2
all_values[3]	auto[0]	auto[0]	auto[1]	114	1			T62	1		T63	7		T150	5
all_values[3]	auto[0]	auto[1]	auto[0]	24	1			T64	1		T228	1		T196	1
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T62	2		T63	1		T64	2
all_values[3]	auto[1]	auto[0]	auto[1]	138	1			T62	2		T63	9		T64	2
all_values[3]	auto[1]	auto[1]	auto[1]	93	1			T62	1		T63	4		T64	2
all_values[4]	auto[0]	auto[0]	auto[0]	44	1			T62	1		T150	7		T163	1
all_values[4]	auto[0]	auto[0]	auto[1]	96	1			T63	4		T64	1		T163	2
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T64	1		T150	4		T231	2
all_values[4]	auto[0]	auto[1]	auto[1]	98	1			T62	1		T63	7		T64	2
all_values[4]	auto[1]	auto[0]	auto[1]	107	1			T62	2		T63	7		T163	3
all_values[4]	auto[1]	auto[1]	auto[1]	100	1			T62	3		T63	3		T64	3
all_values[5]	auto[0]	auto[0]	auto[0]	30	1			T62	1		T227	2		T39	1
all_values[5]	auto[0]	auto[0]	auto[1]	99	1			T62	3		T63	2		T64	2
all_values[5]	auto[0]	auto[1]	auto[0]	33	1			T63	1		T228	1		T196	1
all_values[5]	auto[0]	auto[1]	auto[1]	98	1			T63	7		T150	2		T163	2
all_values[5]	auto[1]	auto[0]	auto[1]	111	1			T62	2		T63	5		T64	1
all_values[5]	auto[1]	auto[1]	auto[1]	105	1			T62	1		T63	6		T64	4
all_values[6]	auto[0]	auto[0]	auto[0]	36	1			T62	1		T150	1		T39	1
all_values[6]	auto[0]	auto[0]	auto[1]	117	1			T62	1		T63	9		T150	4
all_values[6]	auto[0]	auto[1]	auto[0]	27	1			T63	1		T163	1		T228	2
all_values[6]	auto[0]	auto[1]	auto[1]	106	1			T62	2		T63	5		T64	4
all_values[6]	auto[1]	auto[0]	auto[1]	106	1			T62	1		T63	4		T64	1
all_values[6]	auto[1]	auto[1]	auto[1]	84	1			T62	2		T63	2		T64	2
all_values[7]	auto[0]	auto[0]	auto[0]	45	1			T150	7		T163	1		T228	1
all_values[7]	auto[0]	auto[0]	auto[1]	104	1			T62	2		T63	2		T64	2
all_values[7]	auto[0]	auto[1]	auto[0]	48	1			T63	1		T150	4		T228	3
all_values[7]	auto[0]	auto[1]	auto[1]	91	1			T63	7		T64	1		T163	1
all_values[7]	auto[1]	auto[0]	auto[1]	107	1			T62	4		T63	3		T64	3
all_values[7]	auto[1]	auto[1]	auto[1]	81	1			T62	1		T63	8		T64	1
all_values[8]	auto[0]	auto[0]	auto[0]	50	1			T150	1		T163	2		T227	1
all_values[8]	auto[0]	auto[0]	auto[1]	115	1			T62	1		T63	5		T64	4
all_values[8]	auto[0]	auto[1]	auto[0]	30	1			T163	2		T196	1		T229	1
all_values[8]	auto[0]	auto[1]	auto[1]	100	1			T62	2		T63	7		T64	1
all_values[8]	auto[1]	auto[0]	auto[1]	96	1			T62	2		T63	7		T64	2
all_values[8]	auto[1]	auto[1]	auto[1]	85	1			T62	2		T63	2		T150	2
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T196	1		T39	1		T154	1
all_values[9]	auto[0]	auto[0]	auto[1]	111	1			T62	2		T63	3		T64	3
all_values[9]	auto[0]	auto[1]	auto[0]	32	1			T196	1		T229	2		T230	1
all_values[9]	auto[0]	auto[1]	auto[1]	107	1			T62	1		T63	9		T64	2
all_values[9]	auto[1]	auto[0]	auto[1]	108	1			T62	2		T63	5		T64	2
all_values[9]	auto[1]	auto[1]	auto[1]	86	1			T62	2		T63	4		T163	1
all_values[10]	auto[0]	auto[0]	auto[0]	43	1			T150	1		T227	1		T229	1
all_values[10]	auto[0]	auto[0]	auto[1]	111	1			T62	2		T63	8		T64	5
all_values[10]	auto[0]	auto[1]	auto[0]	38	1			T64	1		T228	2		T227	2
all_values[10]	auto[0]	auto[1]	auto[1]	92	1			T62	1		T63	4		T150	3
all_values[10]	auto[1]	auto[0]	auto[1]	100	1			T62	2		T63	2		T150	2
all_values[10]	auto[1]	auto[1]	auto[1]	92	1			T62	2		T63	7		T64	1
all_values[11]	auto[0]	auto[0]	auto[0]	61	1			T62	1		T63	1		T150	1
all_values[11]	auto[0]	auto[0]	auto[1]	81	1			T63	6		T163	3		T228	1
all_values[11]	auto[0]	auto[1]	auto[0]	37	1			T163	1		T228	1		T196	2
all_values[11]	auto[0]	auto[1]	auto[1]	102	1			T62	3		T63	4		T64	5
all_values[11]	auto[1]	auto[0]	auto[1]	98	1			T62	1		T63	8		T64	1
all_values[11]	auto[1]	auto[1]	auto[1]	97	1			T62	2		T63	2		T64	1
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T62	1		T63	1		T150	1
all_values[12]	auto[0]	auto[0]	auto[1]	106	1			T62	1		T63	8		T64	2
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T64	1		T150	1		T163	1
all_values[12]	auto[0]	auto[1]	auto[1]	102	1			T62	1		T63	5		T150	1
all_values[12]	auto[1]	auto[0]	auto[1]	113	1			T62	3		T63	2		T64	1
all_values[12]	auto[1]	auto[1]	auto[1]	93	1			T62	1		T63	5		T64	3
all_values[13]	auto[0]	auto[0]	auto[0]	39	1			T62	1		T142	1		T39	1
all_values[13]	auto[0]	auto[0]	auto[1]	100	1			T62	3		T63	3		T64	1
all_values[13]	auto[0]	auto[1]	auto[0]	41	1			T63	3		T64	3		T163	1
all_values[13]	auto[0]	auto[1]	auto[1]	96	1			T62	1		T63	6		T64	2
all_values[13]	auto[1]	auto[0]	auto[1]	103	1			T63	4		T150	2		T163	1
all_values[13]	auto[1]	auto[1]	auto[1]	97	1			T62	2		T63	5		T64	1
all_values[14]	auto[0]	auto[0]	auto[0]	33	1			T227	1		T231	2		T39	1
all_values[14]	auto[0]	auto[0]	auto[1]	90	1			T63	4		T64	2		T150	3
all_values[14]	auto[0]	auto[1]	auto[0]	32	1			T63	2		T228	2		T227	4
all_values[14]	auto[0]	auto[1]	auto[1]	122	1			T62	3		T63	6		T64	1
all_values[14]	auto[1]	auto[0]	auto[1]	104	1			T62	2		T63	4		T64	4
all_values[14]	auto[1]	auto[1]	auto[1]	95	1			T62	2		T63	5		T150	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal