Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.07 99.07 96.52 100.00 93.04 98.13 100.00 92.75


Total test records in report: 1626
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T134 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1246617923 Feb 21 02:51:51 PM PST 24 Feb 21 02:51:52 PM PST 24 147123688 ps
T1523 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1755448195 Feb 21 02:52:06 PM PST 24 Feb 21 02:52:07 PM PST 24 17611271 ps
T100 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2988346265 Feb 21 02:51:35 PM PST 24 Feb 21 02:51:37 PM PST 24 60680168 ps
T86 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3566096593 Feb 21 02:51:54 PM PST 24 Feb 21 02:51:56 PM PST 24 56182119 ps
T1524 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.384772352 Feb 21 02:51:57 PM PST 24 Feb 21 02:52:00 PM PST 24 87146487 ps
T1525 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3568484710 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:39 PM PST 24 28294087 ps
T206 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3276017961 Feb 21 02:51:56 PM PST 24 Feb 21 02:51:59 PM PST 24 97008325 ps
T1526 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4003652911 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:38 PM PST 24 34328680 ps
T1527 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4042895654 Feb 21 02:51:59 PM PST 24 Feb 21 02:52:01 PM PST 24 38363640 ps
T1528 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3094310730 Feb 21 02:52:04 PM PST 24 Feb 21 02:52:05 PM PST 24 21343543 ps
T1529 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.232320088 Feb 21 02:51:27 PM PST 24 Feb 21 02:51:29 PM PST 24 29012512 ps
T1530 /workspace/coverage/cover_reg_top/33.i2c_intr_test.243841433 Feb 21 02:51:58 PM PST 24 Feb 21 02:52:00 PM PST 24 39302959 ps
T98 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1444445668 Feb 21 02:51:55 PM PST 24 Feb 21 02:51:57 PM PST 24 48571943 ps
T180 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1448651252 Feb 21 02:51:46 PM PST 24 Feb 21 02:51:47 PM PST 24 94905769 ps
T1531 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2818661489 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:33 PM PST 24 36316713 ps
T1532 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.338869402 Feb 21 02:52:15 PM PST 24 Feb 21 02:52:19 PM PST 24 163375465 ps
T1533 /workspace/coverage/cover_reg_top/39.i2c_intr_test.4270304259 Feb 21 02:51:51 PM PST 24 Feb 21 02:51:52 PM PST 24 38188098 ps
T120 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1833353269 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:37 PM PST 24 3415253278 ps
T1534 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1186231200 Feb 21 02:51:29 PM PST 24 Feb 21 02:51:31 PM PST 24 19731796 ps
T1535 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2093579924 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:42 PM PST 24 69697627 ps
T1536 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3566415244 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:35 PM PST 24 23263882 ps
T1537 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2693307144 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:40 PM PST 24 62956126 ps
T1538 /workspace/coverage/cover_reg_top/25.i2c_intr_test.253418007 Feb 21 02:52:18 PM PST 24 Feb 21 02:52:19 PM PST 24 25814678 ps
T1539 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3872787041 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:35 PM PST 24 74589191 ps
T1540 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2346581522 Feb 21 02:52:08 PM PST 24 Feb 21 02:52:09 PM PST 24 16176360 ps
T1541 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3714158596 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:37 PM PST 24 53377025 ps
T121 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1953641814 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:39 PM PST 24 18809110 ps
T1542 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2445380205 Feb 21 02:51:58 PM PST 24 Feb 21 02:52:00 PM PST 24 28953650 ps
T1543 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1594031819 Feb 21 02:51:58 PM PST 24 Feb 21 02:52:01 PM PST 24 35058098 ps
T122 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2739218594 Feb 21 02:51:46 PM PST 24 Feb 21 02:51:48 PM PST 24 30266210 ps
T1544 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.279524149 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:38 PM PST 24 139550158 ps
T207 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.401122160 Feb 21 02:51:39 PM PST 24 Feb 21 02:51:41 PM PST 24 160375413 ps
T1545 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2717123852 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:43 PM PST 24 72540104 ps
T1546 /workspace/coverage/cover_reg_top/42.i2c_intr_test.4168827911 Feb 21 02:52:05 PM PST 24 Feb 21 02:52:06 PM PST 24 38121178 ps
T1547 /workspace/coverage/cover_reg_top/47.i2c_intr_test.640057397 Feb 21 02:51:39 PM PST 24 Feb 21 02:51:41 PM PST 24 27842153 ps
T1548 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2378441845 Feb 21 02:51:51 PM PST 24 Feb 21 02:51:53 PM PST 24 55490747 ps
T1549 /workspace/coverage/cover_reg_top/27.i2c_intr_test.1927244260 Feb 21 02:52:03 PM PST 24 Feb 21 02:52:04 PM PST 24 87280988 ps
T1550 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2498339009 Feb 21 02:51:33 PM PST 24 Feb 21 02:51:34 PM PST 24 47072498 ps
T1551 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1553593007 Feb 21 02:51:42 PM PST 24 Feb 21 02:51:43 PM PST 24 30614526 ps
T1552 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.247774591 Feb 21 02:51:48 PM PST 24 Feb 21 02:51:51 PM PST 24 46751923 ps
T1553 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.80106879 Feb 21 02:51:33 PM PST 24 Feb 21 02:51:36 PM PST 24 118863194 ps
T94 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.200876517 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:40 PM PST 24 84304032 ps
T1554 /workspace/coverage/cover_reg_top/3.i2c_intr_test.864781424 Feb 21 02:51:35 PM PST 24 Feb 21 02:51:36 PM PST 24 27243542 ps
T123 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1873702988 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:37 PM PST 24 1106148638 ps
T1555 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3769812328 Feb 21 02:52:03 PM PST 24 Feb 21 02:52:04 PM PST 24 22740819 ps
T1556 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3816110775 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:39 PM PST 24 45951184 ps
T1557 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4126163206 Feb 21 02:52:14 PM PST 24 Feb 21 02:52:16 PM PST 24 59487448 ps
T1558 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2374361661 Feb 21 02:52:00 PM PST 24 Feb 21 02:52:01 PM PST 24 55148398 ps
T1559 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1124506212 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:37 PM PST 24 35920239 ps
T92 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.221680651 Feb 21 02:51:39 PM PST 24 Feb 21 02:51:41 PM PST 24 130933067 ps
T1560 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2233264388 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:39 PM PST 24 66373725 ps
T124 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.269414377 Feb 21 02:51:48 PM PST 24 Feb 21 02:51:49 PM PST 24 50276994 ps
T1561 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3027623212 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:42 PM PST 24 296428793 ps
T1562 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1626781714 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:42 PM PST 24 160662995 ps
T1563 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1725682930 Feb 21 02:52:20 PM PST 24 Feb 21 02:52:22 PM PST 24 76687147 ps
T1564 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1470526369 Feb 21 02:51:55 PM PST 24 Feb 21 02:51:56 PM PST 24 16973849 ps
T127 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2847067291 Feb 21 02:51:50 PM PST 24 Feb 21 02:51:51 PM PST 24 33472714 ps
T1565 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1106600277 Feb 21 02:52:04 PM PST 24 Feb 21 02:52:05 PM PST 24 81650930 ps
T1566 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2023779807 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:39 PM PST 24 150406399 ps
T1567 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3108721339 Feb 21 02:51:54 PM PST 24 Feb 21 02:51:57 PM PST 24 141593383 ps
T1568 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2617380486 Feb 21 02:51:43 PM PST 24 Feb 21 02:51:44 PM PST 24 42103251 ps
T125 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3131819334 Feb 21 02:51:56 PM PST 24 Feb 21 02:51:58 PM PST 24 48146183 ps
T1569 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.140472981 Feb 21 02:51:40 PM PST 24 Feb 21 02:51:41 PM PST 24 106427626 ps
T1570 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1305051335 Feb 21 02:51:48 PM PST 24 Feb 21 02:51:51 PM PST 24 27965097 ps
T1571 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1802366037 Feb 21 02:51:54 PM PST 24 Feb 21 02:51:56 PM PST 24 62957484 ps
T1572 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2417963903 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:37 PM PST 24 43116990 ps
T208 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3793057508 Feb 21 02:52:13 PM PST 24 Feb 21 02:52:15 PM PST 24 256427700 ps
T1573 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.4134865016 Feb 21 02:51:33 PM PST 24 Feb 21 02:51:35 PM PST 24 96400328 ps
T1574 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4095632733 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:34 PM PST 24 46827460 ps
T1575 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3711864832 Feb 21 02:52:01 PM PST 24 Feb 21 02:52:02 PM PST 24 15541371 ps
T1576 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.4009546055 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:42 PM PST 24 23775933 ps
T1577 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1819526254 Feb 21 02:51:57 PM PST 24 Feb 21 02:52:01 PM PST 24 1753098747 ps
T1578 /workspace/coverage/cover_reg_top/48.i2c_intr_test.27409259 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:38 PM PST 24 87993158 ps
T1579 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1032525553 Feb 21 02:52:20 PM PST 24 Feb 21 02:52:21 PM PST 24 25339346 ps
T1580 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3583259178 Feb 21 02:51:58 PM PST 24 Feb 21 02:52:01 PM PST 24 96017000 ps
T1581 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2582438789 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:42 PM PST 24 49503638 ps
T93 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.384268267 Feb 21 02:51:40 PM PST 24 Feb 21 02:51:42 PM PST 24 578954604 ps
T1582 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2405288174 Feb 21 02:52:10 PM PST 24 Feb 21 02:52:12 PM PST 24 64986342 ps
T1583 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.984962577 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:36 PM PST 24 124556781 ps
T1584 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4156649020 Feb 21 02:52:02 PM PST 24 Feb 21 02:52:04 PM PST 24 16359453 ps
T1585 /workspace/coverage/cover_reg_top/12.i2c_intr_test.869139257 Feb 21 02:52:11 PM PST 24 Feb 21 02:52:12 PM PST 24 19904967 ps
T1586 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1357964238 Feb 21 02:52:16 PM PST 24 Feb 21 02:52:18 PM PST 24 50480299 ps
T1587 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1856219690 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:34 PM PST 24 31729313 ps
T1588 /workspace/coverage/cover_reg_top/21.i2c_intr_test.4173213214 Feb 21 02:51:48 PM PST 24 Feb 21 02:51:49 PM PST 24 22101260 ps
T1589 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.340378989 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:40 PM PST 24 58074481 ps
T126 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1292346820 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:40 PM PST 24 33168740 ps
T99 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3951352628 Feb 21 02:51:50 PM PST 24 Feb 21 02:51:52 PM PST 24 1922812212 ps
T1590 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2228177979 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:38 PM PST 24 24749620 ps
T1591 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2407424206 Feb 21 02:52:22 PM PST 24 Feb 21 02:52:23 PM PST 24 49558193 ps
T1592 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3580930586 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:38 PM PST 24 46965592 ps
T1593 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2574648516 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:34 PM PST 24 229399724 ps
T1594 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.14747872 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:42 PM PST 24 16472822 ps
T1595 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.907538383 Feb 21 02:51:35 PM PST 24 Feb 21 02:51:36 PM PST 24 59879010 ps
T95 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3462578985 Feb 21 02:52:02 PM PST 24 Feb 21 02:52:05 PM PST 24 199012224 ps
T1596 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1142391657 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:37 PM PST 24 18851832 ps
T1597 /workspace/coverage/cover_reg_top/35.i2c_intr_test.106691108 Feb 21 02:51:45 PM PST 24 Feb 21 02:51:46 PM PST 24 23232258 ps
T1598 /workspace/coverage/cover_reg_top/24.i2c_intr_test.219648609 Feb 21 02:52:20 PM PST 24 Feb 21 02:52:21 PM PST 24 50949664 ps
T1599 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2958277997 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:38 PM PST 24 34392592 ps
T1600 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1329962079 Feb 21 02:52:16 PM PST 24 Feb 21 02:52:23 PM PST 24 20195554 ps
T1601 /workspace/coverage/cover_reg_top/45.i2c_intr_test.26530334 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:37 PM PST 24 57911596 ps
T1602 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1796522682 Feb 21 02:51:42 PM PST 24 Feb 21 02:51:44 PM PST 24 214572852 ps
T96 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4025407558 Feb 21 02:51:57 PM PST 24 Feb 21 02:52:00 PM PST 24 1171176497 ps
T1603 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2034809467 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:40 PM PST 24 193796272 ps
T1604 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1258701695 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:39 PM PST 24 49255390 ps
T1605 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1778396033 Feb 21 02:52:15 PM PST 24 Feb 21 02:52:17 PM PST 24 16632932 ps
T1606 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1119368126 Feb 21 02:52:03 PM PST 24 Feb 21 02:52:05 PM PST 24 14558961 ps
T1607 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1603558078 Feb 21 02:52:10 PM PST 24 Feb 21 02:52:12 PM PST 24 18047370 ps
T1608 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3870086263 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:42 PM PST 24 208234667 ps
T1609 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.345980196 Feb 21 02:52:10 PM PST 24 Feb 21 02:52:13 PM PST 24 215343470 ps
T1610 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3440245824 Feb 21 02:52:05 PM PST 24 Feb 21 02:52:07 PM PST 24 30120271 ps
T1611 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3909847231 Feb 21 02:51:39 PM PST 24 Feb 21 02:51:40 PM PST 24 54507190 ps
T1612 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4102377045 Feb 21 02:52:04 PM PST 24 Feb 21 02:52:05 PM PST 24 39813484 ps
T1613 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1880325413 Feb 21 02:51:44 PM PST 24 Feb 21 02:51:46 PM PST 24 50517139 ps
T1614 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3417551382 Feb 21 02:52:01 PM PST 24 Feb 21 02:52:02 PM PST 24 21063009 ps
T1615 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1190121946 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:34 PM PST 24 26898158 ps
T1616 /workspace/coverage/cover_reg_top/0.i2c_intr_test.564117966 Feb 21 02:51:36 PM PST 24 Feb 21 02:51:37 PM PST 24 60120684 ps
T1617 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1028643665 Feb 21 02:51:59 PM PST 24 Feb 21 02:52:01 PM PST 24 46694928 ps
T1618 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.818108263 Feb 21 02:51:33 PM PST 24 Feb 21 02:51:37 PM PST 24 639846195 ps
T1619 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3845697094 Feb 21 02:51:35 PM PST 24 Feb 21 02:51:36 PM PST 24 26921836 ps
T1620 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3276718056 Feb 21 02:51:41 PM PST 24 Feb 21 02:51:44 PM PST 24 182238946 ps
T1621 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4110282061 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:38 PM PST 24 433209904 ps
T1622 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3913116057 Feb 21 02:51:53 PM PST 24 Feb 21 02:51:55 PM PST 24 145758073 ps
T1623 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.737717779 Feb 21 02:51:38 PM PST 24 Feb 21 02:51:39 PM PST 24 31466848 ps
T1624 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2481516652 Feb 21 02:51:37 PM PST 24 Feb 21 02:51:39 PM PST 24 34770953 ps
T1625 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1804404822 Feb 21 02:51:32 PM PST 24 Feb 21 02:51:33 PM PST 24 73607911 ps
T1626 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1630062517 Feb 21 02:51:34 PM PST 24 Feb 21 02:51:35 PM PST 24 27102045 ps

Test location /workspace/coverage/default/6.i2c_target_stress_all.373980548
Short name T6
Test name
Test status
Simulation time 71709477448 ps
CPU time 434.78 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:21:33 PM PST 24
Peak memory 3101704 kb
Host smart-d60f4708-1551-4e78-bb04-c1a505883396
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373980548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_target_stress_all.373980548
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_rx_oversample.3404466486
Short name T3
Test name
Test status
Simulation time 12994415849 ps
CPU time 232.44 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:19:39 PM PST 24
Peak memory 379856 kb
Host smart-71883c87-7e8c-46f4-8a7b-0be93314d14e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404466486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_rx_oversample
.3404466486
Directory /workspace/22.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2880488773
Short name T43
Test name
Test status
Simulation time 754668495 ps
CPU time 3.74 seconds
Started Feb 21 03:13:31 PM PST 24
Finished Feb 21 03:13:37 PM PST 24
Peak memory 203540 kb
Host smart-f5286d16-23b1-4768-9c9e-6927c74a92f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880488773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2880488773
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3630988910
Short name T62
Test name
Test status
Simulation time 45986112877 ps
CPU time 635.58 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:27:14 PM PST 24
Peak memory 1736980 kb
Host smart-c243da0a-5084-4d97-b055-91ba014d1b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630988910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3630988910
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2754434810
Short name T78
Test name
Test status
Simulation time 223556619 ps
CPU time 2.07 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:35 PM PST 24
Peak memory 203148 kb
Host smart-42a4c6f7-3c7e-4070-b660-e5a80956c324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754434810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2754434810
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/default/12.i2c_host_override.4052753266
Short name T166
Test name
Test status
Simulation time 19877891 ps
CPU time 0.66 seconds
Started Feb 21 03:14:29 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 202232 kb
Host smart-595840d8-92ee-4173-95b8-19e3daebcc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052753266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.4052753266
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2335166431
Short name T277
Test name
Test status
Simulation time 58129702368 ps
CPU time 1058.51 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:36:29 PM PST 24
Peak memory 3028396 kb
Host smart-690f962f-9ed8-42af-b364-cc879dd594ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335166431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2335166431
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2534358879
Short name T82
Test name
Test status
Simulation time 78815377 ps
CPU time 0.83 seconds
Started Feb 21 03:13:34 PM PST 24
Finished Feb 21 03:13:36 PM PST 24
Peak memory 219964 kb
Host smart-eefcdc67-c8cc-435e-b0ba-6a13e4c127fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534358879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2534358879
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.303634635
Short name T14
Test name
Test status
Simulation time 4099219024 ps
CPU time 128.59 seconds
Started Feb 21 03:17:40 PM PST 24
Finished Feb 21 03:19:49 PM PST 24
Peak memory 402740 kb
Host smart-0fcd8fb9-8606-4323-be11-68892a272cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303634635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.303634635
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.310226611
Short name T151
Test name
Test status
Simulation time 33087363169 ps
CPU time 341.78 seconds
Started Feb 21 03:20:07 PM PST 24
Finished Feb 21 03:25:49 PM PST 24
Peak memory 1033212 kb
Host smart-037839ae-63a9-4544-9baa-60a0df7a2c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310226611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.310226611
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1606881652
Short name T116
Test name
Test status
Simulation time 38751684 ps
CPU time 0.65 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 202428 kb
Host smart-0608f87b-62fe-4861-9a8d-2b13fc327965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606881652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1606881652
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.144244783
Short name T15
Test name
Test status
Simulation time 12680381715 ps
CPU time 602.31 seconds
Started Feb 21 03:18:08 PM PST 24
Finished Feb 21 03:28:11 PM PST 24
Peak memory 1068676 kb
Host smart-547f8dab-22bd-41f8-836f-35b9a4597957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144244783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.i2c_target_stress_all.144244783
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3417942046
Short name T11
Test name
Test status
Simulation time 4670516098 ps
CPU time 299.04 seconds
Started Feb 21 03:18:38 PM PST 24
Finished Feb 21 03:23:39 PM PST 24
Peak memory 1370736 kb
Host smart-59596c66-f958-4504-bd6b-c5c1a32b941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417942046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3417942046
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1829540053
Short name T7
Test name
Test status
Simulation time 14939380417 ps
CPU time 3.82 seconds
Started Feb 21 03:13:33 PM PST 24
Finished Feb 21 03:13:39 PM PST 24
Peak memory 203440 kb
Host smart-afef2670-1661-41b1-8be5-22e7b3895c01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829540053 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1829540053
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.2351688047
Short name T196
Test name
Test status
Simulation time 19365620837 ps
CPU time 3313.82 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 04:13:10 PM PST 24
Peak memory 2927992 kb
Host smart-a0217c58-d013-47ac-89cf-8de8d2c99483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351688047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.2351688047
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.221680651
Short name T92
Test name
Test status
Simulation time 130933067 ps
CPU time 2 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 203080 kb
Host smart-c4a70eed-e475-4b7b-98ee-4d45bc48baaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221680651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.221680651
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1230724818
Short name T604
Test name
Test status
Simulation time 40783016172 ps
CPU time 377.38 seconds
Started Feb 21 03:14:40 PM PST 24
Finished Feb 21 03:20:59 PM PST 24
Peak memory 1154092 kb
Host smart-dbb33841-040b-48eb-985c-329960a952f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230724818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1230724818
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3092832911
Short name T1265
Test name
Test status
Simulation time 2634207035 ps
CPU time 3.2 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:16:41 PM PST 24
Peak memory 203420 kb
Host smart-e89fd971-5f7a-4cf9-837a-79e07386909d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092832911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3092832911
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.2441540322
Short name T39
Test name
Test status
Simulation time 50703517378 ps
CPU time 1345.87 seconds
Started Feb 21 03:18:30 PM PST 24
Finished Feb 21 03:40:56 PM PST 24
Peak memory 1937832 kb
Host smart-a7679f04-e869-425b-b5c6-340096c5afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441540322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.2441540322
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1130435449
Short name T242
Test name
Test status
Simulation time 130308719 ps
CPU time 0.94 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:34 PM PST 24
Peak memory 203076 kb
Host smart-1895421e-6fc4-4232-9d25-3746d1422e47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130435449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1130435449
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_alert_test.156169849
Short name T348
Test name
Test status
Simulation time 16505690 ps
CPU time 0.6 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:14:22 PM PST 24
Peak memory 202116 kb
Host smart-5968d92e-503c-4c8d-9e14-7e6aa06a00c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156169849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.156169849
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1400086834
Short name T74
Test name
Test status
Simulation time 16680940649 ps
CPU time 141.66 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:18:08 PM PST 24
Peak memory 1027544 kb
Host smart-04de1f94-25c6-489c-bb54-d675cbd2f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400086834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1400086834
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_perf.4155900371
Short name T199
Test name
Test status
Simulation time 54104913520 ps
CPU time 192.01 seconds
Started Feb 21 03:16:47 PM PST 24
Finished Feb 21 03:19:59 PM PST 24
Peak memory 219688 kb
Host smart-140c09e4-ee7b-4ac7-89cf-358d33122e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155900371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.4155900371
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2688981469
Short name T64
Test name
Test status
Simulation time 23996217627 ps
CPU time 761.27 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:27:09 PM PST 24
Peak memory 2036156 kb
Host smart-7478cc9b-5c75-4730-9d79-5b2c1d56dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688981469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2688981469
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.1216303164
Short name T210
Test name
Test status
Simulation time 11456795699 ps
CPU time 6.66 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:16:43 PM PST 24
Peak memory 203408 kb
Host smart-ecb7675e-bed1-47dc-b013-9a49944f0b2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216303164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.i2c_target_unexp_stop.1216303164
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3462578985
Short name T95
Test name
Test status
Simulation time 199012224 ps
CPU time 1.66 seconds
Started Feb 21 02:52:02 PM PST 24
Finished Feb 21 02:52:05 PM PST 24
Peak memory 203172 kb
Host smart-70e59c2a-0902-4892-900c-0f7966664992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462578985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3462578985
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2385366484
Short name T522
Test name
Test status
Simulation time 2513085290 ps
CPU time 85.95 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:15:00 PM PST 24
Peak memory 341696 kb
Host smart-922be3df-4859-4953-b131-ea7a061f95a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385366484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2385366484
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_rx_oversample.2381361266
Short name T615
Test name
Test status
Simulation time 6857041098 ps
CPU time 79.15 seconds
Started Feb 21 03:14:19 PM PST 24
Finished Feb 21 03:15:38 PM PST 24
Peak memory 288088 kb
Host smart-23697173-b1ec-4f4b-a39e-8f81e024f53c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381361266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_rx_oversample
.2381361266
Directory /workspace/10.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_host_override.4220574254
Short name T197
Test name
Test status
Simulation time 24061645 ps
CPU time 0.6 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 202312 kb
Host smart-fc4d321f-5b7a-40eb-ae4e-69550d4ddf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220574254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.4220574254
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2713749203
Short name T202
Test name
Test status
Simulation time 5260276399 ps
CPU time 17.95 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:16:04 PM PST 24
Peak memory 214204 kb
Host smart-81835abb-ad7a-4804-af45-8dac75f98eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713749203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2713749203
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2172348693
Short name T239
Test name
Test status
Simulation time 49291906629 ps
CPU time 3515.25 seconds
Started Feb 21 03:20:22 PM PST 24
Finished Feb 21 04:18:58 PM PST 24
Peak memory 5359428 kb
Host smart-70f6f9e8-2b51-476e-8601-7518661bfcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172348693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2172348693
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2393962813
Short name T1522
Test name
Test status
Simulation time 57490296 ps
CPU time 0.73 seconds
Started Feb 21 02:52:00 PM PST 24
Finished Feb 21 02:52:02 PM PST 24
Peak memory 202912 kb
Host smart-4c11bf6a-3277-42c8-9fe6-39d9f1b715ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393962813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2393962813
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3776985702
Short name T412
Test name
Test status
Simulation time 65893674653 ps
CPU time 1170.44 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:33:05 PM PST 24
Peak memory 2444076 kb
Host smart-ddf7bce6-df6f-4ff7-bb1f-203675fe92a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776985702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3776985702
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2539022431
Short name T209
Test name
Test status
Simulation time 9260948824 ps
CPU time 19.95 seconds
Started Feb 21 03:13:24 PM PST 24
Finished Feb 21 03:13:45 PM PST 24
Peak memory 219788 kb
Host smart-b792c4d7-8be3-4eea-a4d2-17f8f1c82400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539022431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2539022431
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.407233374
Short name T811
Test name
Test status
Simulation time 18782017984 ps
CPU time 549.02 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:23:26 PM PST 24
Peak memory 1376012 kb
Host smart-2791fd75-495f-4fed-88b2-a93ae33aaf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407233374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.407233374
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1156653631
Short name T236
Test name
Test status
Simulation time 12783672268 ps
CPU time 781.8 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:27:23 PM PST 24
Peak memory 1795140 kb
Host smart-135427e7-8106-42f4-aa81-fcf0d669c58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156653631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1156653631
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3538285463
Short name T200
Test name
Test status
Simulation time 633124950 ps
CPU time 2.3 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203376 kb
Host smart-6ce53762-feca-4ebc-8203-7add773486f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538285463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3538285463
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.197372876
Short name T163
Test name
Test status
Simulation time 13105520098 ps
CPU time 1894.54 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:46:06 PM PST 24
Peak memory 2599324 kb
Host smart-149ec198-4ddc-4db9-8136-086cf1953e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197372876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.197372876
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3635547300
Short name T632
Test name
Test status
Simulation time 1813147331 ps
CPU time 4.74 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 229644 kb
Host smart-6bde2253-9a7d-4320-8750-5c10c26d6904
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635547300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3635547300
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.674219744
Short name T215
Test name
Test status
Simulation time 9198457899 ps
CPU time 243.64 seconds
Started Feb 21 03:14:50 PM PST 24
Finished Feb 21 03:18:54 PM PST 24
Peak memory 1314156 kb
Host smart-1be905e3-d6fa-47e6-85c3-03d5282db792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674219744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.674219744
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.259705596
Short name T1147
Test name
Test status
Simulation time 7412772085 ps
CPU time 7.85 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:30 PM PST 24
Peak memory 214648 kb
Host smart-67592f39-5ee5-42a8-a713-5ed08850e644
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259705596 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_unexp_stop.259705596
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.3769017861
Short name T232
Test name
Test status
Simulation time 10131923129 ps
CPU time 15.38 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:19:09 PM PST 24
Peak memory 277152 kb
Host smart-363d1bf6-5a0c-48e4-a4b5-47d6ae47e766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769017861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.3769017861
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1594031819
Short name T1543
Test name
Test status
Simulation time 35058098 ps
CPU time 0.88 seconds
Started Feb 21 02:51:58 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 203100 kb
Host smart-73f59d17-015c-432f-9623-012d9dfd3a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594031819 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1594031819
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3144380109
Short name T68
Test name
Test status
Simulation time 10698248301 ps
CPU time 12.02 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:36 PM PST 24
Peak memory 289108 kb
Host smart-05a71844-1164-407d-867e-05e0391bbd48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144380109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3144380109
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3214665110
Short name T1516
Test name
Test status
Simulation time 37560976 ps
CPU time 0.94 seconds
Started Feb 21 02:51:40 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 202304 kb
Host smart-22b794e6-bb82-4a97-9203-ae1be5d64491
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214665110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3214665110
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3027623212
Short name T1561
Test name
Test status
Simulation time 296428793 ps
CPU time 4.14 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 203108 kb
Host smart-cd7b8afa-a673-4a48-a96a-caa42a678b5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027623212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3027623212
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.14747872
Short name T1594
Test name
Test status
Simulation time 16472822 ps
CPU time 0.7 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 202972 kb
Host smart-f233b07b-fa91-4866-b45b-df6d1a5c7bc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14747872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.14747872
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2717123852
Short name T1545
Test name
Test status
Simulation time 72540104 ps
CPU time 0.99 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:43 PM PST 24
Peak memory 203128 kb
Host smart-5986e703-62ff-4842-bc51-75a9311d35df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717123852 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2717123852
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.177748040
Short name T135
Test name
Test status
Simulation time 20181352 ps
CPU time 0.65 seconds
Started Feb 21 02:51:40 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 202168 kb
Host smart-73eebf4c-ef3a-4750-93b5-32f3e7a1f8ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177748040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.177748040
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.564117966
Short name T1616
Test name
Test status
Simulation time 60120684 ps
CPU time 0.66 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 202932 kb
Host smart-be403767-b463-4ff3-b0c5-1b365bedfb9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564117966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.564117966
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.4009546055
Short name T1576
Test name
Test status
Simulation time 23775933 ps
CPU time 0.94 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 203024 kb
Host smart-3d46fe08-dd1f-49ff-95dc-f646fec347b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009546055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.4009546055
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2417963903
Short name T1572
Test name
Test status
Simulation time 43116990 ps
CPU time 1.95 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 203172 kb
Host smart-4ecc8459-3ac0-41d1-9cf2-3fa661941eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417963903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2417963903
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3276017961
Short name T206
Test name
Test status
Simulation time 97008325 ps
CPU time 1.84 seconds
Started Feb 21 02:51:56 PM PST 24
Finished Feb 21 02:51:59 PM PST 24
Peak memory 203076 kb
Host smart-372e4fce-1a1c-4e37-be54-ca30edd2c161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276017961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3276017961
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1796522682
Short name T1602
Test name
Test status
Simulation time 214572852 ps
CPU time 1.22 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:44 PM PST 24
Peak memory 203056 kb
Host smart-403cd313-fe53-4a9f-bb7e-6b6fdfbeef65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796522682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1796522682
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1819526254
Short name T1577
Test name
Test status
Simulation time 1753098747 ps
CPU time 2.48 seconds
Started Feb 21 02:51:57 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 203004 kb
Host smart-99fdc009-78b7-42a0-873e-7fca105950b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819526254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1819526254
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2522963755
Short name T115
Test name
Test status
Simulation time 53141597 ps
CPU time 0.64 seconds
Started Feb 21 02:51:56 PM PST 24
Finished Feb 21 02:51:58 PM PST 24
Peak memory 201800 kb
Host smart-65b491fc-a191-41bc-87dc-f4ed45704e14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522963755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2522963755
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4156649020
Short name T1584
Test name
Test status
Simulation time 16359453 ps
CPU time 0.66 seconds
Started Feb 21 02:52:02 PM PST 24
Finished Feb 21 02:52:04 PM PST 24
Peak memory 202016 kb
Host smart-3981801e-920d-4f6e-9feb-a111453173d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156649020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.4156649020
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.291025081
Short name T128
Test name
Test status
Simulation time 39807606 ps
CPU time 0.83 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:02 PM PST 24
Peak memory 202980 kb
Host smart-50ff584d-5d9f-427a-bb8d-fba722f1e825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291025081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.291025081
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2115658391
Short name T85
Test name
Test status
Simulation time 546770298 ps
CPU time 2.7 seconds
Started Feb 21 02:51:40 PM PST 24
Finished Feb 21 02:51:43 PM PST 24
Peak memory 203212 kb
Host smart-720b7513-06b6-4d2e-828a-b35b3968c26b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115658391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2115658391
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.150944501
Short name T75
Test name
Test status
Simulation time 86650227 ps
CPU time 1.21 seconds
Started Feb 21 02:51:56 PM PST 24
Finished Feb 21 02:51:59 PM PST 24
Peak memory 203116 kb
Host smart-271c45b2-2dec-4b69-ab91-c437d8cc66f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150944501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.150944501
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4003652911
Short name T1526
Test name
Test status
Simulation time 34328680 ps
CPU time 0.94 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 203060 kb
Host smart-96542f04-c9e9-4aa4-b17d-807b4d59c533
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003652911 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.4003652911
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3816110775
Short name T1556
Test name
Test status
Simulation time 45951184 ps
CPU time 0.67 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 202872 kb
Host smart-c5b12e3a-68dd-4ced-9cba-5ffea8d7445c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816110775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3816110775
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3566415244
Short name T1536
Test name
Test status
Simulation time 23263882 ps
CPU time 0.62 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:35 PM PST 24
Peak memory 202992 kb
Host smart-19321e27-e737-4af7-b84d-269dc3802a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566415244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3566415244
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4095632733
Short name T1574
Test name
Test status
Simulation time 46827460 ps
CPU time 1.18 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:34 PM PST 24
Peak memory 203072 kb
Host smart-538d4912-5550-4237-a15b-39be412c63f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095632733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.4095632733
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.818108263
Short name T1618
Test name
Test status
Simulation time 639846195 ps
CPU time 3.09 seconds
Started Feb 21 02:51:33 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 203168 kb
Host smart-f6eb623f-83e1-457b-8e15-961ca52a4cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818108263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.818108263
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3870086263
Short name T1608
Test name
Test status
Simulation time 208234667 ps
CPU time 1.32 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 203096 kb
Host smart-421a43cf-1dd3-488b-ab2e-46b6caf38d95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870086263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3870086263
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.140472981
Short name T1569
Test name
Test status
Simulation time 106427626 ps
CPU time 1.38 seconds
Started Feb 21 02:51:40 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 203200 kb
Host smart-83d13d8a-1bd0-4af5-b08e-738d66077bd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140472981 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.140472981
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2847067291
Short name T127
Test name
Test status
Simulation time 33472714 ps
CPU time 0.68 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:51:51 PM PST 24
Peak memory 202984 kb
Host smart-21baa3ac-d107-4356-be6a-c00d6827f296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847067291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2847067291
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3525677224
Short name T1518
Test name
Test status
Simulation time 16051076 ps
CPU time 0.65 seconds
Started Feb 21 02:51:31 PM PST 24
Finished Feb 21 02:51:33 PM PST 24
Peak memory 202888 kb
Host smart-25c91c90-c700-4569-96fd-77cb86b57bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525677224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3525677224
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1246617923
Short name T134
Test name
Test status
Simulation time 147123688 ps
CPU time 0.94 seconds
Started Feb 21 02:51:51 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 203116 kb
Host smart-cba0f38e-d655-46ad-a447-e51b6ef9d781
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246617923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1246617923
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.9553619
Short name T77
Test name
Test status
Simulation time 63308640 ps
CPU time 1.25 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 203048 kb
Host smart-d9c600a5-f5b8-4943-9c2e-43d3db0f1c08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9553619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.9553619
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3583259178
Short name T1580
Test name
Test status
Simulation time 96017000 ps
CPU time 0.88 seconds
Started Feb 21 02:51:58 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 203092 kb
Host smart-91c6a842-3d04-418d-9ccd-e30ad4621936
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583259178 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3583259178
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.183251902
Short name T130
Test name
Test status
Simulation time 18413523 ps
CPU time 0.68 seconds
Started Feb 21 02:51:57 PM PST 24
Finished Feb 21 02:51:59 PM PST 24
Peak memory 202888 kb
Host smart-e7a738c4-245b-4bee-9352-4d706ce4bf1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183251902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.183251902
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.869139257
Short name T1585
Test name
Test status
Simulation time 19904967 ps
CPU time 0.7 seconds
Started Feb 21 02:52:11 PM PST 24
Finished Feb 21 02:52:12 PM PST 24
Peak memory 202928 kb
Host smart-24275e5d-d794-4c1e-bae6-01e4a72e526d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869139257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.869139257
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1106600277
Short name T1565
Test name
Test status
Simulation time 81650930 ps
CPU time 0.94 seconds
Started Feb 21 02:52:04 PM PST 24
Finished Feb 21 02:52:05 PM PST 24
Peak memory 203044 kb
Host smart-cf309a7a-c21d-4e7b-95ab-f39f3ad9bd64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106600277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1106600277
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1802366037
Short name T1571
Test name
Test status
Simulation time 62957484 ps
CPU time 1.44 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:51:56 PM PST 24
Peak memory 203188 kb
Host smart-14957d83-95af-4697-9595-231290963839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802366037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1802366037
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3913116057
Short name T1622
Test name
Test status
Simulation time 145758073 ps
CPU time 1.78 seconds
Started Feb 21 02:51:53 PM PST 24
Finished Feb 21 02:51:55 PM PST 24
Peak memory 203156 kb
Host smart-5f60ac6d-1b3a-450b-be8b-8d7e2bee4470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913116057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3913116057
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.4126163206
Short name T1557
Test name
Test status
Simulation time 59487448 ps
CPU time 0.89 seconds
Started Feb 21 02:52:14 PM PST 24
Finished Feb 21 02:52:16 PM PST 24
Peak memory 203096 kb
Host smart-7e6c8b5e-96c1-45ff-80d8-aad1a6c7aafb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126163206 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.4126163206
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1953641814
Short name T121
Test name
Test status
Simulation time 18809110 ps
CPU time 0.67 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 202112 kb
Host smart-be27bc0e-d34f-4d16-aed9-4dabc7f604e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953641814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1953641814
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1778396033
Short name T1605
Test name
Test status
Simulation time 16632932 ps
CPU time 0.66 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 02:52:17 PM PST 24
Peak memory 202936 kb
Host smart-3f7cbcad-308a-4d1f-a86f-5fc6dead47d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778396033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1778396033
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3417551382
Short name T1614
Test name
Test status
Simulation time 21063009 ps
CPU time 0.79 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:02 PM PST 24
Peak memory 203000 kb
Host smart-c608614f-75fa-46e1-974b-1c62a73170d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417551382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3417551382
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3276718056
Short name T1620
Test name
Test status
Simulation time 182238946 ps
CPU time 1.51 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:44 PM PST 24
Peak memory 203164 kb
Host smart-9148556f-bf5e-411a-bdb9-7cf74400e0db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276718056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3276718056
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.384268267
Short name T93
Test name
Test status
Simulation time 578954604 ps
CPU time 1.79 seconds
Started Feb 21 02:51:40 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 203100 kb
Host smart-f71e5b57-d650-4a60-bc2e-4a5ff43a9d73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384268267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.384268267
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.232320088
Short name T1529
Test name
Test status
Simulation time 29012512 ps
CPU time 0.94 seconds
Started Feb 21 02:51:27 PM PST 24
Finished Feb 21 02:51:29 PM PST 24
Peak memory 203104 kb
Host smart-ed5c9d96-2a29-4141-b0e1-3580d6c215c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232320088 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.232320088
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3944148458
Short name T118
Test name
Test status
Simulation time 25818798 ps
CPU time 0.72 seconds
Started Feb 21 02:52:17 PM PST 24
Finished Feb 21 02:52:18 PM PST 24
Peak memory 202932 kb
Host smart-52ef7f42-4e02-4609-a4fc-450fb9002ad7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944148458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3944148458
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.219252094
Short name T1517
Test name
Test status
Simulation time 38321214 ps
CPU time 0.61 seconds
Started Feb 21 02:52:17 PM PST 24
Finished Feb 21 02:52:19 PM PST 24
Peak memory 202940 kb
Host smart-1521b2bc-6432-4c61-ba7e-9291ee85adfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219252094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.219252094
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2445380205
Short name T1542
Test name
Test status
Simulation time 28953650 ps
CPU time 0.76 seconds
Started Feb 21 02:51:58 PM PST 24
Finished Feb 21 02:52:00 PM PST 24
Peak memory 202992 kb
Host smart-877fa752-7b4a-45a0-8b15-e8a1b8ce9b49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445380205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2445380205
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.480570015
Short name T114
Test name
Test status
Simulation time 55803074 ps
CPU time 1.65 seconds
Started Feb 21 02:52:21 PM PST 24
Finished Feb 21 02:52:23 PM PST 24
Peak memory 203136 kb
Host smart-d5cddd5d-0ad9-4044-8067-22f0a03f1258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480570015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.480570015
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3793057508
Short name T208
Test name
Test status
Simulation time 256427700 ps
CPU time 1.27 seconds
Started Feb 21 02:52:13 PM PST 24
Finished Feb 21 02:52:15 PM PST 24
Peak memory 203108 kb
Host smart-36c08af0-661d-4565-8464-443a6fc8bcb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793057508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3793057508
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1973891938
Short name T76
Test name
Test status
Simulation time 24525756 ps
CPU time 0.78 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 203236 kb
Host smart-a93b9eea-84b1-4439-bac3-8573bda82227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973891938 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1973891938
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2407424206
Short name T1591
Test name
Test status
Simulation time 49558193 ps
CPU time 0.64 seconds
Started Feb 21 02:52:22 PM PST 24
Finished Feb 21 02:52:23 PM PST 24
Peak memory 202932 kb
Host smart-3dda1181-e33a-45c0-baec-c49bdc7711e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407424206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2407424206
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1119368126
Short name T1606
Test name
Test status
Simulation time 14558961 ps
CPU time 0.63 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 02:52:05 PM PST 24
Peak memory 202932 kb
Host smart-4fdac9b0-c53a-4d68-bd1a-6e4405a0eeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119368126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1119368126
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2958277997
Short name T1599
Test name
Test status
Simulation time 34392592 ps
CPU time 0.79 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 203004 kb
Host smart-0dea35df-6576-49af-a5be-0a26d66d600e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958277997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2958277997
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3566096593
Short name T86
Test name
Test status
Simulation time 56182119 ps
CPU time 1.43 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:51:56 PM PST 24
Peak memory 203220 kb
Host smart-86c18daf-16c4-452c-8e9c-f0f20a74e567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566096593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3566096593
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1725682930
Short name T1563
Test name
Test status
Simulation time 76687147 ps
CPU time 1.26 seconds
Started Feb 21 02:52:20 PM PST 24
Finished Feb 21 02:52:22 PM PST 24
Peak memory 203184 kb
Host smart-e8f028e3-e598-48c1-8549-dc2ad4214c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725682930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1725682930
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2481516652
Short name T1624
Test name
Test status
Simulation time 34770953 ps
CPU time 1.38 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 202860 kb
Host smart-35264ce5-fbd8-4388-b62e-eee2275d875f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481516652 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2481516652
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3131819334
Short name T125
Test name
Test status
Simulation time 48146183 ps
CPU time 0.68 seconds
Started Feb 21 02:51:56 PM PST 24
Finished Feb 21 02:51:58 PM PST 24
Peak memory 202564 kb
Host smart-a8d2b853-323a-4ede-aeef-d4f52b5e0251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131819334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3131819334
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1463574996
Short name T1512
Test name
Test status
Simulation time 19180721 ps
CPU time 0.67 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 202912 kb
Host smart-6d0f8310-0b8f-4102-b620-0dc6395b3e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463574996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1463574996
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1186231200
Short name T1534
Test name
Test status
Simulation time 19731796 ps
CPU time 0.79 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 202976 kb
Host smart-16004da4-2e80-4840-9775-28c49d467959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186231200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1186231200
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.4214750206
Short name T113
Test name
Test status
Simulation time 83275339 ps
CPU time 1.85 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:44 PM PST 24
Peak memory 203172 kb
Host smart-e16001ed-6c16-4b7d-8f7c-b5c727283709
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214750206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.4214750206
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3951352628
Short name T99
Test name
Test status
Simulation time 1922812212 ps
CPU time 1.87 seconds
Started Feb 21 02:51:50 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 203108 kb
Host smart-42b61462-737c-4698-920f-ca12d2bf504e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951352628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3951352628
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1305051335
Short name T1570
Test name
Test status
Simulation time 27965097 ps
CPU time 0.79 seconds
Started Feb 21 02:51:48 PM PST 24
Finished Feb 21 02:51:51 PM PST 24
Peak memory 203076 kb
Host smart-e6970413-2a4a-4cc2-86f2-0984707ac7c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305051335 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1305051335
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2617380486
Short name T1568
Test name
Test status
Simulation time 42103251 ps
CPU time 0.65 seconds
Started Feb 21 02:51:43 PM PST 24
Finished Feb 21 02:51:44 PM PST 24
Peak memory 202112 kb
Host smart-9a27b491-3c74-4dea-9aa0-7fb2f18b5c7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617380486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2617380486
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2903563259
Short name T1513
Test name
Test status
Simulation time 23542882 ps
CPU time 0.68 seconds
Started Feb 21 02:51:29 PM PST 24
Finished Feb 21 02:51:30 PM PST 24
Peak memory 202928 kb
Host smart-78ce3d8e-0a22-4a97-beae-5026a7bef35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903563259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2903563259
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.247774591
Short name T1552
Test name
Test status
Simulation time 46751923 ps
CPU time 0.75 seconds
Started Feb 21 02:51:48 PM PST 24
Finished Feb 21 02:51:51 PM PST 24
Peak memory 202888 kb
Host smart-3ed36e74-ca89-41e5-95f7-640c10a41dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247774591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.247774591
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1087906207
Short name T97
Test name
Test status
Simulation time 191820440 ps
CPU time 2.41 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:45 PM PST 24
Peak memory 203116 kb
Host smart-6592fdb0-737c-446b-96f2-3afbee99875b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087906207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1087906207
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.569266655
Short name T87
Test name
Test status
Simulation time 73139092 ps
CPU time 1.2 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:44 PM PST 24
Peak memory 203084 kb
Host smart-45758ec7-8770-415c-a441-49fcdbcd5cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569266655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.569266655
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1032525553
Short name T1579
Test name
Test status
Simulation time 25339346 ps
CPU time 0.75 seconds
Started Feb 21 02:52:20 PM PST 24
Finished Feb 21 02:52:21 PM PST 24
Peak memory 203060 kb
Host smart-b2528ec4-f067-482a-b1d8-0e7f1cfd7762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032525553 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1032525553
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2374361661
Short name T1558
Test name
Test status
Simulation time 55148398 ps
CPU time 0.64 seconds
Started Feb 21 02:52:00 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 202088 kb
Host smart-7f905022-5e3c-4809-a186-0dc4dd5745e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374361661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2374361661
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1433901023
Short name T156
Test name
Test status
Simulation time 26592458 ps
CPU time 0.66 seconds
Started Feb 21 02:51:44 PM PST 24
Finished Feb 21 02:51:45 PM PST 24
Peak memory 202928 kb
Host smart-d3279b18-3421-4c42-8a4f-3490a4a447fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433901023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1433901023
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.758279207
Short name T132
Test name
Test status
Simulation time 51059162 ps
CPU time 0.76 seconds
Started Feb 21 02:51:56 PM PST 24
Finished Feb 21 02:51:58 PM PST 24
Peak memory 202980 kb
Host smart-08949dc7-5f89-4c0b-84fb-052836b24636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758279207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou
tstanding.758279207
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3108721339
Short name T1567
Test name
Test status
Simulation time 141593383 ps
CPU time 2.05 seconds
Started Feb 21 02:51:54 PM PST 24
Finished Feb 21 02:51:57 PM PST 24
Peak memory 203132 kb
Host smart-d3fe25b2-696c-40ca-bb51-dbe52d55a6c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108721339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3108721339
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1444445668
Short name T98
Test name
Test status
Simulation time 48571943 ps
CPU time 1.2 seconds
Started Feb 21 02:51:55 PM PST 24
Finished Feb 21 02:51:57 PM PST 24
Peak memory 203156 kb
Host smart-18c7470f-afb5-4903-9cec-479178a136cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444445668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1444445668
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4102377045
Short name T1612
Test name
Test status
Simulation time 39813484 ps
CPU time 0.71 seconds
Started Feb 21 02:52:04 PM PST 24
Finished Feb 21 02:52:05 PM PST 24
Peak memory 203060 kb
Host smart-5d0d4525-909b-42b0-9989-b30d00473519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102377045 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.4102377045
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1028643665
Short name T1617
Test name
Test status
Simulation time 46694928 ps
CPU time 0.71 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 202896 kb
Host smart-4174b43f-5706-420c-9a3d-e587f327ba71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028643665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1028643665
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3440245824
Short name T1610
Test name
Test status
Simulation time 30120271 ps
CPU time 0.69 seconds
Started Feb 21 02:52:05 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 202828 kb
Host smart-227b8194-5ea7-4017-be9a-8b4b4be25ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440245824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3440245824
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2378441845
Short name T1548
Test name
Test status
Simulation time 55490747 ps
CPU time 0.8 seconds
Started Feb 21 02:51:51 PM PST 24
Finished Feb 21 02:51:53 PM PST 24
Peak memory 203024 kb
Host smart-f587ae7f-3dd1-456c-bde3-c26642a65a72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378441845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2378441845
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.345980196
Short name T1609
Test name
Test status
Simulation time 215343470 ps
CPU time 1.42 seconds
Started Feb 21 02:52:10 PM PST 24
Finished Feb 21 02:52:13 PM PST 24
Peak memory 203172 kb
Host smart-dd55f86c-8529-4ea2-b889-2d0553fb6371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345980196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.345980196
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4025407558
Short name T96
Test name
Test status
Simulation time 1171176497 ps
CPU time 1.89 seconds
Started Feb 21 02:51:57 PM PST 24
Finished Feb 21 02:52:00 PM PST 24
Peak memory 203112 kb
Host smart-ab8c11a8-6c24-4949-b3c9-59b59592d026
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025407558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4025407558
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2739218594
Short name T122
Test name
Test status
Simulation time 30266210 ps
CPU time 1.27 seconds
Started Feb 21 02:51:46 PM PST 24
Finished Feb 21 02:51:48 PM PST 24
Peak memory 203052 kb
Host smart-dd692bbe-478f-4a48-8eee-e667a3e05355
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739218594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2739218594
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.338869402
Short name T1532
Test name
Test status
Simulation time 163375465 ps
CPU time 2.12 seconds
Started Feb 21 02:52:15 PM PST 24
Finished Feb 21 02:52:19 PM PST 24
Peak memory 203104 kb
Host smart-4d4b3ce0-b572-4555-9d53-c0d51b30104e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338869402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.338869402
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2405288174
Short name T1582
Test name
Test status
Simulation time 64986342 ps
CPU time 0.71 seconds
Started Feb 21 02:52:10 PM PST 24
Finished Feb 21 02:52:12 PM PST 24
Peak memory 202944 kb
Host smart-d96163ec-2465-4787-a0a0-b1ee717fc4f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405288174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2405288174
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.737717779
Short name T1623
Test name
Test status
Simulation time 31466848 ps
CPU time 0.88 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 203068 kb
Host smart-44c5f584-0239-4c1c-ac1d-8f6bc49832d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737717779 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.737717779
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.269414377
Short name T124
Test name
Test status
Simulation time 50276994 ps
CPU time 0.64 seconds
Started Feb 21 02:51:48 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 202904 kb
Host smart-ab46152f-7d5c-42e5-9b75-d18ce3ec959f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269414377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.269414377
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1681599531
Short name T155
Test name
Test status
Simulation time 41853660 ps
CPU time 0.61 seconds
Started Feb 21 02:51:46 PM PST 24
Finished Feb 21 02:51:47 PM PST 24
Peak memory 202940 kb
Host smart-dbe0d7db-f5fb-4d8a-9bf6-ba37719e18a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681599531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1681599531
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1448651252
Short name T180
Test name
Test status
Simulation time 94905769 ps
CPU time 1.01 seconds
Started Feb 21 02:51:46 PM PST 24
Finished Feb 21 02:51:47 PM PST 24
Peak memory 203040 kb
Host smart-0c847b8f-037b-4781-ab7b-a340b9d117c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448651252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1448651252
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.384772352
Short name T1524
Test name
Test status
Simulation time 87146487 ps
CPU time 1.84 seconds
Started Feb 21 02:51:57 PM PST 24
Finished Feb 21 02:52:00 PM PST 24
Peak memory 203148 kb
Host smart-928ac5c1-99cf-4fee-bd7e-969362d37766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384772352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.384772352
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2141712262
Short name T1515
Test name
Test status
Simulation time 16963713 ps
CPU time 0.65 seconds
Started Feb 21 02:52:05 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 202828 kb
Host smart-0c77cf9a-59bf-4e3e-986d-0a9768db78d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141712262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2141712262
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.4173213214
Short name T1588
Test name
Test status
Simulation time 22101260 ps
CPU time 0.61 seconds
Started Feb 21 02:51:48 PM PST 24
Finished Feb 21 02:51:49 PM PST 24
Peak memory 202940 kb
Host smart-0460e444-5e25-409c-9808-4bb76aa4e3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173213214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.4173213214
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1470526369
Short name T1564
Test name
Test status
Simulation time 16973849 ps
CPU time 0.66 seconds
Started Feb 21 02:51:55 PM PST 24
Finished Feb 21 02:51:56 PM PST 24
Peak memory 202948 kb
Host smart-81b5e5be-c258-4d13-8432-dc586abccb96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470526369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1470526369
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1626781714
Short name T1562
Test name
Test status
Simulation time 160662995 ps
CPU time 0.69 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 202920 kb
Host smart-876a86be-49de-49ae-a08f-84ca941d55e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626781714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1626781714
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.219648609
Short name T1598
Test name
Test status
Simulation time 50949664 ps
CPU time 0.64 seconds
Started Feb 21 02:52:20 PM PST 24
Finished Feb 21 02:52:21 PM PST 24
Peak memory 202940 kb
Host smart-6c7ad73c-3293-4d11-8e4d-2f99bc6f8078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219648609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.219648609
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.253418007
Short name T1538
Test name
Test status
Simulation time 25814678 ps
CPU time 0.62 seconds
Started Feb 21 02:52:18 PM PST 24
Finished Feb 21 02:52:19 PM PST 24
Peak memory 202940 kb
Host smart-b686d7e4-23e2-418d-bc65-66156b3c2af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253418007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.253418007
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2645295934
Short name T1519
Test name
Test status
Simulation time 16084190 ps
CPU time 0.62 seconds
Started Feb 21 02:52:16 PM PST 24
Finished Feb 21 02:52:18 PM PST 24
Peak memory 202936 kb
Host smart-a4add612-5bae-4b44-838b-706b25b2e79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645295934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2645295934
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1927244260
Short name T1549
Test name
Test status
Simulation time 87280988 ps
CPU time 0.71 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 02:52:04 PM PST 24
Peak memory 202924 kb
Host smart-b892e4d8-dc82-45cc-a879-0ebd24d29aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927244260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1927244260
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1435653439
Short name T1511
Test name
Test status
Simulation time 25617832 ps
CPU time 0.7 seconds
Started Feb 21 02:52:14 PM PST 24
Finished Feb 21 02:52:16 PM PST 24
Peak memory 202936 kb
Host smart-0c9bf9a0-5357-4285-9d01-17f1d429bd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435653439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1435653439
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1755448195
Short name T1523
Test name
Test status
Simulation time 17611271 ps
CPU time 0.65 seconds
Started Feb 21 02:52:06 PM PST 24
Finished Feb 21 02:52:07 PM PST 24
Peak memory 202908 kb
Host smart-74b5770a-68e0-4132-abdc-f2823ebbadb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755448195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1755448195
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2228177979
Short name T1590
Test name
Test status
Simulation time 24749620 ps
CPU time 0.88 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 202952 kb
Host smart-b3dcd57e-f47c-489d-b9d9-01064deb0c4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228177979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2228177979
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3602519293
Short name T119
Test name
Test status
Simulation time 176289681 ps
CPU time 3.65 seconds
Started Feb 21 02:51:26 PM PST 24
Finished Feb 21 02:51:31 PM PST 24
Peak memory 203000 kb
Host smart-7f092603-c984-42fa-b5d5-4c8a79fe82c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602519293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3602519293
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1258701695
Short name T1604
Test name
Test status
Simulation time 49255390 ps
CPU time 0.74 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 202952 kb
Host smart-46b81491-f5c2-4233-857c-e7f888bd3929
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258701695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1258701695
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1856219690
Short name T1587
Test name
Test status
Simulation time 31729313 ps
CPU time 0.83 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:34 PM PST 24
Peak memory 203112 kb
Host smart-beb88f2d-64d9-4615-9e35-07ade5125ba0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856219690 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1856219690
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3872787041
Short name T1539
Test name
Test status
Simulation time 74589191 ps
CPU time 0.63 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:35 PM PST 24
Peak memory 202044 kb
Host smart-357dc7cc-884b-4ccc-aa40-4e557f7a0c6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872787041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3872787041
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.864781424
Short name T1554
Test name
Test status
Simulation time 27243542 ps
CPU time 0.7 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 202916 kb
Host smart-593091a2-0528-4c89-a53a-62d66d1e2e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864781424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.864781424
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2023779807
Short name T1566
Test name
Test status
Simulation time 150406399 ps
CPU time 0.91 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 203044 kb
Host smart-f97b0aa4-4076-4673-9025-9b85023f01f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023779807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2023779807
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.4134865016
Short name T1573
Test name
Test status
Simulation time 96400328 ps
CPU time 2.15 seconds
Started Feb 21 02:51:33 PM PST 24
Finished Feb 21 02:51:35 PM PST 24
Peak memory 203116 kb
Host smart-8437f8a5-aa29-4c60-8291-c20dff6ff543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134865016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.4134865016
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2574648516
Short name T1593
Test name
Test status
Simulation time 229399724 ps
CPU time 1.33 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:34 PM PST 24
Peak memory 203172 kb
Host smart-843da297-e82c-491c-ac48-f65e97818c63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574648516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2574648516
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3769812328
Short name T1555
Test name
Test status
Simulation time 22740819 ps
CPU time 0.68 seconds
Started Feb 21 02:52:03 PM PST 24
Finished Feb 21 02:52:04 PM PST 24
Peak memory 202936 kb
Host smart-77b9838e-4fc0-42ff-b727-95b48e666dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769812328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3769812328
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3711864832
Short name T1575
Test name
Test status
Simulation time 15541371 ps
CPU time 0.64 seconds
Started Feb 21 02:52:01 PM PST 24
Finished Feb 21 02:52:02 PM PST 24
Peak memory 202976 kb
Host smart-557c9280-947d-4a6b-96e0-4915b828b845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711864832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3711864832
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1357964238
Short name T1586
Test name
Test status
Simulation time 50480299 ps
CPU time 0.66 seconds
Started Feb 21 02:52:16 PM PST 24
Finished Feb 21 02:52:18 PM PST 24
Peak memory 202972 kb
Host smart-d1ad2f9f-6f55-44df-8f57-f06f03d16757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357964238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1357964238
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.243841433
Short name T1530
Test name
Test status
Simulation time 39302959 ps
CPU time 0.65 seconds
Started Feb 21 02:51:58 PM PST 24
Finished Feb 21 02:52:00 PM PST 24
Peak memory 202900 kb
Host smart-771017ec-6a56-476f-9761-eb70b91b6f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243841433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.243841433
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1329962079
Short name T1600
Test name
Test status
Simulation time 20195554 ps
CPU time 0.72 seconds
Started Feb 21 02:52:16 PM PST 24
Finished Feb 21 02:52:23 PM PST 24
Peak memory 202976 kb
Host smart-0e9debce-315f-49ff-bf8a-9e933f5ea5a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329962079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1329962079
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.106691108
Short name T1597
Test name
Test status
Simulation time 23232258 ps
CPU time 0.64 seconds
Started Feb 21 02:51:45 PM PST 24
Finished Feb 21 02:51:46 PM PST 24
Peak memory 202924 kb
Host smart-9eb207a6-c4ab-4787-8e48-81e41ba9bb6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106691108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.106691108
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2346581522
Short name T1540
Test name
Test status
Simulation time 16176360 ps
CPU time 0.7 seconds
Started Feb 21 02:52:08 PM PST 24
Finished Feb 21 02:52:09 PM PST 24
Peak memory 202908 kb
Host smart-c73b6786-4cef-4d21-92eb-e1eeb063df7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346581522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2346581522
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.147837433
Short name T1520
Test name
Test status
Simulation time 18433951 ps
CPU time 0.71 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 202976 kb
Host smart-c8e9019c-184e-4f05-9182-ae135009c650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147837433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.147837433
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2317600697
Short name T1514
Test name
Test status
Simulation time 59449411 ps
CPU time 0.7 seconds
Started Feb 21 02:52:05 PM PST 24
Finished Feb 21 02:52:06 PM PST 24
Peak memory 202896 kb
Host smart-8b7d8dc5-e6b9-4904-a709-790c77f4ce24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317600697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2317600697
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.4270304259
Short name T1533
Test name
Test status
Simulation time 38188098 ps
CPU time 0.69 seconds
Started Feb 21 02:51:51 PM PST 24
Finished Feb 21 02:51:52 PM PST 24
Peak memory 202980 kb
Host smart-fe01e533-70e8-430b-b8cd-41263327175a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270304259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.4270304259
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1873702988
Short name T123
Test name
Test status
Simulation time 1106148638 ps
CPU time 1.28 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 203132 kb
Host smart-a63e5065-f824-49ce-89f6-1616b56de22a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873702988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1873702988
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1833353269
Short name T120
Test name
Test status
Simulation time 3415253278 ps
CPU time 4.15 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 203140 kb
Host smart-425eb358-27fc-4f59-9b0e-13a658fb652a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833353269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1833353269
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1124506212
Short name T1559
Test name
Test status
Simulation time 35920239 ps
CPU time 0.72 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 202948 kb
Host smart-1bfd3b6e-5474-4494-a0be-411952bfd626
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124506212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1124506212
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1630062517
Short name T1626
Test name
Test status
Simulation time 27102045 ps
CPU time 1.05 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:35 PM PST 24
Peak memory 203112 kb
Host smart-855daf29-1c51-4b1b-a4f7-8bfbf8b78adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630062517 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1630062517
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1804404822
Short name T1625
Test name
Test status
Simulation time 73607911 ps
CPU time 0.76 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:33 PM PST 24
Peak memory 202968 kb
Host smart-bc2a6dbe-b60f-432d-ac07-ccd0315d2eeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804404822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1804404822
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3714158596
Short name T1541
Test name
Test status
Simulation time 53377025 ps
CPU time 0.67 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 202432 kb
Host smart-e06ffb2f-9ea0-4177-a650-bc6be107cfa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714158596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3714158596
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.340378989
Short name T1589
Test name
Test status
Simulation time 58074481 ps
CPU time 0.92 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 203068 kb
Host smart-a1dc984d-20b8-4074-b13f-4cf8e99885c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340378989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.340378989
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1880325413
Short name T1613
Test name
Test status
Simulation time 50517139 ps
CPU time 2.28 seconds
Started Feb 21 02:51:44 PM PST 24
Finished Feb 21 02:51:46 PM PST 24
Peak memory 203124 kb
Host smart-d2962ded-e775-44a5-904e-6e3cdf92ee02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880325413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1880325413
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4042895654
Short name T1527
Test name
Test status
Simulation time 38363640 ps
CPU time 0.66 seconds
Started Feb 21 02:51:59 PM PST 24
Finished Feb 21 02:52:01 PM PST 24
Peak memory 202976 kb
Host smart-6257201a-5f4e-4855-9b88-85dcced1c99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042895654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4042895654
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3094310730
Short name T1528
Test name
Test status
Simulation time 21343543 ps
CPU time 0.63 seconds
Started Feb 21 02:52:04 PM PST 24
Finished Feb 21 02:52:05 PM PST 24
Peak memory 202936 kb
Host smart-7c4c3301-09a1-40ec-89da-7e356f699656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094310730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3094310730
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.4168827911
Short name T1546
Test name
Test status
Simulation time 38121178 ps
CPU time 0.63 seconds
Started Feb 21 02:52:05 PM PST 24
Finished Feb 21 02:52:06 PM PST 24
Peak memory 202888 kb
Host smart-16b71ccc-022b-49eb-a164-df76a18642ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168827911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.4168827911
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1603558078
Short name T1607
Test name
Test status
Simulation time 18047370 ps
CPU time 0.7 seconds
Started Feb 21 02:52:10 PM PST 24
Finished Feb 21 02:52:12 PM PST 24
Peak memory 202928 kb
Host smart-59cc028b-987b-4ee8-b87b-e10e886cb328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603558078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1603558078
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3580930586
Short name T1592
Test name
Test status
Simulation time 46965592 ps
CPU time 0.65 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 203104 kb
Host smart-0ef98181-2ac0-4d13-af11-4c07b1b50b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580930586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3580930586
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.26530334
Short name T1601
Test name
Test status
Simulation time 57911596 ps
CPU time 0.63 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 202872 kb
Host smart-3882535f-f745-4274-a2f7-6fa33ec04bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.26530334
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1553593007
Short name T1551
Test name
Test status
Simulation time 30614526 ps
CPU time 0.63 seconds
Started Feb 21 02:51:42 PM PST 24
Finished Feb 21 02:51:43 PM PST 24
Peak memory 202864 kb
Host smart-da49c78b-ed56-439d-aaec-66edccdf2884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553593007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1553593007
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.640057397
Short name T1547
Test name
Test status
Simulation time 27842153 ps
CPU time 0.66 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 202912 kb
Host smart-2b0a0a49-29bb-4038-a993-387809777141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640057397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.640057397
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.27409259
Short name T1578
Test name
Test status
Simulation time 87993158 ps
CPU time 0.68 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 202800 kb
Host smart-5ec77bf8-1b8b-4627-ab7c-241636d22984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.27409259
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2498339009
Short name T1550
Test name
Test status
Simulation time 47072498 ps
CPU time 0.62 seconds
Started Feb 21 02:51:33 PM PST 24
Finished Feb 21 02:51:34 PM PST 24
Peak memory 202928 kb
Host smart-6f573126-8b05-41aa-888e-ca81a1844061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498339009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2498339009
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2429808070
Short name T79
Test name
Test status
Simulation time 119708824 ps
CPU time 0.97 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 203084 kb
Host smart-104cb102-b5ec-4ae4-b7a4-c4d8e634253a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429808070 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2429808070
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1190121946
Short name T1615
Test name
Test status
Simulation time 26898158 ps
CPU time 0.67 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:34 PM PST 24
Peak memory 202944 kb
Host smart-1facd9c5-783d-46fc-825a-5b4e8d8df604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190121946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1190121946
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3845697094
Short name T1619
Test name
Test status
Simulation time 26921836 ps
CPU time 0.64 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 202916 kb
Host smart-37c5a5a2-c225-4608-ad51-acc479f7a5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845697094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3845697094
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4110282061
Short name T1621
Test name
Test status
Simulation time 433209904 ps
CPU time 0.95 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 203116 kb
Host smart-7e5599eb-2580-4aab-b354-fca1d0be6d7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110282061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4110282061
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.320013694
Short name T91
Test name
Test status
Simulation time 550807287 ps
CPU time 1.95 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 203132 kb
Host smart-5341e872-bbe4-4ebe-adf8-4bc36b3a7601
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320013694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.320013694
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.24269215
Short name T80
Test name
Test status
Simulation time 68960883 ps
CPU time 1.33 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 203148 kb
Host smart-c7c443a2-ea26-4cea-8a51-52a2b02c4a8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24269215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.24269215
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2093579924
Short name T1535
Test name
Test status
Simulation time 69697627 ps
CPU time 0.72 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 203080 kb
Host smart-d5b87b13-1e2d-4a6c-8891-8f23e6126e48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093579924 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2093579924
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3909847231
Short name T1611
Test name
Test status
Simulation time 54507190 ps
CPU time 0.67 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 202896 kb
Host smart-87e7c33e-de5c-40cd-9139-1c0c9bb3cc88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909847231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3909847231
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3031015224
Short name T129
Test name
Test status
Simulation time 96319684 ps
CPU time 0.81 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 203164 kb
Host smart-711c9c5a-bf8d-4962-a49c-73051e232000
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031015224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3031015224
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2988346265
Short name T100
Test name
Test status
Simulation time 60680168 ps
CPU time 1.47 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 203112 kb
Host smart-fb63da10-2908-432c-bf2d-8eaa5c90e085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988346265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2988346265
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.401122160
Short name T207
Test name
Test status
Simulation time 160375413 ps
CPU time 1.2 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:41 PM PST 24
Peak memory 203080 kb
Host smart-a4a623de-a832-43ee-bf36-6743619ee52d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401122160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.401122160
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.984962577
Short name T1583
Test name
Test status
Simulation time 124556781 ps
CPU time 0.9 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 203112 kb
Host smart-0a93daf7-6741-4ee9-8ad1-adee5d441d62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984962577 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.984962577
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1292346820
Short name T126
Test name
Test status
Simulation time 33168740 ps
CPU time 0.63 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 202312 kb
Host smart-b928b496-52de-489d-a217-5203842c0fae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292346820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1292346820
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3568484710
Short name T1525
Test name
Test status
Simulation time 28294087 ps
CPU time 0.67 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 202904 kb
Host smart-cda47b74-9ce9-4134-b686-9d69cd5e6ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568484710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3568484710
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1425074946
Short name T133
Test name
Test status
Simulation time 74562814 ps
CPU time 0.93 seconds
Started Feb 21 02:51:34 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 203012 kb
Host smart-44769b51-42cd-4385-bb14-10b4914425b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425074946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1425074946
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.80106879
Short name T1553
Test name
Test status
Simulation time 118863194 ps
CPU time 2.31 seconds
Started Feb 21 02:51:33 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 203184 kb
Host smart-015f1077-ad4c-4150-a26a-32f1e5acc8eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80106879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.80106879
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2693307144
Short name T1537
Test name
Test status
Simulation time 62956126 ps
CPU time 1.27 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 203124 kb
Host smart-dd8dcffe-a7ac-439b-abd8-6a8f33c9cc39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693307144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2693307144
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.907538383
Short name T1595
Test name
Test status
Simulation time 59879010 ps
CPU time 0.85 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:36 PM PST 24
Peak memory 203084 kb
Host smart-121da79f-13a0-499f-aa09-39725242e7cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907538383 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.907538383
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2818661489
Short name T1531
Test name
Test status
Simulation time 36316713 ps
CPU time 0.69 seconds
Started Feb 21 02:51:32 PM PST 24
Finished Feb 21 02:51:33 PM PST 24
Peak memory 202920 kb
Host smart-090bc8c1-7b61-4c60-b363-03bfb03a9dc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818661489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2818661489
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.2843560592
Short name T1521
Test name
Test status
Simulation time 25118718 ps
CPU time 0.61 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 202916 kb
Host smart-e6338425-be99-4d7e-9d2b-a07b89f025e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843560592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2843560592
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2418609725
Short name T131
Test name
Test status
Simulation time 70344313 ps
CPU time 0.77 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 203000 kb
Host smart-d65c2bbb-5fae-4e7b-b7d9-b214994ff10f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418609725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2418609725
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.279524149
Short name T1544
Test name
Test status
Simulation time 139550158 ps
CPU time 2.03 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 202700 kb
Host smart-5760bc2c-d20d-4182-9dac-11ccb7eaf10c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279524149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.279524149
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2034809467
Short name T1603
Test name
Test status
Simulation time 193796272 ps
CPU time 1.23 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 203136 kb
Host smart-37c31914-1ca9-410c-9df8-f3e918538d24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034809467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2034809467
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2233264388
Short name T1560
Test name
Test status
Simulation time 66373725 ps
CPU time 0.9 seconds
Started Feb 21 02:51:37 PM PST 24
Finished Feb 21 02:51:39 PM PST 24
Peak memory 203100 kb
Host smart-f2ead536-08df-4463-aacb-80939a3799f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233264388 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2233264388
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1672885675
Short name T117
Test name
Test status
Simulation time 24359984 ps
CPU time 0.74 seconds
Started Feb 21 02:51:39 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 202936 kb
Host smart-750eab58-61c5-49b3-aa9c-c1a17a9e3f8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672885675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1672885675
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1142391657
Short name T1596
Test name
Test status
Simulation time 18851832 ps
CPU time 0.67 seconds
Started Feb 21 02:51:36 PM PST 24
Finished Feb 21 02:51:37 PM PST 24
Peak memory 202904 kb
Host smart-a416c024-0e8e-4cc3-8404-0e01036ec8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142391657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1142391657
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2582438789
Short name T1581
Test name
Test status
Simulation time 49503638 ps
CPU time 0.99 seconds
Started Feb 21 02:51:41 PM PST 24
Finished Feb 21 02:51:42 PM PST 24
Peak memory 203124 kb
Host smart-cdd1cc5b-421e-45ee-865b-98356c5fa284
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582438789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2582438789
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2808069213
Short name T81
Test name
Test status
Simulation time 230245130 ps
CPU time 2.35 seconds
Started Feb 21 02:51:35 PM PST 24
Finished Feb 21 02:51:38 PM PST 24
Peak memory 203308 kb
Host smart-150debd8-616c-47de-8b9f-b97ddb38c2e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808069213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2808069213
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.200876517
Short name T94
Test name
Test status
Simulation time 84304032 ps
CPU time 1.74 seconds
Started Feb 21 02:51:38 PM PST 24
Finished Feb 21 02:51:40 PM PST 24
Peak memory 203092 kb
Host smart-9b062577-7b21-440e-b146-fa8bb9780360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200876517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.200876517
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3162123347
Short name T1123
Test name
Test status
Simulation time 17442719 ps
CPU time 0.6 seconds
Started Feb 21 03:13:27 PM PST 24
Finished Feb 21 03:13:27 PM PST 24
Peak memory 202136 kb
Host smart-3f88ed3c-e9a0-4fa6-bd27-17f775da6fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162123347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3162123347
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2864595086
Short name T546
Test name
Test status
Simulation time 97510717 ps
CPU time 1.48 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:33 PM PST 24
Peak memory 211496 kb
Host smart-b47a4066-bada-4ea1-88f3-1364e5864d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864595086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2864595086
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2118327122
Short name T1337
Test name
Test status
Simulation time 468330905 ps
CPU time 10.24 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:13:44 PM PST 24
Peak memory 301524 kb
Host smart-3a46a344-e034-4380-8a54-9965476be119
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118327122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2118327122
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.397871527
Short name T1431
Test name
Test status
Simulation time 45495393743 ps
CPU time 219.17 seconds
Started Feb 21 03:13:23 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 740136 kb
Host smart-1ed5e303-c0be-4015-b201-7c1e4465cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397871527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.397871527
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1576202197
Short name T834
Test name
Test status
Simulation time 11376049808 ps
CPU time 755.96 seconds
Started Feb 21 03:13:24 PM PST 24
Finished Feb 21 03:26:01 PM PST 24
Peak memory 1623704 kb
Host smart-b843e15b-4073-4857-bf89-a4dd1ff775bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576202197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1576202197
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2367311483
Short name T550
Test name
Test status
Simulation time 85284734 ps
CPU time 0.9 seconds
Started Feb 21 03:13:24 PM PST 24
Finished Feb 21 03:13:26 PM PST 24
Peak memory 203036 kb
Host smart-a88632f2-d15b-4872-a423-798e015b69da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367311483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2367311483
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.358102338
Short name T1158
Test name
Test status
Simulation time 266505311 ps
CPU time 13.07 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:47 PM PST 24
Peak memory 203276 kb
Host smart-62b11bd2-db4c-4181-8cdd-2851e47a5d52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358102338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.358102338
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3043126702
Short name T349
Test name
Test status
Simulation time 25740533208 ps
CPU time 470.59 seconds
Started Feb 21 03:13:19 PM PST 24
Finished Feb 21 03:21:10 PM PST 24
Peak memory 1798848 kb
Host smart-a080cb09-e553-4344-a8ec-1e095d3ffa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043126702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3043126702
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2991551874
Short name T1217
Test name
Test status
Simulation time 2059285389 ps
CPU time 72.07 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:14:47 PM PST 24
Peak memory 333964 kb
Host smart-b37db415-e77c-411f-96c0-104212178d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991551874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2991551874
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.325292425
Short name T1506
Test name
Test status
Simulation time 30958965 ps
CPU time 0.64 seconds
Started Feb 21 03:13:24 PM PST 24
Finished Feb 21 03:13:25 PM PST 24
Peak memory 202240 kb
Host smart-3e628cf1-dfaa-450e-aa29-4c2a9446e78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325292425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.325292425
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.441993440
Short name T184
Test name
Test status
Simulation time 3041411351 ps
CPU time 20.6 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:52 PM PST 24
Peak memory 211572 kb
Host smart-f11ebc65-66b0-4e3a-8023-4cbeb8b3cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441993440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.441993440
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_rx_oversample.2497956408
Short name T177
Test name
Test status
Simulation time 2442889994 ps
CPU time 245.18 seconds
Started Feb 21 03:13:22 PM PST 24
Finished Feb 21 03:17:27 PM PST 24
Peak memory 310892 kb
Host smart-1834f5cb-58f7-40f2-9e0b-c9575a712e56
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497956408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_rx_oversample.
2497956408
Directory /workspace/0.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3154747927
Short name T1434
Test name
Test status
Simulation time 9979179798 ps
CPU time 63.73 seconds
Started Feb 21 03:13:24 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 307340 kb
Host smart-596b0d3a-8fae-4749-abf9-00df3fa0a1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154747927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3154747927
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1310059625
Short name T1061
Test name
Test status
Simulation time 2750096668 ps
CPU time 10.13 seconds
Started Feb 21 03:13:24 PM PST 24
Finished Feb 21 03:13:35 PM PST 24
Peak memory 211584 kb
Host smart-8b2ff663-8910-4752-b8a8-05580f2f2a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310059625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1310059625
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2186790091
Short name T84
Test name
Test status
Simulation time 292742658 ps
CPU time 0.99 seconds
Started Feb 21 03:13:41 PM PST 24
Finished Feb 21 03:13:42 PM PST 24
Peak memory 220152 kb
Host smart-bbafad41-4adb-4b97-97eb-55c3eb45f58d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186790091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2186790091
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3526776852
Short name T350
Test name
Test status
Simulation time 10046799528 ps
CPU time 56.74 seconds
Started Feb 21 03:13:45 PM PST 24
Finished Feb 21 03:14:42 PM PST 24
Peak memory 495680 kb
Host smart-22c5f8ac-2d25-49a1-9fca-a9faee91983e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526776852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3526776852
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2226619865
Short name T376
Test name
Test status
Simulation time 10051384366 ps
CPU time 68.61 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:14:43 PM PST 24
Peak memory 555228 kb
Host smart-724628c3-7c9d-4199-8cdc-3f9d179bcbfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226619865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2226619865
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.2899733741
Short name T894
Test name
Test status
Simulation time 1282690062 ps
CPU time 2.83 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:13:38 PM PST 24
Peak memory 203380 kb
Host smart-0a2b8eae-42fc-4350-b526-dbf5b01a064b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899733741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.2899733741
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.4016684783
Short name T437
Test name
Test status
Simulation time 2103841743 ps
CPU time 8.63 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:42 PM PST 24
Peak memory 206124 kb
Host smart-8fe759e4-ffbd-4102-aed0-787c5d8d0742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016684783 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.4016684783
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.208804987
Short name T290
Test name
Test status
Simulation time 13470667237 ps
CPU time 57.84 seconds
Started Feb 21 03:13:39 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 862160 kb
Host smart-ac14c887-397f-4c14-abac-55ac7191b35e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208804987 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.208804987
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.3576052855
Short name T1298
Test name
Test status
Simulation time 371191223 ps
CPU time 2.66 seconds
Started Feb 21 03:13:25 PM PST 24
Finished Feb 21 03:13:28 PM PST 24
Peak memory 203412 kb
Host smart-edeb1822-4054-4845-b71a-9f3ac71d3547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576052855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.3576052855
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2476349629
Short name T59
Test name
Test status
Simulation time 1068530785 ps
CPU time 11.26 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:42 PM PST 24
Peak memory 203356 kb
Host smart-5fe973ed-020a-426c-9277-f945dc6953a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476349629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2476349629
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_all.585897119
Short name T1503
Test name
Test status
Simulation time 20500698328 ps
CPU time 1890.06 seconds
Started Feb 21 03:13:46 PM PST 24
Finished Feb 21 03:45:17 PM PST 24
Peak memory 2163880 kb
Host smart-cab75741-22e5-433b-9e86-0c67a4500a26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585897119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.i2c_target_stress_all.585897119
Directory /workspace/0.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3100055316
Short name T771
Test name
Test status
Simulation time 478353961 ps
CPU time 17.51 seconds
Started Feb 21 03:13:28 PM PST 24
Finished Feb 21 03:13:46 PM PST 24
Peak memory 203424 kb
Host smart-dc8acdf9-bb54-4077-9f08-01638a2976a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100055316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3100055316
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2910094221
Short name T470
Test name
Test status
Simulation time 7763353968 ps
CPU time 39.01 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:14:11 PM PST 24
Peak memory 908376 kb
Host smart-a73e7aa5-c0c4-4b57-97e6-d0476eae301b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910094221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2910094221
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.962426493
Short name T832
Test name
Test status
Simulation time 8982940826 ps
CPU time 8.06 seconds
Started Feb 21 03:13:38 PM PST 24
Finished Feb 21 03:13:47 PM PST 24
Peak memory 205416 kb
Host smart-71d210d1-e759-4c0e-af38-c88c00777017
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962426493 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.962426493
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_ovf.1293617066
Short name T801
Test name
Test status
Simulation time 10478078417 ps
CPU time 154.27 seconds
Started Feb 21 03:13:39 PM PST 24
Finished Feb 21 03:16:14 PM PST 24
Peak memory 353084 kb
Host smart-3dfebc44-1e19-405e-9a87-d184a62b35c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293617066 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_tx_ovf.1293617066
Directory /workspace/0.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.3294319181
Short name T883
Test name
Test status
Simulation time 6946342606 ps
CPU time 8.28 seconds
Started Feb 21 03:13:33 PM PST 24
Finished Feb 21 03:13:43 PM PST 24
Peak memory 214760 kb
Host smart-71c84a06-cfb7-4368-a7b4-9c9d5fcd0f63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294319181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.3294319181
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1854729127
Short name T723
Test name
Test status
Simulation time 46174395 ps
CPU time 0.59 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:30 PM PST 24
Peak memory 202128 kb
Host smart-90cf5d8a-32d9-4730-bd64-25c662b5f645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854729127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1854729127
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.797946150
Short name T921
Test name
Test status
Simulation time 68135670 ps
CPU time 1.66 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:31 PM PST 24
Peak memory 211488 kb
Host smart-e486c91e-91be-46b9-b597-3a5b150bbaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797946150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.797946150
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3484181543
Short name T584
Test name
Test status
Simulation time 1008978093 ps
CPU time 26.74 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:59 PM PST 24
Peak memory 312324 kb
Host smart-ebc158b3-efd1-4c5a-a498-a903ea0121ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484181543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3484181543
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3164838369
Short name T624
Test name
Test status
Simulation time 1980096810 ps
CPU time 39.27 seconds
Started Feb 21 03:13:25 PM PST 24
Finished Feb 21 03:14:04 PM PST 24
Peak memory 219092 kb
Host smart-d8c29ef9-ee70-461b-b33e-2dc092cf45b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164838369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3164838369
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3171882955
Short name T12
Test name
Test status
Simulation time 42688985189 ps
CPU time 923.47 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:28:56 PM PST 24
Peak memory 1830568 kb
Host smart-38e8e877-8b91-4c87-a4c3-8e96f51ee4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171882955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3171882955
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2131767219
Short name T250
Test name
Test status
Simulation time 210887817 ps
CPU time 12.87 seconds
Started Feb 21 03:13:31 PM PST 24
Finished Feb 21 03:13:47 PM PST 24
Peak memory 244524 kb
Host smart-0ff41dd0-a861-49c7-adcb-08e9ce93dfb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131767219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2131767219
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2002255867
Short name T1216
Test name
Test status
Simulation time 27190501304 ps
CPU time 296.99 seconds
Started Feb 21 03:13:28 PM PST 24
Finished Feb 21 03:18:26 PM PST 24
Peak memory 1017728 kb
Host smart-e3fffe20-febd-4009-9d77-4d9c909ae798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002255867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2002255867
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_override.2745389612
Short name T1392
Test name
Test status
Simulation time 49437750 ps
CPU time 0.7 seconds
Started Feb 21 03:13:41 PM PST 24
Finished Feb 21 03:13:43 PM PST 24
Peak memory 202948 kb
Host smart-d27fb947-ddb1-4f41-89d5-2fec92d04eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745389612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2745389612
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_rx_oversample.1072656073
Short name T747
Test name
Test status
Simulation time 3774768201 ps
CPU time 127.52 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:15:43 PM PST 24
Peak memory 261416 kb
Host smart-26968c0e-40ae-445e-911b-fe9a5cee2770
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072656073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_rx_oversample.
1072656073
Directory /workspace/1.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.4128009336
Short name T1017
Test name
Test status
Simulation time 2238211767 ps
CPU time 81.37 seconds
Started Feb 21 03:13:27 PM PST 24
Finished Feb 21 03:14:48 PM PST 24
Peak memory 318352 kb
Host smart-de86118d-b9e2-4e59-b6b3-54781bc48874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128009336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.4128009336
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2319438631
Short name T984
Test name
Test status
Simulation time 2348422198 ps
CPU time 16.32 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:47 PM PST 24
Peak memory 219764 kb
Host smart-6cdc4d6e-6ce0-41d1-9280-d79f28493c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319438631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2319438631
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2480002075
Short name T102
Test name
Test status
Simulation time 89966778 ps
CPU time 0.9 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:32 PM PST 24
Peak memory 220540 kb
Host smart-744b6ad1-5231-4d63-b556-524a81d2f514
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480002075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2480002075
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.320225538
Short name T1345
Test name
Test status
Simulation time 3526788997 ps
CPU time 3.59 seconds
Started Feb 21 03:13:39 PM PST 24
Finished Feb 21 03:13:43 PM PST 24
Peak memory 203392 kb
Host smart-653f5986-d944-43be-a3b4-e761de98f944
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320225538 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.320225538
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2413423158
Short name T637
Test name
Test status
Simulation time 10103228516 ps
CPU time 65.41 seconds
Started Feb 21 03:13:28 PM PST 24
Finished Feb 21 03:14:34 PM PST 24
Peak memory 496564 kb
Host smart-10146a00-5187-4c59-a086-576058e9bf64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413423158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2413423158
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.412132607
Short name T754
Test name
Test status
Simulation time 10162936870 ps
CPU time 35.97 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:14:06 PM PST 24
Peak memory 458748 kb
Host smart-69560280-e628-483f-9b6f-a1c0abd75e84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412132607 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.412132607
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3114214653
Short name T44
Test name
Test status
Simulation time 19228156452 ps
CPU time 4.64 seconds
Started Feb 21 03:13:26 PM PST 24
Finished Feb 21 03:13:31 PM PST 24
Peak memory 203588 kb
Host smart-e2e6bbdc-61d3-4c78-9c55-eae87ab9d609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114214653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3114214653
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.270008074
Short name T1377
Test name
Test status
Simulation time 663368719 ps
CPU time 2.52 seconds
Started Feb 21 03:13:25 PM PST 24
Finished Feb 21 03:13:27 PM PST 24
Peak memory 203404 kb
Host smart-b1cb1666-b7a9-47be-8b7a-10c91e0143d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270008074 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.270008074
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.391945591
Short name T323
Test name
Test status
Simulation time 2034063227 ps
CPU time 8 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:13:43 PM PST 24
Peak memory 211824 kb
Host smart-a1dd1c0b-f695-47b7-b30b-b0b2b3e63c58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391945591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.391945591
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.1525923861
Short name T417
Test name
Test status
Simulation time 7426543198 ps
CPU time 17.78 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:49 PM PST 24
Peak memory 510684 kb
Host smart-be2c6bfa-de9b-4e40-a076-606b3742f79a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525923861 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.1525923861
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.3562749801
Short name T1236
Test name
Test status
Simulation time 1995561113 ps
CPU time 3.49 seconds
Started Feb 21 03:13:25 PM PST 24
Finished Feb 21 03:13:28 PM PST 24
Peak memory 204496 kb
Host smart-458b7483-1084-47a8-a16c-fc1c769666ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562749801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.3562749801
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1033195543
Short name T881
Test name
Test status
Simulation time 1384514187 ps
CPU time 17.76 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:13:52 PM PST 24
Peak memory 203372 kb
Host smart-4f9b8687-1903-48ce-b622-437f405382f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033195543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1033195543
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.2660049562
Short name T1473
Test name
Test status
Simulation time 16355193536 ps
CPU time 104.74 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:15:15 PM PST 24
Peak memory 224320 kb
Host smart-675b8c02-cc9d-4d88-8d2d-960bf5116eb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660049562 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.2660049562
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3519885841
Short name T528
Test name
Test status
Simulation time 919268304 ps
CPU time 39.38 seconds
Started Feb 21 03:13:28 PM PST 24
Finished Feb 21 03:14:08 PM PST 24
Peak memory 203412 kb
Host smart-ebdfced2-7384-4a38-b7a0-f5b657dc5898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519885841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3519885841
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3031392730
Short name T1206
Test name
Test status
Simulation time 27957220873 ps
CPU time 251.33 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 2690756 kb
Host smart-f4af1cec-e903-45a3-b6de-b4acda67e667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031392730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3031392730
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.317092854
Short name T1111
Test name
Test status
Simulation time 8270643151 ps
CPU time 8.4 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:13:38 PM PST 24
Peak memory 215204 kb
Host smart-e1c7400b-0a3f-4135-bcd0-be4970094b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317092854 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.317092854
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_ovf.4085369859
Short name T1172
Test name
Test status
Simulation time 9124291985 ps
CPU time 37.43 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:14:11 PM PST 24
Peak memory 222916 kb
Host smart-0f9167e4-bd31-4dec-8168-4713ff14092f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085369859 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_tx_ovf.4085369859
Directory /workspace/1.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.2878371142
Short name T789
Test name
Test status
Simulation time 1102378161 ps
CPU time 5.01 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:38 PM PST 24
Peak memory 203360 kb
Host smart-3bf7e73f-d650-41b6-afd2-620f52b26654
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878371142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.2878371142
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2286437690
Short name T395
Test name
Test status
Simulation time 137454557 ps
CPU time 1.84 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 219648 kb
Host smart-ff1d304a-d399-4467-948f-bd7f53bfbe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286437690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2286437690
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3618428932
Short name T982
Test name
Test status
Simulation time 274148569 ps
CPU time 13.55 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 253312 kb
Host smart-0e2bd4cc-6b2b-4b01-8cd9-d8765ff6830f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618428932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3618428932
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3708363245
Short name T1279
Test name
Test status
Simulation time 13975372539 ps
CPU time 136.45 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:16:39 PM PST 24
Peak memory 1041664 kb
Host smart-0fa21d28-7e14-482a-9f26-59fc747870e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708363245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3708363245
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1850327443
Short name T226
Test name
Test status
Simulation time 19863043294 ps
CPU time 263.25 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:18:46 PM PST 24
Peak memory 1396116 kb
Host smart-f54bcc94-0445-40aa-b198-f12f4cd433bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850327443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1850327443
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2649312866
Short name T910
Test name
Test status
Simulation time 278111681 ps
CPU time 0.75 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 203056 kb
Host smart-97bbf518-30eb-4059-a022-340e511c6191
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649312866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2649312866
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2346599462
Short name T449
Test name
Test status
Simulation time 730911446 ps
CPU time 5.9 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:34 PM PST 24
Peak memory 245192 kb
Host smart-b787054c-f970-4b53-9302-dbf2aa04db89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346599462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2346599462
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2031214277
Short name T947
Test name
Test status
Simulation time 5629099788 ps
CPU time 43.54 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:15:02 PM PST 24
Peak memory 258676 kb
Host smart-aa02ca73-33ec-48a0-a691-fb90dc5f76da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031214277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2031214277
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3654092969
Short name T831
Test name
Test status
Simulation time 34990126 ps
CPU time 0.67 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:14:22 PM PST 24
Peak memory 202276 kb
Host smart-aa7e8585-446f-4a06-8636-7d0d38fa86b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654092969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3654092969
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.359890914
Short name T25
Test name
Test status
Simulation time 7245247046 ps
CPU time 47.27 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:15:12 PM PST 24
Peak memory 203296 kb
Host smart-45a13195-fcc0-40c4-9458-3e8afc6a5d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359890914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.359890914
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1298319642
Short name T538
Test name
Test status
Simulation time 2907695439 ps
CPU time 41.11 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:15:03 PM PST 24
Peak memory 269908 kb
Host smart-766a73c7-66b5-456c-ba29-d1aa8a660cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298319642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1298319642
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2324298881
Short name T603
Test name
Test status
Simulation time 732302675 ps
CPU time 12.37 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:14:34 PM PST 24
Peak memory 211628 kb
Host smart-b124c96b-fce3-41b4-8a26-ad2b3ac34cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324298881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2324298881
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.24137486
Short name T309
Test name
Test status
Simulation time 644387856 ps
CPU time 2.86 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 203388 kb
Host smart-764b2c03-d6a1-49d4-b8b0-49aceff99fa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137486 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_bad_addr.24137486
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.101691501
Short name T608
Test name
Test status
Simulation time 10095632380 ps
CPU time 81.04 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 562496 kb
Host smart-b19e2597-cb9c-4fca-b122-2f753331d860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101691501 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.101691501
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2314588471
Short name T492
Test name
Test status
Simulation time 10399608081 ps
CPU time 14.1 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:40 PM PST 24
Peak memory 320276 kb
Host smart-1fe737d2-1827-4032-a6d1-8438e3f4183f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314588471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2314588471
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3783632576
Short name T1449
Test name
Test status
Simulation time 358730233 ps
CPU time 2.1 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:20 PM PST 24
Peak memory 203416 kb
Host smart-9700a740-f18e-41f0-9fab-eeaa59de7de3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783632576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3783632576
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1863046168
Short name T1495
Test name
Test status
Simulation time 13674152231 ps
CPU time 4.51 seconds
Started Feb 21 03:14:19 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 203416 kb
Host smart-67ffefdc-04ee-4a14-b7e6-2cfe617fdfc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863046168 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1863046168
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.4082078680
Short name T969
Test name
Test status
Simulation time 22770376437 ps
CPU time 150.85 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:16:55 PM PST 24
Peak memory 1448036 kb
Host smart-1f384033-2100-4b4c-90e0-487f23c88563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082078680 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.4082078680
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.3828311844
Short name T951
Test name
Test status
Simulation time 511934654 ps
CPU time 3.01 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:20 PM PST 24
Peak memory 203336 kb
Host smart-d04f81e7-e3e0-489e-85fe-f932927c19a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828311844 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.3828311844
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2029186627
Short name T271
Test name
Test status
Simulation time 7759983255 ps
CPU time 17.01 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:41 PM PST 24
Peak memory 203432 kb
Host smart-99314b3b-9a42-417e-81a1-5c845bd7265f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029186627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2029186627
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.554812803
Short name T431
Test name
Test status
Simulation time 21997666135 ps
CPU time 681.55 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:25:38 PM PST 24
Peak memory 4001872 kb
Host smart-5ca83df0-0a42-4dc1-8635-1a9283f85ba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554812803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.i2c_target_stress_all.554812803
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2009467819
Short name T792
Test name
Test status
Simulation time 1661335035 ps
CPU time 11.03 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:36 PM PST 24
Peak memory 203388 kb
Host smart-6b0a7ba9-968b-41be-9c4d-eefba24e8f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009467819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2009467819
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1803269322
Short name T453
Test name
Test status
Simulation time 22439780807 ps
CPU time 73.13 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:15:38 PM PST 24
Peak memory 1280028 kb
Host smart-6ed8869d-808c-40fe-95e5-a0d905c1fdc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803269322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1803269322
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.855052636
Short name T255
Test name
Test status
Simulation time 17563944283 ps
CPU time 285.7 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:19:12 PM PST 24
Peak memory 1090416 kb
Host smart-2356c5dc-a448-4d39-ad09-49e24321d6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855052636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.855052636
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3119385674
Short name T862
Test name
Test status
Simulation time 1826384890 ps
CPU time 7.25 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 211172 kb
Host smart-e0cef0df-2dff-41e1-b8de-628c7551a3e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119385674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3119385674
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_ovf.1383432477
Short name T1335
Test name
Test status
Simulation time 5941030322 ps
CPU time 106.23 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:16:11 PM PST 24
Peak memory 328356 kb
Host smart-28db6ca6-6aa8-478d-bbbc-5c1421f1694a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383432477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_tx_ovf.1383432477
Directory /workspace/10.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.664759063
Short name T1293
Test name
Test status
Simulation time 2633712662 ps
CPU time 6.44 seconds
Started Feb 21 03:14:14 PM PST 24
Finished Feb 21 03:14:21 PM PST 24
Peak memory 203484 kb
Host smart-22461e0c-83ae-4c87-8dc0-86a85cd5aa23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664759063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_unexp_stop.664759063
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3376123519
Short name T1438
Test name
Test status
Simulation time 48028438 ps
CPU time 0.63 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 202964 kb
Host smart-e08d3c7d-56b5-419a-9a8d-6ba68db91aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376123519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3376123519
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.996598837
Short name T267
Test name
Test status
Simulation time 55225605 ps
CPU time 1.43 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 213592 kb
Host smart-a4b07e20-3f56-4ba3-bd7b-afa87441b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996598837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.996598837
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.4045171406
Short name T306
Test name
Test status
Simulation time 1243423766 ps
CPU time 11.29 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 311532 kb
Host smart-07b88aa9-23ad-4f11-86a3-e764a791a8ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045171406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.4045171406
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1002683695
Short name T383
Test name
Test status
Simulation time 8169106879 ps
CPU time 246.63 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:18:34 PM PST 24
Peak memory 936028 kb
Host smart-4a8862de-64cc-4710-93fe-9eae585d1b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002683695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1002683695
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2596326692
Short name T1164
Test name
Test status
Simulation time 17879222787 ps
CPU time 276.73 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:18:59 PM PST 24
Peak memory 1276648 kb
Host smart-9afbb268-26ef-4121-839b-3ae46a988599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596326692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2596326692
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.783696717
Short name T1001
Test name
Test status
Simulation time 535822730 ps
CPU time 1.09 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 203224 kb
Host smart-771876be-1d86-4aad-82bc-fe4ab0688d14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783696717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.783696717
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2944563843
Short name T633
Test name
Test status
Simulation time 651471980 ps
CPU time 4.53 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 232480 kb
Host smart-b26265dc-369a-41f4-a4a3-3f0b11711fda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944563843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2944563843
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3111935544
Short name T865
Test name
Test status
Simulation time 6879279581 ps
CPU time 40.88 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:15:08 PM PST 24
Peak memory 276576 kb
Host smart-207650cc-638d-4f60-9c7b-5226846eab61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111935544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3111935544
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.546902307
Short name T4
Test name
Test status
Simulation time 19473671 ps
CPU time 0.62 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:14:23 PM PST 24
Peak memory 202244 kb
Host smart-91665373-87f9-4e9d-95da-583c0459b445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546902307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.546902307
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3058264591
Short name T1261
Test name
Test status
Simulation time 260058348 ps
CPU time 3.45 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 220740 kb
Host smart-3f902b11-a829-4119-b3d2-90444166d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058264591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3058264591
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_rx_oversample.2377987331
Short name T1194
Test name
Test status
Simulation time 8462885368 ps
CPU time 75.2 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:15:35 PM PST 24
Peak memory 292976 kb
Host smart-c7b9863e-fad8-4a2d-b582-e1adccd4848e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377987331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_rx_oversample
.2377987331
Directory /workspace/11.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.696270990
Short name T1338
Test name
Test status
Simulation time 3447122688 ps
CPU time 39.44 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:58 PM PST 24
Peak memory 260868 kb
Host smart-b0df3c4b-f4d2-4ade-8530-8e7e859556ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696270990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.696270990
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3383923381
Short name T38
Test name
Test status
Simulation time 13273639465 ps
CPU time 1161.85 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:33:46 PM PST 24
Peak memory 2852908 kb
Host smart-c0cbcf48-0334-46c9-a9c9-1406c6552bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383923381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3383923381
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3100162483
Short name T73
Test name
Test status
Simulation time 4046307078 ps
CPU time 15.59 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:40 PM PST 24
Peak memory 211548 kb
Host smart-6f5c9bbc-d45c-4861-af25-f8dfda1dd70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100162483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3100162483
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3180190092
Short name T882
Test name
Test status
Simulation time 1302739349 ps
CPU time 4.13 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 203376 kb
Host smart-b321ef18-ebdf-46da-9bbb-03959ceb30a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180190092 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3180190092
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2811997726
Short name T1083
Test name
Test status
Simulation time 10259180522 ps
CPU time 14.05 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:41 PM PST 24
Peak memory 294328 kb
Host smart-cabf3665-ab26-4092-b3c9-e1ac238df0df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811997726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2811997726
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2248572959
Short name T472
Test name
Test status
Simulation time 3430776652 ps
CPU time 3.14 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203484 kb
Host smart-c65ebf9b-c4f6-47e7-8491-14722cd9d7d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248572959 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2248572959
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3700091627
Short name T695
Test name
Test status
Simulation time 2804975967 ps
CPU time 6.06 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:31 PM PST 24
Peak memory 303532 kb
Host smart-e97dc0b3-4bd1-42e7-a5d9-bcd460e2dfc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700091627 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3700091627
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.1158490584
Short name T1156
Test name
Test status
Simulation time 2213383247 ps
CPU time 3.38 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 203264 kb
Host smart-65e67d52-0a17-4f18-91b4-862f9e0298c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158490584 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_perf.1158490584
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3189099292
Short name T428
Test name
Test status
Simulation time 6465840314 ps
CPU time 10.24 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:34 PM PST 24
Peak memory 203384 kb
Host smart-4d20bd6a-c32f-438c-84b6-d12496ffee0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189099292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3189099292
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.3100403342
Short name T445
Test name
Test status
Simulation time 42974651738 ps
CPU time 99.68 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:16:06 PM PST 24
Peak memory 311960 kb
Host smart-68f480d7-b8a9-41e9-9d5e-bdd42fce04e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100403342 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.3100403342
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1867854679
Short name T60
Test name
Test status
Simulation time 755606101 ps
CPU time 13.47 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:39 PM PST 24
Peak memory 203844 kb
Host smart-0588f24c-c62a-4b55-8f54-28183d5ee373
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867854679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1867854679
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1586379760
Short name T1062
Test name
Test status
Simulation time 46203024114 ps
CPU time 923.61 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:29:49 PM PST 24
Peak memory 5388908 kb
Host smart-9902b06a-0f09-4ad4-9838-caaea845c7ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586379760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1586379760
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.786051321
Short name T562
Test name
Test status
Simulation time 6404356508 ps
CPU time 7.01 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 203668 kb
Host smart-54be7562-524d-4ecd-a9f7-a16686d6ef13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786051321 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.786051321
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_ovf.3943263974
Short name T997
Test name
Test status
Simulation time 10588587846 ps
CPU time 30.24 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:54 PM PST 24
Peak memory 211508 kb
Host smart-20534bb0-307d-4732-b94d-7bf1bc6e4f2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943263974 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_tx_ovf.3943263974
Directory /workspace/11.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.1943075676
Short name T34
Test name
Test status
Simulation time 937071943 ps
CPU time 6.2 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:33 PM PST 24
Peak memory 203376 kb
Host smart-fdb4d1a3-978a-4a02-bd96-9ca266243228
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943075676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.i2c_target_unexp_stop.1943075676
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2787553051
Short name T507
Test name
Test status
Simulation time 59421297 ps
CPU time 0.61 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 202092 kb
Host smart-ddc37d63-1c65-4a80-a61c-31fecf250539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787553051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2787553051
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.729742371
Short name T537
Test name
Test status
Simulation time 69466486 ps
CPU time 1.61 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 211500 kb
Host smart-c79ba228-f663-4e16-8bf9-5a127ea04ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729742371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.729742371
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2622026361
Short name T602
Test name
Test status
Simulation time 2262272093 ps
CPU time 12.31 seconds
Started Feb 21 03:14:29 PM PST 24
Finished Feb 21 03:14:42 PM PST 24
Peak memory 323776 kb
Host smart-74bd272e-cb3e-4d41-97a8-b81686b0be1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622026361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2622026361
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2784244708
Short name T451
Test name
Test status
Simulation time 11169330016 ps
CPU time 102.19 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:16:05 PM PST 24
Peak memory 784340 kb
Host smart-1dbb62a8-ac39-4c24-b3a8-4ca1c80b2c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784244708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2784244708
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3640017890
Short name T610
Test name
Test status
Simulation time 23332576993 ps
CPU time 821.12 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:28:03 PM PST 24
Peak memory 1687516 kb
Host smart-5f446a53-75b2-4be4-98cc-9dfbe8f83b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640017890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3640017890
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.449314971
Short name T1260
Test name
Test status
Simulation time 90347177 ps
CPU time 0.9 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 203076 kb
Host smart-39aa6a1c-66d1-47b5-82b9-6cba2025d24d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449314971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.449314971
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1107625478
Short name T464
Test name
Test status
Simulation time 387888374 ps
CPU time 9.88 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:42 PM PST 24
Peak memory 202400 kb
Host smart-5c0b28bb-27bc-47d1-ae1e-8b3e547f4328
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107625478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1107625478
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1391863679
Short name T937
Test name
Test status
Simulation time 12716852077 ps
CPU time 335.92 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:20:02 PM PST 24
Peak memory 1046172 kb
Host smart-4e1c572d-caee-4975-8f43-9f9f56b89b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391863679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1391863679
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3387023080
Short name T909
Test name
Test status
Simulation time 2945544966 ps
CPU time 189.3 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:17:41 PM PST 24
Peak memory 282968 kb
Host smart-9d8bcef2-f02d-4921-952b-937775b1711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387023080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3387023080
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_perf.814742514
Short name T1068
Test name
Test status
Simulation time 7332721050 ps
CPU time 106.56 seconds
Started Feb 21 03:14:30 PM PST 24
Finished Feb 21 03:16:17 PM PST 24
Peak memory 213584 kb
Host smart-6dcf9881-ace7-4291-be48-b8ab93f63d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814742514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.814742514
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_rx_oversample.1149600516
Short name T741
Test name
Test status
Simulation time 1526295872 ps
CPU time 47.84 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:15:06 PM PST 24
Peak memory 276624 kb
Host smart-8400b55f-6e63-4299-8b06-4f8ec486b68f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149600516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_rx_oversample
.1149600516
Directory /workspace/12.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1485533957
Short name T876
Test name
Test status
Simulation time 4872106215 ps
CPU time 131.72 seconds
Started Feb 21 03:14:29 PM PST 24
Finished Feb 21 03:16:41 PM PST 24
Peak memory 261308 kb
Host smart-31942290-88ce-4859-a3c9-e002924b4003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485533957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1485533957
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.699474924
Short name T378
Test name
Test status
Simulation time 15690119199 ps
CPU time 15.61 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:40 PM PST 24
Peak memory 218068 kb
Host smart-6595172e-56dc-4d0d-ac15-88ac2e45ed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699474924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.699474924
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2271084756
Short name T806
Test name
Test status
Simulation time 1610874438 ps
CPU time 3.59 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:14:36 PM PST 24
Peak memory 203280 kb
Host smart-6bfed6fe-8cbf-4aa7-8524-bb050bbdc4fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271084756 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2271084756
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3497788970
Short name T700
Test name
Test status
Simulation time 10657611984 ps
CPU time 10.85 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:39 PM PST 24
Peak memory 264744 kb
Host smart-58bb1c0a-9cc0-434d-86ef-d886dab851d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497788970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3497788970
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2432087627
Short name T471
Test name
Test status
Simulation time 10078194991 ps
CPU time 32.74 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:56 PM PST 24
Peak memory 450904 kb
Host smart-63fe1a68-0bbc-43b7-870a-83f9dfab4a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432087627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2432087627
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.39613428
Short name T51
Test name
Test status
Simulation time 1039951403 ps
CPU time 2.43 seconds
Started Feb 21 03:14:30 PM PST 24
Finished Feb 21 03:14:33 PM PST 24
Peak memory 203400 kb
Host smart-84ef59b3-198b-4c14-b9b4-1f159eceb6d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613428 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.i2c_target_hrst.39613428
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3162317163
Short name T1110
Test name
Test status
Simulation time 2296844995 ps
CPU time 5.39 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203424 kb
Host smart-b0f43887-eeb1-4738-bfc6-c7011c0ec050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162317163 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3162317163
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.616471295
Short name T577
Test name
Test status
Simulation time 19083170725 ps
CPU time 127.64 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:16:29 PM PST 24
Peak memory 1190496 kb
Host smart-67a42d75-2fb1-4bfb-9369-ffdbe3d8c670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616471295 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.616471295
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.3563271929
Short name T1271
Test name
Test status
Simulation time 3194853780 ps
CPU time 3.83 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 203296 kb
Host smart-b6b24158-5eee-4018-934e-0f70cc320a5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563271929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.3563271929
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2422161100
Short name T1141
Test name
Test status
Simulation time 6551780701 ps
CPU time 32.4 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:15:05 PM PST 24
Peak memory 203416 kb
Host smart-4311f397-e904-421f-a22b-7304ed6194dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422161100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2422161100
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1355513928
Short name T658
Test name
Test status
Simulation time 271654383 ps
CPU time 4.21 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:33 PM PST 24
Peak memory 203360 kb
Host smart-e76310ec-434b-4015-b8bb-32d54675ffad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355513928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1355513928
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1463355492
Short name T1065
Test name
Test status
Simulation time 10169641510 ps
CPU time 14.13 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:46 PM PST 24
Peak memory 490204 kb
Host smart-a3b0c252-bece-4eed-b9fb-0cd1df00e583
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463355492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1463355492
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2972800914
Short name T981
Test name
Test status
Simulation time 7235280798 ps
CPU time 7.72 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:39 PM PST 24
Peak memory 207384 kb
Host smart-5693e165-5555-44ad-8b87-1d5c968ce9c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972800914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2972800914
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_ovf.3704200402
Short name T1492
Test name
Test status
Simulation time 2712708569 ps
CPU time 92.53 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:16:04 PM PST 24
Peak memory 317216 kb
Host smart-71901c6c-ab92-463e-8970-46af17f1639a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704200402 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_tx_ovf.3704200402
Directory /workspace/12.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.3819033878
Short name T491
Test name
Test status
Simulation time 2017670716 ps
CPU time 5.23 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:14:27 PM PST 24
Peak memory 203504 kb
Host smart-a6f4842f-f8b7-467e-ad77-ea00fc324e5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819033878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.3819033878
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.1585856039
Short name T1027
Test name
Test status
Simulation time 26714423 ps
CPU time 0.59 seconds
Started Feb 21 03:14:30 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 202112 kb
Host smart-1556fd3c-a8e1-4c27-bc0d-fece65648610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585856039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1585856039
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3739826320
Short name T1323
Test name
Test status
Simulation time 125899743 ps
CPU time 1.07 seconds
Started Feb 21 03:14:30 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 211532 kb
Host smart-e737772f-515c-4361-9c86-e0ea07a1ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739826320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3739826320
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1287907189
Short name T835
Test name
Test status
Simulation time 249777341 ps
CPU time 5.21 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 252620 kb
Host smart-accc2a9a-69f2-4981-aa3a-67c1527b5f2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287907189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1287907189
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1095134120
Short name T1184
Test name
Test status
Simulation time 20536478433 ps
CPU time 107.76 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:16:20 PM PST 24
Peak memory 826980 kb
Host smart-c3c7e9ef-7f65-457c-8104-37c04ad7fb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095134120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1095134120
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.456557609
Short name T913
Test name
Test status
Simulation time 9690276231 ps
CPU time 170.94 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:17:23 PM PST 24
Peak memory 1011104 kb
Host smart-a6e263b5-e761-469a-ac36-f4657cc43cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456557609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.456557609
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1875564574
Short name T240
Test name
Test status
Simulation time 547615276 ps
CPU time 1.02 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 203048 kb
Host smart-12059feb-386c-4051-a2da-781810b4e2cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875564574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1875564574
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.449108113
Short name T223
Test name
Test status
Simulation time 6821764322 ps
CPU time 386.53 seconds
Started Feb 21 03:14:30 PM PST 24
Finished Feb 21 03:20:57 PM PST 24
Peak memory 1851892 kb
Host smart-8a6ff381-acbf-4855-bdc2-b1297f43abe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449108113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.449108113
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2102296619
Short name T1330
Test name
Test status
Simulation time 5977044886 ps
CPU time 97.77 seconds
Started Feb 21 03:14:33 PM PST 24
Finished Feb 21 03:16:11 PM PST 24
Peak memory 240756 kb
Host smart-2137771a-b774-47a4-a72a-5cf5100dc69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102296619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2102296619
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2289644691
Short name T1456
Test name
Test status
Simulation time 5338226666 ps
CPU time 226.97 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:18:16 PM PST 24
Peak memory 219756 kb
Host smart-0fdc8ffa-8bb6-448c-9a55-6a19ee177c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289644691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2289644691
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_rx_oversample.3978052835
Short name T225
Test name
Test status
Simulation time 6288156012 ps
CPU time 49.7 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:15:22 PM PST 24
Peak memory 269544 kb
Host smart-85112c38-6b05-4fcc-b16a-62c07988499d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978052835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_rx_oversample
.3978052835
Directory /workspace/13.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1413449380
Short name T1500
Test name
Test status
Simulation time 16763457430 ps
CPU time 107.88 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:16:19 PM PST 24
Peak memory 246224 kb
Host smart-5188e161-c83e-454f-974f-6bc8f4ee2b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413449380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1413449380
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1525929078
Short name T1383
Test name
Test status
Simulation time 1237701156 ps
CPU time 28.48 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:15:01 PM PST 24
Peak memory 211392 kb
Host smart-7826b669-12e6-4820-9a9f-cf30816ae994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525929078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1525929078
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.720015463
Short name T508
Test name
Test status
Simulation time 930292267 ps
CPU time 3.91 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 203384 kb
Host smart-fc547991-aa96-4539-a065-c37f5f6f73fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720015463 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.720015463
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.4279751712
Short name T389
Test name
Test status
Simulation time 10129809398 ps
CPU time 77.51 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 618236 kb
Host smart-5fc0713d-6ee3-4aee-b3e2-542280d76d48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279751712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.4279751712
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1306805165
Short name T778
Test name
Test status
Simulation time 10083820266 ps
CPU time 59.41 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:15:28 PM PST 24
Peak memory 551972 kb
Host smart-52d9ce9a-f2b5-4761-9d3a-51c0b65bf787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306805165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1306805165
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.700071169
Short name T52
Test name
Test status
Simulation time 3617643455 ps
CPU time 2.48 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 203488 kb
Host smart-14987a28-c8ea-4d8b-9955-b00d3afaef6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700071169 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_hrst.700071169
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3502471440
Short name T618
Test name
Test status
Simulation time 3455548720 ps
CPU time 4.46 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:36 PM PST 24
Peak memory 209508 kb
Host smart-88f0fa55-7260-4808-956c-46d84815812f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502471440 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3502471440
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.417102236
Short name T1150
Test name
Test status
Simulation time 9649828703 ps
CPU time 47.54 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:15:20 PM PST 24
Peak memory 1011220 kb
Host smart-3f7cfd0c-fdec-4d81-9af3-d09c51636c88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417102236 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.417102236
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.4132240553
Short name T1240
Test name
Test status
Simulation time 569708538 ps
CPU time 3.58 seconds
Started Feb 21 03:14:34 PM PST 24
Finished Feb 21 03:14:38 PM PST 24
Peak memory 203416 kb
Host smart-a6ca8f12-e9a4-4b48-816d-b1cab68e0068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132240553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_perf.4132240553
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.904609789
Short name T416
Test name
Test status
Simulation time 3276298705 ps
CPU time 18.65 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:50 PM PST 24
Peak memory 203488 kb
Host smart-b9ea3d07-a36e-4995-be5c-ff1dae5dd099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904609789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.904609789
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3682077534
Short name T1332
Test name
Test status
Simulation time 2083381010 ps
CPU time 81.85 seconds
Started Feb 21 03:14:30 PM PST 24
Finished Feb 21 03:15:52 PM PST 24
Peak memory 203372 kb
Host smart-70ac8d35-d5ed-421f-ab8b-3adaced878f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682077534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3682077534
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2124000301
Short name T1189
Test name
Test status
Simulation time 58054239543 ps
CPU time 521.75 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:23:13 PM PST 24
Peak memory 3384544 kb
Host smart-6b40db5b-55d8-4f41-94aa-a8382026bb97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124000301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2124000301
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.664615105
Short name T765
Test name
Test status
Simulation time 4629704804 ps
CPU time 100.38 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:16:12 PM PST 24
Peak memory 600812 kb
Host smart-d255840d-3296-4f64-bbed-9ee8c9e78789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664615105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.664615105
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.549151284
Short name T1257
Test name
Test status
Simulation time 7498990110 ps
CPU time 7.36 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 203384 kb
Host smart-4b7950c6-c9e1-4f73-bdde-ef885b30541c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549151284 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.549151284
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_ovf.1144112092
Short name T530
Test name
Test status
Simulation time 2318526416 ps
CPU time 74.96 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:15:47 PM PST 24
Peak memory 317232 kb
Host smart-7c54e89b-a690-457f-acc2-8d2b0a2cbc92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144112092 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_tx_ovf.1144112092
Directory /workspace/13.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.373875758
Short name T401
Test name
Test status
Simulation time 5154123219 ps
CPU time 6.69 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:31 PM PST 24
Peak memory 203468 kb
Host smart-351dae63-0c03-4077-b263-58761998da2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373875758 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_unexp_stop.373875758
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3995561189
Short name T390
Test name
Test status
Simulation time 15434535 ps
CPU time 0.62 seconds
Started Feb 21 03:14:42 PM PST 24
Finished Feb 21 03:14:43 PM PST 24
Peak memory 202976 kb
Host smart-472c5877-1d60-49a4-af3c-a53482df2270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995561189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3995561189
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2574620149
Short name T1234
Test name
Test status
Simulation time 42231154 ps
CPU time 1.11 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 211508 kb
Host smart-45a24b09-e5a1-48b7-84ca-a52c6c47f566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574620149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2574620149
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1494275837
Short name T1186
Test name
Test status
Simulation time 388812510 ps
CPU time 7.1 seconds
Started Feb 21 03:14:33 PM PST 24
Finished Feb 21 03:14:40 PM PST 24
Peak memory 288744 kb
Host smart-7cf4e666-42ed-41bc-860b-80a6c6b5033c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494275837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1494275837
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1247411953
Short name T759
Test name
Test status
Simulation time 3348591090 ps
CPU time 151.91 seconds
Started Feb 21 03:14:40 PM PST 24
Finished Feb 21 03:17:13 PM PST 24
Peak memory 1013324 kb
Host smart-9851993a-5a45-4a77-8878-d925f2b3e3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247411953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1247411953
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.4072995747
Short name T821
Test name
Test status
Simulation time 5141538498 ps
CPU time 263.46 seconds
Started Feb 21 03:14:34 PM PST 24
Finished Feb 21 03:18:57 PM PST 24
Peak memory 1282380 kb
Host smart-88ca9d58-78ec-4893-a77f-57d15f1d101b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072995747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.4072995747
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2867282600
Short name T1346
Test name
Test status
Simulation time 128517298 ps
CPU time 1.11 seconds
Started Feb 21 03:14:40 PM PST 24
Finished Feb 21 03:14:42 PM PST 24
Peak memory 203280 kb
Host smart-010eea87-c24e-406a-aaed-f4add736561d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867282600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2867282600
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.4217345407
Short name T1273
Test name
Test status
Simulation time 969871967 ps
CPU time 13.93 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:46 PM PST 24
Peak memory 251860 kb
Host smart-f937e563-e563-4531-9bbf-e5f12744c49e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217345407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.4217345407
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3629394922
Short name T535
Test name
Test status
Simulation time 21594810387 ps
CPU time 636.5 seconds
Started Feb 21 03:14:40 PM PST 24
Finished Feb 21 03:25:17 PM PST 24
Peak memory 1526220 kb
Host smart-04f8838c-4243-42df-b65a-e129d8e74c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629394922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3629394922
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.544142891
Short name T1426
Test name
Test status
Simulation time 8227363290 ps
CPU time 61.49 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:15:34 PM PST 24
Peak memory 324008 kb
Host smart-60c22060-d382-4a3a-b7f2-a57de57f6504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544142891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.544142891
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1850845199
Short name T168
Test name
Test status
Simulation time 92726798 ps
CPU time 0.68 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 202216 kb
Host smart-1aaf193e-20fe-4749-ab8e-e8537eb575d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850845199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1850845199
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3416884618
Short name T892
Test name
Test status
Simulation time 12648195480 ps
CPU time 192.26 seconds
Started Feb 21 03:14:42 PM PST 24
Finished Feb 21 03:17:55 PM PST 24
Peak memory 297200 kb
Host smart-9e856574-7537-4d41-98db-96ad7312bf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416884618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3416884618
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_rx_oversample.646535378
Short name T790
Test name
Test status
Simulation time 3075342670 ps
CPU time 46.03 seconds
Started Feb 21 03:14:43 PM PST 24
Finished Feb 21 03:15:29 PM PST 24
Peak memory 244128 kb
Host smart-424858f3-20ea-4dad-b80d-160abbdd6737
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646535378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_rx_oversample.
646535378
Directory /workspace/14.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3700047984
Short name T588
Test name
Test status
Simulation time 11518500987 ps
CPU time 49.56 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:15:16 PM PST 24
Peak memory 264224 kb
Host smart-9321bf63-f491-4883-b825-21043abc0e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700047984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3700047984
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3345096974
Short name T37
Test name
Test status
Simulation time 154690406655 ps
CPU time 1447.4 seconds
Started Feb 21 03:14:42 PM PST 24
Finished Feb 21 03:38:50 PM PST 24
Peak memory 1770668 kb
Host smart-68511d1c-1097-4212-bccc-6576ca3c9742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345096974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3345096974
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2321354142
Short name T2
Test name
Test status
Simulation time 1939921962 ps
CPU time 42.05 seconds
Started Feb 21 03:14:42 PM PST 24
Finished Feb 21 03:15:25 PM PST 24
Peak memory 211580 kb
Host smart-a30e76a3-63d8-407d-9e4f-2116210fbc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321354142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2321354142
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2910458613
Short name T595
Test name
Test status
Simulation time 841436380 ps
CPU time 3.34 seconds
Started Feb 21 03:14:42 PM PST 24
Finished Feb 21 03:14:45 PM PST 24
Peak memory 203324 kb
Host smart-b5848c71-6dc7-4dc0-962e-aa27a1370905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910458613 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2910458613
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.84963484
Short name T914
Test name
Test status
Simulation time 10061857970 ps
CPU time 23.77 seconds
Started Feb 21 03:14:32 PM PST 24
Finished Feb 21 03:14:57 PM PST 24
Peak memory 332508 kb
Host smart-05f72cd7-6f9b-464a-9ad4-47f53ae2f16c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84963484 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_acq.84963484
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1592770266
Short name T697
Test name
Test status
Simulation time 10481814961 ps
CPU time 14.16 seconds
Started Feb 21 03:14:34 PM PST 24
Finished Feb 21 03:14:48 PM PST 24
Peak memory 314316 kb
Host smart-481c63ef-3e0f-44d8-a737-513d9763622c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592770266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1592770266
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1737473458
Short name T643
Test name
Test status
Simulation time 560953859 ps
CPU time 2.1 seconds
Started Feb 21 03:14:43 PM PST 24
Finished Feb 21 03:14:45 PM PST 24
Peak memory 203388 kb
Host smart-ab550b19-1e25-4919-9968-592eec818361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737473458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1737473458
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2881642322
Short name T796
Test name
Test status
Simulation time 1044972062 ps
CPU time 5.04 seconds
Started Feb 21 03:14:33 PM PST 24
Finished Feb 21 03:14:39 PM PST 24
Peak memory 208452 kb
Host smart-57184fc8-782b-4f56-a545-71cae59ace05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881642322 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2881642322
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.712944618
Short name T596
Test name
Test status
Simulation time 25905952059 ps
CPU time 255.98 seconds
Started Feb 21 03:14:39 PM PST 24
Finished Feb 21 03:18:56 PM PST 24
Peak memory 1674180 kb
Host smart-1028c507-d8f4-4c69-98c3-b1e78e791587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712944618 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.712944618
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.178634617
Short name T905
Test name
Test status
Simulation time 11124740357 ps
CPU time 4.03 seconds
Started Feb 21 03:14:42 PM PST 24
Finished Feb 21 03:14:46 PM PST 24
Peak memory 208712 kb
Host smart-d69ba328-8a2a-4c53-a5d5-04ecdf5cfd35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178634617 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_perf.178634617
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3147526495
Short name T879
Test name
Test status
Simulation time 13454232008 ps
CPU time 29.45 seconds
Started Feb 21 03:14:33 PM PST 24
Finished Feb 21 03:15:03 PM PST 24
Peak memory 203424 kb
Host smart-73affa9b-fa67-42b3-a7a3-bf937603f9ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147526495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3147526495
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.2896065385
Short name T600
Test name
Test status
Simulation time 42574688189 ps
CPU time 507.6 seconds
Started Feb 21 03:14:33 PM PST 24
Finished Feb 21 03:23:01 PM PST 24
Peak memory 2259776 kb
Host smart-4074278e-d024-4ac5-aa05-d257b8ea57e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896065385 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.2896065385
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.966600372
Short name T707
Test name
Test status
Simulation time 3625160814 ps
CPU time 14.8 seconds
Started Feb 21 03:14:36 PM PST 24
Finished Feb 21 03:14:52 PM PST 24
Peak memory 212188 kb
Host smart-c3579f71-6db9-48ff-8d2e-21d9e563c998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966600372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.966600372
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.884574824
Short name T298
Test name
Test status
Simulation time 57046759728 ps
CPU time 466.55 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:22:18 PM PST 24
Peak memory 3331560 kb
Host smart-f50e0361-ea2c-4524-ae93-0abde07abeb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884574824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.884574824
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1063744994
Short name T794
Test name
Test status
Simulation time 2903196001 ps
CPU time 6.42 seconds
Started Feb 21 03:14:38 PM PST 24
Finished Feb 21 03:14:45 PM PST 24
Peak memory 203432 kb
Host smart-f38f7080-a788-4c82-beb9-dfe2a508b3f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063744994 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1063744994
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_ovf.551867855
Short name T644
Test name
Test status
Simulation time 53969199969 ps
CPU time 146.71 seconds
Started Feb 21 03:14:36 PM PST 24
Finished Feb 21 03:17:04 PM PST 24
Peak memory 354864 kb
Host smart-eeb29bfb-41e7-4f3b-9b77-06169554647a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551867855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_tx_ovf.551867855
Directory /workspace/14.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.3925983
Short name T148
Test name
Test status
Simulation time 4496945183 ps
CPU time 5.64 seconds
Started Feb 21 03:14:31 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 203468 kb
Host smart-e5c40fbf-69f5-41af-b451-463e389ccb7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925983 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_unexp_stop.3925983
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3357347615
Short name T580
Test name
Test status
Simulation time 18003950 ps
CPU time 0.63 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:15:25 PM PST 24
Peak memory 201924 kb
Host smart-b8ae05f1-6fc0-413e-b474-6c70ad656813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357347615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3357347615
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1471779054
Short name T283
Test name
Test status
Simulation time 70445858 ps
CPU time 1.36 seconds
Started Feb 21 03:15:18 PM PST 24
Finished Feb 21 03:15:20 PM PST 24
Peak memory 219676 kb
Host smart-3823bccb-bb5c-4b03-b5cb-b18e4441d56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471779054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1471779054
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2289743161
Short name T944
Test name
Test status
Simulation time 491782041 ps
CPU time 11.09 seconds
Started Feb 21 03:15:04 PM PST 24
Finished Feb 21 03:15:16 PM PST 24
Peak memory 309784 kb
Host smart-c96ff297-f681-482e-b001-4a026d390163
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289743161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2289743161
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1555311006
Short name T967
Test name
Test status
Simulation time 7021261346 ps
CPU time 143.25 seconds
Started Feb 21 03:15:18 PM PST 24
Finished Feb 21 03:17:41 PM PST 24
Peak memory 975468 kb
Host smart-39f6f76e-67ed-4399-a823-0222b4de3cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555311006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1555311006
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1230839035
Short name T920
Test name
Test status
Simulation time 31491850351 ps
CPU time 440.17 seconds
Started Feb 21 03:15:18 PM PST 24
Finished Feb 21 03:22:39 PM PST 24
Peak memory 1175088 kb
Host smart-7c231ef2-5418-4b44-b69a-aa1c8f5e06b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230839035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1230839035
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1505393999
Short name T998
Test name
Test status
Simulation time 462256669 ps
CPU time 1.08 seconds
Started Feb 21 03:15:18 PM PST 24
Finished Feb 21 03:15:19 PM PST 24
Peak memory 203236 kb
Host smart-d4eb6ea2-9123-420b-a9f8-59e7e8c06e74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505393999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1505393999
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3700527861
Short name T1091
Test name
Test status
Simulation time 271293688 ps
CPU time 5.81 seconds
Started Feb 21 03:15:15 PM PST 24
Finished Feb 21 03:15:21 PM PST 24
Peak memory 203256 kb
Host smart-6c0615cd-3c7f-4ee0-8768-3c3d59901dec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700527861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3700527861
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.4015528104
Short name T1266
Test name
Test status
Simulation time 4385064551 ps
CPU time 147.31 seconds
Started Feb 21 03:15:31 PM PST 24
Finished Feb 21 03:17:59 PM PST 24
Peak memory 281296 kb
Host smart-73d824a6-4acf-4f2b-8eae-14788ee156e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015528104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.4015528104
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.2780371945
Short name T781
Test name
Test status
Simulation time 20800148 ps
CPU time 0.67 seconds
Started Feb 21 03:14:43 PM PST 24
Finished Feb 21 03:14:44 PM PST 24
Peak memory 202320 kb
Host smart-9a020f85-eeed-43cf-bdbe-87791f90bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780371945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2780371945
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1547583151
Short name T181
Test name
Test status
Simulation time 3573368046 ps
CPU time 40.39 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:16:02 PM PST 24
Peak memory 223320 kb
Host smart-076bf7c5-4948-4009-b4d8-70475dbdb5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547583151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1547583151
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_rx_oversample.214112375
Short name T1455
Test name
Test status
Simulation time 28844620909 ps
CPU time 133.46 seconds
Started Feb 21 03:14:50 PM PST 24
Finished Feb 21 03:17:04 PM PST 24
Peak memory 277872 kb
Host smart-460d594a-a0af-4ff7-8c9f-462a7fd25b57
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214112375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_rx_oversample.
214112375
Directory /workspace/15.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3463585512
Short name T676
Test name
Test status
Simulation time 19127302785 ps
CPU time 133.1 seconds
Started Feb 21 03:14:41 PM PST 24
Finished Feb 21 03:16:55 PM PST 24
Peak memory 244116 kb
Host smart-95a30b88-d89b-477e-adbf-079534b05948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463585512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3463585512
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.4088253923
Short name T1202
Test name
Test status
Simulation time 4001197651 ps
CPU time 16.54 seconds
Started Feb 21 03:15:25 PM PST 24
Finished Feb 21 03:15:42 PM PST 24
Peak memory 227876 kb
Host smart-54debabf-7ee1-405c-a2c5-1d15c5003321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088253923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.4088253923
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1278032744
Short name T1176
Test name
Test status
Simulation time 6657362843 ps
CPU time 2.95 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:15:25 PM PST 24
Peak memory 203460 kb
Host smart-bd0094b0-59d2-4b8a-b5e3-6666d733f45f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278032744 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1278032744
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3329181754
Short name T928
Test name
Test status
Simulation time 10072589685 ps
CPU time 30.33 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:15:53 PM PST 24
Peak memory 345148 kb
Host smart-94cb7130-f7b9-4b55-81b2-28b3ae0f0313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329181754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3329181754
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3316094127
Short name T763
Test name
Test status
Simulation time 10085138435 ps
CPU time 77.1 seconds
Started Feb 21 03:15:19 PM PST 24
Finished Feb 21 03:16:37 PM PST 24
Peak memory 621564 kb
Host smart-81bd3457-d069-46c0-9d6c-01b1858d7885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316094127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3316094127
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.4219622735
Short name T201
Test name
Test status
Simulation time 4395525661 ps
CPU time 3.06 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:25 PM PST 24
Peak memory 203412 kb
Host smart-ae11984e-5c6f-4d3a-8a49-36bb2b957cfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219622735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.4219622735
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1981403037
Short name T798
Test name
Test status
Simulation time 903724073 ps
CPU time 4.39 seconds
Started Feb 21 03:15:19 PM PST 24
Finished Feb 21 03:15:24 PM PST 24
Peak memory 204844 kb
Host smart-9dbd2511-8c6d-4d64-8b14-fe2a95239b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981403037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1981403037
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3941072605
Short name T1080
Test name
Test status
Simulation time 5205733471 ps
CPU time 47.22 seconds
Started Feb 21 03:15:19 PM PST 24
Finished Feb 21 03:16:06 PM PST 24
Peak memory 1058184 kb
Host smart-f96f750e-7cca-40c2-bea0-fd702eff0a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941072605 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3941072605
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.77822498
Short name T1349
Test name
Test status
Simulation time 3290181833 ps
CPU time 4.61 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:15:29 PM PST 24
Peak memory 203400 kb
Host smart-65768c63-dec9-4418-89b2-9df43cea187c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77822498 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.i2c_target_perf.77822498
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.54966834
Short name T818
Test name
Test status
Simulation time 5156962417 ps
CPU time 16.07 seconds
Started Feb 21 03:15:25 PM PST 24
Finished Feb 21 03:15:41 PM PST 24
Peak memory 203388 kb
Host smart-51e53a72-c767-4d11-be8a-bc1e5c4bb33f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54966834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_targ
et_smoke.54966834
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.350669837
Short name T820
Test name
Test status
Simulation time 42053218312 ps
CPU time 2495.95 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:56:59 PM PST 24
Peak memory 6330788 kb
Host smart-031ab765-b3d2-46c1-8a36-239ae528fab3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350669837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.i2c_target_stress_all.350669837
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.781090596
Short name T486
Test name
Test status
Simulation time 6091164231 ps
CPU time 27.12 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 221512 kb
Host smart-474f2e35-147d-42a1-8058-e254706cc8d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781090596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.781090596
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.342336683
Short name T1097
Test name
Test status
Simulation time 49132960834 ps
CPU time 115.77 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:17:48 PM PST 24
Peak memory 1272044 kb
Host smart-c2817985-0a47-4198-8a30-cd329f7118df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342336683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.342336683
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.3340350338
Short name T899
Test name
Test status
Simulation time 44001968104 ps
CPU time 1625.18 seconds
Started Feb 21 03:15:05 PM PST 24
Finished Feb 21 03:42:11 PM PST 24
Peak memory 4688308 kb
Host smart-b4d40197-5f39-4b7f-a691-b818519c778e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340350338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.3340350338
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1388593454
Short name T1283
Test name
Test status
Simulation time 3227449254 ps
CPU time 6.73 seconds
Started Feb 21 03:15:06 PM PST 24
Finished Feb 21 03:15:13 PM PST 24
Peak memory 203444 kb
Host smart-03c3438d-32f5-48d9-9adb-8dd3cdf9ebe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388593454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1388593454
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_ovf.3917357664
Short name T374
Test name
Test status
Simulation time 13147969970 ps
CPU time 103.26 seconds
Started Feb 21 03:15:19 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 338688 kb
Host smart-80af9e2f-378f-40ce-953a-c927678620b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917357664 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_tx_ovf.3917357664
Directory /workspace/15.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.779978600
Short name T1039
Test name
Test status
Simulation time 1077060892 ps
CPU time 5.78 seconds
Started Feb 21 03:15:20 PM PST 24
Finished Feb 21 03:15:26 PM PST 24
Peak memory 203356 kb
Host smart-1d31c783-e27a-40d4-aa24-f8e46ccb2b38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779978600 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_unexp_stop.779978600
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.617214237
Short name T1169
Test name
Test status
Simulation time 18294257 ps
CPU time 0.62 seconds
Started Feb 21 03:15:23 PM PST 24
Finished Feb 21 03:15:24 PM PST 24
Peak memory 202068 kb
Host smart-1bca4253-7024-4e0e-8ae7-b35389d46fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617214237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.617214237
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1689983918
Short name T565
Test name
Test status
Simulation time 32311153 ps
CPU time 1.31 seconds
Started Feb 21 03:15:17 PM PST 24
Finished Feb 21 03:15:18 PM PST 24
Peak memory 203176 kb
Host smart-38d752d1-5fb3-4b1a-8ab3-4ccf44159efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689983918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1689983918
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2373867424
Short name T813
Test name
Test status
Simulation time 1504750573 ps
CPU time 17.42 seconds
Started Feb 21 03:15:20 PM PST 24
Finished Feb 21 03:15:37 PM PST 24
Peak memory 374648 kb
Host smart-a8dc1aa2-f316-457e-9097-fac1b1aedb13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373867424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2373867424
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.31059357
Short name T71
Test name
Test status
Simulation time 3096405126 ps
CPU time 124.05 seconds
Started Feb 21 03:15:16 PM PST 24
Finished Feb 21 03:17:21 PM PST 24
Peak memory 944376 kb
Host smart-132b6abd-9265-4569-9beb-02f95bbfc568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31059357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.31059357
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3605606175
Short name T447
Test name
Test status
Simulation time 5789705413 ps
CPU time 302.74 seconds
Started Feb 21 03:15:20 PM PST 24
Finished Feb 21 03:20:23 PM PST 24
Peak memory 1360604 kb
Host smart-511492a1-3a83-4c2f-ab8f-feeb5e8c41a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605606175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3605606175
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1283548985
Short name T243
Test name
Test status
Simulation time 121002045 ps
CPU time 0.82 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:15:25 PM PST 24
Peak memory 202296 kb
Host smart-6299223a-fe9f-416a-ad96-8e8593e1d330
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283548985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1283548985
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.497053673
Short name T581
Test name
Test status
Simulation time 212942704 ps
CPU time 5.96 seconds
Started Feb 21 03:15:07 PM PST 24
Finished Feb 21 03:15:14 PM PST 24
Peak memory 245016 kb
Host smart-4089c469-4cdb-4c08-b7ba-460afdc38b9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497053673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
497053673
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2729566360
Short name T1447
Test name
Test status
Simulation time 5928898714 ps
CPU time 391.3 seconds
Started Feb 21 03:15:06 PM PST 24
Finished Feb 21 03:21:38 PM PST 24
Peak memory 1654364 kb
Host smart-d3758572-e01c-4540-b858-3b15f214ba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729566360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2729566360
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1515818267
Short name T1135
Test name
Test status
Simulation time 1998887204 ps
CPU time 106.21 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:17:09 PM PST 24
Peak memory 248612 kb
Host smart-5ba33c01-d72f-4ff2-898b-39a416f07c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515818267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1515818267
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1869197957
Short name T1222
Test name
Test status
Simulation time 51452141 ps
CPU time 0.65 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:22 PM PST 24
Peak memory 202284 kb
Host smart-404a311e-97aa-47ad-ae70-a80de0ae9b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869197957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1869197957
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3333673524
Short name T1352
Test name
Test status
Simulation time 50113663098 ps
CPU time 1142.74 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:34:24 PM PST 24
Peak memory 471528 kb
Host smart-47a4bf06-b77c-4647-9c00-1e1a08eccffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333673524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3333673524
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_rx_oversample.3759446340
Short name T1231
Test name
Test status
Simulation time 1751486646 ps
CPU time 116.41 seconds
Started Feb 21 03:15:17 PM PST 24
Finished Feb 21 03:17:14 PM PST 24
Peak memory 246548 kb
Host smart-6b86d909-6841-41d8-afaa-f3f2564374d3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759446340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_rx_oversample
.3759446340
Directory /workspace/16.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3153749073
Short name T847
Test name
Test status
Simulation time 1514971926 ps
CPU time 27.86 seconds
Started Feb 21 03:15:20 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 248956 kb
Host smart-0399e114-e509-4d8d-9827-3ba923f1a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153749073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3153749073
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2291698746
Short name T1201
Test name
Test status
Simulation time 46697983615 ps
CPU time 2311.05 seconds
Started Feb 21 03:15:34 PM PST 24
Finished Feb 21 03:54:06 PM PST 24
Peak memory 2395500 kb
Host smart-ad7d06c4-2023-4ed2-9614-261fd7a9e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291698746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2291698746
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.2529032094
Short name T457
Test name
Test status
Simulation time 5416780273 ps
CPU time 13.73 seconds
Started Feb 21 03:15:32 PM PST 24
Finished Feb 21 03:15:46 PM PST 24
Peak memory 220052 kb
Host smart-8a11856d-4027-4a7d-ac4d-586c845c5b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529032094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2529032094
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3792272340
Short name T1380
Test name
Test status
Simulation time 446943180 ps
CPU time 2.28 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:23 PM PST 24
Peak memory 203360 kb
Host smart-4cfee99a-41c1-49b2-a786-3363d6b9773e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792272340 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3792272340
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3874264723
Short name T178
Test name
Test status
Simulation time 10068140731 ps
CPU time 26.51 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:16:11 PM PST 24
Peak memory 315784 kb
Host smart-9c5fcda0-8a40-42fb-834e-f4536e5bd6d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874264723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3874264723
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.342585977
Short name T443
Test name
Test status
Simulation time 10139767442 ps
CPU time 12.47 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:15:36 PM PST 24
Peak memory 300936 kb
Host smart-c96e78c0-6431-411e-9476-08e6cb579483
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342585977 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.342585977
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.175027227
Short name T1203
Test name
Test status
Simulation time 555668851 ps
CPU time 2.43 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:24 PM PST 24
Peak memory 203368 kb
Host smart-194d09f8-0264-4f90-a1df-119d0fad35a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175027227 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.175027227
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1229134203
Short name T887
Test name
Test status
Simulation time 6026764098 ps
CPU time 5.11 seconds
Started Feb 21 03:15:34 PM PST 24
Finished Feb 21 03:15:40 PM PST 24
Peak memory 203740 kb
Host smart-b89eac9f-e34e-425d-a5ff-fcb63b2e74bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229134203 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1229134203
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3672892877
Short name T1151
Test name
Test status
Simulation time 17964266431 ps
CPU time 96 seconds
Started Feb 21 03:15:32 PM PST 24
Finished Feb 21 03:17:08 PM PST 24
Peak memory 1147024 kb
Host smart-fa418a85-4e22-4c1d-bed5-479ebebb4d66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672892877 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3672892877
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.2924246152
Short name T728
Test name
Test status
Simulation time 629610592 ps
CPU time 3.85 seconds
Started Feb 21 03:15:36 PM PST 24
Finished Feb 21 03:15:41 PM PST 24
Peak memory 203388 kb
Host smart-6de0fb6c-3173-4a02-b1ac-521e8cd4875a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924246152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.2924246152
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2449157496
Short name T340
Test name
Test status
Simulation time 1249467123 ps
CPU time 12.77 seconds
Started Feb 21 03:15:31 PM PST 24
Finished Feb 21 03:15:44 PM PST 24
Peak memory 203376 kb
Host smart-a7c78085-f5e3-4d6a-9458-6f0fac3d8770
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449157496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2449157496
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.1272614030
Short name T203
Test name
Test status
Simulation time 66178650573 ps
CPU time 201.12 seconds
Started Feb 21 03:15:26 PM PST 24
Finished Feb 21 03:18:48 PM PST 24
Peak memory 1680540 kb
Host smart-bfdffc2e-8b56-4bf0-9bd8-e8857bc4d34d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272614030 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.1272614030
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3301925522
Short name T768
Test name
Test status
Simulation time 1900517394 ps
CPU time 35.1 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:16:18 PM PST 24
Peak memory 203332 kb
Host smart-39da990d-3262-4279-82d1-9a2a4ec96ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301925522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3301925522
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.364525701
Short name T70
Test name
Test status
Simulation time 45949955214 ps
CPU time 806.23 seconds
Started Feb 21 03:15:33 PM PST 24
Finished Feb 21 03:28:59 PM PST 24
Peak memory 5119268 kb
Host smart-259df720-2642-412b-9f5a-715974dc0de0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364525701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_wr.364525701
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.2241392507
Short name T1474
Test name
Test status
Simulation time 22368002716 ps
CPU time 2674.13 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:59:57 PM PST 24
Peak memory 4029696 kb
Host smart-d8eba970-e9ff-4d18-928f-ee9c63cdaf76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241392507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.2241392507
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1617167846
Short name T1467
Test name
Test status
Simulation time 3500535351 ps
CPU time 8.02 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:29 PM PST 24
Peak memory 210156 kb
Host smart-e38d2c01-8f77-4cb7-84b5-fa8af1e6181f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617167846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1617167846
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_ovf.2365145082
Short name T854
Test name
Test status
Simulation time 12792920656 ps
CPU time 119.97 seconds
Started Feb 21 03:15:34 PM PST 24
Finished Feb 21 03:17:35 PM PST 24
Peak memory 371272 kb
Host smart-1848fe54-d429-46f4-a0dd-933be4e6179b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365145082 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_tx_ovf.2365145082
Directory /workspace/16.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.70160155
Short name T1106
Test name
Test status
Simulation time 3099230232 ps
CPU time 6.44 seconds
Started Feb 21 03:15:26 PM PST 24
Finished Feb 21 03:15:33 PM PST 24
Peak memory 203292 kb
Host smart-3d8070dc-357d-47ef-a2d2-2f8ce69794d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70160155 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_unexp_stop.70160155
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.659897372
Short name T701
Test name
Test status
Simulation time 38314475 ps
CPU time 0.57 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:44 PM PST 24
Peak memory 202084 kb
Host smart-8f7c251f-7b27-4890-b208-919761ef23dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659897372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.659897372
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.8058290
Short name T1154
Test name
Test status
Simulation time 37364230 ps
CPU time 1.2 seconds
Started Feb 21 03:15:26 PM PST 24
Finished Feb 21 03:15:27 PM PST 24
Peak memory 211372 kb
Host smart-f7697c7e-3c0b-442b-beeb-4d8b3e749a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8058290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.8058290
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3118221876
Short name T842
Test name
Test status
Simulation time 1460086444 ps
CPU time 17.62 seconds
Started Feb 21 03:15:23 PM PST 24
Finished Feb 21 03:15:41 PM PST 24
Peak memory 262860 kb
Host smart-29943784-de28-452d-85f3-7d1600b55171
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118221876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3118221876
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.251207712
Short name T612
Test name
Test status
Simulation time 8324242002 ps
CPU time 115.82 seconds
Started Feb 21 03:15:20 PM PST 24
Finished Feb 21 03:17:17 PM PST 24
Peak memory 787924 kb
Host smart-a07a4c1c-e4dd-44be-8bc8-272a839aaed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251207712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.251207712
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.4161909424
Short name T889
Test name
Test status
Simulation time 18979284360 ps
CPU time 182.11 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:18:45 PM PST 24
Peak memory 952456 kb
Host smart-0ac5378c-38f8-4df9-bcaa-60c4ca5b3f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161909424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.4161909424
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3208175349
Short name T802
Test name
Test status
Simulation time 420071187 ps
CPU time 1.01 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:22 PM PST 24
Peak memory 203200 kb
Host smart-cb69f6d2-179d-4531-861f-942fa07c280f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208175349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3208175349
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.16086437
Short name T386
Test name
Test status
Simulation time 423652797 ps
CPU time 14.45 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:15:58 PM PST 24
Peak memory 249892 kb
Host smart-47bf469b-8eff-4f5a-87ce-353f6f435264
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16086437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.16086437
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1135524565
Short name T1421
Test name
Test status
Simulation time 39156672031 ps
CPU time 390.57 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:21:52 PM PST 24
Peak memory 1753660 kb
Host smart-6f1d0c88-d98f-4a35-9126-083f119cce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135524565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1135524565
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2715443840
Short name T1465
Test name
Test status
Simulation time 8891123457 ps
CPU time 44.88 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:16:23 PM PST 24
Peak memory 250724 kb
Host smart-4047a7df-7591-4929-870f-f8043a335327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715443840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2715443840
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.319807456
Short name T906
Test name
Test status
Simulation time 16648932 ps
CPU time 0.66 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:22 PM PST 24
Peak memory 202344 kb
Host smart-91ce98e0-f0b3-465a-842e-7130b29c62ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319807456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.319807456
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2786093947
Short name T182
Test name
Test status
Simulation time 4368384169 ps
CPU time 18.55 seconds
Started Feb 21 03:15:21 PM PST 24
Finished Feb 21 03:15:41 PM PST 24
Peak memory 211572 kb
Host smart-42fd73df-2c57-4d6e-b391-ece0b7edf173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786093947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2786093947
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_rx_oversample.527504326
Short name T843
Test name
Test status
Simulation time 31248250972 ps
CPU time 350.04 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:21:15 PM PST 24
Peak memory 343184 kb
Host smart-7ade2ee5-4c89-45c3-8c0a-02a1cb97c89f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527504326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_rx_oversample.
527504326
Directory /workspace/17.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3144285372
Short name T1136
Test name
Test status
Simulation time 17531692045 ps
CPU time 64.95 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:16:48 PM PST 24
Peak memory 342872 kb
Host smart-26bbed5b-a702-47fb-aa68-60b34da832ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144285372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3144285372
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3245799963
Short name T950
Test name
Test status
Simulation time 67333703331 ps
CPU time 1282.64 seconds
Started Feb 21 03:15:20 PM PST 24
Finished Feb 21 03:36:43 PM PST 24
Peak memory 1866620 kb
Host smart-28aa9dc3-9890-491b-ba58-dfa6362f2bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245799963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3245799963
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.691938027
Short name T1162
Test name
Test status
Simulation time 6243016117 ps
CPU time 18.79 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:15:43 PM PST 24
Peak memory 218260 kb
Host smart-2374368e-743a-44dd-827f-cea32b7b7f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691938027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.691938027
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2110922138
Short name T32
Test name
Test status
Simulation time 1227851494 ps
CPU time 4.45 seconds
Started Feb 21 03:15:27 PM PST 24
Finished Feb 21 03:15:32 PM PST 24
Peak memory 203360 kb
Host smart-bb2e8757-9c21-4a7e-acc5-a3338334b99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110922138 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2110922138
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.251060740
Short name T144
Test name
Test status
Simulation time 10194627631 ps
CPU time 39.79 seconds
Started Feb 21 03:15:35 PM PST 24
Finished Feb 21 03:16:16 PM PST 24
Peak memory 403504 kb
Host smart-7731886c-2504-41ea-870e-b62f3445e1ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251060740 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.251060740
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.4143624291
Short name T938
Test name
Test status
Simulation time 10086398827 ps
CPU time 93.26 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:17:11 PM PST 24
Peak memory 719712 kb
Host smart-0e85898e-424f-4b61-9457-e08ffe8a0f54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143624291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.4143624291
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.778767482
Short name T1182
Test name
Test status
Simulation time 439507451 ps
CPU time 2.47 seconds
Started Feb 21 03:15:25 PM PST 24
Finished Feb 21 03:15:28 PM PST 24
Peak memory 203348 kb
Host smart-e31798f0-4c04-4bd5-952f-736e7401a233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778767482 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.778767482
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1067378772
Short name T1071
Test name
Test status
Simulation time 1483263306 ps
CPU time 6.68 seconds
Started Feb 21 03:15:35 PM PST 24
Finished Feb 21 03:15:42 PM PST 24
Peak memory 206460 kb
Host smart-a9002801-7118-4bb2-b5e4-dd441b0b62fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067378772 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1067378772
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1549435652
Short name T69
Test name
Test status
Simulation time 10735500359 ps
CPU time 223.79 seconds
Started Feb 21 03:15:26 PM PST 24
Finished Feb 21 03:19:10 PM PST 24
Peak memory 2467108 kb
Host smart-153e63a4-1ad1-4c08-b3c0-0984b64bbbd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549435652 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1549435652
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.1022264259
Short name T369
Test name
Test status
Simulation time 1827675511 ps
CPU time 2.92 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:45 PM PST 24
Peak memory 203368 kb
Host smart-677aa28c-444f-400c-a77a-c4670c6b940b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022264259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.1022264259
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1465518644
Short name T677
Test name
Test status
Simulation time 2919168474 ps
CPU time 8.58 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:15:31 PM PST 24
Peak memory 203356 kb
Host smart-d1f35098-0d38-4d57-9dbb-c8b4cffde5de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465518644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1465518644
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3979091445
Short name T1087
Test name
Test status
Simulation time 714491253 ps
CPU time 24.56 seconds
Started Feb 21 03:15:19 PM PST 24
Finished Feb 21 03:15:43 PM PST 24
Peak memory 203364 kb
Host smart-6994514a-ed86-4d83-98a9-96778cb8c46d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979091445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3979091445
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.1880418789
Short name T1327
Test name
Test status
Simulation time 10461979193 ps
CPU time 97.3 seconds
Started Feb 21 03:15:32 PM PST 24
Finished Feb 21 03:17:09 PM PST 24
Peak memory 1655888 kb
Host smart-5f3ac709-d2fe-45a9-b88e-c1107e132d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880418789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.1880418789
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1992747682
Short name T343
Test name
Test status
Simulation time 3899023573 ps
CPU time 8.56 seconds
Started Feb 21 03:15:25 PM PST 24
Finished Feb 21 03:15:34 PM PST 24
Peak memory 214808 kb
Host smart-19a7a281-e3ec-44ee-b7b5-0e5b7a473622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992747682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1992747682
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_ovf.2102760466
Short name T17
Test name
Test status
Simulation time 2862801569 ps
CPU time 120.91 seconds
Started Feb 21 03:15:31 PM PST 24
Finished Feb 21 03:17:32 PM PST 24
Peak memory 325980 kb
Host smart-9b6609ee-0f3f-418e-827a-9c196e747cd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102760466 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_tx_ovf.2102760466
Directory /workspace/17.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/18.i2c_alert_test.516446846
Short name T924
Test name
Test status
Simulation time 16848915 ps
CPU time 0.62 seconds
Started Feb 21 03:15:39 PM PST 24
Finished Feb 21 03:15:40 PM PST 24
Peak memory 202104 kb
Host smart-058a6375-c12b-4525-a09a-a5f9e2a16e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516446846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.516446846
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3857722142
Short name T501
Test name
Test status
Simulation time 63674874 ps
CPU time 1.43 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:44 PM PST 24
Peak memory 211620 kb
Host smart-8dd87bd1-28d2-474c-87d3-38b96b956285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857722142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3857722142
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3343962725
Short name T1285
Test name
Test status
Simulation time 254183491 ps
CPU time 5.41 seconds
Started Feb 21 03:15:47 PM PST 24
Finished Feb 21 03:15:54 PM PST 24
Peak memory 245828 kb
Host smart-d15a847e-8ca2-4f0e-a344-8f7a38a6aa13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343962725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3343962725
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.777372903
Short name T903
Test name
Test status
Simulation time 3194598228 ps
CPU time 80.85 seconds
Started Feb 21 03:15:35 PM PST 24
Finished Feb 21 03:16:57 PM PST 24
Peak memory 600712 kb
Host smart-abe293f5-1bca-439a-96bc-3b1bab795b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777372903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.777372903
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3527222425
Short name T1400
Test name
Test status
Simulation time 13889330249 ps
CPU time 514.07 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:24:21 PM PST 24
Peak memory 1935316 kb
Host smart-68a8a9a8-29c6-4c9e-841c-0a37c5639682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527222425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3527222425
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1558105975
Short name T1510
Test name
Test status
Simulation time 177627292 ps
CPU time 0.87 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:44 PM PST 24
Peak memory 203128 kb
Host smart-8b59898a-bd47-48bb-a51d-76372e9a4475
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558105975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1558105975
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2402044512
Short name T1300
Test name
Test status
Simulation time 3631942958 ps
CPU time 13.4 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:16:00 PM PST 24
Peak memory 248636 kb
Host smart-9f271412-4fc3-4ca8-ad80-0d32608c0d33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402044512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2402044512
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.233530663
Short name T1264
Test name
Test status
Simulation time 5667685541 ps
CPU time 301.24 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:20:44 PM PST 24
Peak memory 1607940 kb
Host smart-ac064f59-6f30-45cd-9dfd-c89e31144bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233530663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.233530663
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.376515264
Short name T1031
Test name
Test status
Simulation time 6953170471 ps
CPU time 49.31 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:16:27 PM PST 24
Peak memory 296216 kb
Host smart-be27e98f-0b47-4b06-ae1a-b396326f7b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376515264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.376515264
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1151517938
Short name T272
Test name
Test status
Simulation time 25607705 ps
CPU time 0.65 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:15:38 PM PST 24
Peak memory 202264 kb
Host smart-5fd6fa11-4dea-4ed6-878e-e149d7afc318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151517938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1151517938
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1945359757
Short name T1427
Test name
Test status
Simulation time 3500249037 ps
CPU time 39.68 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:16:27 PM PST 24
Peak memory 220860 kb
Host smart-39c2374e-953d-4933-a3e9-9f9013aae298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945359757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1945359757
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_rx_oversample.3025636778
Short name T334
Test name
Test status
Simulation time 1494184555 ps
CPU time 56.6 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:16:41 PM PST 24
Peak memory 305140 kb
Host smart-4344e330-5d0c-4dd2-85ce-6bfc465869ca
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025636778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_rx_oversample
.3025636778
Directory /workspace/18.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3340872638
Short name T722
Test name
Test status
Simulation time 1589692118 ps
CPU time 88.93 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:17:14 PM PST 24
Peak memory 260504 kb
Host smart-f49fd07c-1847-46da-8779-0f21460d323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340872638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3340872638
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.3810473462
Short name T1324
Test name
Test status
Simulation time 132031666297 ps
CPU time 1361.32 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:38:28 PM PST 24
Peak memory 2692100 kb
Host smart-47d2cda4-38f1-4c85-809e-b7737527ba2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810473462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3810473462
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1311685337
Short name T1356
Test name
Test status
Simulation time 2639113108 ps
CPU time 24.81 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:16:10 PM PST 24
Peak memory 219060 kb
Host smart-ba25a68b-91b1-46ce-b8e6-3689a7df60db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311685337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1311685337
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.327421434
Short name T948
Test name
Test status
Simulation time 958599454 ps
CPU time 3.97 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:47 PM PST 24
Peak memory 203548 kb
Host smart-3f0dfd68-e5b6-4f26-a4f3-058be609b696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327421434 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.327421434
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2083992703
Short name T106
Test name
Test status
Simulation time 10467275404 ps
CPU time 23.68 seconds
Started Feb 21 03:15:38 PM PST 24
Finished Feb 21 03:16:02 PM PST 24
Peak memory 350228 kb
Host smart-a8bd16a5-4287-476f-b9ae-c3940b175d31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083992703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2083992703
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3605991273
Short name T506
Test name
Test status
Simulation time 10086718698 ps
CPU time 31.4 seconds
Started Feb 21 03:15:26 PM PST 24
Finished Feb 21 03:15:58 PM PST 24
Peak memory 420428 kb
Host smart-8beca03f-8637-43bf-bdde-22164c13381c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605991273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3605991273
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1024994701
Short name T640
Test name
Test status
Simulation time 1283602747 ps
CPU time 2.08 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:15:26 PM PST 24
Peak memory 203424 kb
Host smart-c21d42b8-6559-4fdf-8180-4d4741f86aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024994701 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1024994701
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3550371943
Short name T756
Test name
Test status
Simulation time 5590271489 ps
CPU time 6.22 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:53 PM PST 24
Peak memory 206864 kb
Host smart-becdc13a-4d19-4da5-b306-9c97e7f5d7c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550371943 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3550371943
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2118092928
Short name T766
Test name
Test status
Simulation time 15831063789 ps
CPU time 489.46 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:23:57 PM PST 24
Peak memory 3664516 kb
Host smart-2cf26b8b-d321-4597-8aae-50260edcf0c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118092928 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2118092928
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.1791230644
Short name T476
Test name
Test status
Simulation time 859780130 ps
CPU time 2.81 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:15:27 PM PST 24
Peak memory 203368 kb
Host smart-3a6ac6dd-9a13-4e19-8683-04569c0459fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791230644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.1791230644
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3744278952
Short name T430
Test name
Test status
Simulation time 1554103999 ps
CPU time 21.31 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:16:07 PM PST 24
Peak memory 203420 kb
Host smart-30963c14-2ea4-429b-aff5-b3d9e30d89e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744278952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3744278952
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_all.2449513191
Short name T438
Test name
Test status
Simulation time 11478004381 ps
CPU time 53.14 seconds
Started Feb 21 03:15:23 PM PST 24
Finished Feb 21 03:16:17 PM PST 24
Peak memory 254944 kb
Host smart-ca477e8d-d0bb-4bae-ab6d-5f109a1e14b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449513191 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_stress_all.2449513191
Directory /workspace/18.i2c_target_stress_all/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2976490960
Short name T1181
Test name
Test status
Simulation time 32311909595 ps
CPU time 277.25 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:20:24 PM PST 24
Peak memory 1666084 kb
Host smart-6d8b0261-0d05-40fb-a84a-86f8273d9aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976490960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2976490960
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1261506191
Short name T1100
Test name
Test status
Simulation time 6066517731 ps
CPU time 7.05 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:54 PM PST 24
Peak memory 203436 kb
Host smart-d789cf6c-3040-4f12-849c-8ea97daad50c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261506191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1261506191
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_ovf.3404615404
Short name T749
Test name
Test status
Simulation time 2390151599 ps
CPU time 37.3 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:16:24 PM PST 24
Peak memory 213648 kb
Host smart-586ea956-b4ec-4a8a-9be7-fbf711ba3e98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404615404 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_tx_ovf.3404615404
Directory /workspace/18.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.4236657804
Short name T999
Test name
Test status
Simulation time 1178109647 ps
CPU time 5.32 seconds
Started Feb 21 03:15:25 PM PST 24
Finished Feb 21 03:15:30 PM PST 24
Peak memory 203380 kb
Host smart-f6a0b5e0-7a4b-4832-a96f-6856f4c4e81f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236657804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.i2c_target_unexp_stop.4236657804
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2943190824
Short name T959
Test name
Test status
Simulation time 14911874 ps
CPU time 0.61 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 203012 kb
Host smart-bb4d1757-cf60-406b-90f7-528b8948570a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943190824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2943190824
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.4271745957
Short name T36
Test name
Test status
Simulation time 43591506 ps
CPU time 1.3 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:15:52 PM PST 24
Peak memory 210444 kb
Host smart-d4dfefec-83c5-4c34-b416-bf17e3d7c78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271745957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4271745957
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3783218224
Short name T631
Test name
Test status
Simulation time 340906033 ps
CPU time 8.93 seconds
Started Feb 21 03:15:47 PM PST 24
Finished Feb 21 03:15:57 PM PST 24
Peak memory 233760 kb
Host smart-ea7a1c2f-1027-4968-b2ae-07311ae52e90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783218224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3783218224
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2144864597
Short name T1102
Test name
Test status
Simulation time 2922148172 ps
CPU time 219.02 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:19:26 PM PST 24
Peak memory 836836 kb
Host smart-562bd39c-88b0-48c9-af4f-8138b6046644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144864597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2144864597
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.4133795252
Short name T1401
Test name
Test status
Simulation time 25257216834 ps
CPU time 161.73 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:18:19 PM PST 24
Peak memory 1087452 kb
Host smart-04f3c232-30f8-4609-a099-538785db9082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133795252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.4133795252
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2957807340
Short name T532
Test name
Test status
Simulation time 95901531 ps
CPU time 0.84 seconds
Started Feb 21 03:15:38 PM PST 24
Finished Feb 21 03:15:40 PM PST 24
Peak memory 203044 kb
Host smart-0ac37005-c61a-4234-b15e-c506a2b3af1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957807340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2957807340
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2681251557
Short name T582
Test name
Test status
Simulation time 305349105 ps
CPU time 3.97 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 229624 kb
Host smart-4b230a0a-7cc7-48c6-8c17-26bcbb854f64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681251557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2681251557
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1582260859
Short name T850
Test name
Test status
Simulation time 5742641777 ps
CPU time 357.14 seconds
Started Feb 21 03:15:38 PM PST 24
Finished Feb 21 03:21:36 PM PST 24
Peak memory 1667328 kb
Host smart-feaf16d7-e9c2-4014-b13d-f83808a97e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582260859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1582260859
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1793308910
Short name T1464
Test name
Test status
Simulation time 1946117266 ps
CPU time 52.07 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:16:39 PM PST 24
Peak memory 297236 kb
Host smart-7d041469-499e-4ed0-a9aa-a909314be39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793308910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1793308910
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3465255484
Short name T1
Test name
Test status
Simulation time 145500555 ps
CPU time 0.69 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:43 PM PST 24
Peak memory 202260 kb
Host smart-9b2c3b24-9827-4dce-acb9-3fd110ebed2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465255484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3465255484
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1603450900
Short name T187
Test name
Test status
Simulation time 300873732 ps
CPU time 3.05 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:15:46 PM PST 24
Peak memory 211520 kb
Host smart-1b48683e-507d-40c5-80f0-f92feadce732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603450900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1603450900
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_rx_oversample.2122204794
Short name T1297
Test name
Test status
Simulation time 2164665412 ps
CPU time 109.33 seconds
Started Feb 21 03:15:24 PM PST 24
Finished Feb 21 03:17:13 PM PST 24
Peak memory 316360 kb
Host smart-7e4d1c99-1e2f-4024-a93e-57e6fdb8afc6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122204794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_rx_oversample
.2122204794
Directory /workspace/19.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2721574629
Short name T516
Test name
Test status
Simulation time 10599796941 ps
CPU time 150.36 seconds
Started Feb 21 03:15:33 PM PST 24
Finished Feb 21 03:18:04 PM PST 24
Peak memory 262984 kb
Host smart-4919b192-9dbb-4141-a02e-8dac05160299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721574629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2721574629
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3479976719
Short name T558
Test name
Test status
Simulation time 3567013074 ps
CPU time 41 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:16:28 PM PST 24
Peak memory 212128 kb
Host smart-c91eaf4d-aef7-4c97-a509-bd249f0c1c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479976719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3479976719
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3017913464
Short name T1094
Test name
Test status
Simulation time 6381812510 ps
CPU time 4.07 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 203484 kb
Host smart-2688ad16-99a8-446d-9ab1-938bdcf43ca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017913464 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3017913464
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3648786580
Short name T1160
Test name
Test status
Simulation time 10159674648 ps
CPU time 11.72 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:15:57 PM PST 24
Peak memory 253616 kb
Host smart-d9f0dadd-060f-4ffd-a3e1-d42c72501782
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648786580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3648786580
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.58044471
Short name T706
Test name
Test status
Simulation time 10120345752 ps
CPU time 72.07 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:16:58 PM PST 24
Peak memory 634524 kb
Host smart-92617bbd-f9b7-49cd-a597-29c1421856b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58044471 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_fifo_reset_tx.58044471
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2066534268
Short name T162
Test name
Test status
Simulation time 2103568742 ps
CPU time 2.61 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 203376 kb
Host smart-d54cfe9f-9f3c-47ac-a07e-f0860486b0e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066534268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2066534268
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.675057495
Short name T485
Test name
Test status
Simulation time 761566023 ps
CPU time 3.55 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 203364 kb
Host smart-ff4b039d-0919-4e1f-aeb0-b57aaa4041c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675057495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.675057495
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.632582124
Short name T858
Test name
Test status
Simulation time 20291301092 ps
CPU time 851.37 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:29:56 PM PST 24
Peak memory 4733160 kb
Host smart-4e6727f3-c118-476b-9b76-372142e16fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632582124 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.632582124
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.3238178901
Short name T1287
Test name
Test status
Simulation time 3665404856 ps
CPU time 5.34 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:53 PM PST 24
Peak memory 207228 kb
Host smart-0533ca7f-3351-473a-b677-60cdfad4e13b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238178901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.3238178901
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.1665425842
Short name T308
Test name
Test status
Simulation time 4165749101 ps
CPU time 10.37 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:54 PM PST 24
Peak memory 203484 kb
Host smart-4d108491-c94b-46f2-baae-5325b8f98784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665425842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.1665425842
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.2381742247
Short name T1363
Test name
Test status
Simulation time 90886034298 ps
CPU time 2205.36 seconds
Started Feb 21 03:15:35 PM PST 24
Finished Feb 21 03:52:22 PM PST 24
Peak memory 7676908 kb
Host smart-d2934969-b5c3-4325-8e2e-8edf5bf49146
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381742247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.2381742247
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3312800244
Short name T294
Test name
Test status
Simulation time 677525549 ps
CPU time 28.97 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:16:20 PM PST 24
Peak memory 203420 kb
Host smart-bef26c60-a965-4bc8-b0b9-f01fbdcb3ba3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312800244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3312800244
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3992993037
Short name T307
Test name
Test status
Simulation time 48032399405 ps
CPU time 3301.85 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 04:10:50 PM PST 24
Peak memory 11170752 kb
Host smart-42d1f1e4-1f4f-4654-8658-c8d167d02c32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992993037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3992993037
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.4082908347
Short name T355
Test name
Test status
Simulation time 8199798274 ps
CPU time 45.18 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:16:32 PM PST 24
Peak memory 605700 kb
Host smart-12519261-4fc9-4326-acaf-7932a9c2bcb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082908347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.4082908347
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.760078828
Short name T551
Test name
Test status
Simulation time 5571061663 ps
CPU time 6.4 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:54 PM PST 24
Peak memory 203448 kb
Host smart-5811a870-e273-4881-bd54-32ab10527ad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760078828 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.760078828
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_ovf.1434132395
Short name T649
Test name
Test status
Simulation time 16054720611 ps
CPU time 121.77 seconds
Started Feb 21 03:15:46 PM PST 24
Finished Feb 21 03:17:49 PM PST 24
Peak memory 358776 kb
Host smart-1b470ead-f966-461e-bdff-f203855d34de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434132395 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_tx_ovf.1434132395
Directory /workspace/19.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.1380531375
Short name T1295
Test name
Test status
Simulation time 1417498662 ps
CPU time 7.82 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:52 PM PST 24
Peak memory 203380 kb
Host smart-a8bff23d-d44c-4418-8791-cc17521a28c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380531375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.1380531375
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.435976687
Short name T474
Test name
Test status
Simulation time 18470014 ps
CPU time 0.61 seconds
Started Feb 21 03:13:34 PM PST 24
Finished Feb 21 03:13:36 PM PST 24
Peak memory 202164 kb
Host smart-e3b2f772-e2a5-4021-9d27-b6d14dbadb0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435976687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.435976687
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1591304174
Short name T53
Test name
Test status
Simulation time 95440634 ps
CPU time 1.63 seconds
Started Feb 21 03:13:38 PM PST 24
Finished Feb 21 03:13:40 PM PST 24
Peak memory 211568 kb
Host smart-f8bed18c-4978-4938-88d8-ab6a3d397544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591304174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1591304174
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.776744946
Short name T257
Test name
Test status
Simulation time 3001287006 ps
CPU time 10.91 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:13:45 PM PST 24
Peak memory 305932 kb
Host smart-a62056a9-5cc3-44c1-86f7-bc11fd0186c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776744946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.776744946
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.428026474
Short name T1344
Test name
Test status
Simulation time 12639978424 ps
CPU time 107.33 seconds
Started Feb 21 03:13:26 PM PST 24
Finished Feb 21 03:15:14 PM PST 24
Peak memory 783468 kb
Host smart-0dff4d07-0f51-4b86-a8fd-f935f0813595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428026474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.428026474
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.31401671
Short name T1229
Test name
Test status
Simulation time 6178597202 ps
CPU time 836.95 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:27:31 PM PST 24
Peak memory 1681068 kb
Host smart-a0c50ed9-2e9e-4313-965e-1e1d54715402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31401671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.31401671
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2662575519
Short name T244
Test name
Test status
Simulation time 810250535 ps
CPU time 1.09 seconds
Started Feb 21 03:13:32 PM PST 24
Finished Feb 21 03:13:35 PM PST 24
Peak memory 202916 kb
Host smart-ffa97c6e-10c4-4f11-b5c9-47b982c7ab3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662575519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2662575519
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.1126098018
Short name T191
Test name
Test status
Simulation time 3267827533 ps
CPU time 4.43 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:37 PM PST 24
Peak memory 234352 kb
Host smart-1ffbb757-9a81-4fea-b32b-e3313226c870
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126098018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
1126098018
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.420333343
Short name T363
Test name
Test status
Simulation time 4692662551 ps
CPU time 458.51 seconds
Started Feb 21 03:13:25 PM PST 24
Finished Feb 21 03:21:04 PM PST 24
Peak memory 1292332 kb
Host smart-705a870c-9a24-4a6f-b64e-51c88c4f1203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420333343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.420333343
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2817009563
Short name T819
Test name
Test status
Simulation time 2573837714 ps
CPU time 96.32 seconds
Started Feb 21 03:13:35 PM PST 24
Finished Feb 21 03:15:13 PM PST 24
Peak memory 347736 kb
Host smart-4e3141d6-5dea-4c16-8d7d-08508c3b27e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817009563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2817009563
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.3162324127
Short name T406
Test name
Test status
Simulation time 17801695 ps
CPU time 0.65 seconds
Started Feb 21 03:13:25 PM PST 24
Finished Feb 21 03:13:26 PM PST 24
Peak memory 202352 kb
Host smart-9147e195-7c76-422e-9dc4-310eb921ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162324127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3162324127
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3953822996
Short name T1414
Test name
Test status
Simulation time 55316323931 ps
CPU time 257.57 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:17:49 PM PST 24
Peak memory 294688 kb
Host smart-e1e21aa0-5956-4474-8482-4484816b9470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953822996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3953822996
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_rx_oversample.2199966000
Short name T312
Test name
Test status
Simulation time 2981801031 ps
CPU time 248.02 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:17:41 PM PST 24
Peak memory 333000 kb
Host smart-d3edd017-0551-4e43-952e-8d21ef82cac5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199966000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_rx_oversample.
2199966000
Directory /workspace/2.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4005140162
Short name T732
Test name
Test status
Simulation time 1931095188 ps
CPU time 44.55 seconds
Started Feb 21 03:13:26 PM PST 24
Finished Feb 21 03:14:10 PM PST 24
Peak memory 264928 kb
Host smart-94fd747b-ca77-4e1a-a93f-f6b7d0d0fd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005140162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4005140162
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2509073343
Short name T1016
Test name
Test status
Simulation time 1553939067 ps
CPU time 30.7 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:14:03 PM PST 24
Peak memory 211532 kb
Host smart-a09c705e-ab06-400f-bbc0-fa8456fd1794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509073343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2509073343
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3137316379
Short name T686
Test name
Test status
Simulation time 4386099024 ps
CPU time 4.53 seconds
Started Feb 21 03:13:33 PM PST 24
Finished Feb 21 03:13:40 PM PST 24
Peak memory 203432 kb
Host smart-1a8209e9-910b-46de-8ef6-a5e3d0521d72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137316379 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3137316379
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1588253459
Short name T1410
Test name
Test status
Simulation time 10040047098 ps
CPU time 64.68 seconds
Started Feb 21 03:13:39 PM PST 24
Finished Feb 21 03:14:44 PM PST 24
Peak memory 512808 kb
Host smart-c9ab2914-d569-4b5c-949d-e14e3783ec37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588253459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1588253459
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2040273046
Short name T734
Test name
Test status
Simulation time 10043238604 ps
CPU time 82.61 seconds
Started Feb 21 03:13:36 PM PST 24
Finished Feb 21 03:14:59 PM PST 24
Peak memory 634344 kb
Host smart-8ad972b4-dd22-4050-8b3e-351a27e03b35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040273046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2040273046
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3950160779
Short name T107
Test name
Test status
Simulation time 1564466092 ps
CPU time 2.48 seconds
Started Feb 21 03:13:39 PM PST 24
Finished Feb 21 03:13:42 PM PST 24
Peak memory 203300 kb
Host smart-38f66ad9-c49b-43c1-b3e1-33f51315b15c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950160779 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3950160779
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.3673659355
Short name T923
Test name
Test status
Simulation time 2483030340 ps
CPU time 2.99 seconds
Started Feb 21 03:13:37 PM PST 24
Finished Feb 21 03:13:40 PM PST 24
Peak memory 203404 kb
Host smart-092bf924-14e1-48ca-9fdd-387accf8dd3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673659355 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.3673659355
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2986934538
Short name T1072
Test name
Test status
Simulation time 22464625290 ps
CPU time 82.45 seconds
Started Feb 21 03:13:36 PM PST 24
Finished Feb 21 03:14:59 PM PST 24
Peak memory 921440 kb
Host smart-a002e9cf-f0a3-4fee-b689-66b57aae8076
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986934538 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2986934538
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.3542453431
Short name T1268
Test name
Test status
Simulation time 1426272248 ps
CPU time 4.07 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:37 PM PST 24
Peak memory 203320 kb
Host smart-a644a852-cf1d-408b-b587-bb1f8a9da957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542453431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.3542453431
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.2619441580
Short name T964
Test name
Test status
Simulation time 1351163363 ps
CPU time 35.73 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:14:06 PM PST 24
Peak memory 203360 kb
Host smart-4c4700f7-34a7-4906-ac55-8a47a90a27a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619441580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.2619441580
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.875814011
Short name T204
Test name
Test status
Simulation time 62394148019 ps
CPU time 219.61 seconds
Started Feb 21 03:13:31 PM PST 24
Finished Feb 21 03:17:14 PM PST 24
Peak memory 1879164 kb
Host smart-4e2dccb8-8745-492a-b3f8-86fa25c90ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875814011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.i2c_target_stress_all.875814011
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.4044771195
Short name T342
Test name
Test status
Simulation time 5921459463 ps
CPU time 17.92 seconds
Started Feb 21 03:13:37 PM PST 24
Finished Feb 21 03:13:55 PM PST 24
Peak memory 215296 kb
Host smart-e01fd86c-865d-40f9-8abb-fb4f10f9ed64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044771195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.4044771195
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1237145869
Short name T1193
Test name
Test status
Simulation time 27850632123 ps
CPU time 106.13 seconds
Started Feb 21 03:13:34 PM PST 24
Finished Feb 21 03:15:22 PM PST 24
Peak memory 1521444 kb
Host smart-2b452c9f-2b82-4316-bc36-3e07dcb3151b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237145869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1237145869
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1707564390
Short name T965
Test name
Test status
Simulation time 15095077480 ps
CPU time 575.8 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:23:08 PM PST 24
Peak memory 2746988 kb
Host smart-301b52e3-bc66-4031-9748-4a01c31bf73d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707564390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1707564390
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1321599500
Short name T296
Test name
Test status
Simulation time 4200832254 ps
CPU time 8.03 seconds
Started Feb 21 03:13:35 PM PST 24
Finished Feb 21 03:13:44 PM PST 24
Peak memory 207864 kb
Host smart-375b2c75-7821-4b5a-9a24-1148e81cfda1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321599500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1321599500
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_ovf.3381593566
Short name T545
Test name
Test status
Simulation time 4387808481 ps
CPU time 44.28 seconds
Started Feb 21 03:13:29 PM PST 24
Finished Feb 21 03:14:16 PM PST 24
Peak memory 228888 kb
Host smart-1baa7ebe-dbba-4aa5-9f7e-eb1bfbda1c8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381593566 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_tx_ovf.3381593566
Directory /workspace/2.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.600219121
Short name T860
Test name
Test status
Simulation time 6253146142 ps
CPU time 8.55 seconds
Started Feb 21 03:13:34 PM PST 24
Finished Feb 21 03:13:44 PM PST 24
Peak memory 203508 kb
Host smart-684357e8-6b2c-4721-964c-4eefeeed74d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600219121 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_unexp_stop.600219121
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.2349242800
Short name T957
Test name
Test status
Simulation time 14729257 ps
CPU time 0.6 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:42 PM PST 24
Peak memory 202048 kb
Host smart-fc13f06a-623d-4b6a-8e48-e91e536a4b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349242800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.2349242800
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.1091873757
Short name T1221
Test name
Test status
Simulation time 32851952 ps
CPU time 1.36 seconds
Started Feb 21 03:15:25 PM PST 24
Finished Feb 21 03:15:27 PM PST 24
Peak memory 203332 kb
Host smart-85e4fd14-53a2-4255-a411-401ee72022a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091873757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1091873757
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2529679475
Short name T1167
Test name
Test status
Simulation time 379729243 ps
CPU time 19.08 seconds
Started Feb 21 03:15:38 PM PST 24
Finished Feb 21 03:15:58 PM PST 24
Peak memory 284172 kb
Host smart-dc3da16f-ecfe-48b7-a0e4-5c0e9c49f0d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529679475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2529679475
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1637014831
Short name T762
Test name
Test status
Simulation time 15547500462 ps
CPU time 178.8 seconds
Started Feb 21 03:15:33 PM PST 24
Finished Feb 21 03:18:33 PM PST 24
Peak memory 277664 kb
Host smart-e31ec6b9-4928-4299-81d3-91ec8be14285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637014831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1637014831
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1829299887
Short name T568
Test name
Test status
Simulation time 29042885193 ps
CPU time 195.29 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:19:02 PM PST 24
Peak memory 1075640 kb
Host smart-9948f413-1624-40b6-b0d0-0d82141f2afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829299887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1829299887
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2763517531
Short name T607
Test name
Test status
Simulation time 334907124 ps
CPU time 0.9 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:15:47 PM PST 24
Peak memory 202988 kb
Host smart-ead81cc1-12d7-4f7a-9161-838b8ca9e360
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763517531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2763517531
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1461008553
Short name T300
Test name
Test status
Simulation time 160598486 ps
CPU time 3.87 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 203312 kb
Host smart-1fb2878f-aae9-419e-81a2-8c0881b1676b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461008553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1461008553
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1389226157
Short name T1416
Test name
Test status
Simulation time 29203274040 ps
CPU time 167.14 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:18:31 PM PST 24
Peak memory 1101456 kb
Host smart-34ae2fca-ca08-4d42-8574-865ae0f7c7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389226157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1389226157
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3551611526
Short name T1146
Test name
Test status
Simulation time 2650208522 ps
CPU time 71.11 seconds
Started Feb 21 03:15:39 PM PST 24
Finished Feb 21 03:16:51 PM PST 24
Peak memory 284672 kb
Host smart-9a9a0ac5-d4d4-430d-9abe-0f85828cec87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551611526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3551611526
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3649922961
Short name T1348
Test name
Test status
Simulation time 17795895 ps
CPU time 0.66 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:46 PM PST 24
Peak memory 202356 kb
Host smart-783d3168-d5ff-490f-b4a2-f621569c929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649922961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3649922961
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2438542407
Short name T1116
Test name
Test status
Simulation time 7578578891 ps
CPU time 83.64 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:17:01 PM PST 24
Peak memory 211540 kb
Host smart-aed304eb-2ae9-4fa6-a24f-fc4fbe887002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438542407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2438542407
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_rx_oversample.278733488
Short name T149
Test name
Test status
Simulation time 4885146612 ps
CPU time 66.19 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:16:53 PM PST 24
Peak memory 294484 kb
Host smart-2cb906b0-7673-42ab-9684-fc5cb1c9ee38
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278733488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_rx_oversample.
278733488
Directory /workspace/20.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.3527286189
Short name T72
Test name
Test status
Simulation time 3900309171 ps
CPU time 111.49 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:17:37 PM PST 24
Peak memory 251556 kb
Host smart-f7949737-a4d3-44d7-8f9b-3c7d0dc2eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527286189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3527286189
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1944168277
Short name T153
Test name
Test status
Simulation time 32393043049 ps
CPU time 905.26 seconds
Started Feb 21 03:15:33 PM PST 24
Finished Feb 21 03:30:39 PM PST 24
Peak memory 1904564 kb
Host smart-02581b5e-0b27-49d9-bc60-5b0a41a234cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944168277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1944168277
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2590224380
Short name T1003
Test name
Test status
Simulation time 1448160688 ps
CPU time 12.89 seconds
Started Feb 21 03:15:34 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 219780 kb
Host smart-ea27cd59-6121-4b03-afcb-b33310c0ebe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590224380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2590224380
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.312109019
Short name T1163
Test name
Test status
Simulation time 1680148835 ps
CPU time 6.03 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 203380 kb
Host smart-84f32aaf-6052-4b76-aaa3-04e86d487560
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312109019 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.312109019
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3174826161
Short name T753
Test name
Test status
Simulation time 10056924238 ps
CPU time 59.52 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:16:37 PM PST 24
Peak memory 492136 kb
Host smart-ea2db287-3ca1-4e81-b27e-91058749f3bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174826161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3174826161
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.135209531
Short name T1258
Test name
Test status
Simulation time 10034942721 ps
CPU time 71.44 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:16:59 PM PST 24
Peak memory 630520 kb
Host smart-3339edc3-2565-4e05-b953-f1c0e21037cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135209531 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.135209531
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1885558593
Short name T1096
Test name
Test status
Simulation time 1992918959 ps
CPU time 2.7 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:43 PM PST 24
Peak memory 203288 kb
Host smart-614b27a9-efd8-41dc-9fe9-922ac0de77ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885558593 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1885558593
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3827341137
Short name T341
Test name
Test status
Simulation time 3098864240 ps
CPU time 5.75 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 205432 kb
Host smart-31d265d4-bd04-438d-8493-9b943f1c62ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827341137 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3827341137
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2949232858
Short name T739
Test name
Test status
Simulation time 19667824358 ps
CPU time 788.7 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:28:50 PM PST 24
Peak memory 4709408 kb
Host smart-85848abd-679e-4949-961a-d28c66c9df9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949232858 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2949232858
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.65756000
Short name T511
Test name
Test status
Simulation time 2851819969 ps
CPU time 4.44 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 207008 kb
Host smart-a7d8875a-ac81-44dd-aa15-4ded26f9b3b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65756000 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 20.i2c_target_perf.65756000
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1623757751
Short name T179
Test name
Test status
Simulation time 1726212650 ps
CPU time 23.32 seconds
Started Feb 21 03:15:34 PM PST 24
Finished Feb 21 03:15:59 PM PST 24
Peak memory 203352 kb
Host smart-0ea1caee-e13d-4247-9fcb-77984d7c4433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623757751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1623757751
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.1357319335
Short name T1386
Test name
Test status
Simulation time 73774870607 ps
CPU time 1750.43 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:44:54 PM PST 24
Peak memory 1276548 kb
Host smart-12e3692a-09e6-4e37-b695-b06b68d27bad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357319335 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.i2c_target_stress_all.1357319335
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.932695294
Short name T253
Test name
Test status
Simulation time 393414587 ps
CPU time 15.68 seconds
Started Feb 21 03:15:39 PM PST 24
Finished Feb 21 03:15:56 PM PST 24
Peak memory 203348 kb
Host smart-2d936218-7243-42e1-af3d-901c7aeadf09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932695294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.932695294
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3146057474
Short name T362
Test name
Test status
Simulation time 42493012159 ps
CPU time 278.94 seconds
Started Feb 21 03:15:59 PM PST 24
Finished Feb 21 03:20:38 PM PST 24
Peak memory 2460628 kb
Host smart-f63e4934-68c1-4c42-a953-e70cdf0d7356
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146057474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3146057474
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3395933811
Short name T807
Test name
Test status
Simulation time 36751180260 ps
CPU time 194.26 seconds
Started Feb 21 03:15:22 PM PST 24
Finished Feb 21 03:18:37 PM PST 24
Peak memory 1319040 kb
Host smart-7cf1c83c-5a24-4d14-9f2c-1107f12b2283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395933811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3395933811
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1365443673
Short name T601
Test name
Test status
Simulation time 3338053925 ps
CPU time 7.35 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:15:51 PM PST 24
Peak memory 216272 kb
Host smart-1e0ccc6d-8408-4bfc-a9ac-2e323a64a8fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365443673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1365443673
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_ovf.2722116876
Short name T1043
Test name
Test status
Simulation time 13434264746 ps
CPU time 103.72 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:17:27 PM PST 24
Peak memory 408728 kb
Host smart-6f0f2c7b-bec7-4cb8-9dee-9cc509aa25df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722116876 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_tx_ovf.2722116876
Directory /workspace/20.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.1913694717
Short name T1398
Test name
Test status
Simulation time 6637967004 ps
CPU time 8.13 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:51 PM PST 24
Peak memory 203512 kb
Host smart-f4837147-b53e-447c-9575-1a2013e0f7e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913694717 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.1913694717
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3790541222
Short name T1177
Test name
Test status
Simulation time 18216673 ps
CPU time 0.61 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:15:45 PM PST 24
Peak memory 203040 kb
Host smart-b8f0b5df-09e6-4f16-b83e-ec7de0e28bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790541222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3790541222
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3161760358
Short name T1157
Test name
Test status
Simulation time 174525233 ps
CPU time 1.42 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:15:45 PM PST 24
Peak memory 219712 kb
Host smart-4b7f1327-b0c4-4d90-83aa-f3e7613f2752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161760358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3161760358
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.4201533705
Short name T1127
Test name
Test status
Simulation time 330009744 ps
CPU time 17.15 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:16:00 PM PST 24
Peak memory 273128 kb
Host smart-b744e8a4-5e07-4e52-9b58-e95dd03413d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201533705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.4201533705
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3633349453
Short name T481
Test name
Test status
Simulation time 2699040079 ps
CPU time 101.14 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:17:26 PM PST 24
Peak memory 875984 kb
Host smart-798ab152-d9d5-412c-b4d2-9a2292f3892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633349453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3633349453
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1463731666
Short name T1237
Test name
Test status
Simulation time 17557644486 ps
CPU time 337.04 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:21:21 PM PST 24
Peak memory 957096 kb
Host smart-77af9ab6-46ba-4e91-a309-3ac81a173e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463731666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1463731666
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2312279535
Short name T609
Test name
Test status
Simulation time 97808235 ps
CPU time 0.95 seconds
Started Feb 21 03:15:47 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 203044 kb
Host smart-d864076c-b75f-4802-bba7-9f778c83f876
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312279535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2312279535
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3788727810
Short name T730
Test name
Test status
Simulation time 613997857 ps
CPU time 4.29 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 230136 kb
Host smart-563a366c-2246-4fd3-acb8-74d686167616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788727810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3788727810
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3591448032
Short name T717
Test name
Test status
Simulation time 3621414374 ps
CPU time 166.67 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:18:38 PM PST 24
Peak memory 1070844 kb
Host smart-f307d72d-8c1f-4b9e-b13f-cc89c23d489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591448032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3591448032
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.492870768
Short name T1355
Test name
Test status
Simulation time 4349581067 ps
CPU time 123.03 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:17:50 PM PST 24
Peak memory 260468 kb
Host smart-4343284e-3621-40c4-9b86-e9b76a0e03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492870768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.492870768
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1780277025
Short name T1439
Test name
Test status
Simulation time 48547579 ps
CPU time 0.63 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:15:52 PM PST 24
Peak memory 202952 kb
Host smart-2de78af7-c7a2-488e-8989-7a6dc4333a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780277025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1780277025
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.74613931
Short name T185
Test name
Test status
Simulation time 3936185748 ps
CPU time 17.71 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:16:09 PM PST 24
Peak memory 202364 kb
Host smart-0a9ba339-35c6-487b-a30a-32a8e4ab319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74613931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.74613931
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_rx_oversample.10007058
Short name T1132
Test name
Test status
Simulation time 44075613416 ps
CPU time 120.7 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 319220 kb
Host smart-e27768a8-8658-4f76-bc59-6d17ad32ea3d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10007058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_rx_oversample.10007058
Directory /workspace/21.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1146448348
Short name T1126
Test name
Test status
Simulation time 3129398669 ps
CPU time 49.32 seconds
Started Feb 21 03:15:38 PM PST 24
Finished Feb 21 03:16:29 PM PST 24
Peak memory 251176 kb
Host smart-47b8cdca-ffd4-47b3-a27a-883285d7e206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146448348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1146448348
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3867382442
Short name T154
Test name
Test status
Simulation time 21173016978 ps
CPU time 689.03 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:27:13 PM PST 24
Peak memory 1516084 kb
Host smart-106780ab-1780-4ee2-922b-16e7486ef4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867382442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3867382442
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3141168468
Short name T1130
Test name
Test status
Simulation time 1077174657 ps
CPU time 47.59 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:16:34 PM PST 24
Peak memory 219732 kb
Host smart-8f0aa3b8-0fe2-4943-b02b-76646954860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141168468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3141168468
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3355023082
Short name T1051
Test name
Test status
Simulation time 839448245 ps
CPU time 4.26 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:51 PM PST 24
Peak memory 203336 kb
Host smart-a647c944-2ab0-41eb-92cb-3e7053d6441a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355023082 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3355023082
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.84005082
Short name T867
Test name
Test status
Simulation time 10048448265 ps
CPU time 56.25 seconds
Started Feb 21 03:15:37 PM PST 24
Finished Feb 21 03:16:34 PM PST 24
Peak memory 533448 kb
Host smart-97218169-033c-4918-988f-8781748b4b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84005082 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_acq.84005082
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3364671707
Short name T359
Test name
Test status
Simulation time 10089980933 ps
CPU time 47.98 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:16:32 PM PST 24
Peak memory 495948 kb
Host smart-574e2169-5ddc-4ffc-a762-de1237ad91a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364671707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3364671707
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1217546755
Short name T926
Test name
Test status
Simulation time 2291262087 ps
CPU time 2.23 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 203448 kb
Host smart-3cae402c-4858-4907-9c17-e4e95b550e18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217546755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1217546755
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1311393717
Short name T1174
Test name
Test status
Simulation time 3658090639 ps
CPU time 3.82 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 203448 kb
Host smart-ca26b1c3-1f4c-4ddb-af57-3dad084c30b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311393717 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1311393717
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2593862570
Short name T1404
Test name
Test status
Simulation time 18501762630 ps
CPU time 99.2 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:17:26 PM PST 24
Peak memory 1153184 kb
Host smart-4277b818-5a68-436d-8d2f-d52fcc2d95cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593862570 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2593862570
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.13392279
Short name T559
Test name
Test status
Simulation time 822476334 ps
CPU time 4.73 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 203416 kb
Host smart-842b8bce-5c03-45c1-8528-efaf16b03968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13392279 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.i2c_target_perf.13392279
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1816358407
Short name T421
Test name
Test status
Simulation time 4991956865 ps
CPU time 35.79 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:16:20 PM PST 24
Peak memory 203416 kb
Host smart-a8488a24-ed6c-4dfc-8fdf-4c95c052c834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816358407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1816358407
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.3039480692
Short name T1269
Test name
Test status
Simulation time 14055475846 ps
CPU time 30.94 seconds
Started Feb 21 03:15:42 PM PST 24
Finished Feb 21 03:16:15 PM PST 24
Peak memory 273816 kb
Host smart-f2657cc4-781a-451f-b501-7e3fe6802d00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039480692 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.3039480692
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1833262957
Short name T941
Test name
Test status
Simulation time 9553314841 ps
CPU time 28.33 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:16:12 PM PST 24
Peak memory 203456 kb
Host smart-ee54c9f2-457b-43f6-8e3e-7f750274adf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833262957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1833262957
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1732349098
Short name T703
Test name
Test status
Simulation time 48644200011 ps
CPU time 360.65 seconds
Started Feb 21 03:15:38 PM PST 24
Finished Feb 21 03:21:40 PM PST 24
Peak memory 3136140 kb
Host smart-80d1f2b1-254a-4f2d-bda1-e38effb895f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732349098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1732349098
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.269610544
Short name T742
Test name
Test status
Simulation time 50282735766 ps
CPU time 1278.43 seconds
Started Feb 21 03:15:58 PM PST 24
Finished Feb 21 03:37:17 PM PST 24
Peak memory 2514116 kb
Host smart-e439d13d-4efe-4a80-8fdd-1f6687431966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269610544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.269610544
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2690208145
Short name T884
Test name
Test status
Simulation time 4785727855 ps
CPU time 5.94 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:15:57 PM PST 24
Peak memory 207220 kb
Host smart-d9a450ff-6e98-44d3-b5f8-af6f5763f3ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690208145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2690208145
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_ovf.3716477012
Short name T846
Test name
Test status
Simulation time 5953843278 ps
CPU time 72.62 seconds
Started Feb 21 03:15:47 PM PST 24
Finished Feb 21 03:17:01 PM PST 24
Peak memory 286312 kb
Host smart-88d9f272-6cea-436d-b723-b22a83da081e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716477012 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_tx_ovf.3716477012
Directory /workspace/21.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.857112132
Short name T1067
Test name
Test status
Simulation time 7418210534 ps
CPU time 4.34 seconds
Started Feb 21 03:15:40 PM PST 24
Finished Feb 21 03:15:46 PM PST 24
Peak memory 203700 kb
Host smart-feb847f1-4c70-43e1-8919-ccc4ead548b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857112132 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_unexp_stop.857112132
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1319172632
Short name T90
Test name
Test status
Simulation time 26280130 ps
CPU time 0.63 seconds
Started Feb 21 03:15:48 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 202108 kb
Host smart-1eb84635-3be7-4aea-94dc-554b4dc8a8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319172632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1319172632
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1268154274
Short name T505
Test name
Test status
Simulation time 129566710 ps
CPU time 1.28 seconds
Started Feb 21 03:15:54 PM PST 24
Finished Feb 21 03:15:56 PM PST 24
Peak memory 219476 kb
Host smart-17041865-0d07-4d48-a2fe-6bda252bde92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268154274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1268154274
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.824756763
Short name T1428
Test name
Test status
Simulation time 1146955772 ps
CPU time 13.97 seconds
Started Feb 21 03:15:46 PM PST 24
Finished Feb 21 03:16:01 PM PST 24
Peak memory 242076 kb
Host smart-fe5ff670-2b76-400d-8e5b-1d2d5e7b81e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824756763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.824756763
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2122473409
Short name T954
Test name
Test status
Simulation time 6459506558 ps
CPU time 274.96 seconds
Started Feb 21 03:15:56 PM PST 24
Finished Feb 21 03:20:31 PM PST 24
Peak memory 974780 kb
Host smart-f749e9d3-3b2d-4638-beb7-8991ccced9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122473409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2122473409
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2879203276
Short name T371
Test name
Test status
Simulation time 6567751343 ps
CPU time 580.62 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:25:25 PM PST 24
Peak memory 1835172 kb
Host smart-71445002-2cd6-43ce-97de-654baffb2c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879203276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2879203276
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.688381785
Short name T1205
Test name
Test status
Simulation time 258227122 ps
CPU time 1.05 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 203288 kb
Host smart-69591074-7ac3-4d92-bc80-e36ace455532
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688381785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.688381785
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3287229268
Short name T1012
Test name
Test status
Simulation time 703069690 ps
CPU time 15.97 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:16:03 PM PST 24
Peak memory 259548 kb
Host smart-d3e45161-cba5-46ea-96d2-4fc64d0c7751
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287229268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3287229268
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3186556675
Short name T193
Test name
Test status
Simulation time 3506522939 ps
CPU time 64.86 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:16:50 PM PST 24
Peak memory 296304 kb
Host smart-304d3762-194c-4efc-a8e6-d8542c1c91a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186556675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3186556675
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2545865235
Short name T554
Test name
Test status
Simulation time 14610578 ps
CPU time 0.62 seconds
Started Feb 21 03:15:41 PM PST 24
Finished Feb 21 03:15:44 PM PST 24
Peak memory 202320 kb
Host smart-fc3087de-93a7-40ae-b016-4fb4f1458353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545865235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2545865235
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2428724106
Short name T1179
Test name
Test status
Simulation time 8078021562 ps
CPU time 55.13 seconds
Started Feb 21 03:15:54 PM PST 24
Finished Feb 21 03:16:50 PM PST 24
Peak memory 218928 kb
Host smart-dd00f36a-97fd-4810-9b81-fbe2f5810f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428724106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2428724106
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3007102676
Short name T313
Test name
Test status
Simulation time 3634318487 ps
CPU time 97.43 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:17:29 PM PST 24
Peak memory 235996 kb
Host smart-94dece93-89e8-45cd-9efb-b8fa8ccdca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007102676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3007102676
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.2505391024
Short name T1082
Test name
Test status
Simulation time 20730534919 ps
CPU time 1765.14 seconds
Started Feb 21 03:15:48 PM PST 24
Finished Feb 21 03:45:15 PM PST 24
Peak memory 2556988 kb
Host smart-050b7c7d-01c7-464c-9c2c-9e1dcf7d30e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505391024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2505391024
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2641932118
Short name T1272
Test name
Test status
Simulation time 6600567452 ps
CPU time 15.64 seconds
Started Feb 21 03:15:49 PM PST 24
Finished Feb 21 03:16:05 PM PST 24
Peak memory 211624 kb
Host smart-9aa6a738-c336-47c5-8e7c-4a7d972a9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641932118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2641932118
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3687420967
Short name T1326
Test name
Test status
Simulation time 730493516 ps
CPU time 3.48 seconds
Started Feb 21 03:15:49 PM PST 24
Finished Feb 21 03:15:53 PM PST 24
Peak memory 203328 kb
Host smart-d497ce8f-5522-4088-a35e-fb909d041038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687420967 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3687420967
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.20379782
Short name T814
Test name
Test status
Simulation time 10285940239 ps
CPU time 23.53 seconds
Started Feb 21 03:15:48 PM PST 24
Finished Feb 21 03:16:12 PM PST 24
Peak memory 325268 kb
Host smart-d84902f6-21d7-46f5-bfd0-100b75879109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20379782 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_acq.20379782
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.765482189
Short name T205
Test name
Test status
Simulation time 10039207522 ps
CPU time 69.01 seconds
Started Feb 21 03:15:49 PM PST 24
Finished Feb 21 03:16:59 PM PST 24
Peak memory 613020 kb
Host smart-dc7042a8-a4b7-4591-b069-148f3efdd0b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765482189 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.765482189
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.1021060441
Short name T1282
Test name
Test status
Simulation time 9872762816 ps
CPU time 2.49 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 203428 kb
Host smart-e9010ad4-c955-436c-8e35-fe2e25d43fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021060441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.1021060441
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.447343257
Short name T692
Test name
Test status
Simulation time 1606060655 ps
CPU time 6.93 seconds
Started Feb 21 03:15:55 PM PST 24
Finished Feb 21 03:16:03 PM PST 24
Peak memory 206552 kb
Host smart-8482c361-0148-4a92-97a4-4d204d0ac574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447343257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.447343257
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1385674768
Short name T373
Test name
Test status
Simulation time 14685832088 ps
CPU time 414.2 seconds
Started Feb 21 03:15:48 PM PST 24
Finished Feb 21 03:22:43 PM PST 24
Peak memory 3447584 kb
Host smart-4940776d-5a97-4b1e-beb4-693ea5225691
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385674768 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1385674768
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.173156398
Short name T578
Test name
Test status
Simulation time 451312637 ps
CPU time 2.66 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:15:49 PM PST 24
Peak memory 203396 kb
Host smart-550bbda4-4448-4ffb-9038-7821fb3c7f56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173156398 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_perf.173156398
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3032892075
Short name T1042
Test name
Test status
Simulation time 32929726497 ps
CPU time 46.24 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:16:33 PM PST 24
Peak memory 203468 kb
Host smart-17829bcd-74d9-43d6-a3dd-a9100c9bb519
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032892075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3032892075
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.3223482967
Short name T635
Test name
Test status
Simulation time 29401005477 ps
CPU time 83.13 seconds
Started Feb 21 03:15:50 PM PST 24
Finished Feb 21 03:17:14 PM PST 24
Peak memory 846120 kb
Host smart-2da713c3-9b55-41f3-a0c8-9641bccfd228
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223482967 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.3223482967
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3918751065
Short name T1218
Test name
Test status
Simulation time 1882787545 ps
CPU time 13.54 seconds
Started Feb 21 03:15:46 PM PST 24
Finished Feb 21 03:16:01 PM PST 24
Peak memory 210032 kb
Host smart-0d4a7811-06cc-4b0b-b497-b1e2894c6283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918751065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3918751065
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.442914081
Short name T311
Test name
Test status
Simulation time 38378364843 ps
CPU time 648.28 seconds
Started Feb 21 03:15:46 PM PST 24
Finished Feb 21 03:26:36 PM PST 24
Peak memory 4393276 kb
Host smart-ddae30d7-023c-4d2a-b6be-55b4d7902fd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442914081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.442914081
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2327808370
Short name T880
Test name
Test status
Simulation time 10350805650 ps
CPU time 29.37 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:16:17 PM PST 24
Peak memory 519696 kb
Host smart-6ff4bbd2-ec45-4db5-82a4-1facc0ac2e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327808370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2327808370
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.461947223
Short name T1255
Test name
Test status
Simulation time 2388008230 ps
CPU time 8.65 seconds
Started Feb 21 03:15:44 PM PST 24
Finished Feb 21 03:15:55 PM PST 24
Peak memory 210524 kb
Host smart-b9b30cde-05f3-4f8b-a8f9-6baa17afa8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461947223 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.461947223
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_ovf.365017899
Short name T435
Test name
Test status
Simulation time 3317279159 ps
CPU time 147.41 seconds
Started Feb 21 03:15:43 PM PST 24
Finished Feb 21 03:18:14 PM PST 24
Peak memory 396676 kb
Host smart-03a83ed0-eead-479d-a4fd-208acd3eecf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365017899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_tx_ovf.365017899
Directory /workspace/22.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.1039610601
Short name T394
Test name
Test status
Simulation time 8256801583 ps
CPU time 8.11 seconds
Started Feb 21 03:15:49 PM PST 24
Finished Feb 21 03:15:58 PM PST 24
Peak memory 208044 kb
Host smart-bb412926-6409-4dce-9cbf-80064fc31180
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039610601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_target_unexp_stop.1039610601
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1880612979
Short name T399
Test name
Test status
Simulation time 32143146 ps
CPU time 0.59 seconds
Started Feb 21 03:16:08 PM PST 24
Finished Feb 21 03:16:10 PM PST 24
Peak memory 202112 kb
Host smart-4e066d0f-903d-42df-8a42-15b458dcfb9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880612979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1880612979
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.253714737
Short name T619
Test name
Test status
Simulation time 90774926 ps
CPU time 1.92 seconds
Started Feb 21 03:15:53 PM PST 24
Finished Feb 21 03:15:56 PM PST 24
Peak memory 213584 kb
Host smart-fcb20f88-972c-4e32-86df-42d626b9b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253714737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.253714737
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.580612186
Short name T745
Test name
Test status
Simulation time 446574336 ps
CPU time 24.86 seconds
Started Feb 21 03:15:58 PM PST 24
Finished Feb 21 03:16:23 PM PST 24
Peak memory 303792 kb
Host smart-0f853f35-6795-40dd-9849-c50870539f3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580612186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.580612186
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.921123285
Short name T1040
Test name
Test status
Simulation time 3115309829 ps
CPU time 84.76 seconds
Started Feb 21 03:15:55 PM PST 24
Finished Feb 21 03:17:21 PM PST 24
Peak memory 746224 kb
Host smart-e85eecb2-b0d1-4dca-906d-e55d8041ceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921123285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.921123285
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2295289894
Short name T1472
Test name
Test status
Simulation time 28212288965 ps
CPU time 895.22 seconds
Started Feb 21 03:15:53 PM PST 24
Finished Feb 21 03:30:48 PM PST 24
Peak memory 1665012 kb
Host smart-c9dea0bc-4737-4ae8-8f3d-09ebc8acd971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295289894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2295289894
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.840104475
Short name T1389
Test name
Test status
Simulation time 66025043 ps
CPU time 0.75 seconds
Started Feb 21 03:15:53 PM PST 24
Finished Feb 21 03:15:55 PM PST 24
Peak memory 203020 kb
Host smart-c3e43294-e256-4f58-8b91-ac6bc49d8296
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840104475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fm
t.840104475
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3173779160
Short name T1385
Test name
Test status
Simulation time 276931679 ps
CPU time 4.41 seconds
Started Feb 21 03:15:58 PM PST 24
Finished Feb 21 03:16:03 PM PST 24
Peak memory 226032 kb
Host smart-98151deb-3dd6-423c-9147-3d489dd61300
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173779160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3173779160
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.528124598
Short name T139
Test name
Test status
Simulation time 4731995641 ps
CPU time 224.94 seconds
Started Feb 21 03:15:58 PM PST 24
Finished Feb 21 03:19:43 PM PST 24
Peak memory 1349100 kb
Host smart-faac2333-9f9d-407f-9fea-e52ca32b0e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528124598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.528124598
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1428291676
Short name T1073
Test name
Test status
Simulation time 13171107501 ps
CPU time 75.04 seconds
Started Feb 21 03:16:16 PM PST 24
Finished Feb 21 03:17:32 PM PST 24
Peak memory 333884 kb
Host smart-db18837b-4f30-4cb7-bbbd-0e55940e671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428291676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1428291676
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.1655189035
Short name T1507
Test name
Test status
Simulation time 40873412 ps
CPU time 0.63 seconds
Started Feb 21 03:15:45 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 202236 kb
Host smart-6a86c38d-117e-4953-9f53-4830bfe1fb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655189035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1655189035
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.130847103
Short name T1364
Test name
Test status
Simulation time 26214080548 ps
CPU time 103.04 seconds
Started Feb 21 03:15:55 PM PST 24
Finished Feb 21 03:17:39 PM PST 24
Peak memory 269020 kb
Host smart-bdfbeb18-47f3-4071-959d-ad042364c0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130847103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.130847103
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_rx_oversample.2400945587
Short name T744
Test name
Test status
Simulation time 3604035368 ps
CPU time 195.56 seconds
Started Feb 21 03:15:57 PM PST 24
Finished Feb 21 03:19:13 PM PST 24
Peak memory 300768 kb
Host smart-07a35e66-2424-4f5f-bc82-7406fc8234e1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400945587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_rx_oversample
.2400945587
Directory /workspace/23.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3048895123
Short name T1316
Test name
Test status
Simulation time 1633246469 ps
CPU time 35.91 seconds
Started Feb 21 03:15:54 PM PST 24
Finished Feb 21 03:16:30 PM PST 24
Peak memory 282212 kb
Host smart-7b6b3929-df91-4eb3-9ee3-481d3542be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048895123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3048895123
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1444341670
Short name T773
Test name
Test status
Simulation time 27119026321 ps
CPU time 743.43 seconds
Started Feb 21 03:15:59 PM PST 24
Finished Feb 21 03:28:23 PM PST 24
Peak memory 1276896 kb
Host smart-8ee7be29-c75b-437b-80be-02335bbf907c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444341670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1444341670
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1470352096
Short name T861
Test name
Test status
Simulation time 6022307851 ps
CPU time 17.76 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:16:09 PM PST 24
Peak memory 229868 kb
Host smart-8ab0ab97-f924-4a9f-a006-aa8338f53410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470352096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1470352096
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1745218206
Short name T448
Test name
Test status
Simulation time 5010813835 ps
CPU time 5.17 seconds
Started Feb 21 03:16:18 PM PST 24
Finished Feb 21 03:16:24 PM PST 24
Peak memory 203480 kb
Host smart-90288bc9-8f17-4f1f-a3b3-9b1550836728
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745218206 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1745218206
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.4264281317
Short name T1310
Test name
Test status
Simulation time 10281768286 ps
CPU time 20.59 seconds
Started Feb 21 03:16:18 PM PST 24
Finished Feb 21 03:16:39 PM PST 24
Peak memory 320492 kb
Host smart-5d77e6db-6cb5-4349-8530-685681293b81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264281317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.4264281317
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.929465093
Short name T400
Test name
Test status
Simulation time 10171874118 ps
CPU time 14.45 seconds
Started Feb 21 03:16:10 PM PST 24
Finished Feb 21 03:16:25 PM PST 24
Peak memory 304104 kb
Host smart-56af7e2c-305c-4993-b31f-67b95abe2cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929465093 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.929465093
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1024634292
Short name T1357
Test name
Test status
Simulation time 455308713 ps
CPU time 2.59 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:16:23 PM PST 24
Peak memory 203360 kb
Host smart-222abe09-7942-4a37-b74b-b9efd5f67a84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024634292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1024634292
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.237526739
Short name T498
Test name
Test status
Simulation time 10785394402 ps
CPU time 3.78 seconds
Started Feb 21 03:15:55 PM PST 24
Finished Feb 21 03:15:59 PM PST 24
Peak memory 203488 kb
Host smart-3ed189df-f309-4bcc-b6c5-183dbd84c40c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237526739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.237526739
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2297666423
Short name T1064
Test name
Test status
Simulation time 2441376453 ps
CPU time 10.1 seconds
Started Feb 21 03:15:52 PM PST 24
Finished Feb 21 03:16:03 PM PST 24
Peak memory 398100 kb
Host smart-a14dcd21-086f-4723-82c5-5c9f925adf84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297666423 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2297666423
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.2391188020
Short name T425
Test name
Test status
Simulation time 2015631531 ps
CPU time 3.53 seconds
Started Feb 21 03:16:25 PM PST 24
Finished Feb 21 03:16:29 PM PST 24
Peak memory 203396 kb
Host smart-f941fc69-4f69-4f1a-b4c2-352be7f153db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391188020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.2391188020
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1330077529
Short name T549
Test name
Test status
Simulation time 4328176145 ps
CPU time 31.26 seconds
Started Feb 21 03:15:53 PM PST 24
Finished Feb 21 03:16:25 PM PST 24
Peak memory 203476 kb
Host smart-ef55ea8f-ce75-4659-a733-df5c10d8cdf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330077529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1330077529
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2859146897
Short name T112
Test name
Test status
Simulation time 621942961 ps
CPU time 9.18 seconds
Started Feb 21 03:15:51 PM PST 24
Finished Feb 21 03:16:01 PM PST 24
Peak memory 203348 kb
Host smart-2b1afb5b-9278-48a4-b767-ccaad9980f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859146897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2859146897
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3934673213
Short name T966
Test name
Test status
Simulation time 34793415780 ps
CPU time 1397.79 seconds
Started Feb 21 03:15:53 PM PST 24
Finished Feb 21 03:39:11 PM PST 24
Peak memory 7437908 kb
Host smart-8f7bc494-9a47-49f5-9b28-2a494f8556b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934673213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3934673213
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2571439085
Short name T1460
Test name
Test status
Simulation time 2230975399 ps
CPU time 8.4 seconds
Started Feb 21 03:15:52 PM PST 24
Finished Feb 21 03:16:01 PM PST 24
Peak memory 206672 kb
Host smart-928a294a-d3ab-44ab-9131-bb0eb952cd53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571439085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2571439085
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_ovf.2658562151
Short name T413
Test name
Test status
Simulation time 6936053754 ps
CPU time 125.1 seconds
Started Feb 21 03:15:55 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 354800 kb
Host smart-252f23c1-09b0-473d-ad34-49b9e59df60b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658562151 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_tx_ovf.2658562151
Directory /workspace/23.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.3606668854
Short name T758
Test name
Test status
Simulation time 2424445487 ps
CPU time 5.48 seconds
Started Feb 21 03:15:54 PM PST 24
Finished Feb 21 03:16:00 PM PST 24
Peak memory 203408 kb
Host smart-16ba4131-06c8-46a5-9622-fa45ff3a3a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606668854 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.3606668854
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1124642615
Short name T364
Test name
Test status
Simulation time 33544443 ps
CPU time 0.61 seconds
Started Feb 21 03:16:17 PM PST 24
Finished Feb 21 03:16:18 PM PST 24
Peak memory 202052 kb
Host smart-cb46af3a-d08a-4634-8a8c-70bf87b2d55e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124642615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1124642615
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.226941271
Short name T1128
Test name
Test status
Simulation time 205841966 ps
CPU time 1.17 seconds
Started Feb 21 03:16:18 PM PST 24
Finished Feb 21 03:16:20 PM PST 24
Peak memory 212948 kb
Host smart-6eb7c392-2498-4e3b-8088-54698032d17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226941271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.226941271
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2587908392
Short name T444
Test name
Test status
Simulation time 424194163 ps
CPU time 8.53 seconds
Started Feb 21 03:16:25 PM PST 24
Finished Feb 21 03:16:34 PM PST 24
Peak memory 297476 kb
Host smart-51da3f83-1496-4ab9-9a1f-8bd4823ddfac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587908392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2587908392
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.4083747321
Short name T684
Test name
Test status
Simulation time 7032418592 ps
CPU time 33.86 seconds
Started Feb 21 03:16:17 PM PST 24
Finished Feb 21 03:16:51 PM PST 24
Peak memory 219152 kb
Host smart-c328921b-3f74-45cf-bcd9-8f8de23083b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083747321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.4083747321
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.119968005
Short name T1393
Test name
Test status
Simulation time 3473089153 ps
CPU time 146.26 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:18:47 PM PST 24
Peak memory 982752 kb
Host smart-9de4280a-4a6f-4afc-9967-f8f744d03a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119968005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.119968005
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1830935350
Short name T1339
Test name
Test status
Simulation time 106144723 ps
CPU time 0.82 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:16:22 PM PST 24
Peak memory 203100 kb
Host smart-efa1984a-7bda-4ca1-b66f-8a0d3fb338da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830935350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1830935350
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1624963256
Short name T874
Test name
Test status
Simulation time 553407515 ps
CPU time 6.02 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:16:28 PM PST 24
Peak memory 203264 kb
Host smart-0552dc00-2c2c-4470-95b1-dd02463e01a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624963256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1624963256
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1180900891
Short name T235
Test name
Test status
Simulation time 16301135294 ps
CPU time 191.48 seconds
Started Feb 21 03:16:24 PM PST 24
Finished Feb 21 03:19:36 PM PST 24
Peak memory 1141084 kb
Host smart-2ee2ff93-e130-40a2-993a-0d71bd8a65ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180900891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1180900891
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2745830736
Short name T27
Test name
Test status
Simulation time 32623638251 ps
CPU time 103.47 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 03:18:07 PM PST 24
Peak memory 249476 kb
Host smart-17f5fb03-80c5-4335-a70d-c0b4647596e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745830736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2745830736
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1006568087
Short name T462
Test name
Test status
Simulation time 55994443 ps
CPU time 0.64 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:16:22 PM PST 24
Peak memory 202352 kb
Host smart-21db2c1e-840a-4ae9-881d-b77b32395455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006568087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1006568087
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2590536097
Short name T321
Test name
Test status
Simulation time 14506423742 ps
CPU time 68.12 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 03:17:31 PM PST 24
Peak memory 203408 kb
Host smart-c3a7d339-0171-4849-845c-ac5e46a25040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590536097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2590536097
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_rx_oversample.710815902
Short name T1342
Test name
Test status
Simulation time 26916777087 ps
CPU time 238.68 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:20:19 PM PST 24
Peak memory 293444 kb
Host smart-e41c57a4-62a5-46a9-ae23-f2f2dabd4fdd
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710815902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_rx_oversample.
710815902
Directory /workspace/24.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3506867193
Short name T1007
Test name
Test status
Simulation time 8831015333 ps
CPU time 130.71 seconds
Started Feb 21 03:16:18 PM PST 24
Finished Feb 21 03:18:29 PM PST 24
Peak memory 266140 kb
Host smart-7bca693a-072d-4b27-b594-12497be402a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506867193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3506867193
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.1452499992
Short name T228
Test name
Test status
Simulation time 31638362147 ps
CPU time 1759.75 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:45:54 PM PST 24
Peak memory 3252488 kb
Host smart-70a5cf25-aadb-45b1-827a-64dba2c2d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452499992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1452499992
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.300797503
Short name T497
Test name
Test status
Simulation time 1035841053 ps
CPU time 47.51 seconds
Started Feb 21 03:16:24 PM PST 24
Finished Feb 21 03:17:12 PM PST 24
Peak memory 211512 kb
Host smart-5b54ed70-85c7-42da-8f7d-2a9dc635cf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300797503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.300797503
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4035518854
Short name T599
Test name
Test status
Simulation time 782877133 ps
CPU time 3.38 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:16:39 PM PST 24
Peak memory 203372 kb
Host smart-f22be984-6828-4952-bdfa-8a75c70e9d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035518854 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4035518854
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1064727705
Short name T760
Test name
Test status
Simulation time 10733058315 ps
CPU time 12.56 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:16:33 PM PST 24
Peak memory 276436 kb
Host smart-ee85fbcf-5a1d-4ec3-83b0-7ce0baf46757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064727705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1064727705
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2472456193
Short name T939
Test name
Test status
Simulation time 10177243634 ps
CPU time 8.02 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:16:29 PM PST 24
Peak memory 249020 kb
Host smart-a4687973-8e2e-465d-8188-b50ed76b2f02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472456193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2472456193
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.772992110
Short name T1010
Test name
Test status
Simulation time 1895539282 ps
CPU time 2.37 seconds
Started Feb 21 03:16:19 PM PST 24
Finished Feb 21 03:16:22 PM PST 24
Peak memory 203304 kb
Host smart-e77ccefa-9fd3-4a66-b274-c2c834415875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772992110 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.772992110
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3632914803
Short name T110
Test name
Test status
Simulation time 2436496503 ps
CPU time 4.89 seconds
Started Feb 21 03:16:22 PM PST 24
Finished Feb 21 03:16:27 PM PST 24
Peak memory 203476 kb
Host smart-fe6d7194-fb1e-43c6-9eac-8a0409aec549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632914803 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3632914803
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1638601908
Short name T1121
Test name
Test status
Simulation time 17864555118 ps
CPU time 647.79 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:27:08 PM PST 24
Peak memory 3969212 kb
Host smart-3d02ffbf-6289-4ab7-be87-9ff4a7ab123f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638601908 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1638601908
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.2471316786
Short name T478
Test name
Test status
Simulation time 1635333709 ps
CPU time 4.44 seconds
Started Feb 21 03:16:24 PM PST 24
Finished Feb 21 03:16:29 PM PST 24
Peak memory 203352 kb
Host smart-bd128d95-2da8-4df4-8ede-f552e6bd9e56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471316786 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_perf.2471316786
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1812352379
Short name T1361
Test name
Test status
Simulation time 2017098164 ps
CPU time 14.68 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:16:56 PM PST 24
Peak memory 203440 kb
Host smart-2d9d8e87-6182-4945-a67a-0096e0d92c47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812352379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1812352379
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.611648937
Short name T845
Test name
Test status
Simulation time 3505634340 ps
CPU time 29.84 seconds
Started Feb 21 03:16:22 PM PST 24
Finished Feb 21 03:16:52 PM PST 24
Peak memory 226888 kb
Host smart-7385d2d7-e2ee-458e-a2bc-ea213a01fe01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611648937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.611648937
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1112843672
Short name T971
Test name
Test status
Simulation time 16364585044 ps
CPU time 36.86 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:16:57 PM PST 24
Peak memory 835420 kb
Host smart-7cef3dcf-8108-4e86-b665-08325906be34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112843672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1112843672
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.922542328
Short name T527
Test name
Test status
Simulation time 21000515199 ps
CPU time 310.27 seconds
Started Feb 21 03:16:24 PM PST 24
Finished Feb 21 03:21:35 PM PST 24
Peak memory 1163276 kb
Host smart-4f6db894-0616-4774-bccf-97006fd3455b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922542328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.922542328
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1925512190
Short name T713
Test name
Test status
Simulation time 5985635568 ps
CPU time 6.45 seconds
Started Feb 21 03:16:25 PM PST 24
Finished Feb 21 03:16:32 PM PST 24
Peak memory 205220 kb
Host smart-623bd1b2-570b-4c26-bd65-b0b1c9270275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925512190 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1925512190
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_ovf.795642281
Short name T1296
Test name
Test status
Simulation time 2900528622 ps
CPU time 49.87 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:17:25 PM PST 24
Peak memory 219328 kb
Host smart-41cafc02-240e-4463-9354-519ce638cd75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795642281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_tx_ovf.795642281
Directory /workspace/24.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.1762471991
Short name T1493
Test name
Test status
Simulation time 3364088596 ps
CPU time 7.63 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:16:29 PM PST 24
Peak memory 210428 kb
Host smart-affb0bfe-4fa3-4459-8d42-25cd639755bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762471991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.i2c_target_unexp_stop.1762471991
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2996598696
Short name T335
Test name
Test status
Simulation time 17308780 ps
CPU time 0.61 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:39 PM PST 24
Peak memory 202104 kb
Host smart-3030f7c9-f3ef-41b7-8a4c-96fdd377c760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996598696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2996598696
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3785173291
Short name T441
Test name
Test status
Simulation time 89023640 ps
CPU time 2.02 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 03:16:26 PM PST 24
Peak memory 213380 kb
Host smart-9add26e3-1248-4fe9-a8ae-9d66c6deb23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785173291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3785173291
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.220124144
Short name T9
Test name
Test status
Simulation time 1069809548 ps
CPU time 4.65 seconds
Started Feb 21 03:16:19 PM PST 24
Finished Feb 21 03:16:24 PM PST 24
Peak memory 246660 kb
Host smart-9ccc16c4-8833-45d2-aa8e-1a0162ab716a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220124144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.220124144
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3291094501
Short name T674
Test name
Test status
Simulation time 5426827842 ps
CPU time 213.32 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:19:54 PM PST 24
Peak memory 821988 kb
Host smart-5846f2af-dfe4-431d-8ffb-8d5fe812bfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291094501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3291094501
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2895775871
Short name T853
Test name
Test status
Simulation time 15363424752 ps
CPU time 180.67 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 03:19:24 PM PST 24
Peak memory 1125020 kb
Host smart-6867958b-b1b4-40d5-8aa7-039da200d750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895775871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2895775871
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2417943339
Short name T1074
Test name
Test status
Simulation time 120475161 ps
CPU time 0.95 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:16:35 PM PST 24
Peak memory 203036 kb
Host smart-fdb94066-569b-48f8-8827-82e33291abf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417943339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2417943339
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2087027994
Short name T192
Test name
Test status
Simulation time 190515487 ps
CPU time 5.84 seconds
Started Feb 21 03:16:33 PM PST 24
Finished Feb 21 03:16:39 PM PST 24
Peak memory 238272 kb
Host smart-5b363ca9-cff4-4eaa-8af5-a96a55ff3303
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087027994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2087027994
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1144898375
Short name T509
Test name
Test status
Simulation time 21549125043 ps
CPU time 556.86 seconds
Started Feb 21 03:16:22 PM PST 24
Finished Feb 21 03:25:39 PM PST 24
Peak memory 1474740 kb
Host smart-48a642ae-82ae-41ab-837d-39da22776597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144898375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1144898375
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2564933360
Short name T28
Test name
Test status
Simulation time 2580080525 ps
CPU time 141.92 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:18:59 PM PST 24
Peak memory 252980 kb
Host smart-516cb2b1-c15b-46b9-8133-2611964b260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564933360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2564933360
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2329614236
Short name T391
Test name
Test status
Simulation time 50700178 ps
CPU time 0.62 seconds
Started Feb 21 03:16:20 PM PST 24
Finished Feb 21 03:16:21 PM PST 24
Peak memory 202268 kb
Host smart-6f268b55-0a2c-4fed-a5aa-40b6fbe7475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329614236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2329614236
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2373771504
Short name T525
Test name
Test status
Simulation time 1201227920 ps
CPU time 11.4 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:16:33 PM PST 24
Peak memory 211472 kb
Host smart-86c76708-b896-4813-97b1-8540455b91e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373771504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2373771504
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_rx_oversample.3596903546
Short name T1477
Test name
Test status
Simulation time 3486807145 ps
CPU time 282.93 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:21:22 PM PST 24
Peak memory 423808 kb
Host smart-dc4de959-a42a-4958-a36e-0327aedbd1e9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596903546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_rx_oversample
.3596903546
Directory /workspace/25.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3008826937
Short name T467
Test name
Test status
Simulation time 8146298555 ps
CPU time 68.61 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 03:17:32 PM PST 24
Peak memory 301688 kb
Host smart-4a7d6e59-fa5a-49b0-9bc4-51b319827632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008826937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3008826937
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.3470460897
Short name T229
Test name
Test status
Simulation time 37851676870 ps
CPU time 3473.79 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 04:14:17 PM PST 24
Peak memory 3437128 kb
Host smart-c0bb34c2-419d-4d68-8538-af2d30d8b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470460897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.3470460897
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2771384542
Short name T1076
Test name
Test status
Simulation time 967297825 ps
CPU time 43.53 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:17:05 PM PST 24
Peak memory 219684 kb
Host smart-42cc5098-3557-41b1-8093-6f69cfa79092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771384542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2771384542
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.736138947
Short name T541
Test name
Test status
Simulation time 4825696992 ps
CPU time 5.1 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:43 PM PST 24
Peak memory 203448 kb
Host smart-e0336ae1-b2bf-4d06-9cc4-8073eb6449f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736138947 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.736138947
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.861766515
Short name T1137
Test name
Test status
Simulation time 10097957596 ps
CPU time 35.54 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:17:10 PM PST 24
Peak memory 376380 kb
Host smart-a080172b-e241-428f-afd7-07c706d7a88d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861766515 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.861766515
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3862306122
Short name T1009
Test name
Test status
Simulation time 10180849608 ps
CPU time 35.45 seconds
Started Feb 21 03:16:27 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 433868 kb
Host smart-ae3429f0-384b-4f4a-ab2d-18cf93a5cfe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862306122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3862306122
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.1318548322
Short name T212
Test name
Test status
Simulation time 7135947377 ps
CPU time 2.53 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:41 PM PST 24
Peak memory 203396 kb
Host smart-d020f622-9115-4ae6-aa1a-4d77576bb9a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318548322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.1318548322
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3047532749
Short name T1365
Test name
Test status
Simulation time 7515653513 ps
CPU time 6.52 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:45 PM PST 24
Peak memory 203844 kb
Host smart-2d93d6ef-b9e1-4499-a3ad-1b5f48ea11b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047532749 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3047532749
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1071598334
Short name T683
Test name
Test status
Simulation time 4000182803 ps
CPU time 25.75 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:17:01 PM PST 24
Peak memory 733944 kb
Host smart-9a8acafe-da17-4462-be25-2ef8befd1984
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071598334 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1071598334
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.3084435023
Short name T252
Test name
Test status
Simulation time 1139244551 ps
CPU time 3.42 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:16:38 PM PST 24
Peak memory 203380 kb
Host smart-aa21cad1-f96c-4f33-873b-def44cba1f98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084435023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_perf.3084435023
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1584242545
Short name T868
Test name
Test status
Simulation time 1002425183 ps
CPU time 12.67 seconds
Started Feb 21 03:16:22 PM PST 24
Finished Feb 21 03:16:35 PM PST 24
Peak memory 203332 kb
Host smart-751bebf6-649e-4f61-9dd3-9c6e9b301d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584242545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1584242545
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.991570526
Short name T1131
Test name
Test status
Simulation time 54483127750 ps
CPU time 3284.14 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 04:11:19 PM PST 24
Peak memory 9076232 kb
Host smart-1e0d808b-d0ae-434e-b105-762b7e4eaaa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991570526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.i2c_target_stress_all.991570526
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.818081326
Short name T414
Test name
Test status
Simulation time 6927141016 ps
CPU time 70.16 seconds
Started Feb 21 03:16:21 PM PST 24
Finished Feb 21 03:17:31 PM PST 24
Peak memory 205188 kb
Host smart-ae37d167-5118-4445-8ce4-ce62eba2c4aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818081326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.818081326
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1768325566
Short name T1178
Test name
Test status
Simulation time 14296042374 ps
CPU time 197.52 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:19:53 PM PST 24
Peak memory 854188 kb
Host smart-b7ad81f8-4515-4572-8e79-179f269a2b36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768325566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1768325566
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.350331991
Short name T319
Test name
Test status
Simulation time 1874004780 ps
CPU time 8.02 seconds
Started Feb 21 03:16:25 PM PST 24
Finished Feb 21 03:16:33 PM PST 24
Peak memory 203556 kb
Host smart-708acde5-26e6-47bb-aa93-ce00ac2070cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350331991 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.350331991
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_ovf.2955474808
Short name T1250
Test name
Test status
Simulation time 14558016681 ps
CPU time 159.34 seconds
Started Feb 21 03:16:31 PM PST 24
Finished Feb 21 03:19:11 PM PST 24
Peak memory 404980 kb
Host smart-0945bb09-4ffb-4c60-8912-09e50814a4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955474808 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_tx_ovf.2955474808
Directory /workspace/25.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.2392942075
Short name T803
Test name
Test status
Simulation time 826612642 ps
CPU time 5.72 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:16:46 PM PST 24
Peak memory 203452 kb
Host smart-61ce246c-31ca-4c44-99d6-97cf65314f7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392942075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.2392942075
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1845908166
Short name T519
Test name
Test status
Simulation time 19582013 ps
CPU time 0.71 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:16:36 PM PST 24
Peak memory 202144 kb
Host smart-6cc5e794-6e26-461e-82e1-76581da84750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845908166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1845908166
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1108285890
Short name T946
Test name
Test status
Simulation time 598072518 ps
CPU time 1.59 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:16:37 PM PST 24
Peak memory 211588 kb
Host smart-9276e295-1211-443b-8093-82af623b5001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108285890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1108285890
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3028550859
Short name T1239
Test name
Test status
Simulation time 2023080984 ps
CPU time 24.71 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 309900 kb
Host smart-a8fd04f7-1715-40b6-b433-c8791bd57f58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028550859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3028550859
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3513562655
Short name T576
Test name
Test status
Simulation time 10784842561 ps
CPU time 90.99 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:18:08 PM PST 24
Peak memory 282480 kb
Host smart-6e369350-d119-4547-8985-38b545cc0821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513562655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3513562655
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3068633656
Short name T927
Test name
Test status
Simulation time 34965038418 ps
CPU time 476.51 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:24:32 PM PST 24
Peak memory 1250848 kb
Host smart-13f2e119-1308-4286-8a94-6a7fcbcc02e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068633656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3068633656
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1588420462
Short name T510
Test name
Test status
Simulation time 81033967 ps
CPU time 1.05 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 03:16:24 PM PST 24
Peak memory 203568 kb
Host smart-d4d85ade-602c-4ceb-a231-efdcde4723e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588420462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1588420462
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2037937739
Short name T1219
Test name
Test status
Simulation time 959984986 ps
CPU time 13.17 seconds
Started Feb 21 03:16:24 PM PST 24
Finished Feb 21 03:16:38 PM PST 24
Peak memory 203256 kb
Host smart-da893edf-1ff9-4981-b983-3e2f8e57b656
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037937739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2037937739
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1534651659
Short name T1372
Test name
Test status
Simulation time 3548254428 ps
CPU time 329.13 seconds
Started Feb 21 03:16:22 PM PST 24
Finished Feb 21 03:21:51 PM PST 24
Peak memory 1069456 kb
Host smart-1f6791ad-66c2-49a3-9301-2fe23835f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534651659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1534651659
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2955604233
Short name T988
Test name
Test status
Simulation time 7657004219 ps
CPU time 63.17 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 322760 kb
Host smart-ff015987-b876-4bc6-bdf5-c59d3f1bef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955604233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2955604233
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.4235403194
Short name T171
Test name
Test status
Simulation time 22422320 ps
CPU time 0.66 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:16:35 PM PST 24
Peak memory 202252 kb
Host smart-5cc2e6e2-2de5-4542-8ae2-b611d16a28d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235403194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4235403194
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3664770728
Short name T381
Test name
Test status
Simulation time 20177217649 ps
CPU time 220.11 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:20:17 PM PST 24
Peak memory 227728 kb
Host smart-aca363db-79e3-442a-b8a7-6a7b88d4023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664770728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3664770728
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_rx_oversample.2395195364
Short name T1089
Test name
Test status
Simulation time 43369398663 ps
CPU time 165.04 seconds
Started Feb 21 03:16:31 PM PST 24
Finished Feb 21 03:19:17 PM PST 24
Peak memory 346460 kb
Host smart-e2df2900-ebbf-4316-ad8b-9b2952091d64
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395195364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_rx_oversample
.2395195364
Directory /workspace/26.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1201347173
Short name T1483
Test name
Test status
Simulation time 2282623686 ps
CPU time 133.76 seconds
Started Feb 21 03:16:23 PM PST 24
Finished Feb 21 03:18:37 PM PST 24
Peak memory 256876 kb
Host smart-6eb028ca-a7ef-44c0-88f6-fbd9e0a94040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201347173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1201347173
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.4185822985
Short name T227
Test name
Test status
Simulation time 7174545252 ps
CPU time 257.6 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:20:53 PM PST 24
Peak memory 418896 kb
Host smart-1e8314b7-7aa7-4ec7-a03e-9c3f4e992cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185822985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.4185822985
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1636264607
Short name T1328
Test name
Test status
Simulation time 4551912986 ps
CPU time 15.87 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:16:54 PM PST 24
Peak memory 216252 kb
Host smart-1caacf87-42d5-452b-bc08-714ef8feef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636264607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1636264607
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3910222074
Short name T273
Test name
Test status
Simulation time 810289088 ps
CPU time 3.55 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:16:40 PM PST 24
Peak memory 203332 kb
Host smart-7ae0641e-09cb-447e-899c-696e72590a00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910222074 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3910222074
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.995446199
Short name T1059
Test name
Test status
Simulation time 10205283320 ps
CPU time 24.34 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 310220 kb
Host smart-1aba7287-de8b-4e86-905b-5a3c5f43a0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995446199 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.995446199
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.886189120
Short name T1371
Test name
Test status
Simulation time 10054460539 ps
CPU time 84.46 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:18:02 PM PST 24
Peak memory 606656 kb
Host smart-24b5837e-c322-47a0-8f7f-65ad69077460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886189120 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.886189120
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1663711322
Short name T1497
Test name
Test status
Simulation time 1184899373 ps
CPU time 5.69 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:16:42 PM PST 24
Peak memory 204968 kb
Host smart-53cbf00b-3353-4a18-9ac4-745b59ba8d40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663711322 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1663711322
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2977909889
Short name T1195
Test name
Test status
Simulation time 20286271990 ps
CPU time 103.54 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:18:20 PM PST 24
Peak memory 1211560 kb
Host smart-d73f8e1e-5570-490c-950b-334f038b95c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977909889 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2977909889
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.876278708
Short name T1280
Test name
Test status
Simulation time 316393128 ps
CPU time 2.32 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:40 PM PST 24
Peak memory 203340 kb
Host smart-f8fc3c11-d7c5-4022-a927-cb6a87226de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876278708 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_perf.876278708
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2702994493
Short name T270
Test name
Test status
Simulation time 1211700308 ps
CPU time 13.16 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:16:48 PM PST 24
Peak memory 203416 kb
Host smart-a6634130-6359-4a40-a581-9d59d0e982e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702994493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2702994493
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.2065129557
Short name T653
Test name
Test status
Simulation time 107028617074 ps
CPU time 917.38 seconds
Started Feb 21 03:16:33 PM PST 24
Finished Feb 21 03:31:51 PM PST 24
Peak memory 1072080 kb
Host smart-b0d61914-c816-40da-83d2-d0e69ce4a53d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065129557 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.2065129557
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3372041332
Short name T254
Test name
Test status
Simulation time 1583810795 ps
CPU time 27.55 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 219600 kb
Host smart-ee90a322-c977-4455-aabc-5e9252c722c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372041332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3372041332
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3420670529
Short name T161
Test name
Test status
Simulation time 44917164847 ps
CPU time 267.56 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:21:05 PM PST 24
Peak memory 2508696 kb
Host smart-b1b721ce-3014-4e15-90b5-6debc8fbf1eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420670529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3420670529
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.190419013
Short name T675
Test name
Test status
Simulation time 15877926806 ps
CPU time 2404.48 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:56:40 PM PST 24
Peak memory 3889352 kb
Host smart-e221bb6f-229a-4724-bd54-51b3542c305a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190419013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stretch.190419013
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3082056481
Short name T1021
Test name
Test status
Simulation time 2838495048 ps
CPU time 6.15 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:16:41 PM PST 24
Peak memory 203424 kb
Host smart-88ac8498-9bed-44ec-a8de-119dd631e903
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082056481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3082056481
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_ovf.110147393
Short name T638
Test name
Test status
Simulation time 2759707471 ps
CPU time 37.39 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:17:18 PM PST 24
Peak memory 217452 kb
Host smart-84312548-030a-4928-a66a-9f14f7d0aac9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110147393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_tx_ovf.110147393
Directory /workspace/26.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.1770016383
Short name T57
Test name
Test status
Simulation time 7366359613 ps
CPU time 9 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:16:46 PM PST 24
Peak memory 213500 kb
Host smart-aa0d8c1f-9504-434d-b16b-0cd8923f1ddc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770016383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.1770016383
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2615937370
Short name T1277
Test name
Test status
Simulation time 67066585 ps
CPU time 0.62 seconds
Started Feb 21 03:16:33 PM PST 24
Finished Feb 21 03:16:34 PM PST 24
Peak memory 202128 kb
Host smart-b5532086-6268-4ff4-93e2-57c44e879fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615937370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2615937370
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.4102266592
Short name T816
Test name
Test status
Simulation time 225470313 ps
CPU time 1.47 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:16:37 PM PST 24
Peak memory 211516 kb
Host smart-3c3bd237-32d6-4186-93cb-7ef1244b0cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102266592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.4102266592
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1215142929
Short name T1382
Test name
Test status
Simulation time 1383996666 ps
CPU time 18.82 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:16:54 PM PST 24
Peak memory 269912 kb
Host smart-1a317bb8-f2cb-4454-b83e-e3b9544caa29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215142929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1215142929
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3839261933
Short name T424
Test name
Test status
Simulation time 6470818225 ps
CPU time 86.16 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:18:10 PM PST 24
Peak memory 626332 kb
Host smart-ce6cf992-4464-49ec-bb90-913d056f7c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839261933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3839261933
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2161770717
Short name T1230
Test name
Test status
Simulation time 11700139053 ps
CPU time 348.36 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:22:23 PM PST 24
Peak memory 1474300 kb
Host smart-12bbd4a5-ee4d-4655-a62b-2e1e0bf19c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161770717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2161770717
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.300178485
Short name T245
Test name
Test status
Simulation time 350289303 ps
CPU time 0.91 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:16:37 PM PST 24
Peak memory 203024 kb
Host smart-40b18929-fbf3-4231-8e27-6d30971676c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300178485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.300178485
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1255164305
Short name T325
Test name
Test status
Simulation time 1127249620 ps
CPU time 14.28 seconds
Started Feb 21 03:16:32 PM PST 24
Finished Feb 21 03:16:46 PM PST 24
Peak memory 203264 kb
Host smart-6fe788e2-e6cf-4d27-9f12-8e5c74212889
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255164305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1255164305
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3567084811
Short name T960
Test name
Test status
Simulation time 4478026433 ps
CPU time 447.22 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:24:11 PM PST 24
Peak memory 1252284 kb
Host smart-0220a5a4-e35a-48c3-baa1-190fb1801041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567084811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3567084811
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.4247837277
Short name T575
Test name
Test status
Simulation time 1892907590 ps
CPU time 72.42 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:17:53 PM PST 24
Peak memory 319208 kb
Host smart-6f792333-3fe2-48fd-b4f8-1f2bfee04cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247837277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.4247837277
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3631471530
Short name T1319
Test name
Test status
Simulation time 55344941 ps
CPU time 0.64 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:16:42 PM PST 24
Peak memory 202332 kb
Host smart-c84ca0e4-e16f-45ed-9bba-95b8effcaed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631471530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3631471530
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1071941810
Short name T489
Test name
Test status
Simulation time 356834642 ps
CPU time 17.61 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:56 PM PST 24
Peak memory 227244 kb
Host smart-198f2ecb-306d-4e0c-a9bf-d84deedaa6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071941810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1071941810
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_rx_oversample.3547515555
Short name T1331
Test name
Test status
Simulation time 2545503359 ps
CPU time 281.45 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:21:19 PM PST 24
Peak memory 342524 kb
Host smart-2abc815f-3de6-49a6-8d81-30cd5a8b10e9
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547515555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_rx_oversample
.3547515555
Directory /workspace/27.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.340175267
Short name T869
Test name
Test status
Simulation time 8726926226 ps
CPU time 57.61 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:17:33 PM PST 24
Peak memory 279700 kb
Host smart-27066a26-d529-4e44-85c6-099941b6a0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340175267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.340175267
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1479409827
Short name T1457
Test name
Test status
Simulation time 937760245 ps
CPU time 12.88 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:16:47 PM PST 24
Peak memory 217152 kb
Host smart-3c81b0c6-6ae9-44b5-b4dc-3f6f45614b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479409827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1479409827
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.491081275
Short name T1302
Test name
Test status
Simulation time 986622354 ps
CPU time 4.07 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:16:48 PM PST 24
Peak memory 203348 kb
Host smart-e8b723da-313b-49e9-9312-b8266c29c641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491081275 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.491081275
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.191739731
Short name T483
Test name
Test status
Simulation time 10187622456 ps
CPU time 60.33 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:17:36 PM PST 24
Peak memory 485284 kb
Host smart-7ccffac8-f490-49c1-a679-2b0e1adb5e55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191739731 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.191739731
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3554501529
Short name T797
Test name
Test status
Simulation time 10094493496 ps
CPU time 28.86 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 03:17:06 PM PST 24
Peak memory 396792 kb
Host smart-ea42e2b6-ac8f-44f3-8c0d-d9a289f648dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554501529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3554501529
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2565506843
Short name T961
Test name
Test status
Simulation time 1707264795 ps
CPU time 2.39 seconds
Started Feb 21 03:16:32 PM PST 24
Finished Feb 21 03:16:35 PM PST 24
Peak memory 203324 kb
Host smart-6f4da94a-abce-4926-a660-291cbe5fe248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565506843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2565506843
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2478280016
Short name T1041
Test name
Test status
Simulation time 1031958658 ps
CPU time 5.22 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:16:46 PM PST 24
Peak memory 204564 kb
Host smart-77fd7a76-c963-41ae-adb3-f56470e110a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478280016 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2478280016
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3626190694
Short name T375
Test name
Test status
Simulation time 27778329532 ps
CPU time 1519.18 seconds
Started Feb 21 03:16:35 PM PST 24
Finished Feb 21 03:41:55 PM PST 24
Peak memory 6630568 kb
Host smart-b524d4bc-2c95-47d1-8da4-28c9a0cefa35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626190694 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3626190694
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.3943179935
Short name T423
Test name
Test status
Simulation time 2621898226 ps
CPU time 4.01 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:16:45 PM PST 24
Peak memory 203452 kb
Host smart-2353faa6-b671-41da-aef4-46a5fb488d84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943179935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.3943179935
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.986020454
Short name T1390
Test name
Test status
Simulation time 1312019989 ps
CPU time 13.2 seconds
Started Feb 21 03:16:48 PM PST 24
Finished Feb 21 03:17:01 PM PST 24
Peak memory 203388 kb
Host smart-b6347671-3727-4886-9875-17c2946d3787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986020454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.986020454
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.3453985132
Short name T780
Test name
Test status
Simulation time 30815580989 ps
CPU time 1691.59 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:44:50 PM PST 24
Peak memory 1501408 kb
Host smart-f08cc7eb-72e0-4168-91e4-e910ab8d4940
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453985132 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.3453985132
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3221767425
Short name T1183
Test name
Test status
Simulation time 9754061362 ps
CPU time 43.41 seconds
Started Feb 21 03:16:36 PM PST 24
Finished Feb 21 03:17:20 PM PST 24
Peak memory 223052 kb
Host smart-7a4b04e4-0f92-4b92-b57e-7db491a0add0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221767425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3221767425
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.882253895
Short name T1478
Test name
Test status
Simulation time 45952341338 ps
CPU time 2642.34 seconds
Started Feb 21 03:16:37 PM PST 24
Finished Feb 21 04:00:40 PM PST 24
Peak memory 10204276 kb
Host smart-25d0bb71-528d-4834-84a1-502fef421feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882253895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_wr.882253895
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2425371302
Short name T752
Test name
Test status
Simulation time 38283921512 ps
CPU time 764.94 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:29:29 PM PST 24
Peak memory 2032056 kb
Host smart-75c572c7-5c2e-4480-9264-b45af72077c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425371302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2425371302
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.540583335
Short name T1369
Test name
Test status
Simulation time 3311295423 ps
CPU time 7.3 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:46 PM PST 24
Peak memory 212660 kb
Host smart-0515d453-7eea-4230-8e9e-e2760b66a57c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540583335 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.540583335
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_ovf.1464344024
Short name T188
Test name
Test status
Simulation time 9680274006 ps
CPU time 40.44 seconds
Started Feb 21 03:16:34 PM PST 24
Finished Feb 21 03:17:14 PM PST 24
Peak memory 217352 kb
Host smart-1b38ba47-5cae-457c-ace9-e6eb04f1a86c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464344024 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_tx_ovf.1464344024
Directory /workspace/27.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1336881286
Short name T682
Test name
Test status
Simulation time 18473773 ps
CPU time 0.62 seconds
Started Feb 21 03:16:47 PM PST 24
Finished Feb 21 03:16:48 PM PST 24
Peak memory 202084 kb
Host smart-a9fee30d-76cd-4764-92af-6d000d8e8a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336881286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1336881286
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.4291109462
Short name T1050
Test name
Test status
Simulation time 53042703 ps
CPU time 1.22 seconds
Started Feb 21 03:16:42 PM PST 24
Finished Feb 21 03:16:43 PM PST 24
Peak memory 203328 kb
Host smart-3664b46a-2fcd-4290-a13e-3b8bc3000883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291109462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.4291109462
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1276094308
Short name T1320
Test name
Test status
Simulation time 539459575 ps
CPU time 11.1 seconds
Started Feb 21 03:16:50 PM PST 24
Finished Feb 21 03:17:02 PM PST 24
Peak memory 325656 kb
Host smart-5f45dcd2-fdf0-40d5-a7ab-dd2fe4f8d54e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276094308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1276094308
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.1666076957
Short name T1336
Test name
Test status
Simulation time 16584161567 ps
CPU time 178.55 seconds
Started Feb 21 03:16:45 PM PST 24
Finished Feb 21 03:19:45 PM PST 24
Peak memory 1157528 kb
Host smart-90e23488-d0f9-4a37-a23f-9adb7bb03184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666076957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.1666076957
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.407328123
Short name T1090
Test name
Test status
Simulation time 5150608336 ps
CPU time 272.91 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:21:17 PM PST 24
Peak memory 1467652 kb
Host smart-4e3fb928-58e7-4b2b-9818-39e106f1df60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407328123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.407328123
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2144655792
Short name T1450
Test name
Test status
Simulation time 438046448 ps
CPU time 1.01 seconds
Started Feb 21 03:16:41 PM PST 24
Finished Feb 21 03:16:42 PM PST 24
Peak memory 203252 kb
Host smart-4f4febad-4885-4218-b164-3038c4f6f0cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144655792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2144655792
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1619708341
Short name T248
Test name
Test status
Simulation time 1795559081 ps
CPU time 14.22 seconds
Started Feb 21 03:16:39 PM PST 24
Finished Feb 21 03:16:53 PM PST 24
Peak memory 252480 kb
Host smart-bbb07e3b-7b2c-4d71-b815-72ca2f375362
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619708341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1619708341
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3550308390
Short name T1347
Test name
Test status
Simulation time 27330766533 ps
CPU time 293.78 seconds
Started Feb 21 03:16:41 PM PST 24
Finished Feb 21 03:21:35 PM PST 24
Peak memory 1599416 kb
Host smart-07b304e2-ea90-47b7-a31d-f733601758aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550308390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3550308390
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.3160809371
Short name T1235
Test name
Test status
Simulation time 1234061395 ps
CPU time 22.74 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:17:07 PM PST 24
Peak memory 250868 kb
Host smart-ac37e6e9-87e8-433e-9c09-2a7d2636303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160809371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3160809371
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.3370637946
Short name T170
Test name
Test status
Simulation time 21026383 ps
CPU time 0.71 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:16:39 PM PST 24
Peak memory 202252 kb
Host smart-87fcc9d1-9306-4842-9dab-6d19677e26f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370637946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3370637946
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1597610870
Short name T996
Test name
Test status
Simulation time 52146214198 ps
CPU time 2432.19 seconds
Started Feb 21 03:16:50 PM PST 24
Finished Feb 21 03:57:23 PM PST 24
Peak memory 203388 kb
Host smart-fb4a93b5-5c60-4129-9c8b-2a716b3853b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597610870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1597610870
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_rx_oversample.1477726227
Short name T574
Test name
Test status
Simulation time 4379658872 ps
CPU time 206.05 seconds
Started Feb 21 03:16:47 PM PST 24
Finished Feb 21 03:20:14 PM PST 24
Peak memory 298560 kb
Host smart-f63e10a8-da12-4e24-ae45-b6e73571746a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477726227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_rx_oversample
.1477726227
Directory /workspace/28.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2827808505
Short name T1424
Test name
Test status
Simulation time 2720256988 ps
CPU time 99.94 seconds
Started Feb 21 03:16:38 PM PST 24
Finished Feb 21 03:18:18 PM PST 24
Peak memory 249408 kb
Host smart-f530717d-3a6e-4d1f-88cd-2f6628a7f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827808505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2827808505
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2023761853
Short name T142
Test name
Test status
Simulation time 26540549352 ps
CPU time 1127.14 seconds
Started Feb 21 03:16:45 PM PST 24
Finished Feb 21 03:35:33 PM PST 24
Peak memory 2734980 kb
Host smart-a70bdf8d-5a00-448d-abc1-e8e93908ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023761853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2023761853
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.4054945156
Short name T668
Test name
Test status
Simulation time 1457841120 ps
CPU time 11.56 seconds
Started Feb 21 03:16:41 PM PST 24
Finished Feb 21 03:16:53 PM PST 24
Peak memory 211512 kb
Host smart-1e41d130-0d83-4c30-bc14-5c55dd8cb5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054945156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.4054945156
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1570508906
Short name T757
Test name
Test status
Simulation time 1651731954 ps
CPU time 5.71 seconds
Started Feb 21 03:16:42 PM PST 24
Finished Feb 21 03:16:48 PM PST 24
Peak memory 203368 kb
Host smart-a0c459a9-770b-4d02-8342-eab167a4b34d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570508906 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1570508906
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1201037855
Short name T708
Test name
Test status
Simulation time 10475290949 ps
CPU time 12.97 seconds
Started Feb 21 03:16:50 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 286236 kb
Host smart-963113d6-c328-41ce-95a8-f2d527d56567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201037855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1201037855
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2907766143
Short name T1445
Test name
Test status
Simulation time 10328845743 ps
CPU time 13.72 seconds
Started Feb 21 03:16:41 PM PST 24
Finished Feb 21 03:16:55 PM PST 24
Peak memory 302036 kb
Host smart-c9c244c6-fd3f-4dea-9c19-7a846401e828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907766143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2907766143
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2815148385
Short name T953
Test name
Test status
Simulation time 1448896909 ps
CPU time 2.18 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:16:46 PM PST 24
Peak memory 203388 kb
Host smart-3f10a4d8-4995-4f7f-bf6d-77e248c45575
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815148385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2815148385
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2901610662
Short name T687
Test name
Test status
Simulation time 5201847564 ps
CPU time 5.84 seconds
Started Feb 21 03:16:39 PM PST 24
Finished Feb 21 03:16:45 PM PST 24
Peak memory 203412 kb
Host smart-719c13bb-5660-4fb8-88e4-cd49b658d5d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901610662 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2901610662
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1862916928
Short name T291
Test name
Test status
Simulation time 8707219117 ps
CPU time 60.75 seconds
Started Feb 21 03:16:50 PM PST 24
Finished Feb 21 03:17:51 PM PST 24
Peak memory 1054540 kb
Host smart-4e939552-2f6f-440d-86f0-f2f1700303f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862916928 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1862916928
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.3099919603
Short name T1292
Test name
Test status
Simulation time 481959138 ps
CPU time 3.02 seconds
Started Feb 21 03:16:42 PM PST 24
Finished Feb 21 03:16:45 PM PST 24
Peak memory 203384 kb
Host smart-727eff68-5e7f-4bb7-bedf-a165b9535ab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099919603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.3099919603
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.4150216705
Short name T1481
Test name
Test status
Simulation time 6032035887 ps
CPU time 41.34 seconds
Started Feb 21 03:16:39 PM PST 24
Finished Feb 21 03:17:21 PM PST 24
Peak memory 203428 kb
Host smart-0ce6babf-3f00-4c41-81ba-ae3c5f2888a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150216705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.4150216705
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.81058844
Short name T852
Test name
Test status
Simulation time 78144518946 ps
CPU time 2413.09 seconds
Started Feb 21 03:16:50 PM PST 24
Finished Feb 21 03:57:04 PM PST 24
Peak memory 2377276 kb
Host smart-cafdc11c-cb07-4097-8848-3f5777990ce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81058844 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.i2c_target_stress_all.81058844
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.4024793283
Short name T1469
Test name
Test status
Simulation time 1417293645 ps
CPU time 18.72 seconds
Started Feb 21 03:16:40 PM PST 24
Finished Feb 21 03:16:59 PM PST 24
Peak memory 215748 kb
Host smart-7219a661-87b4-4d6e-93b7-31b7b3130b88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024793283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.4024793283
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2846387083
Short name T534
Test name
Test status
Simulation time 72913038851 ps
CPU time 2784.91 seconds
Started Feb 21 03:16:41 PM PST 24
Finished Feb 21 04:03:07 PM PST 24
Peak memory 8858720 kb
Host smart-6c32024d-4079-49c9-a8a4-f5512d6d863a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846387083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2846387083
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2297331638
Short name T1251
Test name
Test status
Simulation time 8463462616 ps
CPU time 153.21 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:19:17 PM PST 24
Peak memory 742076 kb
Host smart-ece9c280-8741-46b1-9b10-073b80ec676c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297331638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2297331638
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.111297830
Short name T1034
Test name
Test status
Simulation time 22162402521 ps
CPU time 6.02 seconds
Started Feb 21 03:16:47 PM PST 24
Finished Feb 21 03:16:54 PM PST 24
Peak memory 203420 kb
Host smart-26b7740b-842e-48be-8db9-56310368b4d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111297830 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.111297830
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_ovf.1138363868
Short name T908
Test name
Test status
Simulation time 4839365246 ps
CPU time 47.63 seconds
Started Feb 21 03:16:41 PM PST 24
Finished Feb 21 03:17:29 PM PST 24
Peak memory 222668 kb
Host smart-968a6301-dd27-47cb-8e1c-565d90e992de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138363868 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_tx_ovf.1138363868
Directory /workspace/28.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.911388961
Short name T176
Test name
Test status
Simulation time 1932231807 ps
CPU time 5.55 seconds
Started Feb 21 03:16:46 PM PST 24
Finished Feb 21 03:16:52 PM PST 24
Peak memory 203392 kb
Host smart-52767b88-7402-48e6-9adc-95a55bfc5754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911388961 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_unexp_stop.911388961
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1826403083
Short name T1381
Test name
Test status
Simulation time 37078955 ps
CPU time 0.6 seconds
Started Feb 21 03:16:57 PM PST 24
Finished Feb 21 03:16:59 PM PST 24
Peak memory 202072 kb
Host smart-d49aebad-eb51-44f6-9db5-d6bef11465c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826403083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1826403083
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.4093527400
Short name T504
Test name
Test status
Simulation time 137798294 ps
CPU time 1.72 seconds
Started Feb 21 03:16:47 PM PST 24
Finished Feb 21 03:16:49 PM PST 24
Peak memory 211576 kb
Host smart-a4242f72-098d-474c-b5ba-f5d5a2b20009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093527400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.4093527400
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1355754869
Short name T1233
Test name
Test status
Simulation time 1197847118 ps
CPU time 16.26 seconds
Started Feb 21 03:16:56 PM PST 24
Finished Feb 21 03:17:12 PM PST 24
Peak memory 267728 kb
Host smart-ade4c0ed-8333-444f-bdbb-4359f09cd497
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355754869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1355754869
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.818931428
Short name T571
Test name
Test status
Simulation time 3422166078 ps
CPU time 291.86 seconds
Started Feb 21 03:16:52 PM PST 24
Finished Feb 21 03:21:44 PM PST 24
Peak memory 1011844 kb
Host smart-54c80eb2-1905-4974-b74d-5510caae1075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818931428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.818931428
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2122442846
Short name T823
Test name
Test status
Simulation time 4063657157 ps
CPU time 444.11 seconds
Started Feb 21 03:16:53 PM PST 24
Finished Feb 21 03:24:18 PM PST 24
Peak memory 1164964 kb
Host smart-b7688ba7-09d9-41d8-bb08-363fb92d674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122442846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2122442846
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.499478463
Short name T645
Test name
Test status
Simulation time 268191499 ps
CPU time 1 seconds
Started Feb 21 03:16:50 PM PST 24
Finished Feb 21 03:16:51 PM PST 24
Peak memory 203048 kb
Host smart-e1f03bf8-9001-4db9-b0ee-b9037d518d5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499478463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.499478463
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.363076196
Short name T1312
Test name
Test status
Simulation time 484391131 ps
CPU time 7.7 seconds
Started Feb 21 03:16:48 PM PST 24
Finished Feb 21 03:16:56 PM PST 24
Peak memory 253596 kb
Host smart-76222ac2-ee28-43c6-9f31-01f4ed436eee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363076196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
363076196
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2582602020
Short name T1104
Test name
Test status
Simulation time 12861507317 ps
CPU time 395.26 seconds
Started Feb 21 03:16:51 PM PST 24
Finished Feb 21 03:23:26 PM PST 24
Peak memory 1872280 kb
Host smart-cb4c5a11-40e7-4cee-8a06-ce072d3036b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582602020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2582602020
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1398521441
Short name T1166
Test name
Test status
Simulation time 31594741267 ps
CPU time 92.31 seconds
Started Feb 21 03:17:08 PM PST 24
Finished Feb 21 03:18:42 PM PST 24
Peak memory 348216 kb
Host smart-33e81180-012e-49c8-96ae-9e3c9aa66d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398521441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1398521441
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.2802806831
Short name T1498
Test name
Test status
Simulation time 165932286 ps
CPU time 0.68 seconds
Started Feb 21 03:16:42 PM PST 24
Finished Feb 21 03:16:43 PM PST 24
Peak memory 202256 kb
Host smart-b51fd217-abed-4df8-8cb9-20cb2e7beb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802806831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2802806831
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_rx_oversample.1432336677
Short name T1079
Test name
Test status
Simulation time 11820828398 ps
CPU time 117.98 seconds
Started Feb 21 03:16:47 PM PST 24
Finished Feb 21 03:18:45 PM PST 24
Peak memory 320712 kb
Host smart-c6708c34-4d46-4c35-9cc8-52f7c53915ee
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432336677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_rx_oversample
.1432336677
Directory /workspace/29.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.201219562
Short name T617
Test name
Test status
Simulation time 10364970526 ps
CPU time 87.7 seconds
Started Feb 21 03:16:43 PM PST 24
Finished Feb 21 03:18:11 PM PST 24
Peak memory 228132 kb
Host smart-2a3df35c-385d-4e54-8066-7b1d57cf9dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201219562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.201219562
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.1521750500
Short name T152
Test name
Test status
Simulation time 40339110884 ps
CPU time 600.56 seconds
Started Feb 21 03:16:47 PM PST 24
Finished Feb 21 03:26:48 PM PST 24
Peak memory 2151868 kb
Host smart-b8feb5f7-18dc-4067-9fd7-434f861c0e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521750500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1521750500
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3460032587
Short name T1114
Test name
Test status
Simulation time 5137323941 ps
CPU time 50.46 seconds
Started Feb 21 03:16:53 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 219696 kb
Host smart-af0cbdd0-75e7-4590-922a-d1e8715fd586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460032587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3460032587
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3467607097
Short name T1119
Test name
Test status
Simulation time 1438596514 ps
CPU time 5.8 seconds
Started Feb 21 03:17:00 PM PST 24
Finished Feb 21 03:17:07 PM PST 24
Peak memory 203388 kb
Host smart-e52b8bb9-ef20-41bc-9ac2-9ec14834ad03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467607097 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3467607097
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.435351779
Short name T19
Test name
Test status
Simulation time 10026802709 ps
CPU time 53.95 seconds
Started Feb 21 03:17:00 PM PST 24
Finished Feb 21 03:17:54 PM PST 24
Peak memory 507444 kb
Host smart-e15561ec-3b30-40c3-bf8c-feb15bce1765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435351779 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_acq.435351779
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1266619597
Short name T279
Test name
Test status
Simulation time 10100171205 ps
CPU time 71.03 seconds
Started Feb 21 03:16:59 PM PST 24
Finished Feb 21 03:18:10 PM PST 24
Peak memory 654812 kb
Host smart-aa15aeff-b226-4657-8e00-f0bd0bc61eef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266619597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1266619597
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.3527499951
Short name T985
Test name
Test status
Simulation time 514929432 ps
CPU time 2.64 seconds
Started Feb 21 03:17:00 PM PST 24
Finished Feb 21 03:17:03 PM PST 24
Peak memory 203396 kb
Host smart-e1c0fbf2-c1ec-460a-8539-d47c6f860e7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527499951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.3527499951
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1717027937
Short name T864
Test name
Test status
Simulation time 910816716 ps
CPU time 4.47 seconds
Started Feb 21 03:16:54 PM PST 24
Finished Feb 21 03:16:59 PM PST 24
Peak memory 207928 kb
Host smart-a9ee01f4-14a3-4874-b3c7-c8ae8863fad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717027937 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1717027937
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1005371991
Short name T662
Test name
Test status
Simulation time 23322183954 ps
CPU time 1171.89 seconds
Started Feb 21 03:17:01 PM PST 24
Finished Feb 21 03:36:33 PM PST 24
Peak memory 5029672 kb
Host smart-ee5339d6-a34a-4b6a-9633-b1e5722699d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005371991 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1005371991
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.2572426051
Short name T268
Test name
Test status
Simulation time 1102529994 ps
CPU time 3.46 seconds
Started Feb 21 03:17:07 PM PST 24
Finished Feb 21 03:17:12 PM PST 24
Peak memory 206080 kb
Host smart-7613db5b-9947-438f-903b-f1fa13daef97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572426051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.2572426051
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.4230811616
Short name T1047
Test name
Test status
Simulation time 3710846495 ps
CPU time 47.11 seconds
Started Feb 21 03:16:53 PM PST 24
Finished Feb 21 03:17:41 PM PST 24
Peak memory 203424 kb
Host smart-6ad58cba-5ca2-472b-97ed-6c917b5da808
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230811616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.4230811616
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.2688125919
Short name T1191
Test name
Test status
Simulation time 53845895658 ps
CPU time 1137.53 seconds
Started Feb 21 03:17:02 PM PST 24
Finished Feb 21 03:36:00 PM PST 24
Peak memory 924476 kb
Host smart-4e0ee65b-ff18-44a1-895b-acbc1665f1f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688125919 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.2688125919
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.775592949
Short name T699
Test name
Test status
Simulation time 4198390963 ps
CPU time 13.26 seconds
Started Feb 21 03:16:49 PM PST 24
Finished Feb 21 03:17:02 PM PST 24
Peak memory 205292 kb
Host smart-28acf688-289e-4ee1-89de-1639417225da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775592949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.775592949
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.2976104664
Short name T885
Test name
Test status
Simulation time 33999364824 ps
CPU time 211.36 seconds
Started Feb 21 03:16:56 PM PST 24
Finished Feb 21 03:20:27 PM PST 24
Peak memory 1650020 kb
Host smart-a1bc753a-1cee-4d55-a539-8f289e130706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976104664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.2976104664
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2162595912
Short name T1496
Test name
Test status
Simulation time 1583596176 ps
CPU time 7.29 seconds
Started Feb 21 03:17:00 PM PST 24
Finished Feb 21 03:17:08 PM PST 24
Peak memory 214908 kb
Host smart-ba620f68-2dfa-4d74-941b-d8ffe4397c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162595912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2162595912
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_ovf.1897121043
Short name T1313
Test name
Test status
Simulation time 6283771001 ps
CPU time 49.6 seconds
Started Feb 21 03:17:06 PM PST 24
Finished Feb 21 03:17:56 PM PST 24
Peak memory 223452 kb
Host smart-edcd7736-7645-4de0-9579-ed248db9e1a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897121043 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_tx_ovf.1897121043
Directory /workspace/29.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.652772755
Short name T641
Test name
Test status
Simulation time 11355584890 ps
CPU time 6.09 seconds
Started Feb 21 03:17:00 PM PST 24
Finished Feb 21 03:17:07 PM PST 24
Peak memory 205480 kb
Host smart-242f0235-0be0-47f4-9aa7-e3fdd404e04d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652772755 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_unexp_stop.652772755
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4253279823
Short name T902
Test name
Test status
Simulation time 106134112 ps
CPU time 0.62 seconds
Started Feb 21 03:14:09 PM PST 24
Finished Feb 21 03:14:12 PM PST 24
Peak memory 202148 kb
Host smart-abafbc43-9729-46e8-81be-03763c19463e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253279823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4253279823
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3001367288
Short name T479
Test name
Test status
Simulation time 90451685 ps
CPU time 1.4 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:14:15 PM PST 24
Peak memory 211448 kb
Host smart-9e3b9805-58e7-4162-875f-f38832d1b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001367288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3001367288
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1446939356
Short name T339
Test name
Test status
Simulation time 1540465544 ps
CPU time 21.18 seconds
Started Feb 21 03:13:39 PM PST 24
Finished Feb 21 03:14:01 PM PST 24
Peak memory 289772 kb
Host smart-8aee5e29-0cbe-4930-9574-bb7a45dfb66d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446939356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1446939356
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1765133779
Short name T1451
Test name
Test status
Simulation time 5413528176 ps
CPU time 214.73 seconds
Started Feb 21 03:13:43 PM PST 24
Finished Feb 21 03:17:18 PM PST 24
Peak memory 863200 kb
Host smart-d7474ecd-d11d-4d1c-83ac-b1b22f9cb70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765133779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1765133779
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3370313295
Short name T13
Test name
Test status
Simulation time 8470310160 ps
CPU time 459.24 seconds
Started Feb 21 03:13:33 PM PST 24
Finished Feb 21 03:21:14 PM PST 24
Peak memory 1204788 kb
Host smart-486ba51c-628e-43a1-ab61-2caf9cb0354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370313295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3370313295
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3859695631
Short name T553
Test name
Test status
Simulation time 504110202 ps
CPU time 0.97 seconds
Started Feb 21 03:13:30 PM PST 24
Finished Feb 21 03:13:34 PM PST 24
Peak memory 203016 kb
Host smart-ec05872b-f704-40f2-abc1-d6bcf86556eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859695631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3859695631
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.387457135
Short name T190
Test name
Test status
Simulation time 158610672 ps
CPU time 9.02 seconds
Started Feb 21 03:13:34 PM PST 24
Finished Feb 21 03:13:45 PM PST 24
Peak memory 230328 kb
Host smart-ba62f9e3-ecfb-489d-afd9-b6ab213a9cc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387457135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.387457135
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.233172751
Short name T237
Test name
Test status
Simulation time 6043383723 ps
CPU time 225.49 seconds
Started Feb 21 03:13:37 PM PST 24
Finished Feb 21 03:17:23 PM PST 24
Peak memory 1260300 kb
Host smart-46e0b6e8-150d-4db8-87f3-ab684331c519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233172751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.233172751
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.1062701752
Short name T1095
Test name
Test status
Simulation time 11251316832 ps
CPU time 157.46 seconds
Started Feb 21 03:14:07 PM PST 24
Finished Feb 21 03:16:48 PM PST 24
Peak memory 257124 kb
Host smart-67f054da-3802-4a8b-b300-d5d34e106b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062701752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.1062701752
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3538453610
Short name T165
Test name
Test status
Simulation time 54467155 ps
CPU time 0.61 seconds
Started Feb 21 03:13:33 PM PST 24
Finished Feb 21 03:13:36 PM PST 24
Peak memory 202324 kb
Host smart-fc701d9c-7cd6-4a7d-9ecc-aaaafd939b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538453610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3538453610
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.217155983
Short name T145
Test name
Test status
Simulation time 362168525 ps
CPU time 18.19 seconds
Started Feb 21 03:13:37 PM PST 24
Finished Feb 21 03:13:55 PM PST 24
Peak memory 225216 kb
Host smart-c24bcbda-753b-4b8e-8e64-a7665c6987d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217155983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.217155983
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_rx_oversample.999134837
Short name T385
Test name
Test status
Simulation time 1681315351 ps
CPU time 114.28 seconds
Started Feb 21 03:13:42 PM PST 24
Finished Feb 21 03:15:37 PM PST 24
Peak memory 264388 kb
Host smart-5914db98-cf6d-49b9-ad5d-4cfa269f3a1d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999134837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_rx_oversample.999134837
Directory /workspace/3.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3041643501
Short name T983
Test name
Test status
Simulation time 15284715073 ps
CPU time 54.42 seconds
Started Feb 21 03:13:39 PM PST 24
Finished Feb 21 03:14:34 PM PST 24
Peak memory 299632 kb
Host smart-b016398a-40bc-46ab-8bad-570a275506e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041643501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3041643501
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.443209785
Short name T230
Test name
Test status
Simulation time 22691274655 ps
CPU time 224.08 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:18:10 PM PST 24
Peak memory 935428 kb
Host smart-b866c48f-1320-426f-81d1-0612c2565254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443209785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.443209785
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2604631795
Short name T737
Test name
Test status
Simulation time 2677425007 ps
CPU time 19.03 seconds
Started Feb 21 03:13:34 PM PST 24
Finished Feb 21 03:13:55 PM PST 24
Peak memory 228060 kb
Host smart-fd1b5fb3-7c09-4432-9b3f-61d5171ae8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604631795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2604631795
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1167049957
Short name T83
Test name
Test status
Simulation time 66507105 ps
CPU time 0.91 seconds
Started Feb 21 03:14:06 PM PST 24
Finished Feb 21 03:14:10 PM PST 24
Peak memory 221576 kb
Host smart-c60e502b-5f7e-4a79-b4cd-1d3fcfca0557
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167049957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1167049957
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2640438317
Short name T770
Test name
Test status
Simulation time 6084495954 ps
CPU time 5.69 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:22 PM PST 24
Peak memory 203444 kb
Host smart-3ae81308-9e7a-4341-83aa-af89d5d38dc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640438317 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2640438317
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3711054201
Short name T286
Test name
Test status
Simulation time 10084030369 ps
CPU time 14.72 seconds
Started Feb 21 03:14:11 PM PST 24
Finished Feb 21 03:14:27 PM PST 24
Peak memory 304532 kb
Host smart-bb7eebab-7e55-451e-9675-cacd157f3edb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711054201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3711054201
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1744311272
Short name T1429
Test name
Test status
Simulation time 10130764039 ps
CPU time 60.91 seconds
Started Feb 21 03:14:06 PM PST 24
Finished Feb 21 03:15:10 PM PST 24
Peak memory 507520 kb
Host smart-d8d96d6e-091e-4a55-9318-14ea6df87d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744311272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1744311272
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.473347937
Short name T469
Test name
Test status
Simulation time 629390952 ps
CPU time 2.37 seconds
Started Feb 21 03:14:06 PM PST 24
Finished Feb 21 03:14:10 PM PST 24
Peak memory 203296 kb
Host smart-d7009a6e-5cf4-4be0-bd35-79448a81a674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473347937 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.473347937
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2017120080
Short name T8
Test name
Test status
Simulation time 2720270172 ps
CPU time 3.35 seconds
Started Feb 21 03:14:13 PM PST 24
Finished Feb 21 03:14:17 PM PST 24
Peak memory 203420 kb
Host smart-9ff8f823-0861-4135-b717-b513e2599a35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017120080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2017120080
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.1643852158
Short name T426
Test name
Test status
Simulation time 12677731606 ps
CPU time 41.82 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:14:55 PM PST 24
Peak memory 824664 kb
Host smart-0426b4f0-06f0-4ebd-a700-29bd17b809b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643852158 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.1643852158
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.4060692085
Short name T698
Test name
Test status
Simulation time 863792291 ps
CPU time 4.6 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:21 PM PST 24
Peak memory 206592 kb
Host smart-67963a6e-1099-4af4-8852-a7bbf2be0f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060692085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.4060692085
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3290430988
Short name T233
Test name
Test status
Simulation time 30849104778 ps
CPU time 20.25 seconds
Started Feb 21 03:13:58 PM PST 24
Finished Feb 21 03:14:19 PM PST 24
Peak memory 203432 kb
Host smart-6c243545-1332-43c1-97e4-57d5dac6fd25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290430988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3290430988
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.729956256
Short name T729
Test name
Test status
Simulation time 56603515803 ps
CPU time 955.32 seconds
Started Feb 21 03:14:10 PM PST 24
Finished Feb 21 03:30:07 PM PST 24
Peak memory 1497704 kb
Host smart-9431fbfc-9f82-4dff-97a4-1f7c1cf5a93b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729956256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.i2c_target_stress_all.729956256
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1297784876
Short name T405
Test name
Test status
Simulation time 1956514710 ps
CPU time 54.99 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:15:08 PM PST 24
Peak memory 203340 kb
Host smart-2f14e06a-c42f-4ea2-8f08-ddb57b7c8796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297784876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1297784876
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2944121017
Short name T249
Test name
Test status
Simulation time 51495321230 ps
CPU time 177.9 seconds
Started Feb 21 03:14:10 PM PST 24
Finished Feb 21 03:17:09 PM PST 24
Peak memory 1943616 kb
Host smart-f88a8936-41ce-4759-87c1-e5e0d3dfbeb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944121017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2944121017
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3267610411
Short name T47
Test name
Test status
Simulation time 18676559541 ps
CPU time 136.96 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:16:34 PM PST 24
Peak memory 1070404 kb
Host smart-287d06a9-07e0-44ef-bcb4-18a14f26ec8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267610411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3267610411
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.4160413358
Short name T943
Test name
Test status
Simulation time 1600742449 ps
CPU time 6.71 seconds
Started Feb 21 03:14:06 PM PST 24
Finished Feb 21 03:14:15 PM PST 24
Peak memory 208072 kb
Host smart-d16d8128-c5df-4ad5-9dcd-6d007249941c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160413358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.4160413358
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_ovf.2206566646
Short name T259
Test name
Test status
Simulation time 5177960297 ps
CPU time 41.32 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:58 PM PST 24
Peak memory 223800 kb
Host smart-2dccab23-9f75-466b-a844-b6ef6fd67edf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206566646 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_tx_ovf.2206566646
Directory /workspace/3.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.4221714857
Short name T1000
Test name
Test status
Simulation time 15289943038 ps
CPU time 6.49 seconds
Started Feb 21 03:14:04 PM PST 24
Finished Feb 21 03:14:11 PM PST 24
Peak memory 205208 kb
Host smart-192af1de-085e-47b3-930d-a83cce1fc8dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221714857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.4221714857
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.4064760031
Short name T1343
Test name
Test status
Simulation time 18079861 ps
CPU time 0.62 seconds
Started Feb 21 03:17:15 PM PST 24
Finished Feb 21 03:17:16 PM PST 24
Peak memory 202936 kb
Host smart-6e5e33f8-4ede-4371-9f17-fa49b07d754a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064760031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.4064760031
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2167261170
Short name T1107
Test name
Test status
Simulation time 33678380 ps
CPU time 1.55 seconds
Started Feb 21 03:17:29 PM PST 24
Finished Feb 21 03:17:31 PM PST 24
Peak memory 211512 kb
Host smart-f0f7e99e-c077-471b-a862-9a87db026443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167261170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2167261170
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3923782528
Short name T775
Test name
Test status
Simulation time 1201931745 ps
CPU time 13.77 seconds
Started Feb 21 03:17:25 PM PST 24
Finished Feb 21 03:17:39 PM PST 24
Peak memory 322100 kb
Host smart-cb221324-034a-4cca-bdb7-63f9c160d44d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923782528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3923782528
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1218914873
Short name T594
Test name
Test status
Simulation time 11901028587 ps
CPU time 85.91 seconds
Started Feb 21 03:17:14 PM PST 24
Finished Feb 21 03:18:40 PM PST 24
Peak memory 701596 kb
Host smart-c6b34a6f-a495-4a28-982e-b9e393c3d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218914873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1218914873
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.786640132
Short name T561
Test name
Test status
Simulation time 12508833695 ps
CPU time 372.31 seconds
Started Feb 21 03:17:32 PM PST 24
Finished Feb 21 03:23:44 PM PST 24
Peak memory 1605876 kb
Host smart-66aeb989-7f62-41bf-ac76-0d78dc702bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786640132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.786640132
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3421141542
Short name T552
Test name
Test status
Simulation time 107708447 ps
CPU time 0.93 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:17:39 PM PST 24
Peak memory 203024 kb
Host smart-ea4a8bd3-cf91-4657-bbbf-842dd8897f23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421141542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3421141542
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3151301345
Short name T877
Test name
Test status
Simulation time 283904077 ps
CPU time 7.47 seconds
Started Feb 21 03:17:14 PM PST 24
Finished Feb 21 03:17:22 PM PST 24
Peak memory 259412 kb
Host smart-fbc0d305-c1b8-4a5c-8f3c-8e6ad8af9038
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151301345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3151301345
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1757782443
Short name T962
Test name
Test status
Simulation time 3702868464 ps
CPU time 163.99 seconds
Started Feb 21 03:17:19 PM PST 24
Finished Feb 21 03:20:03 PM PST 24
Peak memory 1006820 kb
Host smart-5b83bbc8-f8c6-4c0a-ad31-51bbe5840c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757782443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1757782443
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1083897632
Short name T1435
Test name
Test status
Simulation time 9743422671 ps
CPU time 53.03 seconds
Started Feb 21 03:17:15 PM PST 24
Finished Feb 21 03:18:08 PM PST 24
Peak memory 277672 kb
Host smart-a2901660-9e05-47be-b159-4f47b5fc7ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083897632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1083897632
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.2459908055
Short name T1281
Test name
Test status
Simulation time 17833554 ps
CPU time 0.67 seconds
Started Feb 21 03:16:58 PM PST 24
Finished Feb 21 03:16:59 PM PST 24
Peak memory 202236 kb
Host smart-cb6c0b92-70ea-49c6-aebe-cfdcda4b6822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459908055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2459908055
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.4276078319
Short name T556
Test name
Test status
Simulation time 373055860 ps
CPU time 2.03 seconds
Started Feb 21 03:17:48 PM PST 24
Finished Feb 21 03:17:50 PM PST 24
Peak memory 211564 kb
Host smart-fd169bf1-c41d-4941-a95c-69c8a2b18663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276078319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.4276078319
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_rx_oversample.4083593804
Short name T217
Test name
Test status
Simulation time 6252690602 ps
CPU time 99.36 seconds
Started Feb 21 03:16:59 PM PST 24
Finished Feb 21 03:18:39 PM PST 24
Peak memory 252500 kb
Host smart-5bcba7ba-ce0d-4a0a-9cad-4fc42c8499a3
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083593804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_rx_oversample
.4083593804
Directory /workspace/30.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1090222641
Short name T1396
Test name
Test status
Simulation time 7246978882 ps
CPU time 49.71 seconds
Started Feb 21 03:17:01 PM PST 24
Finished Feb 21 03:17:51 PM PST 24
Peak memory 284744 kb
Host smart-f8248257-0581-4d36-9e8a-1368da3102b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090222641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1090222641
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2650322301
Short name T570
Test name
Test status
Simulation time 1159194773 ps
CPU time 8.77 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 211560 kb
Host smart-c9920586-4c58-4012-a11a-6381caef7cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650322301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2650322301
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1765776377
Short name T1358
Test name
Test status
Simulation time 3342413386 ps
CPU time 3.43 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:17:30 PM PST 24
Peak memory 203476 kb
Host smart-2ab9058f-77d7-4567-9095-40028de8b911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765776377 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1765776377
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1859054939
Short name T833
Test name
Test status
Simulation time 10130841191 ps
CPU time 18.11 seconds
Started Feb 21 03:17:15 PM PST 24
Finished Feb 21 03:17:34 PM PST 24
Peak memory 311836 kb
Host smart-fbaae1c2-4e45-4793-a369-12228d2815ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859054939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1859054939
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.1670757708
Short name T1220
Test name
Test status
Simulation time 10168938879 ps
CPU time 12.68 seconds
Started Feb 21 03:17:15 PM PST 24
Finished Feb 21 03:17:29 PM PST 24
Peak memory 317692 kb
Host smart-4df89723-2d7e-4770-951f-05eff065bb6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670757708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.1670757708
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2728949175
Short name T111
Test name
Test status
Simulation time 2396260956 ps
CPU time 3.05 seconds
Started Feb 21 03:17:15 PM PST 24
Finished Feb 21 03:17:19 PM PST 24
Peak memory 203440 kb
Host smart-640b17d8-a740-42a0-8e56-4f713a7a818b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728949175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2728949175
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.3564467748
Short name T1419
Test name
Test status
Simulation time 1262335948 ps
CPU time 4.6 seconds
Started Feb 21 03:17:16 PM PST 24
Finished Feb 21 03:17:21 PM PST 24
Peak memory 203344 kb
Host smart-2c016d33-a459-4541-b72e-e67334f1a7c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564467748 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.3564467748
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3729576967
Short name T955
Test name
Test status
Simulation time 5692088079 ps
CPU time 26.3 seconds
Started Feb 21 03:17:18 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 656180 kb
Host smart-fe15cb1e-0eeb-47cf-974b-cc2876de812f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729576967 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3729576967
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.17075844
Short name T805
Test name
Test status
Simulation time 820221312 ps
CPU time 4.79 seconds
Started Feb 21 03:17:31 PM PST 24
Finished Feb 21 03:17:36 PM PST 24
Peak memory 212892 kb
Host smart-f385598e-8deb-4655-b4aa-69f0291b4248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075844 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.i2c_target_perf.17075844
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.3130298712
Short name T1171
Test name
Test status
Simulation time 1837561187 ps
CPU time 12.36 seconds
Started Feb 21 03:17:35 PM PST 24
Finished Feb 21 03:17:47 PM PST 24
Peak memory 203304 kb
Host smart-3fd7e752-37a1-4ff2-b69c-f2c9324a0de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130298712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.3130298712
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.2327942484
Short name T776
Test name
Test status
Simulation time 32367691275 ps
CPU time 243.03 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:21:30 PM PST 24
Peak memory 1534624 kb
Host smart-4db2140b-6db2-4958-90b2-a4a241bfbc46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327942484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.2327942484
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1339335170
Short name T465
Test name
Test status
Simulation time 597407537 ps
CPU time 23.97 seconds
Started Feb 21 03:17:16 PM PST 24
Finished Feb 21 03:17:41 PM PST 24
Peak memory 203200 kb
Host smart-324d6b57-1f56-47de-846f-efc0ed798d1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339335170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1339335170
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3686759431
Short name T598
Test name
Test status
Simulation time 13608881663 ps
CPU time 24.4 seconds
Started Feb 21 03:17:25 PM PST 24
Finished Feb 21 03:17:50 PM PST 24
Peak memory 696364 kb
Host smart-bb6988ba-8c27-46e8-8167-7afc4c6e2b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686759431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3686759431
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3500072733
Short name T281
Test name
Test status
Simulation time 15543899839 ps
CPU time 2354.75 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:56:42 PM PST 24
Peak memory 3847040 kb
Host smart-c927a311-e044-4e9f-a08e-bd0c95ffc013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500072733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3500072733
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.4148009275
Short name T408
Test name
Test status
Simulation time 1612423045 ps
CPU time 6.84 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:17:33 PM PST 24
Peak memory 212204 kb
Host smart-92515856-8a41-4f0e-9b86-652873e7cbfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148009275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.4148009275
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_ovf.2077846086
Short name T886
Test name
Test status
Simulation time 5606782330 ps
CPU time 32.86 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:18:00 PM PST 24
Peak memory 214276 kb
Host smart-d660a06c-be23-4040-8050-04aefc590c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077846086 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_tx_ovf.2077846086
Directory /workspace/30.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.4182423216
Short name T673
Test name
Test status
Simulation time 1278960508 ps
CPU time 6.32 seconds
Started Feb 21 03:17:24 PM PST 24
Finished Feb 21 03:17:31 PM PST 24
Peak memory 212820 kb
Host smart-36083a3c-5af7-41ad-b31e-847d3d5d4b77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182423216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.4182423216
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.923534705
Short name T337
Test name
Test status
Simulation time 18583559 ps
CPU time 0.62 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:17:43 PM PST 24
Peak memory 202076 kb
Host smart-298328c5-7658-4cfd-a26d-5e1c21c9324e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923534705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.923534705
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2523496208
Short name T263
Test name
Test status
Simulation time 50384897 ps
CPU time 1.28 seconds
Started Feb 21 03:17:15 PM PST 24
Finished Feb 21 03:17:17 PM PST 24
Peak memory 211556 kb
Host smart-1d0e3e27-face-4ff1-be73-85c5092b854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523496208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2523496208
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.121655113
Short name T630
Test name
Test status
Simulation time 335878056 ps
CPU time 5.59 seconds
Started Feb 21 03:17:15 PM PST 24
Finished Feb 21 03:17:21 PM PST 24
Peak memory 242640 kb
Host smart-7b25e1fb-919c-4587-80f5-a0838e99840b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121655113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.121655113
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.4244671690
Short name T433
Test name
Test status
Simulation time 13938823082 ps
CPU time 152.87 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:20:12 PM PST 24
Peak memory 1039304 kb
Host smart-bba764d5-5c2e-4662-a810-e403fb6cb9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244671690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.4244671690
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.4197059314
Short name T513
Test name
Test status
Simulation time 13756663685 ps
CPU time 155.8 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:20:14 PM PST 24
Peak memory 1006072 kb
Host smart-e9074c7e-f1f3-43b3-9abb-25d188d57fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197059314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.4197059314
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2457322952
Short name T1153
Test name
Test status
Simulation time 135163034 ps
CPU time 1.01 seconds
Started Feb 21 03:17:16 PM PST 24
Finished Feb 21 03:17:18 PM PST 24
Peak memory 203108 kb
Host smart-ab3a20e7-1f94-44e9-bcf1-acb88fee0a12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457322952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2457322952
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2848386516
Short name T1494
Test name
Test status
Simulation time 327570149 ps
CPU time 10.04 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:17:48 PM PST 24
Peak memory 233124 kb
Host smart-f162873b-8729-44f8-bf05-a5897b873e43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848386516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2848386516
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.4040331616
Short name T1387
Test name
Test status
Simulation time 5950531072 ps
CPU time 483.36 seconds
Started Feb 21 03:17:16 PM PST 24
Finished Feb 21 03:25:20 PM PST 24
Peak memory 1330956 kb
Host smart-5db73f04-d56f-4184-9807-55e07eec6f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040331616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4040331616
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.483913181
Short name T1307
Test name
Test status
Simulation time 15003071394 ps
CPU time 187.82 seconds
Started Feb 21 03:17:54 PM PST 24
Finished Feb 21 03:21:02 PM PST 24
Peak memory 251488 kb
Host smart-d6b4fa6a-449d-43e7-ad58-c39f9fa7b672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483913181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.483913181
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2608446180
Short name T970
Test name
Test status
Simulation time 48321979 ps
CPU time 0.68 seconds
Started Feb 21 03:17:19 PM PST 24
Finished Feb 21 03:17:20 PM PST 24
Peak memory 202128 kb
Host smart-06b30c57-a29e-4b75-a860-bfb0196f1a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608446180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2608446180
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2646263354
Short name T976
Test name
Test status
Simulation time 7368396157 ps
CPU time 309.35 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:22:48 PM PST 24
Peak memory 211556 kb
Host smart-435a1955-5e38-4d43-926f-281eead47a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646263354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2646263354
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_rx_oversample.3169380304
Short name T1408
Test name
Test status
Simulation time 2529748860 ps
CPU time 161.67 seconds
Started Feb 21 03:17:37 PM PST 24
Finished Feb 21 03:20:19 PM PST 24
Peak memory 266388 kb
Host smart-f6d30e58-8473-4027-aa43-29ed5b73c974
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169380304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_rx_oversample
.3169380304
Directory /workspace/31.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.858171787
Short name T346
Test name
Test status
Simulation time 16865126505 ps
CPU time 103.11 seconds
Started Feb 21 03:17:27 PM PST 24
Finished Feb 21 03:19:11 PM PST 24
Peak memory 427872 kb
Host smart-1b702e6b-92a8-49f8-b674-324eec471ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858171787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.858171787
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.146526609
Short name T150
Test name
Test status
Simulation time 36067506720 ps
CPU time 382.13 seconds
Started Feb 21 03:17:37 PM PST 24
Finished Feb 21 03:24:00 PM PST 24
Peak memory 1603360 kb
Host smart-06f99ca7-c274-427d-9064-3da1b7845777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146526609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.146526609
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1116606785
Short name T890
Test name
Test status
Simulation time 853000147 ps
CPU time 36.99 seconds
Started Feb 21 03:17:18 PM PST 24
Finished Feb 21 03:17:55 PM PST 24
Peak memory 211508 kb
Host smart-1c0562cb-7007-4215-9d52-58bc578e723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116606785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1116606785
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.255139273
Short name T688
Test name
Test status
Simulation time 699675545 ps
CPU time 3.12 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:18:00 PM PST 24
Peak memory 203336 kb
Host smart-14cb8410-2c07-4dbe-9805-dfbc9607d464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255139273 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.255139273
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3840175406
Short name T284
Test name
Test status
Simulation time 10085204524 ps
CPU time 51.15 seconds
Started Feb 21 03:17:16 PM PST 24
Finished Feb 21 03:18:08 PM PST 24
Peak memory 439632 kb
Host smart-98f91e3b-98ff-4303-b214-50a75bc252c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840175406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3840175406
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3487609083
Short name T18
Test name
Test status
Simulation time 10349695069 ps
CPU time 13.55 seconds
Started Feb 21 03:17:36 PM PST 24
Finished Feb 21 03:17:50 PM PST 24
Peak memory 313944 kb
Host smart-78868962-10f8-4e73-a44b-af0e1d20a684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487609083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3487609083
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1670214002
Short name T812
Test name
Test status
Simulation time 2075195146 ps
CPU time 2.33 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 203348 kb
Host smart-76b02b80-2233-43a6-80ad-eda7e80b158c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670214002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1670214002
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3163859273
Short name T1360
Test name
Test status
Simulation time 2106280417 ps
CPU time 7.68 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:17:34 PM PST 24
Peak memory 203344 kb
Host smart-c7a1ed27-db9b-4916-86fd-0007ec9905ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163859273 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3163859273
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.63758219
Short name T1140
Test name
Test status
Simulation time 6395728196 ps
CPU time 15.41 seconds
Started Feb 21 03:17:29 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 478964 kb
Host smart-f62f7e58-672c-4117-8aed-1b8f8199cf40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63758219 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.63758219
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.3699618409
Short name T512
Test name
Test status
Simulation time 556555397 ps
CPU time 3.16 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 203440 kb
Host smart-db1d7a76-e2e5-4e47-b917-dbf417111553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699618409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.3699618409
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2475067507
Short name T1046
Test name
Test status
Simulation time 2217521148 ps
CPU time 13.43 seconds
Started Feb 21 03:17:19 PM PST 24
Finished Feb 21 03:17:33 PM PST 24
Peak memory 203464 kb
Host smart-4057d053-3220-477e-a100-708071e1ddb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475067507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2475067507
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.2410545287
Short name T1284
Test name
Test status
Simulation time 43532278215 ps
CPU time 214.15 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:21:14 PM PST 24
Peak memory 1217624 kb
Host smart-cc261f56-5c8c-4e9c-86e3-09a7e566fe5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410545287 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.2410545287
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.4160151872
Short name T234
Test name
Test status
Simulation time 2048343038 ps
CPU time 18.05 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 205196 kb
Host smart-7f46a72e-e320-4f43-974b-1199674cdd6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160151872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.4160151872
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1356004871
Short name T774
Test name
Test status
Simulation time 37331866740 ps
CPU time 188.17 seconds
Started Feb 21 03:17:26 PM PST 24
Finished Feb 21 03:20:35 PM PST 24
Peak memory 2141660 kb
Host smart-bca6d435-17d9-4cae-87a5-8124cfdddc2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356004871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1356004871
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2372394108
Short name T1215
Test name
Test status
Simulation time 31128959906 ps
CPU time 85.59 seconds
Started Feb 21 03:17:28 PM PST 24
Finished Feb 21 03:18:54 PM PST 24
Peak memory 816188 kb
Host smart-4beb9987-0905-4c84-bc80-86afcc6ea0c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372394108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2372394108
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3627778573
Short name T22
Test name
Test status
Simulation time 8127830347 ps
CPU time 7.73 seconds
Started Feb 21 03:17:49 PM PST 24
Finished Feb 21 03:17:57 PM PST 24
Peak memory 209072 kb
Host smart-064b0d91-124d-4557-9f17-ff3210899ed0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627778573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3627778573
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_ovf.4039362357
Short name T517
Test name
Test status
Simulation time 7516431150 ps
CPU time 249.7 seconds
Started Feb 21 03:17:16 PM PST 24
Finished Feb 21 03:21:26 PM PST 24
Peak memory 473972 kb
Host smart-8628b25c-35af-4fbc-bd91-a0bf0430f973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039362357 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_tx_ovf.4039362357
Directory /workspace/31.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.3763271485
Short name T1161
Test name
Test status
Simulation time 5003864590 ps
CPU time 6.44 seconds
Started Feb 21 03:17:37 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 203452 kb
Host smart-6f1d4e47-b825-4924-b2a0-9f309682f319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763271485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.i2c_target_unexp_stop.3763271485
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1562944929
Short name T824
Test name
Test status
Simulation time 48358264 ps
CPU time 0.61 seconds
Started Feb 21 03:17:53 PM PST 24
Finished Feb 21 03:17:54 PM PST 24
Peak memory 202088 kb
Host smart-30dce39d-a94f-4e99-97db-843cadcd955f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562944929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1562944929
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.597839374
Short name T1490
Test name
Test status
Simulation time 126142344 ps
CPU time 1.27 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:17:40 PM PST 24
Peak memory 203320 kb
Host smart-ad62cbdf-70e9-49ad-9061-7176073e0aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597839374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.597839374
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3598470594
Short name T21
Test name
Test status
Simulation time 1016804216 ps
CPU time 6.03 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:17:58 PM PST 24
Peak memory 255060 kb
Host smart-95f10cc4-0a21-4856-831c-4c93247d835e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598470594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3598470594
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2307823659
Short name T221
Test name
Test status
Simulation time 5938834031 ps
CPU time 183.8 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:20:56 PM PST 24
Peak memory 610648 kb
Host smart-54d2b6fb-2242-4e0f-9650-6a1cf9209242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307823659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2307823659
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2943887671
Short name T104
Test name
Test status
Simulation time 5707150027 ps
CPU time 387.26 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:24:09 PM PST 24
Peak memory 1586816 kb
Host smart-7699fee6-0c61-4909-be2b-3abc3c2fcc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943887671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2943887671
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3152101036
Short name T41
Test name
Test status
Simulation time 385358887 ps
CPU time 0.91 seconds
Started Feb 21 03:17:51 PM PST 24
Finished Feb 21 03:17:52 PM PST 24
Peak memory 203052 kb
Host smart-39141879-a128-48ba-8608-aabbbbba8e20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152101036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3152101036
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3661342110
Short name T978
Test name
Test status
Simulation time 166638924 ps
CPU time 5.03 seconds
Started Feb 21 03:17:40 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 233196 kb
Host smart-cec04ef2-0304-4ce1-8b12-10074519a3e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661342110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3661342110
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3169066337
Short name T1370
Test name
Test status
Simulation time 20832744865 ps
CPU time 279.5 seconds
Started Feb 21 03:17:54 PM PST 24
Finished Feb 21 03:22:34 PM PST 24
Peak memory 1535080 kb
Host smart-c147982b-9303-478f-81c3-755421406e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169066337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3169066337
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_override.912806610
Short name T495
Test name
Test status
Simulation time 43389088 ps
CPU time 0.64 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:17:40 PM PST 24
Peak memory 202960 kb
Host smart-36944c56-dbb1-472b-842b-30c9ef629358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912806610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.912806610
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.921833629
Short name T986
Test name
Test status
Simulation time 32093738177 ps
CPU time 101.78 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:19:24 PM PST 24
Peak memory 316404 kb
Host smart-047d3b1f-ed93-4c43-a208-2a6b804c1c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921833629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.921833629
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_rx_oversample.3905196385
Short name T264
Test name
Test status
Simulation time 2276017981 ps
CPU time 76.68 seconds
Started Feb 21 03:17:54 PM PST 24
Finished Feb 21 03:19:11 PM PST 24
Peak memory 299292 kb
Host smart-bbf47c8b-857e-467c-8d57-5e880f02a947
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905196385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_rx_oversample
.3905196385
Directory /workspace/32.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2858921331
Short name T344
Test name
Test status
Simulation time 1512868456 ps
CPU time 95.85 seconds
Started Feb 21 03:17:54 PM PST 24
Finished Feb 21 03:19:30 PM PST 24
Peak memory 244336 kb
Host smart-1d251fcc-644f-40b1-a85d-e31e23be1304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858921331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2858921331
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2657860001
Short name T1484
Test name
Test status
Simulation time 1040929870 ps
CPU time 7.96 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:17:47 PM PST 24
Peak memory 211588 kb
Host smart-e7c47e79-8956-49c9-b7f3-4f353e726248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657860001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2657860001
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1003144494
Short name T262
Test name
Test status
Simulation time 1275340689 ps
CPU time 4.54 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:17:47 PM PST 24
Peak memory 203384 kb
Host smart-585dc231-895b-46db-9443-13af0275331f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003144494 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1003144494
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1986430427
Short name T636
Test name
Test status
Simulation time 10033097115 ps
CPU time 72.66 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:18:54 PM PST 24
Peak memory 529960 kb
Host smart-afa6c001-c1bb-4ff2-b525-0304c6af625f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986430427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1986430427
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.243972470
Short name T826
Test name
Test status
Simulation time 10072667089 ps
CPU time 81.23 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:19:03 PM PST 24
Peak memory 692204 kb
Host smart-6f608012-ed42-459b-8e99-0b680ca03361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243972470 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_tx.243972470
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.2293845373
Short name T1055
Test name
Test status
Simulation time 475934168 ps
CPU time 2.86 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:18:00 PM PST 24
Peak memory 203368 kb
Host smart-77d6f48c-39c6-49ad-96d4-260c0848faac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293845373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.2293845373
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3966388034
Short name T526
Test name
Test status
Simulation time 1684717783 ps
CPU time 6.39 seconds
Started Feb 21 03:17:37 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 203312 kb
Host smart-5f7da265-40e3-4d0b-abf8-0bdaf29838ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966388034 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3966388034
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.275904552
Short name T360
Test name
Test status
Simulation time 6825134536 ps
CPU time 72.57 seconds
Started Feb 21 03:17:53 PM PST 24
Finished Feb 21 03:19:06 PM PST 24
Peak memory 1374604 kb
Host smart-a6318def-c836-4c47-bd26-f4b598749559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275904552 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.275904552
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.3127388707
Short name T555
Test name
Test status
Simulation time 828443420 ps
CPU time 4.83 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 206180 kb
Host smart-7899e6ee-d246-4f84-b02d-3381554dd9cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127388707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_perf.3127388707
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2009108874
Short name T523
Test name
Test status
Simulation time 1408688484 ps
CPU time 37.6 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:18:19 PM PST 24
Peak memory 203376 kb
Host smart-334c7ec5-56b1-49bd-92c3-3e0cf9445853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009108874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2009108874
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.29501544
Short name T158
Test name
Test status
Simulation time 6902529053 ps
CPU time 75.36 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:18:54 PM PST 24
Peak memory 204060 kb
Host smart-5dd95066-73e8-47b9-b083-42a49e00f19a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stress_rd.29501544
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2370498176
Short name T1028
Test name
Test status
Simulation time 22696892491 ps
CPU time 540.69 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:26:43 PM PST 24
Peak memory 4232464 kb
Host smart-d834c0eb-1a9e-4fed-99dc-832f47796166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370498176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2370498176
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1380563287
Short name T514
Test name
Test status
Simulation time 34507894454 ps
CPU time 437.52 seconds
Started Feb 21 03:17:50 PM PST 24
Finished Feb 21 03:25:08 PM PST 24
Peak memory 2294588 kb
Host smart-f67151d2-75cc-4d98-83e7-dc784d4fd8eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380563287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1380563287
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2447409737
Short name T1351
Test name
Test status
Simulation time 3683855525 ps
CPU time 6.88 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:17:49 PM PST 24
Peak memory 203436 kb
Host smart-64268595-0e73-45c4-8d4b-717189db958b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447409737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2447409737
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_ovf.2319230109
Short name T460
Test name
Test status
Simulation time 2893389306 ps
CPU time 128.42 seconds
Started Feb 21 03:17:40 PM PST 24
Finished Feb 21 03:19:49 PM PST 24
Peak memory 417612 kb
Host smart-1df36296-eff0-448e-a51e-d016ac08f8e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319230109 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_tx_ovf.2319230109
Directory /workspace/32.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.3079068955
Short name T466
Test name
Test status
Simulation time 3297515658 ps
CPU time 7.15 seconds
Started Feb 21 03:17:53 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 204096 kb
Host smart-a09d4c91-da7a-4c89-a096-617794a01317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079068955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.3079068955
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.81688358
Short name T564
Test name
Test status
Simulation time 16970590 ps
CPU time 0.61 seconds
Started Feb 21 03:17:53 PM PST 24
Finished Feb 21 03:17:54 PM PST 24
Peak memory 202540 kb
Host smart-39211392-d8f0-4b82-9384-2f75d10e5101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81688358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.81688358
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3687074255
Short name T533
Test name
Test status
Simulation time 325206298 ps
CPU time 1.71 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:17:44 PM PST 24
Peak memory 211508 kb
Host smart-fb8cc6be-d717-4354-8266-7fe55c3ab0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687074255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3687074255
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1489660466
Short name T901
Test name
Test status
Simulation time 966100367 ps
CPU time 4.57 seconds
Started Feb 21 03:17:43 PM PST 24
Finished Feb 21 03:17:47 PM PST 24
Peak memory 251340 kb
Host smart-819b78a9-7987-413c-88ac-d0339beb2649
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489660466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1489660466
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.4021064146
Short name T1098
Test name
Test status
Simulation time 2317994382 ps
CPU time 93.32 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:19:15 PM PST 24
Peak memory 774184 kb
Host smart-1b80ca77-b5a8-4069-abee-1beee27f6448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021064146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.4021064146
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.123426968
Short name T331
Test name
Test status
Simulation time 87497749001 ps
CPU time 448.52 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:25:26 PM PST 24
Peak memory 1765372 kb
Host smart-b271a0a2-76ea-4ab4-b4f3-87ee8b879e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123426968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.123426968
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.386770023
Short name T1223
Test name
Test status
Simulation time 119174664 ps
CPU time 0.88 seconds
Started Feb 21 03:17:51 PM PST 24
Finished Feb 21 03:17:52 PM PST 24
Peak memory 203056 kb
Host smart-42d57e30-c616-493a-af81-df794ccb9d10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386770023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.386770023
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.88557515
Short name T1243
Test name
Test status
Simulation time 980135872 ps
CPU time 5.84 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 203380 kb
Host smart-a5d14a9d-51d8-4fe5-921e-97c0a7d2b71b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88557515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.88557515
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2862295133
Short name T952
Test name
Test status
Simulation time 6687646111 ps
CPU time 402.95 seconds
Started Feb 21 03:17:50 PM PST 24
Finished Feb 21 03:24:34 PM PST 24
Peak memory 1775496 kb
Host smart-4efd5b2c-f011-4d4e-a724-50d25e170e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862295133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2862295133
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.3276726820
Short name T1244
Test name
Test status
Simulation time 3807690916 ps
CPU time 60.66 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:18:40 PM PST 24
Peak memory 294764 kb
Host smart-3bcaccc4-ba96-47b6-acef-5427a12607fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276726820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.3276726820
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.379971756
Short name T1303
Test name
Test status
Simulation time 40777292 ps
CPU time 0.65 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:17:56 PM PST 24
Peak memory 202312 kb
Host smart-5c8e0408-7cbb-4c67-b73d-0decbcc03397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379971756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.379971756
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.2709096850
Short name T26
Test name
Test status
Simulation time 3258692224 ps
CPU time 39.75 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:18:22 PM PST 24
Peak memory 221036 kb
Host smart-3c6c60cf-1ded-4c86-989b-b4064d1fdd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709096850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2709096850
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_rx_oversample.3050750120
Short name T755
Test name
Test status
Simulation time 4255905127 ps
CPU time 81.43 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:19:01 PM PST 24
Peak memory 284696 kb
Host smart-9487ebc0-4ae0-496c-97a9-cdfb4608b76e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050750120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_rx_oversample
.3050750120
Directory /workspace/33.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2297500140
Short name T432
Test name
Test status
Simulation time 1621006234 ps
CPU time 84.26 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:19:07 PM PST 24
Peak memory 232436 kb
Host smart-036765fa-297c-48d4-9595-54fd0a304fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297500140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2297500140
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.3895652774
Short name T143
Test name
Test status
Simulation time 59499849332 ps
CPU time 2509.1 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:59:32 PM PST 24
Peak memory 1963308 kb
Host smart-f4a18cd2-c3d4-4af0-a5c4-b4b0b9789556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895652774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3895652774
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.3340243029
Short name T302
Test name
Test status
Simulation time 3842696219 ps
CPU time 34.26 seconds
Started Feb 21 03:17:54 PM PST 24
Finished Feb 21 03:18:28 PM PST 24
Peak memory 211524 kb
Host smart-cce9e04a-70f0-40cb-bbd7-1bdec19cc0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340243029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3340243029
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.4098947426
Short name T915
Test name
Test status
Simulation time 1339030161 ps
CPU time 4.91 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:17:47 PM PST 24
Peak memory 203332 kb
Host smart-cf253994-8b76-47f4-8742-87f0d4afa4a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098947426 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.4098947426
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2798751838
Short name T704
Test name
Test status
Simulation time 10175592972 ps
CPU time 6.11 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:17:48 PM PST 24
Peak memory 227152 kb
Host smart-8a7ce0bc-1102-4f62-8df9-86f9f7070b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798751838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2798751838
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2927339812
Short name T1504
Test name
Test status
Simulation time 10082403123 ps
CPU time 65.87 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:19:03 PM PST 24
Peak memory 583880 kb
Host smart-e891794e-1841-4ada-b3fc-efe36936f75e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927339812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2927339812
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1233216760
Short name T1487
Test name
Test status
Simulation time 710548615 ps
CPU time 3.18 seconds
Started Feb 21 03:17:51 PM PST 24
Finished Feb 21 03:17:54 PM PST 24
Peak memory 203444 kb
Host smart-50e4777e-d8a7-4130-a247-9c61bc3768d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233216760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1233216760
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2199280319
Short name T591
Test name
Test status
Simulation time 1300496802 ps
CPU time 4.69 seconds
Started Feb 21 03:17:51 PM PST 24
Finished Feb 21 03:17:56 PM PST 24
Peak memory 203424 kb
Host smart-f4a8de4d-394e-42af-8e70-1d5a13381ac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199280319 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2199280319
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.867766793
Short name T388
Test name
Test status
Simulation time 4457413211 ps
CPU time 35.57 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:18:33 PM PST 24
Peak memory 857640 kb
Host smart-6de30248-13be-40a1-b9b8-54fec8fc8392
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867766793 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.867766793
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3942116474
Short name T329
Test name
Test status
Simulation time 612608781 ps
CPU time 3.63 seconds
Started Feb 21 03:17:38 PM PST 24
Finished Feb 21 03:17:43 PM PST 24
Peak memory 205628 kb
Host smart-e0e449d6-c9f0-463c-b621-80ad98c515b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942116474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3942116474
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.4222289229
Short name T829
Test name
Test status
Simulation time 1140975670 ps
CPU time 14.48 seconds
Started Feb 21 03:17:42 PM PST 24
Finished Feb 21 03:17:57 PM PST 24
Peak memory 203428 kb
Host smart-b7c347b7-6422-4bce-b7b9-7afcc9928652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222289229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.4222289229
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.1189342171
Short name T23
Test name
Test status
Simulation time 41381071232 ps
CPU time 2448.21 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:58:28 PM PST 24
Peak memory 2646500 kb
Host smart-17eb1af2-b089-40c8-a8df-e3e27f1513d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189342171 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.1189342171
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3278175251
Short name T366
Test name
Test status
Simulation time 15638130214 ps
CPU time 27.09 seconds
Started Feb 21 03:17:37 PM PST 24
Finished Feb 21 03:18:04 PM PST 24
Peak memory 229556 kb
Host smart-7e8513e3-ca1a-4e60-9724-e8a72b3372ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278175251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3278175251
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2694535533
Short name T20
Test name
Test status
Simulation time 29881146994 ps
CPU time 1068.11 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:35:46 PM PST 24
Peak memory 6458556 kb
Host smart-c6530815-a23b-41a5-912e-f96716e8799b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694535533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2694535533
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1763347535
Short name T642
Test name
Test status
Simulation time 30693284371 ps
CPU time 681.67 seconds
Started Feb 21 03:17:41 PM PST 24
Finished Feb 21 03:29:03 PM PST 24
Peak memory 1780324 kb
Host smart-4f2b877f-1b63-4d37-937a-d5bfbc5120e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763347535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1763347535
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.175969274
Short name T1359
Test name
Test status
Simulation time 6786443846 ps
CPU time 9.1 seconds
Started Feb 21 03:17:39 PM PST 24
Finished Feb 21 03:17:49 PM PST 24
Peak memory 211884 kb
Host smart-4ca6e8a2-296c-4db1-9b6b-427156c4fbb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175969274 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_timeout.175969274
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_ovf.604888198
Short name T949
Test name
Test status
Simulation time 2327849448 ps
CPU time 108.55 seconds
Started Feb 21 03:17:53 PM PST 24
Finished Feb 21 03:19:42 PM PST 24
Peak memory 340284 kb
Host smart-943f4753-ea94-4fe3-9daf-9e5239c88ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604888198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_tx_ovf.604888198
Directory /workspace/33.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.3956437001
Short name T1317
Test name
Test status
Simulation time 6233599343 ps
CPU time 7.38 seconds
Started Feb 21 03:17:49 PM PST 24
Finished Feb 21 03:17:57 PM PST 24
Peak memory 210408 kb
Host smart-ab1917e5-c603-4b1a-af73-ec04c875ccd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956437001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.i2c_target_unexp_stop.3956437001
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1132139257
Short name T685
Test name
Test status
Simulation time 43097355 ps
CPU time 0.61 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:17:53 PM PST 24
Peak memory 202972 kb
Host smart-754ce13f-b39d-41d6-a1d5-5aff4b3771bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132139257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1132139257
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3707394915
Short name T54
Test name
Test status
Simulation time 160569887 ps
CPU time 1.3 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:17:53 PM PST 24
Peak memory 211408 kb
Host smart-1e264e80-fd39-48c5-88c0-a3ac11255c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707394915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3707394915
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3310428825
Short name T251
Test name
Test status
Simulation time 664285506 ps
CPU time 3.61 seconds
Started Feb 21 03:17:58 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 224188 kb
Host smart-abad150a-36ab-4296-8a25-495e68fa32d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310428825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3310428825
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1368682317
Short name T410
Test name
Test status
Simulation time 12350921852 ps
CPU time 87.77 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:19:23 PM PST 24
Peak memory 751360 kb
Host smart-4a668e4a-dcc3-4b67-b7d2-04a69ec47b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368682317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1368682317
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2162655981
Short name T1214
Test name
Test status
Simulation time 5674744700 ps
CPU time 774.57 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:30:52 PM PST 24
Peak memory 1646692 kb
Host smart-de316a4b-64fa-4af1-8657-618e719da06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162655981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2162655981
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1921059874
Short name T907
Test name
Test status
Simulation time 271843449 ps
CPU time 1 seconds
Started Feb 21 03:17:50 PM PST 24
Finished Feb 21 03:17:52 PM PST 24
Peak memory 203308 kb
Host smart-288afbd3-40fb-4359-ae9e-cbf50376c27c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921059874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1921059874
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.967373589
Short name T572
Test name
Test status
Simulation time 852552552 ps
CPU time 5.5 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 203308 kb
Host smart-a1421565-d6ea-431b-b99b-38e723294c70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967373589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
967373589
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3797499076
Short name T141
Test name
Test status
Simulation time 7288207492 ps
CPU time 401.75 seconds
Started Feb 21 03:18:06 PM PST 24
Finished Feb 21 03:24:48 PM PST 24
Peak memory 1871272 kb
Host smart-bad17dd6-fe4a-4333-bba1-dce04862634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797499076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3797499076
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.504838931
Short name T542
Test name
Test status
Simulation time 5628581786 ps
CPU time 73.21 seconds
Started Feb 21 03:18:16 PM PST 24
Finished Feb 21 03:19:30 PM PST 24
Peak memory 234904 kb
Host smart-09936b46-5766-46b9-a304-4c933ced68fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504838931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.504838931
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1797396442
Short name T5
Test name
Test status
Simulation time 47366100 ps
CPU time 0.63 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:17:53 PM PST 24
Peak memory 202252 kb
Host smart-fd55d0f2-1826-4c12-9249-f3303af4621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797396442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1797396442
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1379697937
Short name T361
Test name
Test status
Simulation time 1179124257 ps
CPU time 57.45 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:18:49 PM PST 24
Peak memory 203284 kb
Host smart-810e278a-f138-4e47-be02-23c8b20f0220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379697937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1379697937
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_rx_oversample.3352271111
Short name T30
Test name
Test status
Simulation time 8442135345 ps
CPU time 154.96 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:20:31 PM PST 24
Peak memory 268544 kb
Host smart-e13250a0-faa1-49c1-bced-a56cf20d5c0a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352271111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_rx_oversample
.3352271111
Directory /workspace/34.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2365343496
Short name T1120
Test name
Test status
Simulation time 5026891827 ps
CPU time 85.49 seconds
Started Feb 21 03:17:40 PM PST 24
Finished Feb 21 03:19:07 PM PST 24
Peak memory 325380 kb
Host smart-3cbdfa36-f3c0-4f0f-95ba-fad7f8eaab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365343496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2365343496
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2689400419
Short name T844
Test name
Test status
Simulation time 2493382680 ps
CPU time 16.08 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:18:12 PM PST 24
Peak memory 219792 kb
Host smart-cc0f0c30-a120-48f1-8d3a-ba3a3733be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689400419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2689400419
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.3257075182
Short name T1185
Test name
Test status
Simulation time 881312219 ps
CPU time 3.65 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:17:56 PM PST 24
Peak memory 203384 kb
Host smart-9891eab3-e965-4480-9260-aa771e70a97f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257075182 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3257075182
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3973596762
Short name T1112
Test name
Test status
Simulation time 11605654058 ps
CPU time 5.54 seconds
Started Feb 21 03:17:58 PM PST 24
Finished Feb 21 03:18:03 PM PST 24
Peak memory 223648 kb
Host smart-a307f767-5d42-46fd-90ee-ba0087c26c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973596762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3973596762
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.630976614
Short name T324
Test name
Test status
Simulation time 10697193301 ps
CPU time 7.2 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:18:00 PM PST 24
Peak memory 246988 kb
Host smart-ede464c4-cce1-40f3-b055-58f92a0aecd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630976614 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.630976614
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3907110499
Short name T333
Test name
Test status
Simulation time 1341495280 ps
CPU time 6.21 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 203380 kb
Host smart-f6e8950b-8f18-4742-8756-19484c047b41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907110499 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3907110499
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1898174891
Short name T827
Test name
Test status
Simulation time 7513718494 ps
CPU time 26.52 seconds
Started Feb 21 03:17:58 PM PST 24
Finished Feb 21 03:18:24 PM PST 24
Peak memory 614236 kb
Host smart-a70ff505-0427-45f3-a05d-7f4b83ac12be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898174891 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1898174891
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.1266619742
Short name T1211
Test name
Test status
Simulation time 1339608809 ps
CPU time 4.17 seconds
Started Feb 21 03:18:09 PM PST 24
Finished Feb 21 03:18:13 PM PST 24
Peak memory 208836 kb
Host smart-6d2e8bec-1ffa-4c5b-9647-79a6b6a2e69d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266619742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.1266619742
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1480120725
Short name T440
Test name
Test status
Simulation time 1506000770 ps
CPU time 19.71 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:18:15 PM PST 24
Peak memory 203420 kb
Host smart-3292b3c2-9fb7-46c9-8a42-6fc4402a7753
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480120725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1480120725
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3615911567
Short name T439
Test name
Test status
Simulation time 705170223 ps
CPU time 14.78 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:18:11 PM PST 24
Peak memory 203392 kb
Host smart-82223b8e-cefa-4648-8eba-efed413fdacc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615911567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3615911567
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.595454948
Short name T146
Test name
Test status
Simulation time 46280194233 ps
CPU time 49.55 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:18:47 PM PST 24
Peak memory 622328 kb
Host smart-53cf9e0e-ee18-41ca-82e4-79f08f9462fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595454948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.595454948
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1953579312
Short name T1415
Test name
Test status
Simulation time 2865922190 ps
CPU time 6.85 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:18:03 PM PST 24
Peak memory 207608 kb
Host smart-d406262f-093b-4d8a-9360-e2041db50e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953579312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1953579312
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_ovf.2476938885
Short name T822
Test name
Test status
Simulation time 16236872577 ps
CPU time 243.14 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:22:00 PM PST 24
Peak memory 470636 kb
Host smart-b3dd70a7-d490-483a-a3f1-0e6c52d9bfba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476938885 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_tx_ovf.2476938885
Directory /workspace/34.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.1793519801
Short name T377
Test name
Test status
Simulation time 1866132839 ps
CPU time 8.34 seconds
Started Feb 21 03:17:51 PM PST 24
Finished Feb 21 03:17:59 PM PST 24
Peak memory 203420 kb
Host smart-45b55815-5669-4faa-83e5-3209bc4f424f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793519801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.1793519801
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.1797869395
Short name T627
Test name
Test status
Simulation time 49396919 ps
CPU time 0.59 seconds
Started Feb 21 03:18:17 PM PST 24
Finished Feb 21 03:18:19 PM PST 24
Peak memory 202116 kb
Host smart-e49b33d4-ba31-4920-8284-a89415384c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797869395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1797869395
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.137144282
Short name T878
Test name
Test status
Simulation time 118508904 ps
CPU time 1.2 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:17:57 PM PST 24
Peak memory 211464 kb
Host smart-ad7c775f-8d0a-4e84-b5ed-474f0094172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137144282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.137144282
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1170503362
Short name T461
Test name
Test status
Simulation time 1793136250 ps
CPU time 5.4 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 252404 kb
Host smart-02cd5fa5-d26b-4ec2-bf18-996d9d45eaab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170503362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1170503362
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1848360644
Short name T1466
Test name
Test status
Simulation time 5488813756 ps
CPU time 94.81 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:19:31 PM PST 24
Peak memory 875200 kb
Host smart-8182f43c-211f-4cb5-b160-2f2f1b279231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848360644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1848360644
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3022069117
Short name T855
Test name
Test status
Simulation time 26099174296 ps
CPU time 509.18 seconds
Started Feb 21 03:18:07 PM PST 24
Finished Feb 21 03:26:37 PM PST 24
Peak memory 1780556 kb
Host smart-899371c5-1dcf-4a3c-909a-7cefccb17fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022069117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3022069117
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2234373512
Short name T42
Test name
Test status
Simulation time 200963575 ps
CPU time 0.85 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:17:53 PM PST 24
Peak memory 203060 kb
Host smart-9155164e-678a-4142-9486-449e4e6ccb52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234373512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2234373512
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1647722151
Short name T896
Test name
Test status
Simulation time 353565011 ps
CPU time 4.04 seconds
Started Feb 21 03:17:58 PM PST 24
Finished Feb 21 03:18:02 PM PST 24
Peak memory 203268 kb
Host smart-679b0137-53fe-45c7-b63d-1f61b1a08377
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647722151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1647722151
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3674722096
Short name T569
Test name
Test status
Simulation time 6509634723 ps
CPU time 759.65 seconds
Started Feb 21 03:18:16 PM PST 24
Finished Feb 21 03:30:56 PM PST 24
Peak memory 1824276 kb
Host smart-638ccc2f-42ba-4e9c-b7f8-d8210c2135de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674722096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3674722096
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2008522472
Short name T761
Test name
Test status
Simulation time 8500115837 ps
CPU time 105.56 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:19:43 PM PST 24
Peak memory 259168 kb
Host smart-337f53f1-f7b7-4130-bf71-fb6b930dbde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008522472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2008522472
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1353889404
Short name T1432
Test name
Test status
Simulation time 38724172 ps
CPU time 0.63 seconds
Started Feb 21 03:17:50 PM PST 24
Finished Feb 21 03:17:51 PM PST 24
Peak memory 202240 kb
Host smart-928ea767-d142-4b61-90de-d6f680218420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353889404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1353889404
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2812880805
Short name T563
Test name
Test status
Simulation time 24944637279 ps
CPU time 373.85 seconds
Started Feb 21 03:17:55 PM PST 24
Finished Feb 21 03:24:10 PM PST 24
Peak memory 289856 kb
Host smart-7c89261e-f12d-49b0-885c-b1da135448f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812880805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2812880805
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_rx_oversample.3135823971
Short name T945
Test name
Test status
Simulation time 4162168895 ps
CPU time 208.58 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:21:26 PM PST 24
Peak memory 292204 kb
Host smart-8a023fbd-2146-4e5e-81e8-bc1735096dd4
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135823971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_rx_oversample
.3135823971
Directory /workspace/35.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3133498665
Short name T392
Test name
Test status
Simulation time 2844012440 ps
CPU time 53.58 seconds
Started Feb 21 03:18:05 PM PST 24
Finished Feb 21 03:18:59 PM PST 24
Peak memory 266760 kb
Host smart-63f8fd9c-005a-46b9-a399-fdfbc64f478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133498665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3133498665
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2720619681
Short name T1375
Test name
Test status
Simulation time 67213741705 ps
CPU time 444.7 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:25:21 PM PST 24
Peak memory 1494564 kb
Host smart-002e1bb5-1863-402b-963b-79efdb55f5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720619681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2720619681
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2788717112
Short name T494
Test name
Test status
Simulation time 3408223766 ps
CPU time 12.95 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:18:05 PM PST 24
Peak memory 215832 kb
Host smart-ff60b20b-459b-4cf8-a4f8-8e0db2a64f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788717112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2788717112
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1928105243
Short name T1036
Test name
Test status
Simulation time 2190502829 ps
CPU time 2.62 seconds
Started Feb 21 03:18:17 PM PST 24
Finished Feb 21 03:18:21 PM PST 24
Peak memory 203456 kb
Host smart-a1ddb921-a75c-4cf4-8926-d258e188f824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928105243 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1928105243
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.948603461
Short name T1422
Test name
Test status
Simulation time 10042135569 ps
CPU time 54.09 seconds
Started Feb 21 03:17:54 PM PST 24
Finished Feb 21 03:18:48 PM PST 24
Peak memory 469632 kb
Host smart-d85c8c5f-c5e3-41f7-8287-e4a5a03ee111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948603461 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.948603461
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.921690615
Short name T626
Test name
Test status
Simulation time 10215098633 ps
CPU time 14.03 seconds
Started Feb 21 03:18:10 PM PST 24
Finished Feb 21 03:18:24 PM PST 24
Peak memory 336920 kb
Host smart-b0a7eb65-311f-4480-a41b-526ced2e5cdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921690615 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.921690615
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.1024214613
Short name T1196
Test name
Test status
Simulation time 1142771566 ps
CPU time 2.67 seconds
Started Feb 21 03:18:11 PM PST 24
Finished Feb 21 03:18:14 PM PST 24
Peak memory 203424 kb
Host smart-42b37043-2c9a-44cc-ab9d-1b6cd42a5292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024214613 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.1024214613
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1180987919
Short name T667
Test name
Test status
Simulation time 9269866304 ps
CPU time 4.14 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:18:01 PM PST 24
Peak memory 205156 kb
Host smart-5253df33-2aac-49d1-ade1-caa8da9da357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180987919 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1180987919
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2052800057
Short name T1144
Test name
Test status
Simulation time 4396761179 ps
CPU time 5.9 seconds
Started Feb 21 03:17:52 PM PST 24
Finished Feb 21 03:17:58 PM PST 24
Peak memory 294532 kb
Host smart-9cc0af78-8ccf-4230-8578-a45f7eddfc32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052800057 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2052800057
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.1780740826
Short name T1070
Test name
Test status
Simulation time 2285811804 ps
CPU time 3.19 seconds
Started Feb 21 03:18:18 PM PST 24
Finished Feb 21 03:18:22 PM PST 24
Peak memory 203460 kb
Host smart-f1c1f289-0e9b-46cf-93cd-6304052ab231
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780740826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.1780740826
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3816214484
Short name T108
Test name
Test status
Simulation time 574561774 ps
CPU time 15.05 seconds
Started Feb 21 03:18:08 PM PST 24
Finished Feb 21 03:18:24 PM PST 24
Peak memory 203328 kb
Host smart-66a894b4-2856-4e2f-8140-723c0ed90c5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816214484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3816214484
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1362774793
Short name T696
Test name
Test status
Simulation time 3202718797 ps
CPU time 16.14 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:18:12 PM PST 24
Peak memory 205888 kb
Host smart-719753df-b042-4745-b941-7ac6cba517aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362774793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1362774793
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2407442528
Short name T875
Test name
Test status
Simulation time 37562271063 ps
CPU time 2161.76 seconds
Started Feb 21 03:18:16 PM PST 24
Finished Feb 21 03:54:19 PM PST 24
Peak memory 8545452 kb
Host smart-25e9b00c-4f4b-4a81-9387-077bac94f013
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407442528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2407442528
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.3080425875
Short name T1077
Test name
Test status
Simulation time 17790098361 ps
CPU time 243.9 seconds
Started Feb 21 03:17:56 PM PST 24
Finished Feb 21 03:22:00 PM PST 24
Peak memory 959820 kb
Host smart-e9ddc077-4477-41b5-a469-d83085537c54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080425875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.3080425875
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3821897582
Short name T524
Test name
Test status
Simulation time 7975859344 ps
CPU time 7.21 seconds
Started Feb 21 03:17:57 PM PST 24
Finished Feb 21 03:18:04 PM PST 24
Peak memory 206996 kb
Host smart-143f08cc-698c-403d-ba6c-5cbb6bb8c55c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821897582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3821897582
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_ovf.2431401587
Short name T1322
Test name
Test status
Simulation time 2302235195 ps
CPU time 38.85 seconds
Started Feb 21 03:18:04 PM PST 24
Finished Feb 21 03:18:43 PM PST 24
Peak memory 221384 kb
Host smart-8bd03294-1966-46e5-b0b5-8b90f24d8165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431401587 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_tx_ovf.2431401587
Directory /workspace/35.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.3515873525
Short name T261
Test name
Test status
Simulation time 1246888077 ps
CPU time 7.11 seconds
Started Feb 21 03:18:04 PM PST 24
Finished Feb 21 03:18:12 PM PST 24
Peak memory 203428 kb
Host smart-8d644a36-9264-4d6f-bb0e-a13afb94c539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515873525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.3515873525
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1922939296
Short name T338
Test name
Test status
Simulation time 17218294 ps
CPU time 0.61 seconds
Started Feb 21 03:18:16 PM PST 24
Finished Feb 21 03:18:17 PM PST 24
Peak memory 202100 kb
Host smart-b7ef3024-3039-4459-b3cb-2abf9c01026d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922939296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1922939296
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1893970801
Short name T849
Test name
Test status
Simulation time 156786968 ps
CPU time 1.37 seconds
Started Feb 21 03:18:17 PM PST 24
Finished Feb 21 03:18:19 PM PST 24
Peak memory 212948 kb
Host smart-8df12570-408d-4522-b9e7-aff0411799f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893970801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1893970801
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1766548411
Short name T539
Test name
Test status
Simulation time 527196666 ps
CPU time 11.62 seconds
Started Feb 21 03:18:23 PM PST 24
Finished Feb 21 03:18:35 PM PST 24
Peak memory 318208 kb
Host smart-dd550ae5-6c83-43b0-803a-b2af162b7ebf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766548411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1766548411
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1192967641
Short name T897
Test name
Test status
Simulation time 4817255317 ps
CPU time 87.42 seconds
Started Feb 21 03:18:22 PM PST 24
Finished Feb 21 03:19:50 PM PST 24
Peak memory 756548 kb
Host smart-b9c9a398-8d3d-40de-9b08-5e7583c11c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192967641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1192967641
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1662821972
Short name T459
Test name
Test status
Simulation time 4995449900 ps
CPU time 305.03 seconds
Started Feb 21 03:18:16 PM PST 24
Finished Feb 21 03:23:22 PM PST 24
Peak memory 1413644 kb
Host smart-378cf246-b7c8-4f51-af95-f61a05344d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662821972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1662821972
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2240294675
Short name T795
Test name
Test status
Simulation time 117042759 ps
CPU time 1.11 seconds
Started Feb 21 03:18:16 PM PST 24
Finished Feb 21 03:18:18 PM PST 24
Peak memory 203304 kb
Host smart-389819f7-fa4e-4434-9985-a27084f47bc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240294675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2240294675
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.4007241144
Short name T531
Test name
Test status
Simulation time 622430561 ps
CPU time 4.24 seconds
Started Feb 21 03:18:20 PM PST 24
Finished Feb 21 03:18:25 PM PST 24
Peak memory 230552 kb
Host smart-1bfad650-a3c9-4744-84f6-2cc14ebc20c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007241144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.4007241144
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2721559191
Short name T422
Test name
Test status
Simulation time 15295207870 ps
CPU time 480.39 seconds
Started Feb 21 03:18:23 PM PST 24
Finished Feb 21 03:26:23 PM PST 24
Peak memory 1303624 kb
Host smart-178bf335-4c81-464d-9d3c-74e726939021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721559191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2721559191
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1434403968
Short name T370
Test name
Test status
Simulation time 4218512955 ps
CPU time 141.56 seconds
Started Feb 21 03:18:24 PM PST 24
Finished Feb 21 03:20:47 PM PST 24
Peak memory 235872 kb
Host smart-d768542a-ec2e-4749-ae85-771010a59f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434403968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1434403968
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3776751820
Short name T1168
Test name
Test status
Simulation time 42221143 ps
CPU time 0.65 seconds
Started Feb 21 03:18:10 PM PST 24
Finished Feb 21 03:18:11 PM PST 24
Peak memory 202220 kb
Host smart-c76d4def-5b7e-4518-bb07-5c7fbb752462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776751820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3776751820
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3720396604
Short name T1241
Test name
Test status
Simulation time 28343244902 ps
CPU time 316.24 seconds
Started Feb 21 03:18:18 PM PST 24
Finished Feb 21 03:23:36 PM PST 24
Peak memory 218936 kb
Host smart-24e46a13-1880-4b8e-ae68-9ef4ee8fafc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720396604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3720396604
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_rx_oversample.2247400221
Short name T786
Test name
Test status
Simulation time 17794146503 ps
CPU time 160.79 seconds
Started Feb 21 03:18:11 PM PST 24
Finished Feb 21 03:20:53 PM PST 24
Peak memory 359828 kb
Host smart-156e4779-ebd7-4e39-8249-cd1642a641ae
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247400221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_rx_oversample
.2247400221
Directory /workspace/36.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3187270871
Short name T274
Test name
Test status
Simulation time 1585963853 ps
CPU time 92.92 seconds
Started Feb 21 03:18:11 PM PST 24
Finished Feb 21 03:19:44 PM PST 24
Peak memory 270720 kb
Host smart-dc5cd7fd-46b9-4736-b542-6e61cfa3aff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187270871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3187270871
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3358273482
Short name T1033
Test name
Test status
Simulation time 2773135696 ps
CPU time 10.03 seconds
Started Feb 21 03:18:17 PM PST 24
Finished Feb 21 03:18:28 PM PST 24
Peak memory 219628 kb
Host smart-39a69d91-49e1-4491-9738-95151954b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358273482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3358273482
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1100775757
Short name T681
Test name
Test status
Simulation time 7304965555 ps
CPU time 6.14 seconds
Started Feb 21 03:18:19 PM PST 24
Finished Feb 21 03:18:26 PM PST 24
Peak memory 204532 kb
Host smart-c9189d4e-da90-4c28-bcb8-35af0a7978d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100775757 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1100775757
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.4035712671
Short name T655
Test name
Test status
Simulation time 10082344383 ps
CPU time 21.88 seconds
Started Feb 21 03:18:22 PM PST 24
Finished Feb 21 03:18:44 PM PST 24
Peak memory 318388 kb
Host smart-1f2be03a-96e5-48e5-bda8-73e1f6ef74fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035712671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.4035712671
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2249289467
Short name T1405
Test name
Test status
Simulation time 10139421367 ps
CPU time 50.33 seconds
Started Feb 21 03:18:18 PM PST 24
Finished Feb 21 03:19:10 PM PST 24
Peak memory 541440 kb
Host smart-fb399020-2df9-4da0-8254-bec1d1a695a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249289467 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2249289467
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2118342636
Short name T1263
Test name
Test status
Simulation time 360032469 ps
CPU time 2.18 seconds
Started Feb 21 03:18:23 PM PST 24
Finished Feb 21 03:18:25 PM PST 24
Peak memory 203364 kb
Host smart-87ef3d6d-151d-4457-9912-7419babc227c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118342636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2118342636
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1751199153
Short name T1406
Test name
Test status
Simulation time 1326529127 ps
CPU time 4.28 seconds
Started Feb 21 03:18:25 PM PST 24
Finished Feb 21 03:18:30 PM PST 24
Peak memory 203420 kb
Host smart-45bc4a2f-011a-4686-b783-09f99f0c1583
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751199153 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1751199153
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2706416197
Short name T1063
Test name
Test status
Simulation time 3468460350 ps
CPU time 20.14 seconds
Started Feb 21 03:18:25 PM PST 24
Finished Feb 21 03:18:45 PM PST 24
Peak memory 588680 kb
Host smart-283d106b-027a-4d37-a387-2711d1c6995d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706416197 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2706416197
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.1025691723
Short name T1446
Test name
Test status
Simulation time 2097112843 ps
CPU time 3.3 seconds
Started Feb 21 03:18:19 PM PST 24
Finished Feb 21 03:18:23 PM PST 24
Peak memory 203436 kb
Host smart-3fe01eb1-6320-4800-9420-097977e554ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025691723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.1025691723
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1179568824
Short name T705
Test name
Test status
Simulation time 1557934404 ps
CPU time 8.64 seconds
Started Feb 21 03:18:16 PM PST 24
Finished Feb 21 03:18:25 PM PST 24
Peak memory 203308 kb
Host smart-5be9a3fd-0cf7-4b3a-a2dc-939322119d6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179568824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1179568824
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3289132639
Short name T1482
Test name
Test status
Simulation time 1968990901 ps
CPU time 38.5 seconds
Started Feb 21 03:18:23 PM PST 24
Finished Feb 21 03:19:02 PM PST 24
Peak memory 203308 kb
Host smart-73cac2f4-ca8f-4ed7-b7fa-13e2e6e30e33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289132639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3289132639
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.720453788
Short name T372
Test name
Test status
Simulation time 44516379661 ps
CPU time 1696.48 seconds
Started Feb 21 03:18:20 PM PST 24
Finished Feb 21 03:46:37 PM PST 24
Peak memory 7455844 kb
Host smart-5137d39d-57e4-420c-aec3-4ae01309c7e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720453788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.720453788
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.188065954
Short name T895
Test name
Test status
Simulation time 32194796806 ps
CPU time 2072.29 seconds
Started Feb 21 03:18:24 PM PST 24
Finished Feb 21 03:52:57 PM PST 24
Peak memory 5951036 kb
Host smart-bf9fd272-c51b-401a-be08-958f398b2e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188065954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.188065954
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.349469754
Short name T1238
Test name
Test status
Simulation time 8100743904 ps
CPU time 7.17 seconds
Started Feb 21 03:18:25 PM PST 24
Finished Feb 21 03:18:33 PM PST 24
Peak memory 203480 kb
Host smart-cedc1b35-f9f4-4823-b259-a2f5dac0fa16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349469754 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_timeout.349469754
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_ovf.2332557236
Short name T1384
Test name
Test status
Simulation time 3518978212 ps
CPU time 117.55 seconds
Started Feb 21 03:18:17 PM PST 24
Finished Feb 21 03:20:15 PM PST 24
Peak memory 319656 kb
Host smart-57695f1b-7d63-42da-8aa8-f8ab6a9caa14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332557236 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_tx_ovf.2332557236
Directory /workspace/36.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.2468425964
Short name T974
Test name
Test status
Simulation time 4461427846 ps
CPU time 7.14 seconds
Started Feb 21 03:18:18 PM PST 24
Finished Feb 21 03:18:27 PM PST 24
Peak memory 203444 kb
Host smart-2eba25c7-2961-4ab8-8b08-8258391936d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468425964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.2468425964
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3989059573
Short name T605
Test name
Test status
Simulation time 15640370 ps
CPU time 0.6 seconds
Started Feb 21 03:18:32 PM PST 24
Finished Feb 21 03:18:34 PM PST 24
Peak memory 202988 kb
Host smart-716519fa-69a8-4d22-ae3d-6fa1143aead0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989059573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3989059573
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1433067124
Short name T669
Test name
Test status
Simulation time 261653919 ps
CPU time 1.27 seconds
Started Feb 21 03:18:32 PM PST 24
Finished Feb 21 03:18:34 PM PST 24
Peak memory 219696 kb
Host smart-59ee6b5e-0996-4e23-a087-4d1fa785e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433067124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1433067124
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1044855059
Short name T1299
Test name
Test status
Simulation time 270998494 ps
CPU time 13.77 seconds
Started Feb 21 03:18:33 PM PST 24
Finished Feb 21 03:18:48 PM PST 24
Peak memory 248724 kb
Host smart-8204f3af-c855-4c41-99c3-95d612518f90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044855059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1044855059
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2560824244
Short name T1420
Test name
Test status
Simulation time 28754112808 ps
CPU time 200.83 seconds
Started Feb 21 03:18:34 PM PST 24
Finished Feb 21 03:21:57 PM PST 24
Peak memory 802752 kb
Host smart-c10f4bb0-85ce-40be-863c-aa47da976860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560824244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2560824244
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2182072166
Short name T1134
Test name
Test status
Simulation time 18711751836 ps
CPU time 203.72 seconds
Started Feb 21 03:18:24 PM PST 24
Finished Feb 21 03:21:49 PM PST 24
Peak memory 1220928 kb
Host smart-4c6762f5-d5fd-432a-9600-feb4ad70ad44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182072166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2182072166
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2223056630
Short name T661
Test name
Test status
Simulation time 83805902 ps
CPU time 0.93 seconds
Started Feb 21 03:18:17 PM PST 24
Finished Feb 21 03:18:19 PM PST 24
Peak memory 203028 kb
Host smart-a7f738a9-2b26-4614-806a-b18e8468efa7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223056630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2223056630
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2926934147
Short name T276
Test name
Test status
Simulation time 1134545556 ps
CPU time 17.48 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:18:56 PM PST 24
Peak memory 264852 kb
Host smart-21253874-e0a5-42d4-ac98-8cdf4a130135
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926934147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2926934147
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.249610148
Short name T1476
Test name
Test status
Simulation time 5923533655 ps
CPU time 304.97 seconds
Started Feb 21 03:18:18 PM PST 24
Finished Feb 21 03:23:24 PM PST 24
Peak memory 1653076 kb
Host smart-9a577d14-bf3e-46ef-af01-33fd672d0824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249610148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.249610148
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1406450598
Short name T1291
Test name
Test status
Simulation time 1786369631 ps
CPU time 98.72 seconds
Started Feb 21 03:18:33 PM PST 24
Finished Feb 21 03:20:13 PM PST 24
Peak memory 235756 kb
Host smart-d93132a3-bde2-46eb-b05c-731520838796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406450598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1406450598
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3466710785
Short name T167
Test name
Test status
Simulation time 18353946 ps
CPU time 0.63 seconds
Started Feb 21 03:18:24 PM PST 24
Finished Feb 21 03:18:26 PM PST 24
Peak memory 202328 kb
Host smart-9e789cb6-9185-4980-833f-5f3c41f8c6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466710785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3466710785
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2353326700
Short name T1267
Test name
Test status
Simulation time 13479230798 ps
CPU time 74.24 seconds
Started Feb 21 03:18:39 PM PST 24
Finished Feb 21 03:19:54 PM PST 24
Peak memory 318580 kb
Host smart-49dfe3ff-8f0b-4574-982c-a5cec66b2df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353326700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2353326700
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_rx_oversample.984505039
Short name T1444
Test name
Test status
Simulation time 4237547206 ps
CPU time 60.39 seconds
Started Feb 21 03:18:24 PM PST 24
Finished Feb 21 03:19:25 PM PST 24
Peak memory 295464 kb
Host smart-823c265f-fe2d-4011-aae1-febcee1f77dc
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984505039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_rx_oversample.
984505039
Directory /workspace/37.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1244613694
Short name T746
Test name
Test status
Simulation time 1383361180 ps
CPU time 27.71 seconds
Started Feb 21 03:18:25 PM PST 24
Finished Feb 21 03:18:53 PM PST 24
Peak memory 267252 kb
Host smart-3229adb4-2476-44cf-9dfc-e89fab535d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244613694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1244613694
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.1931428068
Short name T159
Test name
Test status
Simulation time 3804624836 ps
CPU time 42.35 seconds
Started Feb 21 03:18:36 PM PST 24
Finished Feb 21 03:19:21 PM PST 24
Peak memory 212952 kb
Host smart-1665077e-558f-4607-933d-d52b89716d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931428068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1931428068
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3591194077
Short name T1433
Test name
Test status
Simulation time 6505893211 ps
CPU time 3.65 seconds
Started Feb 21 03:18:31 PM PST 24
Finished Feb 21 03:18:36 PM PST 24
Peak memory 203456 kb
Host smart-086bb25c-c188-4ef0-a40d-4bb0b8a6769f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591194077 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3591194077
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.404189042
Short name T67
Test name
Test status
Simulation time 10895249699 ps
CPU time 9.03 seconds
Started Feb 21 03:18:30 PM PST 24
Finished Feb 21 03:18:39 PM PST 24
Peak memory 266292 kb
Host smart-cf91aa5b-e1f6-44a4-b825-d964750a1654
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404189042 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.404189042
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1788492
Short name T712
Test name
Test status
Simulation time 10080331946 ps
CPU time 68.59 seconds
Started Feb 21 03:18:34 PM PST 24
Finished Feb 21 03:19:44 PM PST 24
Peak memory 550080 kb
Host smart-d17992fe-f2a7-4325-b0e1-1af5fa07bba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788492 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.i2c_target_fifo_reset_tx.1788492
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1246590053
Short name T1461
Test name
Test status
Simulation time 409333192 ps
CPU time 2.22 seconds
Started Feb 21 03:18:30 PM PST 24
Finished Feb 21 03:18:33 PM PST 24
Peak memory 203352 kb
Host smart-fb1b32a6-8a4e-440c-ba08-607bd7490a5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246590053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1246590053
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2468967555
Short name T1013
Test name
Test status
Simulation time 2024037335 ps
CPU time 8.63 seconds
Started Feb 21 03:18:32 PM PST 24
Finished Feb 21 03:18:42 PM PST 24
Peak memory 207972 kb
Host smart-822c2fd0-818a-433a-9c88-df0b5cc43e92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468967555 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2468967555
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.509519737
Short name T1286
Test name
Test status
Simulation time 22387623759 ps
CPU time 1060.24 seconds
Started Feb 21 03:18:31 PM PST 24
Finished Feb 21 03:36:12 PM PST 24
Peak memory 5384440 kb
Host smart-c2deb09f-4115-4ef6-a3ac-93b190684083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509519737 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.509519737
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.3457155632
Short name T870
Test name
Test status
Simulation time 2931453613 ps
CPU time 4.42 seconds
Started Feb 21 03:18:29 PM PST 24
Finished Feb 21 03:18:33 PM PST 24
Peak memory 207360 kb
Host smart-1fcbc01e-9844-4ec2-ac7b-f2211600e76a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457155632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.3457155632
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2026245729
Short name T1314
Test name
Test status
Simulation time 7475006595 ps
CPU time 9.88 seconds
Started Feb 21 03:18:36 PM PST 24
Finished Feb 21 03:18:47 PM PST 24
Peak memory 203408 kb
Host smart-76a2c9ea-3865-4137-b784-c6e4698a0196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026245729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2026245729
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.4196882013
Short name T1276
Test name
Test status
Simulation time 7062673623 ps
CPU time 70.3 seconds
Started Feb 21 03:18:29 PM PST 24
Finished Feb 21 03:19:40 PM PST 24
Peak memory 203680 kb
Host smart-7b39e58b-3365-4744-a33c-459e2aa5d750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196882013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.4196882013
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3119891519
Short name T1118
Test name
Test status
Simulation time 62036861560 ps
CPU time 1593.51 seconds
Started Feb 21 03:18:36 PM PST 24
Finished Feb 21 03:45:12 PM PST 24
Peak memory 7312248 kb
Host smart-945b6edb-8a47-44b3-b270-16ecb3d1f2e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119891519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3119891519
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1597398135
Short name T804
Test name
Test status
Simulation time 9663677846 ps
CPU time 57.93 seconds
Started Feb 21 03:18:35 PM PST 24
Finished Feb 21 03:19:34 PM PST 24
Peak memory 690500 kb
Host smart-1866b05a-ad0d-4030-9239-da0ea67a3784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597398135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1597398135
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1005216792
Short name T499
Test name
Test status
Simulation time 3998279696 ps
CPU time 8.24 seconds
Started Feb 21 03:18:32 PM PST 24
Finished Feb 21 03:18:42 PM PST 24
Peak memory 203400 kb
Host smart-b0a0b4a4-cc8a-421a-a47b-0393a3b38261
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005216792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1005216792
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_ovf.3036553491
Short name T1391
Test name
Test status
Simulation time 13329738692 ps
CPU time 116.81 seconds
Started Feb 21 03:18:32 PM PST 24
Finished Feb 21 03:20:30 PM PST 24
Peak memory 345924 kb
Host smart-798672fa-c154-49f3-94ea-c5de42e2c284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036553491 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_tx_ovf.3036553491
Directory /workspace/37.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.1504030468
Short name T1253
Test name
Test status
Simulation time 3538585080 ps
CPU time 6.83 seconds
Started Feb 21 03:18:35 PM PST 24
Finished Feb 21 03:18:43 PM PST 24
Peak memory 203404 kb
Host smart-fd101d40-97cc-46a4-a258-8721c2b79d44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504030468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.1504030468
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.940581858
Short name T1325
Test name
Test status
Simulation time 20208738 ps
CPU time 0.6 seconds
Started Feb 21 03:18:36 PM PST 24
Finished Feb 21 03:18:39 PM PST 24
Peak memory 202100 kb
Host smart-59e8222b-21f6-411e-9b3d-ff738089e199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940581858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.940581858
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3249990175
Short name T828
Test name
Test status
Simulation time 39831014 ps
CPU time 1.14 seconds
Started Feb 21 03:18:38 PM PST 24
Finished Feb 21 03:18:41 PM PST 24
Peak memory 203340 kb
Host smart-369d06aa-09eb-4294-a47b-a5af9353e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249990175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3249990175
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3384860318
Short name T817
Test name
Test status
Simulation time 3099366093 ps
CPU time 9.55 seconds
Started Feb 21 03:18:42 PM PST 24
Finished Feb 21 03:18:52 PM PST 24
Peak memory 294604 kb
Host smart-ce013dec-6173-4b19-b422-5a6c80b54d86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384860318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3384860318
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.4135394903
Short name T1254
Test name
Test status
Simulation time 12728696326 ps
CPU time 155.02 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:21:13 PM PST 24
Peak memory 1120444 kb
Host smart-66cc526a-e650-4266-95ac-1314e546bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135394903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4135394903
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.1566397566
Short name T1485
Test name
Test status
Simulation time 7007246561 ps
CPU time 202.47 seconds
Started Feb 21 03:18:32 PM PST 24
Finished Feb 21 03:21:56 PM PST 24
Peak memory 1079580 kb
Host smart-a6008707-9627-497a-84a2-e6958bddfe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566397566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1566397566
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.7300364
Short name T963
Test name
Test status
Simulation time 156587266 ps
CPU time 1.11 seconds
Started Feb 21 03:18:34 PM PST 24
Finished Feb 21 03:18:36 PM PST 24
Peak memory 203284 kb
Host smart-b986b0d9-d68f-4621-966b-1159ce9cc668
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7300364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.7300364
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1908077934
Short name T65
Test name
Test status
Simulation time 298464473 ps
CPU time 6.97 seconds
Started Feb 21 03:18:33 PM PST 24
Finished Feb 21 03:18:42 PM PST 24
Peak memory 203252 kb
Host smart-e3a670bc-4fb1-4deb-b908-328d89c81b61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908077934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1908077934
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1323394915
Short name T367
Test name
Test status
Simulation time 4717746140 ps
CPU time 495.07 seconds
Started Feb 21 03:18:31 PM PST 24
Finished Feb 21 03:26:47 PM PST 24
Peak memory 1320792 kb
Host smart-07f32801-2896-4f52-991a-65de1382a342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323394915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1323394915
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1836420001
Short name T738
Test name
Test status
Simulation time 8782662050 ps
CPU time 35.43 seconds
Started Feb 21 03:18:39 PM PST 24
Finished Feb 21 03:19:16 PM PST 24
Peak memory 244180 kb
Host smart-6c2e9220-3381-4e9f-b117-7fe346b0547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836420001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1836420001
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1906419210
Short name T287
Test name
Test status
Simulation time 34948163 ps
CPU time 0.64 seconds
Started Feb 21 03:18:34 PM PST 24
Finished Feb 21 03:18:36 PM PST 24
Peak memory 202256 kb
Host smart-20682586-e426-4fc0-91c4-aa1d058a25be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906419210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1906419210
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.788288209
Short name T987
Test name
Test status
Simulation time 1351008719 ps
CPU time 7.39 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:18:47 PM PST 24
Peak memory 228196 kb
Host smart-fd66e193-d1f6-423a-a241-b2040c12e8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788288209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.788288209
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_rx_oversample.564902310
Short name T888
Test name
Test status
Simulation time 3106290464 ps
CPU time 172.26 seconds
Started Feb 21 03:18:34 PM PST 24
Finished Feb 21 03:21:28 PM PST 24
Peak memory 357052 kb
Host smart-29e42820-e8ae-4f01-a86b-c51ac9b880f5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564902310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_rx_oversample.
564902310
Directory /workspace/38.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2193190112
Short name T1207
Test name
Test status
Simulation time 4938998956 ps
CPU time 35.6 seconds
Started Feb 21 03:18:33 PM PST 24
Finished Feb 21 03:19:09 PM PST 24
Peak memory 260452 kb
Host smart-d0a37d00-d0ac-4727-bacf-0ee58838de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193190112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2193190112
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3314191898
Short name T224
Test name
Test status
Simulation time 4394641702 ps
CPU time 40.28 seconds
Started Feb 21 03:18:39 PM PST 24
Finished Feb 21 03:19:21 PM PST 24
Peak memory 211628 kb
Host smart-43529a4b-89a4-479a-bd8c-b03817364dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314191898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3314191898
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.661797919
Short name T540
Test name
Test status
Simulation time 6595761045 ps
CPU time 4 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:18:44 PM PST 24
Peak memory 203472 kb
Host smart-20889744-e123-4a44-b216-4720fb37680f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661797919 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.661797919
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.592540173
Short name T326
Test name
Test status
Simulation time 10091711501 ps
CPU time 11.26 seconds
Started Feb 21 03:18:35 PM PST 24
Finished Feb 21 03:18:47 PM PST 24
Peak memory 273328 kb
Host smart-1ba6be5c-1314-44f1-b26d-58f0c3199cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592540173 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.592540173
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2978099989
Short name T980
Test name
Test status
Simulation time 10158446545 ps
CPU time 29.69 seconds
Started Feb 21 03:18:40 PM PST 24
Finished Feb 21 03:19:11 PM PST 24
Peak memory 384052 kb
Host smart-b25ba1ae-8ace-4944-9400-fd45c243accc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978099989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2978099989
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3708785735
Short name T1190
Test name
Test status
Simulation time 752209280 ps
CPU time 3.41 seconds
Started Feb 21 03:18:34 PM PST 24
Finished Feb 21 03:18:39 PM PST 24
Peak memory 203384 kb
Host smart-31c5cff1-8b81-4d6b-ba04-844ef9942bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708785735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3708785735
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.4140496526
Short name T1088
Test name
Test status
Simulation time 861205809 ps
CPU time 4.14 seconds
Started Feb 21 03:18:39 PM PST 24
Finished Feb 21 03:18:44 PM PST 24
Peak memory 203344 kb
Host smart-5dd611f8-29a6-46ee-8893-5d994110cee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140496526 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.4140496526
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1961776162
Short name T659
Test name
Test status
Simulation time 12547134611 ps
CPU time 290.81 seconds
Started Feb 21 03:18:36 PM PST 24
Finished Feb 21 03:23:28 PM PST 24
Peak memory 2865044 kb
Host smart-d9e1070a-320b-406d-a139-ca53479a2a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961776162 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1961776162
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.657005832
Short name T1057
Test name
Test status
Simulation time 500193261 ps
CPU time 3.26 seconds
Started Feb 21 03:18:40 PM PST 24
Finished Feb 21 03:18:44 PM PST 24
Peak memory 203368 kb
Host smart-a259b6a4-b659-4ba2-8462-d35f877f144e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657005832 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_perf.657005832
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.291745204
Short name T1004
Test name
Test status
Simulation time 1586309114 ps
CPU time 40.07 seconds
Started Feb 21 03:18:35 PM PST 24
Finished Feb 21 03:19:15 PM PST 24
Peak memory 203372 kb
Host smart-4a5285ce-5e67-4e07-ba7b-a026aa04d265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291745204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_tar
get_smoke.291745204
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.3927945504
Short name T189
Test name
Test status
Simulation time 73509262486 ps
CPU time 93.52 seconds
Started Feb 21 03:18:36 PM PST 24
Finished Feb 21 03:20:11 PM PST 24
Peak memory 419236 kb
Host smart-9903c689-8f77-4eea-a2f7-8c15726ed9ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927945504 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.3927945504
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3621682264
Short name T912
Test name
Test status
Simulation time 2227457728 ps
CPU time 9.77 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:18:49 PM PST 24
Peak memory 203320 kb
Host smart-7b3d0d96-7eeb-4076-9616-7990443e2fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621682264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3621682264
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2770230440
Short name T318
Test name
Test status
Simulation time 68552580440 ps
CPU time 690.37 seconds
Started Feb 21 03:18:40 PM PST 24
Finished Feb 21 03:30:11 PM PST 24
Peak memory 4174184 kb
Host smart-a1a5f50e-321e-4b0c-9628-adef336d2000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770230440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2770230440
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.2131309613
Short name T1329
Test name
Test status
Simulation time 7203429346 ps
CPU time 214.93 seconds
Started Feb 21 03:18:36 PM PST 24
Finished Feb 21 03:22:13 PM PST 24
Peak memory 1628376 kb
Host smart-40a36fc4-fa15-4565-95df-9f6d6bc8d427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131309613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.2131309613
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1586756996
Short name T740
Test name
Test status
Simulation time 2007172297 ps
CPU time 7.65 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:18:58 PM PST 24
Peak memory 203360 kb
Host smart-0e38ba10-5c2c-48b4-bc1a-143cd9b85cb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586756996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1586756996
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_ovf.1565725134
Short name T1288
Test name
Test status
Simulation time 15567143602 ps
CPU time 271.56 seconds
Started Feb 21 03:18:42 PM PST 24
Finished Feb 21 03:23:14 PM PST 24
Peak memory 514972 kb
Host smart-a638a414-2a55-4bf6-adb6-ac8b17e076ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565725134 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_tx_ovf.1565725134
Directory /workspace/38.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.2090768117
Short name T436
Test name
Test status
Simulation time 3554005346 ps
CPU time 7.08 seconds
Started Feb 21 03:18:42 PM PST 24
Finished Feb 21 03:18:50 PM PST 24
Peak memory 206752 kb
Host smart-078bcfde-6254-47ba-9faa-8a018b237e74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090768117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.2090768117
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3802172179
Short name T663
Test name
Test status
Simulation time 17752984 ps
CPU time 0.64 seconds
Started Feb 21 03:19:01 PM PST 24
Finished Feb 21 03:19:02 PM PST 24
Peak memory 202132 kb
Host smart-8da5fad0-3f34-4ba9-9bde-e61e0f5a4252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802172179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3802172179
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.624446592
Short name T1403
Test name
Test status
Simulation time 53761139 ps
CPU time 1.26 seconds
Started Feb 21 03:18:52 PM PST 24
Finished Feb 21 03:18:54 PM PST 24
Peak memory 203268 kb
Host smart-3a1fc73b-549b-4964-84e0-f08a90e0979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624446592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.624446592
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.810465443
Short name T482
Test name
Test status
Simulation time 436556955 ps
CPU time 22.1 seconds
Started Feb 21 03:18:34 PM PST 24
Finished Feb 21 03:18:57 PM PST 24
Peak memory 289840 kb
Host smart-e9604d53-2cab-4501-b997-3743439fa515
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810465443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.810465443
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.1620534079
Short name T1213
Test name
Test status
Simulation time 13108713331 ps
CPU time 142.54 seconds
Started Feb 21 03:18:48 PM PST 24
Finished Feb 21 03:21:12 PM PST 24
Peak memory 989532 kb
Host smart-38ca80a5-63b3-406c-acb6-3af0ff12d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620534079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1620534079
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1874022621
Short name T1030
Test name
Test status
Simulation time 118878484 ps
CPU time 1.02 seconds
Started Feb 21 03:18:39 PM PST 24
Finished Feb 21 03:18:41 PM PST 24
Peak memory 203028 kb
Host smart-42669e5f-9e31-4a8d-a275-74ad4e73cfec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874022621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1874022621
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1088288234
Short name T174
Test name
Test status
Simulation time 271103161 ps
CPU time 6.1 seconds
Started Feb 21 03:18:33 PM PST 24
Finished Feb 21 03:18:41 PM PST 24
Peak memory 203292 kb
Host smart-9b3bf9cc-246f-46ee-a1f9-7be1864f08c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088288234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1088288234
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3389519848
Short name T1301
Test name
Test status
Simulation time 26974584114 ps
CPU time 438.39 seconds
Started Feb 21 03:18:35 PM PST 24
Finished Feb 21 03:25:55 PM PST 24
Peak memory 1851900 kb
Host smart-60381089-3815-4cdb-a8f7-e0ba645b9552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389519848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3389519848
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.4291616818
Short name T1103
Test name
Test status
Simulation time 6040545163 ps
CPU time 76.42 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:20:09 PM PST 24
Peak memory 301168 kb
Host smart-a6c7b79a-956f-4c2b-9813-705dc8de1b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291616818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.4291616818
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.335338421
Short name T956
Test name
Test status
Simulation time 34343122 ps
CPU time 0.61 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:18:40 PM PST 24
Peak memory 202136 kb
Host smart-4dd288c9-1ae5-4782-99e0-733b94d2e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335338421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.335338421
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2171704068
Short name T1278
Test name
Test status
Simulation time 53705317745 ps
CPU time 700.79 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:30:34 PM PST 24
Peak memory 203464 kb
Host smart-c7d29829-2f3a-464c-a001-45a7594c6589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171704068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2171704068
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_rx_oversample.1434314011
Short name T295
Test name
Test status
Simulation time 2800126359 ps
CPU time 85.08 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:20:04 PM PST 24
Peak memory 279112 kb
Host smart-66e20e0e-3943-4c60-a7d1-9806b1becf60
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434314011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_rx_oversample
.1434314011
Directory /workspace/39.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2020046070
Short name T839
Test name
Test status
Simulation time 7249434989 ps
CPU time 107.69 seconds
Started Feb 21 03:18:37 PM PST 24
Finished Feb 21 03:20:27 PM PST 24
Peak memory 259940 kb
Host smart-5cdc543c-9083-4f39-b0f6-7d5dcb0b4e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020046070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2020046070
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1371776114
Short name T195
Test name
Test status
Simulation time 38263723864 ps
CPU time 2142 seconds
Started Feb 21 03:18:51 PM PST 24
Finished Feb 21 03:54:34 PM PST 24
Peak memory 2998212 kb
Host smart-86dad4ab-adea-458e-82a4-b3f6271c9ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371776114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1371776114
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1047505442
Short name T1376
Test name
Test status
Simulation time 886494267 ps
CPU time 39.95 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:19:30 PM PST 24
Peak memory 212588 kb
Host smart-8440a50c-fcae-49f1-b683-faf895acfaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047505442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1047505442
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2175616952
Short name T265
Test name
Test status
Simulation time 924350963 ps
CPU time 3.85 seconds
Started Feb 21 03:18:57 PM PST 24
Finished Feb 21 03:19:01 PM PST 24
Peak memory 203376 kb
Host smart-9dbcc668-d629-4ba7-ad61-bc7530c9e5cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175616952 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2175616952
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.699456576
Short name T1462
Test name
Test status
Simulation time 10256554030 ps
CPU time 27.28 seconds
Started Feb 21 03:18:52 PM PST 24
Finished Feb 21 03:19:20 PM PST 24
Peak memory 342148 kb
Host smart-dfdbad4e-d713-42dd-9124-317b351d5ddb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699456576 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_acq.699456576
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1184056018
Short name T1448
Test name
Test status
Simulation time 10073579249 ps
CPU time 14.7 seconds
Started Feb 21 03:18:46 PM PST 24
Finished Feb 21 03:19:01 PM PST 24
Peak memory 315288 kb
Host smart-580f6a84-0233-44cd-9fca-842b867b6c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184056018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1184056018
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.235456644
Short name T292
Test name
Test status
Simulation time 1807493230 ps
CPU time 2.25 seconds
Started Feb 21 03:18:48 PM PST 24
Finished Feb 21 03:18:52 PM PST 24
Peak memory 203388 kb
Host smart-6d770e7a-426e-4841-b681-fa81dadebcf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235456644 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_hrst.235456644
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1750000435
Short name T1294
Test name
Test status
Simulation time 977215513 ps
CPU time 5.06 seconds
Started Feb 21 03:18:54 PM PST 24
Finished Feb 21 03:18:59 PM PST 24
Peak memory 204076 kb
Host smart-5e04451f-b143-4fdb-915d-a0c2d4c45feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750000435 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1750000435
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3737488542
Short name T1232
Test name
Test status
Simulation time 20483051355 ps
CPU time 411.66 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:25:42 PM PST 24
Peak memory 3055144 kb
Host smart-c0fa4ca6-4eee-409f-b4e1-d274f04f707d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737488542 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3737488542
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.357596260
Short name T1321
Test name
Test status
Simulation time 1196786239 ps
CPU time 3.57 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:18:54 PM PST 24
Peak memory 203776 kb
Host smart-b575a011-371b-4b92-baa1-eaf88a5bf405
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357596260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_perf.357596260
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2029725487
Short name T1502
Test name
Test status
Simulation time 6636006623 ps
CPU time 42.84 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:19:36 PM PST 24
Peak memory 203492 kb
Host smart-c9e4580f-0f30-4829-83c8-9ad0ca2dd693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029725487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2029725487
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.2137120228
Short name T841
Test name
Test status
Simulation time 13606601177 ps
CPU time 65.1 seconds
Started Feb 21 03:18:50 PM PST 24
Finished Feb 21 03:19:55 PM PST 24
Peak memory 243136 kb
Host smart-ba0faa98-86dd-468c-a91a-c978aa6e9067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137120228 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.2137120228
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.558125659
Short name T1122
Test name
Test status
Simulation time 9731598764 ps
CPU time 95.28 seconds
Started Feb 21 03:18:51 PM PST 24
Finished Feb 21 03:20:26 PM PST 24
Peak memory 205040 kb
Host smart-5c13a498-4f65-4a51-aaf1-e9d03959e928
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558125659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.558125659
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.307113083
Short name T716
Test name
Test status
Simulation time 24675163681 ps
CPU time 28.92 seconds
Started Feb 21 03:18:48 PM PST 24
Finished Feb 21 03:19:19 PM PST 24
Peak memory 662944 kb
Host smart-fc2b1145-9504-4244-927f-6156fc6a1ac6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307113083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.307113083
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.18274461
Short name T1105
Test name
Test status
Simulation time 30159776587 ps
CPU time 217.56 seconds
Started Feb 21 03:18:52 PM PST 24
Finished Feb 21 03:22:30 PM PST 24
Peak memory 1595968 kb
Host smart-e4d5f375-b36f-451a-a8e3-6d23b9991c81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18274461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_stretch.18274461
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2944574294
Short name T345
Test name
Test status
Simulation time 5926222071 ps
CPU time 6.81 seconds
Started Feb 21 03:18:51 PM PST 24
Finished Feb 21 03:18:58 PM PST 24
Peak memory 212920 kb
Host smart-e8bffa82-c9d3-4f16-b52f-05c6727e82a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944574294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2944574294
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_ovf.3338394652
Short name T891
Test name
Test status
Simulation time 11628833774 ps
CPU time 79.89 seconds
Started Feb 21 03:18:51 PM PST 24
Finished Feb 21 03:20:12 PM PST 24
Peak memory 331028 kb
Host smart-c7b46bfb-3ccf-4063-8ce6-f451c8124c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338394652 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_tx_ovf.3338394652
Directory /workspace/39.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.2946521910
Short name T463
Test name
Test status
Simulation time 6390251065 ps
CPU time 6.07 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:19:00 PM PST 24
Peak memory 203916 kb
Host smart-e06430ef-1360-4447-af57-8639920b370e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946521910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.2946521910
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.1520484047
Short name T89
Test name
Test status
Simulation time 56411936 ps
CPU time 0.59 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 203008 kb
Host smart-d7d84cf1-de3c-4c55-b62b-8e88701c93f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520484047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1520484047
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.4234097469
Short name T1366
Test name
Test status
Simulation time 69947678 ps
CPU time 1.08 seconds
Started Feb 21 03:14:14 PM PST 24
Finished Feb 21 03:14:15 PM PST 24
Peak memory 211484 kb
Host smart-18bcbb80-8dfc-444e-ab5b-3cf8e9d0b277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234097469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.4234097469
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2149275257
Short name T484
Test name
Test status
Simulation time 1530083242 ps
CPU time 18.43 seconds
Started Feb 21 03:14:10 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 269416 kb
Host smart-4485e2a1-2949-4689-8ed6-6a10e8f91a34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149275257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2149275257
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3497272618
Short name T1052
Test name
Test status
Simulation time 3189264300 ps
CPU time 114.72 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:16:13 PM PST 24
Peak memory 958580 kb
Host smart-b85dfdb6-2f2e-497e-a645-0172f8f0c5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497272618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3497272618
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.4020785345
Short name T1505
Test name
Test status
Simulation time 25212362730 ps
CPU time 925.39 seconds
Started Feb 21 03:13:51 PM PST 24
Finished Feb 21 03:29:17 PM PST 24
Peak memory 1806624 kb
Host smart-42af6adf-a26f-4cc7-a520-a399088e52c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020785345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.4020785345
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.448562892
Short name T480
Test name
Test status
Simulation time 142127589 ps
CPU time 1.06 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:27 PM PST 24
Peak memory 203236 kb
Host smart-151e5465-a462-4de0-8ff3-33d695a3c684
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448562892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.448562892
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.466584545
Short name T1078
Test name
Test status
Simulation time 189772647 ps
CPU time 10.21 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 203272 kb
Host smart-2891c7c9-9070-4255-b884-8e1ec83510d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466584545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.466584545
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1000413737
Short name T477
Test name
Test status
Simulation time 9914129677 ps
CPU time 416.37 seconds
Started Feb 21 03:14:09 PM PST 24
Finished Feb 21 03:21:08 PM PST 24
Peak memory 1267212 kb
Host smart-0c4c4108-d036-45d4-933d-e3abff3fb3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000413737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1000413737
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1846542372
Short name T29
Test name
Test status
Simulation time 19934319595 ps
CPU time 87.91 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:15:41 PM PST 24
Peak memory 227924 kb
Host smart-71048be1-bb6a-4453-932e-c57bbd4957ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846542372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1846542372
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2528727164
Short name T169
Test name
Test status
Simulation time 18584976 ps
CPU time 0.63 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:17 PM PST 24
Peak memory 202316 kb
Host smart-cc17cb33-eb27-4b38-ad3d-eff228839a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528727164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2528727164
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2417711406
Short name T679
Test name
Test status
Simulation time 7310566663 ps
CPU time 47.05 seconds
Started Feb 21 03:14:07 PM PST 24
Finished Feb 21 03:14:57 PM PST 24
Peak memory 273344 kb
Host smart-09abd659-e60a-42da-b93c-80ea6f66bd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417711406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2417711406
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_rx_oversample.932612488
Short name T543
Test name
Test status
Simulation time 9773467856 ps
CPU time 93.41 seconds
Started Feb 21 03:14:05 PM PST 24
Finished Feb 21 03:15:40 PM PST 24
Peak memory 316900 kb
Host smart-97892c5e-17b0-41b6-8d7f-8982fa00adb0
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932612488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_rx_oversample.932612488
Directory /workspace/4.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1619565552
Short name T1304
Test name
Test status
Simulation time 8856493906 ps
CPU time 129.52 seconds
Started Feb 21 03:14:06 PM PST 24
Finished Feb 21 03:16:18 PM PST 24
Peak memory 252440 kb
Host smart-448b3cd9-23d7-4c9a-af91-241e219e9a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619565552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1619565552
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2886647440
Short name T719
Test name
Test status
Simulation time 13001083342 ps
CPU time 15.67 seconds
Started Feb 21 03:14:14 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 219816 kb
Host smart-920968ce-12af-4a58-aaa4-ef703a07b30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886647440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2886647440
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.596966780
Short name T103
Test name
Test status
Simulation time 153898296 ps
CPU time 0.87 seconds
Started Feb 21 03:14:11 PM PST 24
Finished Feb 21 03:14:14 PM PST 24
Peak memory 219892 kb
Host smart-0993ae02-d67e-4f72-bbfa-8af3cfb06017
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596966780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.596966780
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.877780931
Short name T402
Test name
Test status
Simulation time 12359191590 ps
CPU time 3.88 seconds
Started Feb 21 03:14:11 PM PST 24
Finished Feb 21 03:14:16 PM PST 24
Peak memory 203400 kb
Host smart-23ea4038-4998-42dc-8243-122344d2da75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877780931 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.877780931
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.466744423
Short name T1248
Test name
Test status
Simulation time 10085964196 ps
CPU time 65.9 seconds
Started Feb 21 03:14:09 PM PST 24
Finished Feb 21 03:15:17 PM PST 24
Peak memory 543356 kb
Host smart-95b31b53-7a3c-4c77-a7d1-f4d6ce3a15b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466744423 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.466744423
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2622810914
Short name T387
Test name
Test status
Simulation time 10103399000 ps
CPU time 89.96 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:15:43 PM PST 24
Peak memory 712692 kb
Host smart-202c2b7f-d3c5-4e25-bd71-3d8537756e60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622810914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2622810914
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3298483279
Short name T815
Test name
Test status
Simulation time 412134818 ps
CPU time 2.19 seconds
Started Feb 21 03:14:09 PM PST 24
Finished Feb 21 03:14:14 PM PST 24
Peak memory 203268 kb
Host smart-c09dcff7-129d-44e5-b38e-80b80a7f82e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298483279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3298483279
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.4137262154
Short name T848
Test name
Test status
Simulation time 13178198419 ps
CPU time 7.27 seconds
Started Feb 21 03:14:08 PM PST 24
Finished Feb 21 03:14:18 PM PST 24
Peak memory 212416 kb
Host smart-d0d44bf2-6e43-46c1-b37d-d8df60d43870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137262154 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.4137262154
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.4133728273
Short name T665
Test name
Test status
Simulation time 4140201362 ps
CPU time 12.54 seconds
Started Feb 21 03:14:13 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 433600 kb
Host smart-b9463523-6d47-424b-933f-9e54d6759047
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133728273 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.4133728273
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.1251549164
Short name T614
Test name
Test status
Simulation time 784695534 ps
CPU time 4.16 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:14:17 PM PST 24
Peak memory 204808 kb
Host smart-9d22e1ec-3a89-4af7-a5f8-bfa213bf8479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251549164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.1251549164
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1462458031
Short name T420
Test name
Test status
Simulation time 5876247458 ps
CPU time 37.27 seconds
Started Feb 21 03:14:06 PM PST 24
Finished Feb 21 03:14:46 PM PST 24
Peak memory 203444 kb
Host smart-79571b24-3d1a-46ea-a487-947e875cad8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462458031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1462458031
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1115665268
Short name T783
Test name
Test status
Simulation time 2434723856 ps
CPU time 108.59 seconds
Started Feb 21 03:14:13 PM PST 24
Finished Feb 21 03:16:02 PM PST 24
Peak memory 205252 kb
Host smart-b4102015-8453-4b33-ae32-ce7eb69f709a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115665268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1115665268
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3502471546
Short name T1054
Test name
Test status
Simulation time 9020236795 ps
CPU time 56.48 seconds
Started Feb 21 03:14:09 PM PST 24
Finished Feb 21 03:15:08 PM PST 24
Peak memory 395208 kb
Host smart-5c2944a4-0ddc-4d4c-b6f1-16733a91d9c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502471546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3502471546
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2826734519
Short name T784
Test name
Test status
Simulation time 3128815237 ps
CPU time 7.06 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:14:20 PM PST 24
Peak memory 215380 kb
Host smart-d63ed33a-33b0-4931-9bcd-103ba2f9376a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826734519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2826734519
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_ovf.3062808027
Short name T898
Test name
Test status
Simulation time 4695070018 ps
CPU time 39.27 seconds
Started Feb 21 03:14:00 PM PST 24
Finished Feb 21 03:14:41 PM PST 24
Peak memory 224776 kb
Host smart-a5da002b-353d-4b4f-9ec1-6f4b579a880c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062808027 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_tx_ovf.3062808027
Directory /workspace/4.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.1325463234
Short name T793
Test name
Test status
Simulation time 8369171316 ps
CPU time 5.32 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:14:19 PM PST 24
Peak memory 203444 kb
Host smart-67b6f896-a0c0-4efd-a4e7-0d5d4facbdd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325463234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.1325463234
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.4273789546
Short name T382
Test name
Test status
Simulation time 25251631 ps
CPU time 0.61 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:19:14 PM PST 24
Peak memory 202100 kb
Host smart-17dc3720-6ca8-4415-8c3b-596a1c096f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273789546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.4273789546
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.853665283
Short name T496
Test name
Test status
Simulation time 36434881 ps
CPU time 1.17 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:18:51 PM PST 24
Peak memory 211720 kb
Host smart-9b975228-f5fa-4e14-8bed-aae3951b1fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853665283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.853665283
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.468572580
Short name T652
Test name
Test status
Simulation time 1156251423 ps
CPU time 9.26 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:18:59 PM PST 24
Peak memory 291212 kb
Host smart-85b945f9-a295-4c9b-a054-1e8e7de7ce8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468572580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.468572580
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3837334804
Short name T942
Test name
Test status
Simulation time 3967153270 ps
CPU time 113.27 seconds
Started Feb 21 03:18:51 PM PST 24
Finished Feb 21 03:20:45 PM PST 24
Peak memory 946316 kb
Host smart-e60278ce-1aff-4ddc-aafe-210b01d04e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837334804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3837334804
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3749616729
Short name T1459
Test name
Test status
Simulation time 7758459172 ps
CPU time 715.02 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:30:48 PM PST 24
Peak memory 1490568 kb
Host smart-3823297a-d6a5-471c-8d4c-67fa697515f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749616729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3749616729
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.226521797
Short name T1486
Test name
Test status
Simulation time 682254832 ps
CPU time 0.89 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:18:51 PM PST 24
Peak memory 203036 kb
Host smart-f0dd9c16-f7a2-4b37-92f7-71201a475808
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226521797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.226521797
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1170240828
Short name T368
Test name
Test status
Simulation time 205076455 ps
CPU time 5.71 seconds
Started Feb 21 03:18:57 PM PST 24
Finished Feb 21 03:19:03 PM PST 24
Peak memory 240480 kb
Host smart-28a38e34-661f-44cb-8ce3-1f9daa5de68f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170240828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1170240828
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.235230533
Short name T140
Test name
Test status
Simulation time 7129221973 ps
CPU time 112.42 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:20:42 PM PST 24
Peak memory 875644 kb
Host smart-d78f0cca-aa0f-4cac-99a2-cdf18562edf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235230533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.235230533
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.2146317400
Short name T975
Test name
Test status
Simulation time 9685391227 ps
CPU time 125.2 seconds
Started Feb 21 03:19:06 PM PST 24
Finished Feb 21 03:21:12 PM PST 24
Peak memory 258344 kb
Host smart-7f0d91be-e5b8-458a-aa67-bed851ecdb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146317400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.2146317400
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2760690163
Short name T1480
Test name
Test status
Simulation time 33587151 ps
CPU time 0.64 seconds
Started Feb 21 03:18:54 PM PST 24
Finished Feb 21 03:18:55 PM PST 24
Peak memory 202948 kb
Host smart-7d0ba080-0485-4c81-8a6a-7aa5bfcf02b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760690163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2760690163
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.721551276
Short name T592
Test name
Test status
Simulation time 3038370569 ps
CPU time 25.06 seconds
Started Feb 21 03:18:47 PM PST 24
Finished Feb 21 03:19:13 PM PST 24
Peak memory 266776 kb
Host smart-73a38162-2091-4a55-b795-1513f7fae7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721551276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.721551276
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_rx_oversample.2671543257
Short name T931
Test name
Test status
Simulation time 2640487707 ps
CPU time 229.91 seconds
Started Feb 21 03:18:48 PM PST 24
Finished Feb 21 03:22:40 PM PST 24
Peak memory 310172 kb
Host smart-d361a6c4-309b-449d-ae7a-fa7d8cb93aab
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671543257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_rx_oversample
.2671543257
Directory /workspace/40.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.549149372
Short name T940
Test name
Test status
Simulation time 2288472524 ps
CPU time 53.32 seconds
Started Feb 21 03:18:47 PM PST 24
Finished Feb 21 03:19:41 PM PST 24
Peak memory 211588 kb
Host smart-5a6c6d28-af0e-42c9-8e26-5c3b857c09af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549149372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.549149372
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3921751021
Short name T544
Test name
Test status
Simulation time 1466379904 ps
CPU time 33.46 seconds
Started Feb 21 03:18:49 PM PST 24
Finished Feb 21 03:19:23 PM PST 24
Peak memory 211448 kb
Host smart-36d3e54e-a527-4c24-8ca4-3e7c7c1b6622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921751021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3921751021
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3176108153
Short name T1340
Test name
Test status
Simulation time 3524024504 ps
CPU time 3.77 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:18:57 PM PST 24
Peak memory 203428 kb
Host smart-20984aa8-9233-4177-a19d-2235ddfa000e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176108153 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3176108153
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1736568841
Short name T808
Test name
Test status
Simulation time 10138154936 ps
CPU time 26.4 seconds
Started Feb 21 03:19:00 PM PST 24
Finished Feb 21 03:19:28 PM PST 24
Peak memory 364884 kb
Host smart-7fd79d54-b01c-4f12-8346-e1fe6a8b3e50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736568841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1736568841
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1737066844
Short name T194
Test name
Test status
Simulation time 3175857182 ps
CPU time 2.82 seconds
Started Feb 21 03:18:55 PM PST 24
Finished Feb 21 03:18:58 PM PST 24
Peak memory 203392 kb
Host smart-7e1001a3-f5e3-4318-95c5-4fced422e9a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737066844 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1737066844
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1769243705
Short name T455
Test name
Test status
Simulation time 8427530298 ps
CPU time 6.47 seconds
Started Feb 21 03:18:55 PM PST 24
Finished Feb 21 03:19:02 PM PST 24
Peak memory 208036 kb
Host smart-24a91458-9fee-4e41-954d-52b9c919f9bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769243705 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1769243705
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.4232951277
Short name T1309
Test name
Test status
Simulation time 4766049072 ps
CPU time 17.27 seconds
Started Feb 21 03:18:58 PM PST 24
Finished Feb 21 03:19:16 PM PST 24
Peak memory 546336 kb
Host smart-3d65d47e-9c51-4805-a0e1-256ebf4e41bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232951277 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.4232951277
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.1033728177
Short name T1397
Test name
Test status
Simulation time 478964547 ps
CPU time 3.04 seconds
Started Feb 21 03:18:54 PM PST 24
Finished Feb 21 03:18:57 PM PST 24
Peak memory 203380 kb
Host smart-6662ff0a-3456-4fd8-a6d9-8e95ea14522d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033728177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.1033728177
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.2298816004
Short name T922
Test name
Test status
Simulation time 1630431119 ps
CPU time 19.78 seconds
Started Feb 21 03:18:54 PM PST 24
Finished Feb 21 03:19:14 PM PST 24
Peak memory 203324 kb
Host smart-89a662d0-bbaf-4f84-911f-d2fdfa614add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298816004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.2298816004
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.599315271
Short name T164
Test name
Test status
Simulation time 1465954633 ps
CPU time 11.39 seconds
Started Feb 21 03:18:52 PM PST 24
Finished Feb 21 03:19:04 PM PST 24
Peak memory 205464 kb
Host smart-6bb743ed-7deb-46f7-a1fd-58722d3d4220
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599315271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_rd.599315271
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3392842516
Short name T1290
Test name
Test status
Simulation time 15693977215 ps
CPU time 34.27 seconds
Started Feb 21 03:18:54 PM PST 24
Finished Feb 21 03:19:28 PM PST 24
Peak memory 782596 kb
Host smart-fac39b88-e181-4d16-b7db-6c39d8f0f0b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392842516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3392842516
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.656138066
Short name T46
Test name
Test status
Simulation time 32305599010 ps
CPU time 142.61 seconds
Started Feb 21 03:18:55 PM PST 24
Finished Feb 21 03:21:18 PM PST 24
Peak memory 1045324 kb
Host smart-4d20f114-ff8e-48f7-a353-c0e9636f2687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656138066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.656138066
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.917741032
Short name T995
Test name
Test status
Simulation time 8534922073 ps
CPU time 7.99 seconds
Started Feb 21 03:18:53 PM PST 24
Finished Feb 21 03:19:01 PM PST 24
Peak memory 208532 kb
Host smart-9f815717-d91c-464b-9ed6-a28213ab568c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917741032 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.917741032
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_ovf.244341877
Short name T718
Test name
Test status
Simulation time 4843814540 ps
CPU time 48 seconds
Started Feb 21 03:18:58 PM PST 24
Finished Feb 21 03:19:47 PM PST 24
Peak memory 235164 kb
Host smart-c23487c3-e8ec-4a51-9e9f-981201817580
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244341877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_tx_ovf.244341877
Directory /workspace/40.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.2181935908
Short name T303
Test name
Test status
Simulation time 5694056356 ps
CPU time 5.65 seconds
Started Feb 21 03:18:55 PM PST 24
Finished Feb 21 03:19:02 PM PST 24
Peak memory 206168 kb
Host smart-16ca814d-cc5f-4213-80ec-c66779662d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181935908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.i2c_target_unexp_stop.2181935908
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3252550527
Short name T1306
Test name
Test status
Simulation time 14954911 ps
CPU time 0.65 seconds
Started Feb 21 03:19:26 PM PST 24
Finished Feb 21 03:19:27 PM PST 24
Peak memory 202088 kb
Host smart-8f4c137c-02ce-4e70-8b52-fdadf5586b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252550527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3252550527
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1374765808
Short name T35
Test name
Test status
Simulation time 106913099 ps
CPU time 1.43 seconds
Started Feb 21 03:19:13 PM PST 24
Finished Feb 21 03:19:16 PM PST 24
Peak memory 214872 kb
Host smart-f519024f-12eb-4e2d-9f88-fe04983a14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374765808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1374765808
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.166644439
Short name T1192
Test name
Test status
Simulation time 2125715284 ps
CPU time 10.52 seconds
Started Feb 21 03:19:10 PM PST 24
Finished Feb 21 03:19:22 PM PST 24
Peak memory 319936 kb
Host smart-27632788-a075-41d5-9125-59d73d332dcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166644439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.166644439
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2926375409
Short name T1024
Test name
Test status
Simulation time 8324707851 ps
CPU time 175.37 seconds
Started Feb 21 03:19:10 PM PST 24
Finished Feb 21 03:22:07 PM PST 24
Peak memory 762796 kb
Host smart-27f80d9c-bbfe-4118-abf3-cee51b2ede85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926375409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2926375409
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1250520578
Short name T1491
Test name
Test status
Simulation time 6976147722 ps
CPU time 362.94 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:25:17 PM PST 24
Peak memory 1073636 kb
Host smart-46f7c720-81e2-494e-8e3b-430d178f6212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250520578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1250520578
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.622002872
Short name T1035
Test name
Test status
Simulation time 597347307 ps
CPU time 1.15 seconds
Started Feb 21 03:19:09 PM PST 24
Finished Feb 21 03:19:11 PM PST 24
Peak memory 203240 kb
Host smart-25e6fb59-46fc-44ca-baa7-ed202d462ed1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622002872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.622002872
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2650103474
Short name T160
Test name
Test status
Simulation time 3174506647 ps
CPU time 13.95 seconds
Started Feb 21 03:19:08 PM PST 24
Finished Feb 21 03:19:23 PM PST 24
Peak memory 249740 kb
Host smart-531e9fad-51d5-4408-9e7b-fa4199610538
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650103474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2650103474
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.3618402557
Short name T137
Test name
Test status
Simulation time 5051515934 ps
CPU time 240.39 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:23:14 PM PST 24
Peak memory 1414772 kb
Host smart-13abed5d-5865-457d-9ebf-b4da26047a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618402557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.3618402557
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.3921129402
Short name T419
Test name
Test status
Simulation time 5405979861 ps
CPU time 124.51 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:21:17 PM PST 24
Peak memory 403584 kb
Host smart-ed965860-1d33-41e2-8dc5-1ad04fccf4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921129402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.3921129402
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3226035267
Short name T787
Test name
Test status
Simulation time 33308894 ps
CPU time 0.65 seconds
Started Feb 21 03:19:09 PM PST 24
Finished Feb 21 03:19:11 PM PST 24
Peak memory 202328 kb
Host smart-d7a2eed6-0ee0-4994-afa3-5403a9251ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226035267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3226035267
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.4055517606
Short name T1443
Test name
Test status
Simulation time 981841809 ps
CPU time 5.17 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:19:18 PM PST 24
Peak memory 219632 kb
Host smart-276b4e29-7cd5-40bb-ba42-7155c5e66746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055517606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.4055517606
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_rx_oversample.2229998973
Short name T611
Test name
Test status
Simulation time 8318956493 ps
CPU time 58.95 seconds
Started Feb 21 03:19:17 PM PST 24
Finished Feb 21 03:20:17 PM PST 24
Peak memory 279980 kb
Host smart-5551ab64-319c-4409-aa7b-3d1781cab7ed
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229998973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_rx_oversample
.2229998973
Directory /workspace/41.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2893317561
Short name T266
Test name
Test status
Simulation time 5264327895 ps
CPU time 82.94 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:20:36 PM PST 24
Peak memory 310640 kb
Host smart-3bda732e-0009-416f-b603-32fa7bd3f32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893317561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2893317561
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2046863406
Short name T493
Test name
Test status
Simulation time 5054161907 ps
CPU time 16.28 seconds
Started Feb 21 03:19:10 PM PST 24
Finished Feb 21 03:19:29 PM PST 24
Peak memory 219768 kb
Host smart-ac0ed687-54b2-4b86-aebe-0c75254b386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046863406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2046863406
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3846036838
Short name T269
Test name
Test status
Simulation time 3227975401 ps
CPU time 3.7 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:19:16 PM PST 24
Peak memory 203420 kb
Host smart-d679684a-4738-4fd8-81b7-1171a90cb148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846036838 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3846036838
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.2769968038
Short name T566
Test name
Test status
Simulation time 10208505596 ps
CPU time 38.06 seconds
Started Feb 21 03:19:10 PM PST 24
Finished Feb 21 03:19:50 PM PST 24
Peak memory 407840 kb
Host smart-d4368ffe-9823-42a1-b9d4-764f680f5264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769968038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.2769968038
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3047071953
Short name T1442
Test name
Test status
Simulation time 10312762843 ps
CPU time 13.55 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:19:26 PM PST 24
Peak memory 304884 kb
Host smart-d21c3b15-f8c6-4d00-8ec7-4d12d93ad758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047071953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3047071953
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1823538073
Short name T322
Test name
Test status
Simulation time 736296469 ps
CPU time 2.05 seconds
Started Feb 21 03:19:14 PM PST 24
Finished Feb 21 03:19:17 PM PST 24
Peak memory 203420 kb
Host smart-11b4c707-b28d-456a-85bf-7b4dbf856e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823538073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1823538073
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.705891866
Short name T280
Test name
Test status
Simulation time 17313279137 ps
CPU time 8.24 seconds
Started Feb 21 03:19:09 PM PST 24
Finished Feb 21 03:19:18 PM PST 24
Peak memory 203360 kb
Host smart-a5f6770b-42a7-4f94-8ee7-85021fe4963e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705891866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.705891866
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.598174911
Short name T45
Test name
Test status
Simulation time 22336140171 ps
CPU time 152.5 seconds
Started Feb 21 03:19:10 PM PST 24
Finished Feb 21 03:21:45 PM PST 24
Peak memory 1478476 kb
Host smart-d455809e-891c-45c2-a6bb-3c6a87bf84c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598174911 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.598174911
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.3703478745
Short name T606
Test name
Test status
Simulation time 459756390 ps
CPU time 2.92 seconds
Started Feb 21 03:19:10 PM PST 24
Finished Feb 21 03:19:14 PM PST 24
Peak memory 203436 kb
Host smart-f00ae23d-f6fa-4e0c-8780-619a4b476268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703478745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_perf.3703478745
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2980249642
Short name T791
Test name
Test status
Simulation time 5729948307 ps
CPU time 38.95 seconds
Started Feb 21 03:19:09 PM PST 24
Finished Feb 21 03:19:50 PM PST 24
Peak memory 203360 kb
Host smart-50f70308-a27b-4665-a1e8-68c0077bc4fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980249642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2980249642
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.3876981885
Short name T911
Test name
Test status
Simulation time 185348379385 ps
CPU time 148.4 seconds
Started Feb 21 03:19:10 PM PST 24
Finished Feb 21 03:21:41 PM PST 24
Peak memory 607468 kb
Host smart-1a745ba0-05f9-46af-b766-809265736328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876981885 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.3876981885
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.1954944943
Short name T105
Test name
Test status
Simulation time 1534761403 ps
CPU time 26.46 seconds
Started Feb 21 03:19:13 PM PST 24
Finished Feb 21 03:19:41 PM PST 24
Peak memory 212680 kb
Host smart-63da644e-cc25-4e13-bf21-47a2adfd0ef8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954944943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.1954944943
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.2579604873
Short name T327
Test name
Test status
Simulation time 13864060571 ps
CPU time 8.69 seconds
Started Feb 21 03:19:15 PM PST 24
Finished Feb 21 03:19:25 PM PST 24
Peak memory 357480 kb
Host smart-9efd8217-1e89-42cd-a593-7194b63688b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579604873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.2579604873
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2910863625
Short name T518
Test name
Test status
Simulation time 34852954780 ps
CPU time 273.92 seconds
Started Feb 21 03:19:09 PM PST 24
Finished Feb 21 03:23:44 PM PST 24
Peak memory 1528588 kb
Host smart-2d86c5cb-5d69-4212-80aa-afcf198ea1ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910863625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2910863625
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3881409934
Short name T788
Test name
Test status
Simulation time 12081344624 ps
CPU time 6.6 seconds
Started Feb 21 03:19:11 PM PST 24
Finished Feb 21 03:19:19 PM PST 24
Peak memory 203436 kb
Host smart-eaf615f4-ecad-4340-b1be-544c67c3d4ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881409934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3881409934
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_ovf.2795734108
Short name T710
Test name
Test status
Simulation time 8831431899 ps
CPU time 67.04 seconds
Started Feb 21 03:19:17 PM PST 24
Finished Feb 21 03:20:25 PM PST 24
Peak memory 289248 kb
Host smart-1a30c059-1fe3-47ac-876f-eed26753243d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795734108 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_tx_ovf.2795734108
Directory /workspace/41.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.3129101425
Short name T1173
Test name
Test status
Simulation time 4673467480 ps
CPU time 5.17 seconds
Started Feb 21 03:19:14 PM PST 24
Finished Feb 21 03:19:20 PM PST 24
Peak memory 203836 kb
Host smart-7694d44b-23b0-4176-a0c7-dda8a1199bc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129101425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_target_unexp_stop.3129101425
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.954612470
Short name T1425
Test name
Test status
Simulation time 24636858 ps
CPU time 0.62 seconds
Started Feb 21 03:19:22 PM PST 24
Finished Feb 21 03:19:23 PM PST 24
Peak memory 202988 kb
Host smart-1486069f-fa29-44a4-9fd9-93777fefb3b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954612470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.954612470
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2994453374
Short name T275
Test name
Test status
Simulation time 135394238 ps
CPU time 1.29 seconds
Started Feb 21 03:19:25 PM PST 24
Finished Feb 21 03:19:26 PM PST 24
Peak memory 211548 kb
Host smart-ee7567a3-5042-44e7-9306-af9fe5590f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994453374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2994453374
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3889796950
Short name T1402
Test name
Test status
Simulation time 6409148321 ps
CPU time 21.37 seconds
Started Feb 21 03:19:23 PM PST 24
Finished Feb 21 03:19:44 PM PST 24
Peak memory 290100 kb
Host smart-4607f911-1dc1-493d-97a6-dd6c07727cc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889796950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3889796950
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3584220390
Short name T936
Test name
Test status
Simulation time 2068548434 ps
CPU time 148.09 seconds
Started Feb 21 03:19:25 PM PST 24
Finished Feb 21 03:21:54 PM PST 24
Peak memory 663124 kb
Host smart-68aecc81-1c12-4138-a0fa-415cf3037b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584220390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3584220390
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.252488245
Short name T837
Test name
Test status
Simulation time 8651685286 ps
CPU time 271.66 seconds
Started Feb 21 03:19:23 PM PST 24
Finished Feb 21 03:23:55 PM PST 24
Peak memory 1284320 kb
Host smart-fd6a70ac-34df-4ca2-90a7-ad07927b786b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252488245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.252488245
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1160729262
Short name T654
Test name
Test status
Simulation time 87699637 ps
CPU time 0.98 seconds
Started Feb 21 03:19:13 PM PST 24
Finished Feb 21 03:19:15 PM PST 24
Peak memory 203012 kb
Host smart-7bc947ae-3dab-48e3-acdd-5e3efd50e44c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160729262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1160729262
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1385254349
Short name T1018
Test name
Test status
Simulation time 313229099 ps
CPU time 10.99 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:19:48 PM PST 24
Peak memory 237000 kb
Host smart-7335600d-6e04-49fd-b9d9-c1338374ee5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385254349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1385254349
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3047859977
Short name T1247
Test name
Test status
Simulation time 5812968500 ps
CPU time 343.21 seconds
Started Feb 21 03:19:38 PM PST 24
Finished Feb 21 03:25:21 PM PST 24
Peak memory 1595996 kb
Host smart-a1eda104-46c4-4f3c-9322-1c36d37d5903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047859977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3047859977
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3434828461
Short name T809
Test name
Test status
Simulation time 3040706224 ps
CPU time 43.53 seconds
Started Feb 21 03:19:37 PM PST 24
Finished Feb 21 03:20:21 PM PST 24
Peak memory 266068 kb
Host smart-c34c6537-c675-4a30-a52d-e1b1f6bd5998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434828461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3434828461
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2091053494
Short name T583
Test name
Test status
Simulation time 49075653 ps
CPU time 0.67 seconds
Started Feb 21 03:19:38 PM PST 24
Finished Feb 21 03:19:39 PM PST 24
Peak memory 202468 kb
Host smart-746d51df-31e6-42ca-ac50-60827cd0abcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091053494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2091053494
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2648084966
Short name T1224
Test name
Test status
Simulation time 484962793 ps
CPU time 6.58 seconds
Started Feb 21 03:19:22 PM PST 24
Finished Feb 21 03:19:29 PM PST 24
Peak memory 219712 kb
Host smart-f8aa948e-7c44-4f91-bfd8-cb080a9009a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648084966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2648084966
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_rx_oversample.641849718
Short name T748
Test name
Test status
Simulation time 8871670587 ps
CPU time 182.47 seconds
Started Feb 21 03:19:24 PM PST 24
Finished Feb 21 03:22:27 PM PST 24
Peak memory 276704 kb
Host smart-7301282c-d747-4df7-b99e-d37cc99ad9a8
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641849718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_rx_oversample.
641849718
Directory /workspace/42.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3184107245
Short name T709
Test name
Test status
Simulation time 4202537744 ps
CPU time 64.3 seconds
Started Feb 21 03:19:39 PM PST 24
Finished Feb 21 03:20:43 PM PST 24
Peak memory 301048 kb
Host smart-cde40465-d268-45b3-adda-1a5ac384ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184107245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3184107245
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.3519248265
Short name T1002
Test name
Test status
Simulation time 12884805254 ps
CPU time 12.13 seconds
Started Feb 21 03:19:23 PM PST 24
Finished Feb 21 03:19:36 PM PST 24
Peak memory 219696 kb
Host smart-07823c8d-b9b0-4fd8-b6a1-c9749b8ce53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519248265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3519248265
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1748417131
Short name T288
Test name
Test status
Simulation time 4928043455 ps
CPU time 4.5 seconds
Started Feb 21 03:19:38 PM PST 24
Finished Feb 21 03:19:43 PM PST 24
Peak memory 203408 kb
Host smart-2374fc31-d84e-4621-ae05-52f7d594b1d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748417131 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1748417131
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.2002558603
Short name T1032
Test name
Test status
Simulation time 10399221083 ps
CPU time 8.17 seconds
Started Feb 21 03:19:33 PM PST 24
Finished Feb 21 03:19:42 PM PST 24
Peak memory 255336 kb
Host smart-7fb7de8f-8e35-49ea-91fe-8c7a40f4e313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002558603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.2002558603
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.2623870286
Short name T622
Test name
Test status
Simulation time 10210091388 ps
CPU time 27.84 seconds
Started Feb 21 03:19:38 PM PST 24
Finished Feb 21 03:20:06 PM PST 24
Peak memory 383196 kb
Host smart-2738b965-53e0-4912-b096-0f18a22af9b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623870286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.2623870286
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1422996185
Short name T1499
Test name
Test status
Simulation time 1392001715 ps
CPU time 3.28 seconds
Started Feb 21 03:19:38 PM PST 24
Finished Feb 21 03:19:41 PM PST 24
Peak memory 203348 kb
Host smart-62fec26e-5124-4c4c-9e39-0a48cd531c8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422996185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1422996185
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.4244016340
Short name T429
Test name
Test status
Simulation time 3865348697 ps
CPU time 7.65 seconds
Started Feb 21 03:19:12 PM PST 24
Finished Feb 21 03:19:22 PM PST 24
Peak memory 209088 kb
Host smart-22322a5f-f1ec-4820-b100-9bbaa8f8f2c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244016340 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.4244016340
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2150027199
Short name T304
Test name
Test status
Simulation time 18233649545 ps
CPU time 603.4 seconds
Started Feb 21 03:19:21 PM PST 24
Finished Feb 21 03:29:25 PM PST 24
Peak memory 4187600 kb
Host smart-7ed98348-57b3-4b2f-82db-12c3a404ec7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150027199 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2150027199
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.2603911126
Short name T991
Test name
Test status
Simulation time 1548433795 ps
CPU time 4.62 seconds
Started Feb 21 03:19:38 PM PST 24
Finished Feb 21 03:19:43 PM PST 24
Peak memory 204660 kb
Host smart-0e1de11e-e0ad-49ba-96de-cb6d79a68a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603911126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.2603911126
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.666963560
Short name T670
Test name
Test status
Simulation time 829462986 ps
CPU time 22.27 seconds
Started Feb 21 03:19:12 PM PST 24
Finished Feb 21 03:19:36 PM PST 24
Peak memory 203376 kb
Host smart-5e09c209-c654-4885-9ae4-2c2c45ff44c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666963560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.666963560
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.1834730242
Short name T58
Test name
Test status
Simulation time 60884721695 ps
CPU time 156.43 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:22:13 PM PST 24
Peak memory 1287520 kb
Host smart-73f936c1-d760-4ba3-9670-2cf639ccf058
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834730242 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.1834730242
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.3224072807
Short name T1075
Test name
Test status
Simulation time 1625466029 ps
CPU time 48.97 seconds
Started Feb 21 03:19:25 PM PST 24
Finished Feb 21 03:20:14 PM PST 24
Peak memory 203260 kb
Host smart-3cacf3e0-d7b7-4cb3-9bd1-5f57c4906354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224072807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.3224072807
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3176492449
Short name T1245
Test name
Test status
Simulation time 37317834559 ps
CPU time 1782.43 seconds
Started Feb 21 03:19:25 PM PST 24
Finished Feb 21 03:49:08 PM PST 24
Peak memory 8333776 kb
Host smart-179a9a24-ed67-48b6-a378-d01d22d1206f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176492449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3176492449
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1830638556
Short name T320
Test name
Test status
Simulation time 29177820593 ps
CPU time 2541.92 seconds
Started Feb 21 03:19:35 PM PST 24
Finished Feb 21 04:01:58 PM PST 24
Peak memory 6646792 kb
Host smart-0994e57c-268a-481a-826e-34c44f27e3e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830638556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1830638556
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1587081554
Short name T628
Test name
Test status
Simulation time 1559109173 ps
CPU time 6.88 seconds
Started Feb 21 03:19:23 PM PST 24
Finished Feb 21 03:19:30 PM PST 24
Peak memory 205248 kb
Host smart-ceb6ec94-69dd-4912-a20a-cca61d71fc4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587081554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1587081554
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_ovf.561422157
Short name T16
Test name
Test status
Simulation time 5249716254 ps
CPU time 35.12 seconds
Started Feb 21 03:19:37 PM PST 24
Finished Feb 21 03:20:12 PM PST 24
Peak memory 215812 kb
Host smart-8067caef-3d34-48da-af05-5192b6290005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561422157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_tx_ovf.561422157
Directory /workspace/42.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.1809617889
Short name T1334
Test name
Test status
Simulation time 1663036032 ps
CPU time 6.25 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:19:42 PM PST 24
Peak memory 206384 kb
Host smart-cd1b4091-422c-4d43-bc6c-7984c897965b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809617889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.1809617889
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3261886141
Short name T427
Test name
Test status
Simulation time 35292604 ps
CPU time 0.62 seconds
Started Feb 21 03:19:58 PM PST 24
Finished Feb 21 03:19:59 PM PST 24
Peak memory 202052 kb
Host smart-9cc29133-84d9-4233-a3ec-e4213a8f5103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261886141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3261886141
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.4071587970
Short name T175
Test name
Test status
Simulation time 34048884 ps
CPU time 1.15 seconds
Started Feb 21 03:19:33 PM PST 24
Finished Feb 21 03:19:34 PM PST 24
Peak memory 211516 kb
Host smart-82cd901a-af47-4ce7-80e9-a759f71651f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071587970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.4071587970
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.375567354
Short name T1289
Test name
Test status
Simulation time 2198539199 ps
CPU time 31.11 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:20:07 PM PST 24
Peak memory 327764 kb
Host smart-38b86e48-0683-40c7-9fbe-fd6dcc84a0c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375567354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.375567354
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.4281990937
Short name T585
Test name
Test status
Simulation time 3452093091 ps
CPU time 243.7 seconds
Started Feb 21 03:19:23 PM PST 24
Finished Feb 21 03:23:27 PM PST 24
Peak memory 813828 kb
Host smart-6a6028bb-1b41-4dd8-91f6-569c2fdb9cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281990937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.4281990937
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.890018421
Short name T1198
Test name
Test status
Simulation time 6347643033 ps
CPU time 681.69 seconds
Started Feb 21 03:19:24 PM PST 24
Finished Feb 21 03:30:46 PM PST 24
Peak memory 1521176 kb
Host smart-05ee236a-2bf6-4f3e-985f-81f5ca44d1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890018421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.890018421
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2005744275
Short name T800
Test name
Test status
Simulation time 1662313439 ps
CPU time 0.85 seconds
Started Feb 21 03:19:22 PM PST 24
Finished Feb 21 03:19:23 PM PST 24
Peak memory 203036 kb
Host smart-15ea0113-10cb-427f-ba76-be22b0da5302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005744275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2005744275
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.926908797
Short name T620
Test name
Test status
Simulation time 2312327551 ps
CPU time 11.21 seconds
Started Feb 21 03:19:37 PM PST 24
Finished Feb 21 03:19:49 PM PST 24
Peak memory 203364 kb
Host smart-13c8faaf-08d9-41f4-85f7-5ee1e64954ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926908797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
926908797
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1315253357
Short name T138
Test name
Test status
Simulation time 20940070786 ps
CPU time 250.77 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:23:47 PM PST 24
Peak memory 1489504 kb
Host smart-aa8a1973-566d-4924-8769-755daa952a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315253357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1315253357
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3757218022
Short name T1270
Test name
Test status
Simulation time 3535686899 ps
CPU time 110.51 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:21:42 PM PST 24
Peak memory 251720 kb
Host smart-41d9c9f4-9618-4e72-ba85-c74f59afbcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757218022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3757218022
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3523676569
Short name T393
Test name
Test status
Simulation time 44867349 ps
CPU time 0.63 seconds
Started Feb 21 03:19:21 PM PST 24
Finished Feb 21 03:19:22 PM PST 24
Peak memory 202260 kb
Host smart-620755f8-0a08-479c-bc86-2f948d1cb99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523676569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3523676569
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1813807043
Short name T352
Test name
Test status
Simulation time 7215732986 ps
CPU time 39.1 seconds
Started Feb 21 03:19:35 PM PST 24
Finished Feb 21 03:20:14 PM PST 24
Peak memory 234200 kb
Host smart-d141e1b3-1a78-40b6-b41c-e776e49eccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813807043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1813807043
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_rx_oversample.1340369274
Short name T218
Test name
Test status
Simulation time 4436289549 ps
CPU time 135.41 seconds
Started Feb 21 03:19:35 PM PST 24
Finished Feb 21 03:21:50 PM PST 24
Peak memory 349788 kb
Host smart-fda2e75a-929d-44d1-bf38-586118ae0fd8
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340369274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_rx_oversample
.1340369274
Directory /workspace/43.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1978145711
Short name T851
Test name
Test status
Simulation time 14212016992 ps
CPU time 39.13 seconds
Started Feb 21 03:19:34 PM PST 24
Finished Feb 21 03:20:13 PM PST 24
Peak memory 261268 kb
Host smart-12fc0270-ef57-45b0-ae7f-6126ffe9459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978145711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1978145711
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.1574586983
Short name T198
Test name
Test status
Simulation time 91164920159 ps
CPU time 2428.74 seconds
Started Feb 21 03:19:35 PM PST 24
Finished Feb 21 04:00:04 PM PST 24
Peak memory 1243124 kb
Host smart-9c97e3e5-2cf7-424e-9861-79eba8b484c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574586983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1574586983
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2195271796
Short name T1148
Test name
Test status
Simulation time 4633495259 ps
CPU time 18.37 seconds
Started Feb 21 03:19:35 PM PST 24
Finished Feb 21 03:19:54 PM PST 24
Peak memory 230396 kb
Host smart-bc24d8d6-cace-4b3d-8e48-6e554fcec8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195271796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2195271796
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1212318587
Short name T347
Test name
Test status
Simulation time 551634790 ps
CPU time 2.54 seconds
Started Feb 21 03:19:30 PM PST 24
Finished Feb 21 03:19:32 PM PST 24
Peak memory 203368 kb
Host smart-5efa871d-7e6c-47b7-b61c-5c0b99389071
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212318587 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1212318587
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2869418765
Short name T1015
Test name
Test status
Simulation time 11389348398 ps
CPU time 3.36 seconds
Started Feb 21 03:19:38 PM PST 24
Finished Feb 21 03:19:41 PM PST 24
Peak memory 216664 kb
Host smart-17ee55cc-181a-4a94-a75d-64aa55ea47d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869418765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2869418765
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.872938654
Short name T1006
Test name
Test status
Simulation time 10126053171 ps
CPU time 37.86 seconds
Started Feb 21 03:19:35 PM PST 24
Finished Feb 21 03:20:13 PM PST 24
Peak memory 475104 kb
Host smart-9235cea2-2e37-43eb-a370-e5bb1331eb3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872938654 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.872938654
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1501775108
Short name T1311
Test name
Test status
Simulation time 474422588 ps
CPU time 2.48 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:19:38 PM PST 24
Peak memory 203384 kb
Host smart-402636d0-ce14-4708-b396-74516af2e7d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501775108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1501775108
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2656329786
Short name T488
Test name
Test status
Simulation time 876061772 ps
CPU time 4.3 seconds
Started Feb 21 03:19:32 PM PST 24
Finished Feb 21 03:19:37 PM PST 24
Peak memory 203376 kb
Host smart-a2c9c0c3-968d-4c0f-bcba-f21c1d1669a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656329786 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2656329786
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2017192297
Short name T1029
Test name
Test status
Simulation time 15575938205 ps
CPU time 457.75 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:27:14 PM PST 24
Peak memory 3659220 kb
Host smart-53796de8-3971-4685-8958-b7d328ce736c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017192297 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2017192297
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_perf.1156734919
Short name T1026
Test name
Test status
Simulation time 3981072540 ps
CPU time 4.45 seconds
Started Feb 21 03:19:30 PM PST 24
Finished Feb 21 03:19:35 PM PST 24
Peak memory 206500 kb
Host smart-a0027e5d-5c77-4812-abeb-7dd850b5f433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156734919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_perf.1156734919
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.715817700
Short name T935
Test name
Test status
Simulation time 6277642071 ps
CPU time 40.66 seconds
Started Feb 21 03:19:37 PM PST 24
Finished Feb 21 03:20:18 PM PST 24
Peak memory 203496 kb
Host smart-3170e0d5-c0d0-442e-bd67-f8bd0a66088d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715817700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.715817700
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.1357162708
Short name T830
Test name
Test status
Simulation time 8826120995 ps
CPU time 163.55 seconds
Started Feb 21 03:19:33 PM PST 24
Finished Feb 21 03:22:16 PM PST 24
Peak memory 332052 kb
Host smart-3d4bd479-9c4e-4a09-9808-ddab00ad6d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357162708 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.1357162708
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1216209479
Short name T1470
Test name
Test status
Simulation time 2252744716 ps
CPU time 36.33 seconds
Started Feb 21 03:19:36 PM PST 24
Finished Feb 21 03:20:12 PM PST 24
Peak memory 226336 kb
Host smart-9c06f757-b5b6-450b-9e2a-63a60518121c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216209479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1216209479
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2375061001
Short name T247
Test name
Test status
Simulation time 16183695564 ps
CPU time 27.13 seconds
Started Feb 21 03:19:37 PM PST 24
Finished Feb 21 03:20:04 PM PST 24
Peak memory 695712 kb
Host smart-110539d3-78a3-4f0b-bdf0-0361f25ab096
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375061001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2375061001
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3553679274
Short name T1226
Test name
Test status
Simulation time 1485699495 ps
CPU time 6.94 seconds
Started Feb 21 03:19:34 PM PST 24
Finished Feb 21 03:19:41 PM PST 24
Peak memory 207688 kb
Host smart-55b653b4-78af-44d2-894b-83b53940cf8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553679274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3553679274
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_ovf.1790826089
Short name T725
Test name
Test status
Simulation time 17988521529 ps
CPU time 142.11 seconds
Started Feb 21 03:19:27 PM PST 24
Finished Feb 21 03:21:50 PM PST 24
Peak memory 378696 kb
Host smart-14361188-d443-42e3-b3c5-142dfc8ff8a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790826089 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_tx_ovf.1790826089
Directory /workspace/43.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.3464991312
Short name T357
Test name
Test status
Simulation time 1096763545 ps
CPU time 6 seconds
Started Feb 21 03:19:39 PM PST 24
Finished Feb 21 03:19:45 PM PST 24
Peak memory 203420 kb
Host smart-baccf9f5-f0f3-4d57-91f5-9b9f017f61b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464991312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.i2c_target_unexp_stop.3464991312
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.948455264
Short name T101
Test name
Test status
Simulation time 38682828 ps
CPU time 0.63 seconds
Started Feb 21 03:19:58 PM PST 24
Finished Feb 21 03:19:59 PM PST 24
Peak memory 202996 kb
Host smart-b89e4cc7-1499-40aa-a284-836f08018445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948455264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.948455264
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2474909197
Short name T418
Test name
Test status
Simulation time 37692625 ps
CPU time 1.71 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:19:55 PM PST 24
Peak memory 211516 kb
Host smart-00873055-fbba-4a73-ac21-c6c3394ed662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474909197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2474909197
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3479246958
Short name T1069
Test name
Test status
Simulation time 205234283 ps
CPU time 4.51 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:19:56 PM PST 24
Peak memory 226924 kb
Host smart-923aa6e9-824e-465a-bbb3-81158c32f9a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479246958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3479246958
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2932209746
Short name T407
Test name
Test status
Simulation time 2201358000 ps
CPU time 162.97 seconds
Started Feb 21 03:19:58 PM PST 24
Finished Feb 21 03:22:42 PM PST 24
Peak memory 749136 kb
Host smart-df50e581-e603-421d-955f-819d97423537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932209746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2932209746
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2489933031
Short name T857
Test name
Test status
Simulation time 19372996514 ps
CPU time 245.11 seconds
Started Feb 21 03:19:50 PM PST 24
Finished Feb 21 03:23:55 PM PST 24
Peak memory 1366776 kb
Host smart-553c69ea-ef29-4a3d-ac2a-725bd5d57545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489933031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2489933031
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.4248952819
Short name T1440
Test name
Test status
Simulation time 81620752 ps
CPU time 0.88 seconds
Started Feb 21 03:19:52 PM PST 24
Finished Feb 21 03:19:54 PM PST 24
Peak memory 203128 kb
Host smart-435cc62a-9ab3-4680-a43c-e3ad900b3df2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248952819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.4248952819
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.2810515943
Short name T973
Test name
Test status
Simulation time 685958965 ps
CPU time 10.87 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:20:02 PM PST 24
Peak memory 237372 kb
Host smart-8a2aedbf-1ef9-43c4-80fe-84a5cbb66bd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810515943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.2810515943
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.4061419218
Short name T1407
Test name
Test status
Simulation time 3265998690 ps
CPU time 289.58 seconds
Started Feb 21 03:19:50 PM PST 24
Finished Feb 21 03:24:40 PM PST 24
Peak memory 980692 kb
Host smart-fd3506ed-1704-4e42-86d3-ab6a8ee45c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061419218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.4061419218
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2073238602
Short name T1081
Test name
Test status
Simulation time 5198536385 ps
CPU time 34.83 seconds
Started Feb 21 03:19:58 PM PST 24
Finished Feb 21 03:20:34 PM PST 24
Peak memory 227784 kb
Host smart-90176269-e1af-4c49-902e-c5048566b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073238602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2073238602
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2980329783
Short name T1139
Test name
Test status
Simulation time 19534725 ps
CPU time 0.66 seconds
Started Feb 21 03:19:58 PM PST 24
Finished Feb 21 03:19:59 PM PST 24
Peak memory 202948 kb
Host smart-9222fd10-1106-4ab6-8b67-3069f7f4f31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980329783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2980329783
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.639593004
Short name T186
Test name
Test status
Simulation time 51635636145 ps
CPU time 413.49 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:26:45 PM PST 24
Peak memory 343988 kb
Host smart-d529fd87-1bce-477a-8217-d8324dd1be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639593004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.639593004
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_rx_oversample.3647076002
Short name T411
Test name
Test status
Simulation time 10640122802 ps
CPU time 127.72 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:22:01 PM PST 24
Peak memory 319604 kb
Host smart-280c7812-f5e0-4cd7-b386-11906f174bc2
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647076002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_rx_oversample
.3647076002
Directory /workspace/44.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2573523702
Short name T1058
Test name
Test status
Simulation time 10752499642 ps
CPU time 84.76 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:21:17 PM PST 24
Peak memory 227920 kb
Host smart-d6102a90-be33-4c2f-a3b9-2bfdee376d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573523702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2573523702
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.56607629
Short name T1262
Test name
Test status
Simulation time 2520644083 ps
CPU time 11.79 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:20:06 PM PST 24
Peak memory 215272 kb
Host smart-14eb025f-23bf-46e3-980f-fe2374feb73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56607629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.56607629
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1214040296
Short name T916
Test name
Test status
Simulation time 1073380189 ps
CPU time 4.13 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:19:58 PM PST 24
Peak memory 203396 kb
Host smart-cab63d19-14d8-4085-af54-11cc4a0ff0fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214040296 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1214040296
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2772598850
Short name T799
Test name
Test status
Simulation time 10076937649 ps
CPU time 31.98 seconds
Started Feb 21 03:19:50 PM PST 24
Finished Feb 21 03:20:23 PM PST 24
Peak memory 372116 kb
Host smart-51cafa13-7e8c-430e-8d35-10f2c52d8712
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772598850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2772598850
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1750472355
Short name T310
Test name
Test status
Simulation time 10836040268 ps
CPU time 8.34 seconds
Started Feb 21 03:19:50 PM PST 24
Finished Feb 21 03:19:58 PM PST 24
Peak memory 263484 kb
Host smart-141bfcd8-8c79-422e-86a1-52b5a6759e7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750472355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1750472355
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.200226462
Short name T871
Test name
Test status
Simulation time 2833315192 ps
CPU time 2.12 seconds
Started Feb 21 03:19:59 PM PST 24
Finished Feb 21 03:20:02 PM PST 24
Peak memory 203372 kb
Host smart-9e08a001-673a-4998-aa7b-ecfefc9bec03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200226462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.200226462
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1247286164
Short name T317
Test name
Test status
Simulation time 925603267 ps
CPU time 4.29 seconds
Started Feb 21 03:19:52 PM PST 24
Finished Feb 21 03:19:57 PM PST 24
Peak memory 203412 kb
Host smart-4f9c7f30-3be8-476c-b5bd-63aa1b8da0b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247286164 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1247286164
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.4039650771
Short name T694
Test name
Test status
Simulation time 6387250651 ps
CPU time 31.11 seconds
Started Feb 21 03:19:52 PM PST 24
Finished Feb 21 03:20:24 PM PST 24
Peak memory 731456 kb
Host smart-1d7265e4-250c-4782-8e8c-343600029f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039650771 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.4039650771
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.281800939
Short name T1056
Test name
Test status
Simulation time 649358155 ps
CPU time 3.85 seconds
Started Feb 21 03:19:52 PM PST 24
Finished Feb 21 03:19:56 PM PST 24
Peak memory 208012 kb
Host smart-12725345-b531-4a8e-9360-1bf30e04c7bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281800939 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_perf.281800939
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2855150399
Short name T1409
Test name
Test status
Simulation time 3108012048 ps
CPU time 36.47 seconds
Started Feb 21 03:19:52 PM PST 24
Finished Feb 21 03:20:29 PM PST 24
Peak memory 203428 kb
Host smart-8094f913-9904-4617-a6a5-804b5c5f67ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855150399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2855150399
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.738314788
Short name T1249
Test name
Test status
Simulation time 47922131288 ps
CPU time 70.59 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:21:02 PM PST 24
Peak memory 250292 kb
Host smart-8bf5cc9f-9d7f-4f0e-8519-fd0a3e12ca37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738314788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_stress_all.738314788
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2340828418
Short name T1125
Test name
Test status
Simulation time 546079443 ps
CPU time 9.76 seconds
Started Feb 21 03:19:49 PM PST 24
Finished Feb 21 03:20:00 PM PST 24
Peak memory 203336 kb
Host smart-d9b014e3-8d7c-4c03-822b-6fbd93ec0ab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340828418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2340828418
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3642610112
Short name T1246
Test name
Test status
Simulation time 35398949146 ps
CPU time 1909.53 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:51:43 PM PST 24
Peak memory 8003616 kb
Host smart-8ad0c019-dbf7-4abc-83c7-1190ab7750e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642610112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3642610112
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3378274859
Short name T1394
Test name
Test status
Simulation time 28153674489 ps
CPU time 1961.3 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:52:35 PM PST 24
Peak memory 5826664 kb
Host smart-0bdd5c10-5c9c-4507-94d1-1ac3dc08504d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378274859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3378274859
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.173544348
Short name T548
Test name
Test status
Simulation time 1776722416 ps
CPU time 7.73 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:19:59 PM PST 24
Peak memory 203400 kb
Host smart-77eb3166-a9a3-401a-836d-a7d93a5b812e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173544348 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.173544348
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_ovf.2169360411
Short name T1101
Test name
Test status
Simulation time 6738001123 ps
CPU time 128.52 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:22:02 PM PST 24
Peak memory 434012 kb
Host smart-c94eb30d-1413-49ea-81a9-cb6ffc5354d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169360411 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_tx_ovf.2169360411
Directory /workspace/44.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.3119709937
Short name T213
Test name
Test status
Simulation time 7704209453 ps
CPU time 8.32 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:19:59 PM PST 24
Peak memory 213012 kb
Host smart-f3409f39-efc5-46a0-a06f-9dba86ebb494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119709937 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.3119709937
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1051316114
Short name T979
Test name
Test status
Simulation time 44432534 ps
CPU time 0.69 seconds
Started Feb 21 03:20:27 PM PST 24
Finished Feb 21 03:20:28 PM PST 24
Peak memory 202152 kb
Host smart-49a2127e-8cdc-41f5-bccc-814713b0a318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051316114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1051316114
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2662744374
Short name T415
Test name
Test status
Simulation time 70920951 ps
CPU time 1.24 seconds
Started Feb 21 03:20:08 PM PST 24
Finished Feb 21 03:20:10 PM PST 24
Peak memory 211396 kb
Host smart-9291ed6c-2c80-4270-a593-84b6726ded0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662744374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2662744374
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1147522861
Short name T671
Test name
Test status
Simulation time 2242681111 ps
CPU time 9.05 seconds
Started Feb 21 03:19:52 PM PST 24
Finished Feb 21 03:20:01 PM PST 24
Peak memory 271456 kb
Host smart-3091c742-e223-4ed2-8553-7c2ca0630525
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147522861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1147522861
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1303968666
Short name T736
Test name
Test status
Simulation time 8811301525 ps
CPU time 74.45 seconds
Started Feb 21 03:19:58 PM PST 24
Finished Feb 21 03:21:13 PM PST 24
Peak memory 731124 kb
Host smart-42346f58-94c0-4559-b896-1695a55503bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303968666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1303968666
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3734922151
Short name T222
Test name
Test status
Simulation time 23445707147 ps
CPU time 308.62 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:25:00 PM PST 24
Peak memory 1376576 kb
Host smart-7ff18c3a-fa30-496e-b57a-134ebf48205b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734922151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3734922151
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1746249533
Short name T1170
Test name
Test status
Simulation time 112237023 ps
CPU time 0.92 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:19:53 PM PST 24
Peak memory 202996 kb
Host smart-7ab0fce7-5ee0-4fa0-9d2c-9c04be06392a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746249533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1746249533
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2362146417
Short name T1038
Test name
Test status
Simulation time 204549215 ps
CPU time 6.01 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:20:00 PM PST 24
Peak memory 239700 kb
Host smart-98ae511a-4374-451b-855c-32d5ece6a654
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362146417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2362146417
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1407650939
Short name T1149
Test name
Test status
Simulation time 4497988241 ps
CPU time 450.36 seconds
Started Feb 21 03:19:53 PM PST 24
Finished Feb 21 03:27:23 PM PST 24
Peak memory 1290340 kb
Host smart-558f194b-c86d-4356-8db7-081108ed70a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407650939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1407650939
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.4178798682
Short name T475
Test name
Test status
Simulation time 2320613288 ps
CPU time 65.91 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:21:32 PM PST 24
Peak memory 268972 kb
Host smart-ff55c8f3-fd63-4a62-941e-776482417895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178798682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.4178798682
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3090668680
Short name T866
Test name
Test status
Simulation time 32842407 ps
CPU time 0.63 seconds
Started Feb 21 03:19:58 PM PST 24
Finished Feb 21 03:19:59 PM PST 24
Peak memory 202220 kb
Host smart-d0150ddc-7c41-470a-a315-e4bb58e58a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090668680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3090668680
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.215891652
Short name T24
Test name
Test status
Simulation time 49024876723 ps
CPU time 410.23 seconds
Started Feb 21 03:20:21 PM PST 24
Finished Feb 21 03:27:11 PM PST 24
Peak memory 219392 kb
Host smart-ea166624-6e95-4d3b-8ecc-80648c086a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215891652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.215891652
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_rx_oversample.1125961879
Short name T214
Test name
Test status
Simulation time 2383866464 ps
CPU time 163.09 seconds
Started Feb 21 03:19:50 PM PST 24
Finished Feb 21 03:22:33 PM PST 24
Peak memory 276660 kb
Host smart-deb09727-c0bc-4173-83b4-b7f8dad8e113
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125961879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_rx_oversample
.1125961879
Directory /workspace/45.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.4181617311
Short name T278
Test name
Test status
Simulation time 4356550685 ps
CPU time 28.71 seconds
Started Feb 21 03:19:51 PM PST 24
Finished Feb 21 03:20:20 PM PST 24
Peak memory 240964 kb
Host smart-b6b811a9-0892-4b9f-9cc5-f66205a7d7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181617311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.4181617311
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.601914695
Short name T314
Test name
Test status
Simulation time 5689665685 ps
CPU time 12 seconds
Started Feb 21 03:20:25 PM PST 24
Finished Feb 21 03:20:37 PM PST 24
Peak memory 219684 kb
Host smart-a5040e88-9682-45dc-8bbb-7b9f7787734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601914695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.601914695
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.422874440
Short name T777
Test name
Test status
Simulation time 2057574960 ps
CPU time 2.75 seconds
Started Feb 21 03:20:08 PM PST 24
Finished Feb 21 03:20:11 PM PST 24
Peak memory 203436 kb
Host smart-cf7d1067-dcfd-4a6f-94df-bf80f00b768c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422874440 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.422874440
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2258855283
Short name T691
Test name
Test status
Simulation time 10180655894 ps
CPU time 28.31 seconds
Started Feb 21 03:20:08 PM PST 24
Finished Feb 21 03:20:36 PM PST 24
Peak memory 410144 kb
Host smart-595f1595-f8e7-4a6c-a40f-0a9229691c76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258855283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2258855283
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3880343688
Short name T629
Test name
Test status
Simulation time 10120761366 ps
CPU time 29.04 seconds
Started Feb 21 03:20:15 PM PST 24
Finished Feb 21 03:20:45 PM PST 24
Peak memory 402740 kb
Host smart-f256723e-325f-44e4-b91a-e795c83f79ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880343688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3880343688
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.4106562599
Short name T61
Test name
Test status
Simulation time 475253113 ps
CPU time 2.5 seconds
Started Feb 21 03:20:22 PM PST 24
Finished Feb 21 03:20:25 PM PST 24
Peak memory 203236 kb
Host smart-52275dcb-4f79-4644-a45d-0bd8d85cf46e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106562599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.4106562599
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2070086432
Short name T727
Test name
Test status
Simulation time 4222017587 ps
CPU time 7.57 seconds
Started Feb 21 03:20:23 PM PST 24
Finished Feb 21 03:20:31 PM PST 24
Peak memory 203444 kb
Host smart-b84321b0-8361-41df-a36c-fb59394670e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070086432 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2070086432
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3131247145
Short name T893
Test name
Test status
Simulation time 7217519645 ps
CPU time 38.76 seconds
Started Feb 21 03:20:07 PM PST 24
Finished Feb 21 03:20:46 PM PST 24
Peak memory 860352 kb
Host smart-eab43ae6-eaa7-4aba-918b-13ed2332b758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131247145 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3131247145
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.1717254422
Short name T972
Test name
Test status
Simulation time 2422440817 ps
CPU time 3.84 seconds
Started Feb 21 03:20:25 PM PST 24
Finished Feb 21 03:20:29 PM PST 24
Peak memory 203384 kb
Host smart-e605935c-f9fb-4a1e-a502-15f4f79d642f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717254422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.1717254422
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2393488333
Short name T365
Test name
Test status
Simulation time 2229148143 ps
CPU time 29.44 seconds
Started Feb 21 03:20:10 PM PST 24
Finished Feb 21 03:20:40 PM PST 24
Peak memory 203428 kb
Host smart-2b3e7e9c-1940-489a-8320-c6a7222dadf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393488333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2393488333
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.206528460
Short name T260
Test name
Test status
Simulation time 12171060662 ps
CPU time 47.87 seconds
Started Feb 21 03:20:09 PM PST 24
Finished Feb 21 03:20:58 PM PST 24
Peak memory 219756 kb
Host smart-2ec3e069-b2d5-4d84-b205-9473b8bc5db2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206528460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_target_stress_all.206528460
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3793426766
Short name T1508
Test name
Test status
Simulation time 2883963527 ps
CPU time 32.51 seconds
Started Feb 21 03:20:21 PM PST 24
Finished Feb 21 03:20:54 PM PST 24
Peak memory 203436 kb
Host smart-9cf7b4e2-9bd5-4a77-b8e9-9fbd4fc59bdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793426766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3793426766
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1663501936
Short name T711
Test name
Test status
Simulation time 55738076421 ps
CPU time 403.04 seconds
Started Feb 21 03:20:21 PM PST 24
Finished Feb 21 03:27:04 PM PST 24
Peak memory 3269808 kb
Host smart-03d4df74-d6f4-4b36-a37b-98bcb8c6a5d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663501936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1663501936
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3698478075
Short name T1048
Test name
Test status
Simulation time 6072898476 ps
CPU time 30.77 seconds
Started Feb 21 03:20:06 PM PST 24
Finished Feb 21 03:20:38 PM PST 24
Peak memory 501632 kb
Host smart-7299fcab-0f93-414d-8e5d-c44e6c4c7c87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698478075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3698478075
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2254268845
Short name T1108
Test name
Test status
Simulation time 2909073248 ps
CPU time 6.45 seconds
Started Feb 21 03:20:21 PM PST 24
Finished Feb 21 03:20:28 PM PST 24
Peak memory 207364 kb
Host smart-37915126-8333-467e-90f4-37235921f524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254268845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2254268845
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_ovf.3329984168
Short name T1197
Test name
Test status
Simulation time 5494167682 ps
CPU time 169.64 seconds
Started Feb 21 03:20:08 PM PST 24
Finished Feb 21 03:22:58 PM PST 24
Peak memory 492824 kb
Host smart-e05d09e3-1b6c-46d3-9f6c-3804a816bd36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329984168 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_tx_ovf.3329984168
Directory /workspace/45.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.52944674
Short name T1204
Test name
Test status
Simulation time 1233890504 ps
CPU time 6.4 seconds
Started Feb 21 03:20:08 PM PST 24
Finished Feb 21 03:20:15 PM PST 24
Peak memory 203420 kb
Host smart-c63edcb7-5bca-4ad9-9888-67f0f57da34f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52944674 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_unexp_stop.52944674
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3525988920
Short name T900
Test name
Test status
Simulation time 26989496 ps
CPU time 0.61 seconds
Started Feb 21 03:20:15 PM PST 24
Finished Feb 21 03:20:16 PM PST 24
Peak memory 202108 kb
Host smart-1b4099b6-ab29-473c-a04f-6021cf7053a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525988920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3525988920
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.4218630420
Short name T55
Test name
Test status
Simulation time 75030097 ps
CPU time 1.42 seconds
Started Feb 21 03:20:25 PM PST 24
Finished Feb 21 03:20:27 PM PST 24
Peak memory 219632 kb
Host smart-34b6e016-2ff1-4694-bae8-887a73f31a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218630420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.4218630420
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.1252916096
Short name T932
Test name
Test status
Simulation time 288620648 ps
CPU time 5.29 seconds
Started Feb 21 03:20:09 PM PST 24
Finished Feb 21 03:20:15 PM PST 24
Peak memory 259872 kb
Host smart-f6a3f57a-921a-45a6-b013-fc89c1cdf840
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252916096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.1252916096
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.463514400
Short name T503
Test name
Test status
Simulation time 11204852659 ps
CPU time 112.41 seconds
Started Feb 21 03:20:06 PM PST 24
Finished Feb 21 03:21:59 PM PST 24
Peak memory 874284 kb
Host smart-434dab78-ac2d-484e-b379-7cc148624858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463514400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.463514400
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1335380044
Short name T1044
Test name
Test status
Simulation time 5857079529 ps
CPU time 447.98 seconds
Started Feb 21 03:20:21 PM PST 24
Finished Feb 21 03:27:49 PM PST 24
Peak memory 1666552 kb
Host smart-cd69af57-fed6-439f-99a8-e56fe4995df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335380044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1335380044
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3462828550
Short name T1489
Test name
Test status
Simulation time 409714987 ps
CPU time 0.93 seconds
Started Feb 21 03:20:04 PM PST 24
Finished Feb 21 03:20:06 PM PST 24
Peak memory 202984 kb
Host smart-a11da68d-5d7e-4da8-995a-dd458d45b58d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462828550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3462828550
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2049834696
Short name T1133
Test name
Test status
Simulation time 268643636 ps
CPU time 14.11 seconds
Started Feb 21 03:20:05 PM PST 24
Finished Feb 21 03:20:20 PM PST 24
Peak memory 203240 kb
Host smart-13633c2b-8b41-4039-8206-c89760bb5f0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049834696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2049834696
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.4231490626
Short name T1305
Test name
Test status
Simulation time 3819862886 ps
CPU time 184.92 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:23:31 PM PST 24
Peak memory 1128180 kb
Host smart-49894525-620f-4d65-aef9-447dffd811e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231490626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4231490626
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3347800605
Short name T1200
Test name
Test status
Simulation time 5118909636 ps
CPU time 112.65 seconds
Started Feb 21 03:20:09 PM PST 24
Finished Feb 21 03:22:02 PM PST 24
Peak memory 262840 kb
Host smart-f3acb6e6-f5ff-42d6-94b6-244bf4dee739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347800605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3347800605
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2030355788
Short name T172
Test name
Test status
Simulation time 27655718 ps
CPU time 0.64 seconds
Started Feb 21 03:20:11 PM PST 24
Finished Feb 21 03:20:13 PM PST 24
Peak memory 202968 kb
Host smart-83a7f98b-92cd-44ce-ae79-ea1971b57243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030355788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2030355788
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.4087882032
Short name T1129
Test name
Test status
Simulation time 14250183398 ps
CPU time 141.42 seconds
Started Feb 21 03:20:08 PM PST 24
Finished Feb 21 03:22:30 PM PST 24
Peak memory 269036 kb
Host smart-8fa47351-7fb2-481c-bf28-95b94504826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087882032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.4087882032
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_rx_oversample.1497947846
Short name T702
Test name
Test status
Simulation time 2280424720 ps
CPU time 138.71 seconds
Started Feb 21 03:20:24 PM PST 24
Finished Feb 21 03:22:43 PM PST 24
Peak memory 256176 kb
Host smart-9881f0bc-face-4480-ab8c-b39392873f5f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497947846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_rx_oversample
.1497947846
Directory /workspace/46.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.178274447
Short name T1175
Test name
Test status
Simulation time 11127329467 ps
CPU time 68.69 seconds
Started Feb 21 03:20:07 PM PST 24
Finished Feb 21 03:21:16 PM PST 24
Peak memory 307456 kb
Host smart-d6ef5fa8-940f-470d-8e9d-06c22a767132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178274447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.178274447
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1042638110
Short name T1509
Test name
Test status
Simulation time 2441039761 ps
CPU time 52.24 seconds
Started Feb 21 03:20:09 PM PST 24
Finished Feb 21 03:21:02 PM PST 24
Peak memory 219676 kb
Host smart-e9f1c959-28eb-4a5c-9d58-ad98ed7cd0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042638110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1042638110
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.4072846808
Short name T536
Test name
Test status
Simulation time 929912591 ps
CPU time 4.05 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:20:30 PM PST 24
Peak memory 203344 kb
Host smart-61b87296-c999-45fd-b2de-cd7987a8184a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072846808 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.4072846808
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2350202608
Short name T397
Test name
Test status
Simulation time 10236739750 ps
CPU time 11.42 seconds
Started Feb 21 03:20:25 PM PST 24
Finished Feb 21 03:20:37 PM PST 24
Peak memory 253712 kb
Host smart-23f62e43-ec28-41fe-99f8-51db132804cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350202608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2350202608
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.966115823
Short name T863
Test name
Test status
Simulation time 10033346919 ps
CPU time 82.68 seconds
Started Feb 21 03:20:07 PM PST 24
Finished Feb 21 03:21:30 PM PST 24
Peak memory 671736 kb
Host smart-395dd46a-21c0-4b8b-a7a8-93a4ed1c159d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966115823 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.966115823
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1972608652
Short name T1037
Test name
Test status
Simulation time 2613890890 ps
CPU time 2.91 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:20:29 PM PST 24
Peak memory 203456 kb
Host smart-a983a431-f21d-487b-ab0f-1808b1745cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972608652 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1972608652
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2640822348
Short name T680
Test name
Test status
Simulation time 6302655467 ps
CPU time 3.22 seconds
Started Feb 21 03:20:24 PM PST 24
Finished Feb 21 03:20:28 PM PST 24
Peak memory 203416 kb
Host smart-85682fb5-c392-457f-bc42-8061bbeaaaf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640822348 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2640822348
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.3098304876
Short name T714
Test name
Test status
Simulation time 27025601738 ps
CPU time 369.06 seconds
Started Feb 21 03:20:15 PM PST 24
Finished Feb 21 03:26:25 PM PST 24
Peak memory 2437904 kb
Host smart-8fc9f4f3-897a-4982-aa09-bcbeff4fedb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098304876 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.3098304876
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.426426495
Short name T258
Test name
Test status
Simulation time 988526841 ps
CPU time 5.57 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:20:32 PM PST 24
Peak memory 209176 kb
Host smart-381d2ed7-cbff-4b94-9f56-799605e3086b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426426495 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_perf.426426495
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.974088457
Short name T872
Test name
Test status
Simulation time 2740616593 ps
CPU time 8.71 seconds
Started Feb 21 03:20:38 PM PST 24
Finished Feb 21 03:20:47 PM PST 24
Peak memory 203392 kb
Host smart-6bafbaf7-8686-4576-a551-8146c828cc9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974088457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.974088457
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.861429915
Short name T560
Test name
Test status
Simulation time 5069959531 ps
CPU time 61.06 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:21:27 PM PST 24
Peak memory 203420 kb
Host smart-5fa1e20a-b4e4-4842-b45b-7510cf38521a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861429915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.861429915
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2090337382
Short name T1060
Test name
Test status
Simulation time 1346477836 ps
CPU time 6.67 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:20:33 PM PST 24
Peak memory 215584 kb
Host smart-8ca119e0-4243-4df2-b07c-536b2010d91a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090337382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2090337382
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_ovf.2275598359
Short name T623
Test name
Test status
Simulation time 42863294228 ps
CPU time 174.36 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:23:21 PM PST 24
Peak memory 472200 kb
Host smart-98cd5964-9453-4fd2-9cda-5fa8a75e347d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275598359 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_tx_ovf.2275598359
Directory /workspace/46.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.2721520498
Short name T690
Test name
Test status
Simulation time 12648970786 ps
CPU time 5.46 seconds
Started Feb 21 03:20:27 PM PST 24
Finished Feb 21 03:20:33 PM PST 24
Peak memory 203664 kb
Host smart-7b6d8e7e-d134-4489-8346-41e745f00736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721520498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.2721520498
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1408055608
Short name T1374
Test name
Test status
Simulation time 34791229 ps
CPU time 0.6 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 03:20:40 PM PST 24
Peak memory 202072 kb
Host smart-a2795f29-0c25-4479-b05d-ca4c1e0ff1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408055608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1408055608
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3201411061
Short name T353
Test name
Test status
Simulation time 55620455 ps
CPU time 1.46 seconds
Started Feb 21 03:20:29 PM PST 24
Finished Feb 21 03:20:31 PM PST 24
Peak memory 211608 kb
Host smart-c69346ed-1d07-44c2-b850-71a0c1b994b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201411061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3201411061
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1259378704
Short name T1085
Test name
Test status
Simulation time 306669406 ps
CPU time 7.18 seconds
Started Feb 21 03:20:27 PM PST 24
Finished Feb 21 03:20:35 PM PST 24
Peak memory 266392 kb
Host smart-27b93a28-e3c1-4ec3-822b-4a597cea7150
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259378704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1259378704
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2969928518
Short name T332
Test name
Test status
Simulation time 60533851869 ps
CPU time 118.71 seconds
Started Feb 21 03:20:27 PM PST 24
Finished Feb 21 03:22:27 PM PST 24
Peak memory 880284 kb
Host smart-3ea96a3d-d384-4a23-9746-8228071174e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969928518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2969928518
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1255937031
Short name T933
Test name
Test status
Simulation time 5748396533 ps
CPU time 808.34 seconds
Started Feb 21 03:20:24 PM PST 24
Finished Feb 21 03:33:53 PM PST 24
Peak memory 1665828 kb
Host smart-65ecf19b-ab71-4e65-ba9c-a6189338829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255937031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1255937031
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1775702280
Short name T450
Test name
Test status
Simulation time 114297007 ps
CPU time 1.01 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:20:43 PM PST 24
Peak memory 203216 kb
Host smart-0729685d-064c-4449-a94e-48ba3198ce54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775702280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1775702280
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.555710461
Short name T1138
Test name
Test status
Simulation time 871679533 ps
CPU time 5.51 seconds
Started Feb 21 03:20:39 PM PST 24
Finished Feb 21 03:20:45 PM PST 24
Peak memory 244748 kb
Host smart-f6b6aebe-8f64-4c53-a4cc-05c0884b5cf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555710461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
555710461
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2782478211
Short name T1086
Test name
Test status
Simulation time 57046303065 ps
CPU time 308.36 seconds
Started Feb 21 03:20:28 PM PST 24
Finished Feb 21 03:25:37 PM PST 24
Peak memory 1517388 kb
Host smart-faf547fa-744d-4e8c-964d-a008ed1e70e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782478211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2782478211
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.701656598
Short name T521
Test name
Test status
Simulation time 9060974506 ps
CPU time 73.09 seconds
Started Feb 21 03:20:38 PM PST 24
Finished Feb 21 03:21:52 PM PST 24
Peak memory 309228 kb
Host smart-f57254cd-11d2-45eb-8afa-c9e1a6f3727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701656598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.701656598
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.436701752
Short name T454
Test name
Test status
Simulation time 54167757 ps
CPU time 0.66 seconds
Started Feb 21 03:20:27 PM PST 24
Finished Feb 21 03:20:28 PM PST 24
Peak memory 202332 kb
Host smart-b16d47cb-c587-427c-97f3-6fa2a203dc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436701752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.436701752
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.562332645
Short name T764
Test name
Test status
Simulation time 1363815323 ps
CPU time 13.48 seconds
Started Feb 21 03:20:39 PM PST 24
Finished Feb 21 03:20:52 PM PST 24
Peak memory 218908 kb
Host smart-4d7aad59-77e2-45be-a76b-979cd69d6cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562332645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.562332645
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_rx_oversample.3047657779
Short name T396
Test name
Test status
Simulation time 6812591691 ps
CPU time 123.79 seconds
Started Feb 21 03:20:32 PM PST 24
Finished Feb 21 03:22:36 PM PST 24
Peak memory 259248 kb
Host smart-eac10bb2-7117-4bb3-8933-8193328b7d65
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047657779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_rx_oversample
.3047657779
Directory /workspace/47.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.4010019486
Short name T1388
Test name
Test status
Simulation time 4285826686 ps
CPU time 121.18 seconds
Started Feb 21 03:20:29 PM PST 24
Finished Feb 21 03:22:31 PM PST 24
Peak memory 252132 kb
Host smart-cf94aff3-710a-419d-b3e4-97bb067a5a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010019486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.4010019486
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.4211858977
Short name T779
Test name
Test status
Simulation time 14576919881 ps
CPU time 1002.03 seconds
Started Feb 21 03:20:29 PM PST 24
Finished Feb 21 03:37:12 PM PST 24
Peak memory 2677328 kb
Host smart-99afa898-be2c-4206-a37b-d317acddcb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211858977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.4211858977
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1276941238
Short name T918
Test name
Test status
Simulation time 787081813 ps
CPU time 33.55 seconds
Started Feb 21 03:20:27 PM PST 24
Finished Feb 21 03:21:01 PM PST 24
Peak memory 211544 kb
Host smart-05ef9709-de3c-47b7-85f0-a5c6994c4262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276941238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1276941238
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3196656372
Short name T586
Test name
Test status
Simulation time 4611723737 ps
CPU time 4.95 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 03:20:45 PM PST 24
Peak memory 203500 kb
Host smart-21938c50-a295-4fb1-83e1-c357da37b7f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196656372 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3196656372
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2049507354
Short name T66
Test name
Test status
Simulation time 10039975032 ps
CPU time 73.74 seconds
Started Feb 21 03:20:39 PM PST 24
Finished Feb 21 03:21:53 PM PST 24
Peak memory 553476 kb
Host smart-678b1e1b-7086-4f84-912d-6b87edffbdcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049507354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2049507354
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3644643066
Short name T356
Test name
Test status
Simulation time 10105768334 ps
CPU time 25.38 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 03:21:05 PM PST 24
Peak memory 345712 kb
Host smart-facfa805-e7f4-418e-91e6-0e9b3664c20d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644643066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3644643066
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3765630657
Short name T1256
Test name
Test status
Simulation time 739615307 ps
CPU time 3.06 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 03:20:43 PM PST 24
Peak memory 203336 kb
Host smart-27211e99-a158-471d-8690-d2d1ffd218dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765630657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3765630657
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2994537215
Short name T456
Test name
Test status
Simulation time 1712243943 ps
CPU time 4.24 seconds
Started Feb 21 03:20:39 PM PST 24
Finished Feb 21 03:20:43 PM PST 24
Peak memory 203312 kb
Host smart-3ed1e70e-16ac-41ba-9eb2-c3b03c7d6a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994537215 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2994537215
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2637899643
Short name T157
Test name
Test status
Simulation time 21482378372 ps
CPU time 155.69 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:23:03 PM PST 24
Peak memory 1550064 kb
Host smart-db3c968d-6ad8-403f-b116-de34010c7b1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637899643 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2637899643
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.2870077848
Short name T1463
Test name
Test status
Simulation time 2201126352 ps
CPU time 3.45 seconds
Started Feb 21 03:20:38 PM PST 24
Finished Feb 21 03:20:42 PM PST 24
Peak memory 203448 kb
Host smart-a97702a5-f352-499f-b6af-0b00a097f9b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870077848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.2870077848
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1311845196
Short name T721
Test name
Test status
Simulation time 8841951462 ps
CPU time 16.89 seconds
Started Feb 21 03:20:29 PM PST 24
Finished Feb 21 03:20:46 PM PST 24
Peak memory 203228 kb
Host smart-a69cb28d-dabf-4ac1-9fae-b18916d83759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311845196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1311845196
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_all.30985427
Short name T751
Test name
Test status
Simulation time 27099730224 ps
CPU time 28.76 seconds
Started Feb 21 03:20:42 PM PST 24
Finished Feb 21 03:21:12 PM PST 24
Peak memory 213460 kb
Host smart-b10382d1-c96f-46cf-965c-309eb14b5fa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30985427 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.i2c_target_stress_all.30985427
Directory /workspace/47.i2c_target_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.636018726
Short name T994
Test name
Test status
Simulation time 1006357603 ps
CPU time 20.51 seconds
Started Feb 21 03:20:27 PM PST 24
Finished Feb 21 03:20:48 PM PST 24
Peak memory 203432 kb
Host smart-9d77fe39-f3e5-4b1f-85f7-5ccfb6c2732a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636018726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.636018726
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2004925097
Short name T689
Test name
Test status
Simulation time 46619744056 ps
CPU time 150.33 seconds
Started Feb 21 03:20:42 PM PST 24
Finished Feb 21 03:23:12 PM PST 24
Peak memory 1649956 kb
Host smart-2fd0ebd2-46da-4bf8-9749-099c8e586919
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004925097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2004925097
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.634713126
Short name T1188
Test name
Test status
Simulation time 7341647750 ps
CPU time 36.25 seconds
Started Feb 21 03:20:42 PM PST 24
Finished Feb 21 03:21:20 PM PST 24
Peak memory 533852 kb
Host smart-4af0bd4f-d2c9-41d2-9043-4e8dc3fee4cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634713126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_t
arget_stretch.634713126
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2097234400
Short name T1165
Test name
Test status
Simulation time 1630819217 ps
CPU time 6.88 seconds
Started Feb 21 03:20:32 PM PST 24
Finished Feb 21 03:20:39 PM PST 24
Peak memory 208044 kb
Host smart-f982672a-4ffc-4b9b-8e3c-15f91c417713
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097234400 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2097234400
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_ovf.202429651
Short name T315
Test name
Test status
Simulation time 8785372270 ps
CPU time 59.46 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:21:26 PM PST 24
Peak memory 234600 kb
Host smart-654b4606-129d-411c-a016-3e07840c5fc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202429651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_tx_ovf.202429651
Directory /workspace/47.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.1785629463
Short name T733
Test name
Test status
Simulation time 7015087968 ps
CPU time 7.67 seconds
Started Feb 21 03:20:26 PM PST 24
Finished Feb 21 03:20:34 PM PST 24
Peak memory 206752 kb
Host smart-dcf97317-fd0f-4478-b9dc-e50ad5093256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785629463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.1785629463
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.506991920
Short name T664
Test name
Test status
Simulation time 17861643 ps
CPU time 0.59 seconds
Started Feb 21 03:20:45 PM PST 24
Finished Feb 21 03:20:48 PM PST 24
Peak memory 202120 kb
Host smart-55e27232-3f56-46a7-82a5-d15eb337a15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506991920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.506991920
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.895182786
Short name T358
Test name
Test status
Simulation time 92155200 ps
CPU time 1.42 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:20:43 PM PST 24
Peak memory 219616 kb
Host smart-ab1eb8a6-52fc-453d-8bd1-99c35472c5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895182786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.895182786
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.787785807
Short name T1014
Test name
Test status
Simulation time 554773872 ps
CPU time 12.32 seconds
Started Feb 21 03:20:30 PM PST 24
Finished Feb 21 03:20:43 PM PST 24
Peak memory 312040 kb
Host smart-2a5a222b-f935-4255-9a79-1391a7f60201
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787785807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.787785807
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3677453199
Short name T597
Test name
Test status
Simulation time 17842116543 ps
CPU time 119.43 seconds
Started Feb 21 03:20:38 PM PST 24
Finished Feb 21 03:22:38 PM PST 24
Peak memory 1006320 kb
Host smart-362325bc-944b-4848-8cd8-333f8a451ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677453199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3677453199
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.14315583
Short name T1212
Test name
Test status
Simulation time 24591486246 ps
CPU time 864.58 seconds
Started Feb 21 03:20:30 PM PST 24
Finished Feb 21 03:34:54 PM PST 24
Peak memory 1767228 kb
Host smart-92b3dc05-f140-4f6d-8285-e7a16c590e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14315583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.14315583
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1749130464
Short name T1333
Test name
Test status
Simulation time 88387473 ps
CPU time 0.83 seconds
Started Feb 21 03:20:42 PM PST 24
Finished Feb 21 03:20:44 PM PST 24
Peak memory 203060 kb
Host smart-32269d1f-7ac1-40fd-b2e5-74c67cac6df7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749130464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1749130464
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3485697540
Short name T1362
Test name
Test status
Simulation time 878459966 ps
CPU time 5.92 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:20:47 PM PST 24
Peak memory 203320 kb
Host smart-8b7b3877-2a7b-4219-aee2-72abb96f71aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485697540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3485697540
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2876585872
Short name T136
Test name
Test status
Simulation time 20847661494 ps
CPU time 247.22 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 03:24:48 PM PST 24
Peak memory 1448512 kb
Host smart-02010442-f3dd-4303-9316-d6a45c4eedb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876585872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2876585872
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1447508862
Short name T1117
Test name
Test status
Simulation time 6674250407 ps
CPU time 40.85 seconds
Started Feb 21 03:20:45 PM PST 24
Finished Feb 21 03:21:27 PM PST 24
Peak memory 276636 kb
Host smart-cf15b09f-a2f1-4d61-a341-250b34e6512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447508862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1447508862
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.1868829463
Short name T1453
Test name
Test status
Simulation time 17508568 ps
CPU time 0.63 seconds
Started Feb 21 03:20:42 PM PST 24
Finished Feb 21 03:20:43 PM PST 24
Peak memory 202252 kb
Host smart-331bb5d5-b44a-46cd-9fc1-156ae598c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868829463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.1868829463
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1717914601
Short name T183
Test name
Test status
Simulation time 5791858074 ps
CPU time 167.22 seconds
Started Feb 21 03:20:42 PM PST 24
Finished Feb 21 03:23:30 PM PST 24
Peak memory 246416 kb
Host smart-15f12ea8-e294-4ed6-996c-42b28a0feb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717914601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1717914601
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_rx_oversample.3990145069
Short name T109
Test name
Test status
Simulation time 17154503590 ps
CPU time 241.65 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:24:43 PM PST 24
Peak memory 297436 kb
Host smart-0cab6ed1-1db3-42ea-abbb-b77f78864163
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990145069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_rx_oversample
.3990145069
Directory /workspace/48.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2374666935
Short name T473
Test name
Test status
Simulation time 3707475190 ps
CPU time 56.42 seconds
Started Feb 21 03:20:32 PM PST 24
Finished Feb 21 03:21:28 PM PST 24
Peak memory 300024 kb
Host smart-892d2b01-8698-4dbd-aa68-567ec73aa4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374666935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2374666935
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2332870027
Short name T231
Test name
Test status
Simulation time 40071057472 ps
CPU time 1509.93 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 03:45:50 PM PST 24
Peak memory 2579324 kb
Host smart-89147b29-b93f-4ec6-bea3-d46062f214ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332870027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2332870027
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2956890195
Short name T919
Test name
Test status
Simulation time 4467669395 ps
CPU time 7.91 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:20:49 PM PST 24
Peak memory 211572 kb
Host smart-c408e611-d689-4482-b8ea-1374c4858918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956890195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2956890195
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3025311094
Short name T958
Test name
Test status
Simulation time 6961877341 ps
CPU time 3.4 seconds
Started Feb 21 03:20:48 PM PST 24
Finished Feb 21 03:20:54 PM PST 24
Peak memory 203132 kb
Host smart-e136d489-8df6-40d0-a7a7-1bdd76586798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025311094 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3025311094
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.4155646867
Short name T1436
Test name
Test status
Simulation time 10034524749 ps
CPU time 66.56 seconds
Started Feb 21 03:20:39 PM PST 24
Finished Feb 21 03:21:46 PM PST 24
Peak memory 526360 kb
Host smart-06ca861e-a34d-4be2-9743-59755bd08aba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155646867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.4155646867
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3504206656
Short name T647
Test name
Test status
Simulation time 10248346039 ps
CPU time 16.04 seconds
Started Feb 21 03:20:51 PM PST 24
Finished Feb 21 03:21:09 PM PST 24
Peak memory 327816 kb
Host smart-9551faab-7e89-4619-a781-a167f6a50ff5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504206656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3504206656
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.4095658048
Short name T1092
Test name
Test status
Simulation time 2063009586 ps
CPU time 2.68 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:20:44 PM PST 24
Peak memory 203388 kb
Host smart-97d32982-1432-49e3-bc08-01432e1683f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095658048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.4095658048
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1404730638
Short name T1399
Test name
Test status
Simulation time 5549426104 ps
CPU time 5.23 seconds
Started Feb 21 03:20:43 PM PST 24
Finished Feb 21 03:20:50 PM PST 24
Peak memory 203488 kb
Host smart-ed0a9b4a-6b7b-4262-b0c1-0734204d4c39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404730638 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1404730638
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.452801778
Short name T1115
Test name
Test status
Simulation time 4893906829 ps
CPU time 43.8 seconds
Started Feb 21 03:20:48 PM PST 24
Finished Feb 21 03:21:35 PM PST 24
Peak memory 965236 kb
Host smart-159e9c27-921b-4b44-b74c-31d333e7eb0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452801778 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.452801778
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.2837055323
Short name T446
Test name
Test status
Simulation time 1885255243 ps
CPU time 2.99 seconds
Started Feb 21 03:20:48 PM PST 24
Finished Feb 21 03:20:53 PM PST 24
Peak memory 203364 kb
Host smart-a59fe56e-cb9d-462b-af90-1dfae2ae5635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837055323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.2837055323
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1191937053
Short name T468
Test name
Test status
Simulation time 4208429792 ps
CPU time 12.88 seconds
Started Feb 21 03:20:45 PM PST 24
Finished Feb 21 03:20:59 PM PST 24
Peak memory 203396 kb
Host smart-6f2e3320-5b92-48a9-8007-4c801646819a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191937053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1191937053
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1132630708
Short name T1066
Test name
Test status
Simulation time 1207468153 ps
CPU time 17.99 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:20:59 PM PST 24
Peak memory 212900 kb
Host smart-51412764-41b6-4863-9e81-66e268c126f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132630708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1132630708
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.482600005
Short name T246
Test name
Test status
Simulation time 63882237349 ps
CPU time 102.87 seconds
Started Feb 21 03:20:54 PM PST 24
Finished Feb 21 03:22:37 PM PST 24
Peak memory 1172924 kb
Host smart-0f596b65-8b01-4697-a72d-a4dca0b98050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482600005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.482600005
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3822538894
Short name T289
Test name
Test status
Simulation time 6571882212 ps
CPU time 84.5 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 03:22:05 PM PST 24
Peak memory 522396 kb
Host smart-47641c3b-b885-49b9-9ea8-0d7efbfb39e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822538894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3822538894
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1144080372
Short name T1084
Test name
Test status
Simulation time 1603762761 ps
CPU time 7.1 seconds
Started Feb 21 03:20:41 PM PST 24
Finished Feb 21 03:20:48 PM PST 24
Peak memory 208408 kb
Host smart-39e5e80c-4bfd-4a92-9d64-05f3f04f9a1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144080372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1144080372
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_ovf.2465695632
Short name T434
Test name
Test status
Simulation time 2142843386 ps
CPU time 34.34 seconds
Started Feb 21 03:20:44 PM PST 24
Finished Feb 21 03:21:20 PM PST 24
Peak memory 221728 kb
Host smart-013f48e6-033c-4a8e-8571-e619e649f0a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465695632 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_tx_ovf.2465695632
Directory /workspace/48.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.3897242616
Short name T1274
Test name
Test status
Simulation time 1307574490 ps
CPU time 4.8 seconds
Started Feb 21 03:20:43 PM PST 24
Finished Feb 21 03:20:49 PM PST 24
Peak memory 203432 kb
Host smart-46896f7e-6436-44e8-827f-47fe1799d94a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897242616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.3897242616
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1759053325
Short name T873
Test name
Test status
Simulation time 15138678 ps
CPU time 0.59 seconds
Started Feb 21 03:20:55 PM PST 24
Finished Feb 21 03:20:56 PM PST 24
Peak memory 203016 kb
Host smart-bd51dcfb-42b4-4702-8dbd-e375fefec5f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759053325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1759053325
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1514564593
Short name T1395
Test name
Test status
Simulation time 141164434 ps
CPU time 1.21 seconds
Started Feb 21 03:20:53 PM PST 24
Finished Feb 21 03:20:55 PM PST 24
Peak memory 211488 kb
Host smart-1a711ccc-fb27-424d-801f-28270e91693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514564593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1514564593
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1034175811
Short name T1045
Test name
Test status
Simulation time 1612619411 ps
CPU time 8.04 seconds
Started Feb 21 03:20:47 PM PST 24
Finished Feb 21 03:20:58 PM PST 24
Peak memory 290456 kb
Host smart-0beb76b5-9904-402c-871d-9473a50526c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034175811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1034175811
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1800487443
Short name T1441
Test name
Test status
Simulation time 2714422242 ps
CPU time 181.02 seconds
Started Feb 21 03:20:50 PM PST 24
Finished Feb 21 03:23:54 PM PST 24
Peak memory 693956 kb
Host smart-305d90d2-8217-4a5b-9c5f-6b2fd487c974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800487443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1800487443
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2800866399
Short name T219
Test name
Test status
Simulation time 15868238342 ps
CPU time 194.36 seconds
Started Feb 21 03:20:50 PM PST 24
Finished Feb 21 03:24:06 PM PST 24
Peak memory 1156720 kb
Host smart-ce178d26-f959-49f5-8ec1-b8bb09f27099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800866399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2800866399
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3842772272
Short name T1145
Test name
Test status
Simulation time 985115663 ps
CPU time 0.88 seconds
Started Feb 21 03:20:46 PM PST 24
Finished Feb 21 03:20:50 PM PST 24
Peak memory 203056 kb
Host smart-dc2da7f8-a49f-45da-84e1-7303412b1679
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842772272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3842772272
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3372785987
Short name T336
Test name
Test status
Simulation time 1118949885 ps
CPU time 7.03 seconds
Started Feb 21 03:20:46 PM PST 24
Finished Feb 21 03:20:55 PM PST 24
Peak memory 258152 kb
Host smart-db3f6dd8-94fc-433d-a191-80ef823f9b73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372785987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3372785987
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.601818841
Short name T1418
Test name
Test status
Simulation time 13757377508 ps
CPU time 380.62 seconds
Started Feb 21 03:20:54 PM PST 24
Finished Feb 21 03:27:15 PM PST 24
Peak memory 1917776 kb
Host smart-b873d04d-88ac-45b5-bc01-d4700fe571f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601818841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.601818841
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.2388205494
Short name T56
Test name
Test status
Simulation time 11467743654 ps
CPU time 64.42 seconds
Started Feb 21 03:20:54 PM PST 24
Finished Feb 21 03:21:59 PM PST 24
Peak memory 314608 kb
Host smart-c28e19b6-ecca-4151-9703-0f24ddc8faaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388205494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2388205494
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3603455084
Short name T639
Test name
Test status
Simulation time 36991046 ps
CPU time 0.61 seconds
Started Feb 21 03:20:50 PM PST 24
Finished Feb 21 03:20:52 PM PST 24
Peak memory 202272 kb
Host smart-f1b2114b-b7cc-4a81-b0f7-4bdac6a57714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603455084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3603455084
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1132472149
Short name T1209
Test name
Test status
Simulation time 8247241125 ps
CPU time 22.03 seconds
Started Feb 21 03:20:45 PM PST 24
Finished Feb 21 03:21:09 PM PST 24
Peak memory 203360 kb
Host smart-9fd3901a-c8a2-4953-8324-6f0a665c966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132472149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1132472149
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_rx_oversample.80265482
Short name T613
Test name
Test status
Simulation time 11878674491 ps
CPU time 221.47 seconds
Started Feb 21 03:20:45 PM PST 24
Finished Feb 21 03:24:28 PM PST 24
Peak memory 437676 kb
Host smart-ae5715b3-66c5-4b42-bbd5-b982d7a8ef18
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80265482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_rx_oversample.80265482
Directory /workspace/49.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4288531438
Short name T328
Test name
Test status
Simulation time 28073197374 ps
CPU time 52.98 seconds
Started Feb 21 03:20:46 PM PST 24
Finished Feb 21 03:21:41 PM PST 24
Peak memory 299208 kb
Host smart-c85ced7f-0c43-4f54-bc84-e9f9cf503838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288531438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4288531438
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.4263944955
Short name T238
Test name
Test status
Simulation time 83853693866 ps
CPU time 3095.32 seconds
Started Feb 21 03:20:40 PM PST 24
Finished Feb 21 04:12:16 PM PST 24
Peak memory 3813676 kb
Host smart-89108c02-bc32-421f-8358-4d2288914151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263944955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.4263944955
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3128858049
Short name T216
Test name
Test status
Simulation time 2650682074 ps
CPU time 10.81 seconds
Started Feb 21 03:20:45 PM PST 24
Finished Feb 21 03:20:57 PM PST 24
Peak memory 214532 kb
Host smart-7ca88048-fbfd-43d0-8bd0-aabf2e38ba05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128858049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3128858049
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3773640783
Short name T992
Test name
Test status
Simulation time 1749713454 ps
CPU time 2.38 seconds
Started Feb 21 03:20:52 PM PST 24
Finished Feb 21 03:20:55 PM PST 24
Peak memory 203372 kb
Host smart-6cc0db7a-2342-4284-ab73-8a2d3b1379d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773640783 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3773640783
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3674786576
Short name T616
Test name
Test status
Simulation time 10870368283 ps
CPU time 2.86 seconds
Started Feb 21 03:20:49 PM PST 24
Finished Feb 21 03:20:54 PM PST 24
Peak memory 214436 kb
Host smart-2289ea40-b755-4a90-9bd0-cadfe0969c8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674786576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3674786576
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1424182583
Short name T403
Test name
Test status
Simulation time 10145157788 ps
CPU time 14.32 seconds
Started Feb 21 03:20:54 PM PST 24
Finished Feb 21 03:21:09 PM PST 24
Peak memory 296184 kb
Host smart-28ab72b9-c47a-4c4f-bc64-730163bd7df4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424182583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1424182583
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.843653381
Short name T1023
Test name
Test status
Simulation time 656114128 ps
CPU time 2.89 seconds
Started Feb 21 03:20:53 PM PST 24
Finished Feb 21 03:20:57 PM PST 24
Peak memory 203372 kb
Host smart-fa36d52d-c9dc-4147-9958-8baecf3d8cf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843653381 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.843653381
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3883896428
Short name T147
Test name
Test status
Simulation time 6745902731 ps
CPU time 7.02 seconds
Started Feb 21 03:20:50 PM PST 24
Finished Feb 21 03:20:59 PM PST 24
Peak memory 203444 kb
Host smart-0ed04c8f-4ca5-41e5-8c71-22a8556e4826
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883896428 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3883896428
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2853807763
Short name T1458
Test name
Test status
Simulation time 18133201833 ps
CPU time 204.14 seconds
Started Feb 21 03:20:46 PM PST 24
Finished Feb 21 03:24:13 PM PST 24
Peak memory 2030656 kb
Host smart-6c8bafc6-2a97-4ac3-88a5-92a765360ff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853807763 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2853807763
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.3647263011
Short name T442
Test name
Test status
Simulation time 854881745 ps
CPU time 2.99 seconds
Started Feb 21 03:20:53 PM PST 24
Finished Feb 21 03:20:57 PM PST 24
Peak memory 203368 kb
Host smart-442206e2-0d04-4c69-91e8-d27314df4174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647263011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.3647263011
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3212226915
Short name T490
Test name
Test status
Simulation time 5611499707 ps
CPU time 37.89 seconds
Started Feb 21 03:20:54 PM PST 24
Finished Feb 21 03:21:32 PM PST 24
Peak memory 203412 kb
Host smart-d4ce269d-4e2a-4ad3-aa76-02783178e2c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212226915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3212226915
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.579738523
Short name T211
Test name
Test status
Simulation time 65582151745 ps
CPU time 152.15 seconds
Started Feb 21 03:20:54 PM PST 24
Finished Feb 21 03:23:26 PM PST 24
Peak memory 1015000 kb
Host smart-e68899b8-ed43-48f7-a0fd-0d14e233bab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579738523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_stress_all.579738523
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.4118338362
Short name T836
Test name
Test status
Simulation time 1994442756 ps
CPU time 20.77 seconds
Started Feb 21 03:20:44 PM PST 24
Finished Feb 21 03:21:06 PM PST 24
Peak memory 203432 kb
Host smart-d0776a8a-1588-490d-9837-b593fd176259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118338362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.4118338362
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1833967264
Short name T650
Test name
Test status
Simulation time 47749153299 ps
CPU time 314.97 seconds
Started Feb 21 03:20:50 PM PST 24
Finished Feb 21 03:26:08 PM PST 24
Peak memory 2764436 kb
Host smart-18c637b1-ec55-44ac-a4bc-1d929d6fc4e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833967264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1833967264
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.628774433
Short name T458
Test name
Test status
Simulation time 1757863540 ps
CPU time 7.11 seconds
Started Feb 21 03:20:46 PM PST 24
Finished Feb 21 03:20:56 PM PST 24
Peak memory 203380 kb
Host smart-9cd8aef2-f302-42db-9270-d2d79360ba8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628774433 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.628774433
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_ovf.2090040646
Short name T1109
Test name
Test status
Simulation time 8404407579 ps
CPU time 113.72 seconds
Started Feb 21 03:20:51 PM PST 24
Finished Feb 21 03:22:47 PM PST 24
Peak memory 329664 kb
Host smart-108bf4d6-a6e8-4312-b5a0-38d8bcc711ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090040646 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_tx_ovf.2090040646
Directory /workspace/49.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.2727583033
Short name T1471
Test name
Test status
Simulation time 10113224882 ps
CPU time 8.94 seconds
Started Feb 21 03:20:50 PM PST 24
Finished Feb 21 03:21:01 PM PST 24
Peak memory 210228 kb
Host smart-20b5b8f4-377e-4553-b3c4-b6d04369a8e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727583033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.2727583033
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.1118276713
Short name T88
Test name
Test status
Simulation time 22284867 ps
CPU time 0.6 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 203180 kb
Host smart-f50e02b2-f77b-4e03-ba82-9dbfa69af149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118276713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1118276713
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3562578667
Short name T529
Test name
Test status
Simulation time 30776423 ps
CPU time 1.29 seconds
Started Feb 21 03:14:19 PM PST 24
Finished Feb 21 03:14:21 PM PST 24
Peak memory 211468 kb
Host smart-909a75e0-3f0d-49a1-b053-520c3064eba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562578667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3562578667
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1194673977
Short name T1275
Test name
Test status
Simulation time 3012392172 ps
CPU time 31.52 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:14:45 PM PST 24
Peak memory 337352 kb
Host smart-b021e23c-cbfc-4655-a85c-76394caa999f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194673977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1194673977
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.21977695
Short name T693
Test name
Test status
Simulation time 3393283761 ps
CPU time 316.1 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:19:34 PM PST 24
Peak memory 1048304 kb
Host smart-b2ef8db5-a8f0-435e-a3ef-2c2d3b8f564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21977695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.21977695
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1302192752
Short name T1315
Test name
Test status
Simulation time 6366710459 ps
CPU time 397.86 seconds
Started Feb 21 03:14:19 PM PST 24
Finished Feb 21 03:20:57 PM PST 24
Peak memory 1676992 kb
Host smart-30ecf1fb-a37a-4864-b451-2340bbfaa31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302192752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1302192752
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2491982211
Short name T40
Test name
Test status
Simulation time 659124462 ps
CPU time 1.06 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:19 PM PST 24
Peak memory 203484 kb
Host smart-54fcf84a-d495-4679-be71-b87436a78551
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491982211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2491982211
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1303975300
Short name T380
Test name
Test status
Simulation time 966258752 ps
CPU time 6.84 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 253852 kb
Host smart-416e5929-6048-46a5-a17e-674e77adfd8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303975300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1303975300
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3625222461
Short name T648
Test name
Test status
Simulation time 9743960947 ps
CPU time 516.64 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:22:58 PM PST 24
Peak memory 1395308 kb
Host smart-ed52a3cc-74ad-41f7-9480-7a43b562df68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625222461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3625222461
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.567544650
Short name T672
Test name
Test status
Simulation time 4130261090 ps
CPU time 45.98 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:15:11 PM PST 24
Peak memory 293716 kb
Host smart-c8544e6d-3906-4e70-a41e-5a5173317f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567544650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.567544650
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3370348493
Short name T925
Test name
Test status
Simulation time 31555206 ps
CPU time 0.62 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 202264 kb
Host smart-7cb2539a-97b4-4754-8757-ae93b6c210df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370348493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3370348493
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.2649341282
Short name T646
Test name
Test status
Simulation time 13022316080 ps
CPU time 712.34 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:26:11 PM PST 24
Peak memory 326336 kb
Host smart-2714b58f-6074-48f2-8596-8be7e30af97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649341282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2649341282
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_rx_oversample.3346333540
Short name T1020
Test name
Test status
Simulation time 1976249018 ps
CPU time 64.51 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:15:32 PM PST 24
Peak memory 295508 kb
Host smart-583ac288-a160-4f50-a8e2-e95b0c3cb88d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346333540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_rx_oversample.
3346333540
Directory /workspace/5.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1971177558
Short name T293
Test name
Test status
Simulation time 4431915645 ps
CPU time 50.17 seconds
Started Feb 21 03:14:14 PM PST 24
Finished Feb 21 03:15:04 PM PST 24
Peak memory 252256 kb
Host smart-695eec94-c8ba-4838-bec5-d5b82954f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971177558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1971177558
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.4012151647
Short name T656
Test name
Test status
Simulation time 5087580738 ps
CPU time 10.98 seconds
Started Feb 21 03:14:19 PM PST 24
Finished Feb 21 03:14:31 PM PST 24
Peak memory 219692 kb
Host smart-cc0175f8-bdb0-4074-9dae-c403d9ff3e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012151647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.4012151647
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3160590614
Short name T33
Test name
Test status
Simulation time 795461214 ps
CPU time 3.78 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:27 PM PST 24
Peak memory 203340 kb
Host smart-46078fc2-3f31-4ac3-a979-513a54fd45dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160590614 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3160590614
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3943669602
Short name T840
Test name
Test status
Simulation time 10072049254 ps
CPU time 25.87 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:48 PM PST 24
Peak memory 336540 kb
Host smart-1e96c327-bb21-4a93-af04-2203ccad6024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943669602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3943669602
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1856239228
Short name T934
Test name
Test status
Simulation time 10691390891 ps
CPU time 3.54 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 225256 kb
Host smart-e33b67d1-0154-4a4e-aac2-dadf6465ea81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856239228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1856239228
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3699457510
Short name T666
Test name
Test status
Simulation time 928573893 ps
CPU time 3.15 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 203320 kb
Host smart-e39df4bb-7939-427d-b6cb-cbea063bc8e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699457510 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3699457510
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1144696734
Short name T590
Test name
Test status
Simulation time 19322998807 ps
CPU time 6.14 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 206264 kb
Host smart-85bfe56a-5a60-487d-a556-4b9b773b4a4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144696734 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1144696734
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2207894571
Short name T726
Test name
Test status
Simulation time 12290393542 ps
CPU time 127.07 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:16:24 PM PST 24
Peak memory 1378136 kb
Host smart-34c94eaf-6d4b-47fc-8499-41024338b3ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207894571 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2207894571
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.627615095
Short name T1159
Test name
Test status
Simulation time 11875730771 ps
CPU time 5.13 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 210236 kb
Host smart-02e13c20-bcdb-43ea-a167-60ad1293ed22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627615095 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_perf.627615095
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.1450511699
Short name T769
Test name
Test status
Simulation time 963591868 ps
CPU time 25.06 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:46 PM PST 24
Peak memory 203340 kb
Host smart-5197c247-e0cf-4639-9a5f-e518b37160fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450511699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.1450511699
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.2626267999
Short name T256
Test name
Test status
Simulation time 42430747322 ps
CPU time 88.85 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:15:54 PM PST 24
Peak memory 748216 kb
Host smart-a2bbd85e-1706-406e-b8ff-1faec94dd982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626267999 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.i2c_target_stress_all.2626267999
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3593478958
Short name T678
Test name
Test status
Simulation time 922560912 ps
CPU time 38.56 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:15:02 PM PST 24
Peak memory 203360 kb
Host smart-73abaf0b-6ee9-46bb-90fc-a0a85a2822e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593478958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3593478958
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1138132534
Short name T1417
Test name
Test status
Simulation time 48851881215 ps
CPU time 2602.15 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:57:46 PM PST 24
Peak memory 10019600 kb
Host smart-209635b8-d7ac-4ea7-b7b9-fafa13e0d5dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138132534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1138132534
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3106757266
Short name T579
Test name
Test status
Simulation time 7608744699 ps
CPU time 94.62 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:15:57 PM PST 24
Peak memory 1138936 kb
Host smart-6412cedb-82f3-4ef4-82db-573803049449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106757266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3106757266
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.4087773479
Short name T1259
Test name
Test status
Simulation time 6742116130 ps
CPU time 7.08 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:31 PM PST 24
Peak memory 206452 kb
Host smart-51fde9ca-ce67-475d-9bb1-ca2445dc6f67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087773479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.4087773479
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_ovf.919773754
Short name T715
Test name
Test status
Simulation time 2655695352 ps
CPU time 35.77 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:15:04 PM PST 24
Peak memory 213728 kb
Host smart-165ca7fd-87c2-4cc6-950c-b4e3cd1066f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919773754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_tx_ovf.919773754
Directory /workspace/5.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.2630570015
Short name T1022
Test name
Test status
Simulation time 1941045827 ps
CPU time 9.1 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:37 PM PST 24
Peak memory 214212 kb
Host smart-29f47d44-3cd4-4920-8f06-76e6d4294795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630570015 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.2630570015
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.606756706
Short name T557
Test name
Test status
Simulation time 42633728 ps
CPU time 0.59 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 202112 kb
Host smart-26e95a2f-a610-4688-8121-ba4c8c8207a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606756706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.606756706
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1120348123
Short name T316
Test name
Test status
Simulation time 44147001 ps
CPU time 1.89 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 219596 kb
Host smart-4e8702b8-cb3a-424a-94aa-f476334a2cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120348123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1120348123
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1653504513
Short name T354
Test name
Test status
Simulation time 1558031271 ps
CPU time 20.01 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:47 PM PST 24
Peak memory 285012 kb
Host smart-1304da3d-92bf-40da-97d1-edc9d095a74e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653504513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1653504513
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2478262698
Short name T917
Test name
Test status
Simulation time 9105059715 ps
CPU time 51.45 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:15:19 PM PST 24
Peak memory 400564 kb
Host smart-fed1646b-9996-4d47-80b9-1eb165af8945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478262698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2478262698
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1398277347
Short name T1099
Test name
Test status
Simulation time 8883210624 ps
CPU time 201.49 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:17:48 PM PST 24
Peak memory 1069532 kb
Host smart-adc208ce-1ecd-45cd-ad2a-18dedcd6f524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398277347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1398277347
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1062436922
Short name T515
Test name
Test status
Simulation time 205113763 ps
CPU time 0.92 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 202900 kb
Host smart-0e991e2d-90b8-4fdf-bb62-d9d58d092e9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062436922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1062436922
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3648382536
Short name T735
Test name
Test status
Simulation time 778213531 ps
CPU time 10.73 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:39 PM PST 24
Peak memory 203252 kb
Host smart-5133d152-a3ac-403f-a584-916735bb474b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648382536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3648382536
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.4258392441
Short name T1430
Test name
Test status
Simulation time 6427024612 ps
CPU time 391.81 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:20:58 PM PST 24
Peak memory 1773484 kb
Host smart-76e6af4d-92c7-4e2b-838b-18ed02b72579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258392441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.4258392441
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2222991489
Short name T1228
Test name
Test status
Simulation time 7497784224 ps
CPU time 44.03 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:15:05 PM PST 24
Peak memory 266160 kb
Host smart-c6c2554e-c9e1-411e-ad19-6c52001fff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222991489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2222991489
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3647121757
Short name T1208
Test name
Test status
Simulation time 16934455 ps
CPU time 0.65 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 202248 kb
Host smart-332f9411-1541-4947-bf22-910d25c17516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647121757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3647121757
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1859254736
Short name T660
Test name
Test status
Simulation time 28815683410 ps
CPU time 107.65 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:16:14 PM PST 24
Peak memory 333060 kb
Host smart-1d2b5d81-9156-4813-9430-dad4b1c323e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859254736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1859254736
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_rx_oversample.1123842017
Short name T299
Test name
Test status
Simulation time 5711859169 ps
CPU time 154.43 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:16:59 PM PST 24
Peak memory 348708 kb
Host smart-c439d28f-df7d-4f17-b247-12c4eb611314
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123842017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_rx_oversample.
1123842017
Directory /workspace/6.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1359242450
Short name T1210
Test name
Test status
Simulation time 3514340286 ps
CPU time 43.13 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:15:07 PM PST 24
Peak memory 260420 kb
Host smart-c4019747-4102-478a-946f-2c3bcee9ac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359242450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1359242450
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3938572005
Short name T63
Test name
Test status
Simulation time 60688171261 ps
CPU time 3190.75 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 04:07:38 PM PST 24
Peak memory 772196 kb
Host smart-1dd31cb7-c2ec-41fb-a3c2-268d54d6a790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938572005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3938572005
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.4025584875
Short name T567
Test name
Test status
Simulation time 2915160533 ps
CPU time 33.58 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:15:02 PM PST 24
Peak memory 211600 kb
Host smart-77c562ff-c739-4af6-8acf-eb214f9e8240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025584875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.4025584875
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.918201099
Short name T810
Test name
Test status
Simulation time 1695230738 ps
CPU time 3.37 seconds
Started Feb 21 03:14:19 PM PST 24
Finished Feb 21 03:14:23 PM PST 24
Peak memory 203440 kb
Host smart-2bf8bc33-3f9b-44e4-a0d2-d479e3d4488c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918201099 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.918201099
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1131531837
Short name T1252
Test name
Test status
Simulation time 10057846528 ps
CPU time 44.2 seconds
Started Feb 21 03:14:14 PM PST 24
Finished Feb 21 03:14:58 PM PST 24
Peak memory 417776 kb
Host smart-05228ddc-f184-48d9-9770-f9872ad30dc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131531837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1131531837
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.609578385
Short name T1501
Test name
Test status
Simulation time 10231991725 ps
CPU time 12.28 seconds
Started Feb 21 03:14:12 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 304108 kb
Host smart-a9049d23-63b7-4656-a2df-dd676afa6804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609578385 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.609578385
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3185298159
Short name T49
Test name
Test status
Simulation time 2746827688 ps
CPU time 2.83 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 203412 kb
Host smart-e773cf78-61cf-4b68-b9d8-52aec323419f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185298159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3185298159
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.4088311994
Short name T1155
Test name
Test status
Simulation time 8523118440 ps
CPU time 7.05 seconds
Started Feb 21 03:14:14 PM PST 24
Finished Feb 21 03:14:21 PM PST 24
Peak memory 204484 kb
Host smart-ccef0242-7236-45ff-b122-633f3989f9e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088311994 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.4088311994
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1691541894
Short name T1354
Test name
Test status
Simulation time 17821750520 ps
CPU time 6.68 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 321384 kb
Host smart-24660a17-4090-42f2-b68f-7a4027a39b55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691541894 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1691541894
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.596031920
Short name T1049
Test name
Test status
Simulation time 2947948914 ps
CPU time 4.47 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:22 PM PST 24
Peak memory 209440 kb
Host smart-00a0e1b6-2856-41b1-a110-b2d588f6351d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596031920 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_perf.596031920
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.4247340272
Short name T1452
Test name
Test status
Simulation time 1845849701 ps
CPU time 44.73 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:15:03 PM PST 24
Peak memory 203312 kb
Host smart-ccb21743-44f3-4512-b31f-0d7268f816d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247340272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.4247340272
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.4155693248
Short name T731
Test name
Test status
Simulation time 15587005690 ps
CPU time 64.76 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:15:23 PM PST 24
Peak memory 203268 kb
Host smart-2ea7670f-1829-4230-bbc6-3f4ed72c6b8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155693248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.4155693248
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.399609350
Short name T1005
Test name
Test status
Simulation time 61558034435 ps
CPU time 536.91 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:23:14 PM PST 24
Peak memory 3601104 kb
Host smart-0b5148f9-fa30-4f33-abd8-014cdabc460f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399609350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_wr.399609350
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2813458448
Short name T1011
Test name
Test status
Simulation time 24282639368 ps
CPU time 7.34 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 214148 kb
Host smart-50f8439d-bb97-457e-88d4-1dbdf9306824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813458448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2813458448
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_ovf.1536025310
Short name T767
Test name
Test status
Simulation time 37635623440 ps
CPU time 114.53 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:16:17 PM PST 24
Peak memory 375988 kb
Host smart-a583d3cb-8c7d-4755-b49b-f117c413a6a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536025310 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_tx_ovf.1536025310
Directory /workspace/6.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.3903746278
Short name T1367
Test name
Test status
Simulation time 4773042538 ps
CPU time 6.2 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:33 PM PST 24
Peak memory 203472 kb
Host smart-7da87b2e-f370-4951-b0e4-8b5001a1684a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903746278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.i2c_target_unexp_stop.3903746278
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1554623015
Short name T500
Test name
Test status
Simulation time 19931629 ps
CPU time 0.59 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:14:23 PM PST 24
Peak memory 202128 kb
Host smart-508e1f84-d84b-46ce-9483-9566c273d87a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554623015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1554623015
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2427303866
Short name T593
Test name
Test status
Simulation time 191735489 ps
CPU time 1.39 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 211488 kb
Host smart-5b7a2181-8edf-40ea-9028-9babfb1118ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427303866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2427303866
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2715298656
Short name T1308
Test name
Test status
Simulation time 442044211 ps
CPU time 8.89 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:30 PM PST 24
Peak memory 301716 kb
Host smart-428d11d1-e438-4915-86df-87936178497c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715298656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2715298656
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2604126926
Short name T1019
Test name
Test status
Simulation time 6301864391 ps
CPU time 214.68 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:17:59 PM PST 24
Peak memory 801280 kb
Host smart-1ee934dc-620e-4b15-bd32-1dcb734a4040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604126926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2604126926
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1725627120
Short name T621
Test name
Test status
Simulation time 6006624129 ps
CPU time 788.75 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:27:37 PM PST 24
Peak memory 1663352 kb
Host smart-eaa05ce6-6f5b-4a19-b7aa-e24def0983c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725627120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1725627120
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3577028081
Short name T241
Test name
Test status
Simulation time 87820212 ps
CPU time 0.89 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203080 kb
Host smart-a1c98840-31a4-450a-8d01-afa28160cd1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577028081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3577028081
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1245172674
Short name T404
Test name
Test status
Simulation time 242930508 ps
CPU time 5.3 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 203228 kb
Host smart-e7edf35b-56c8-4d58-96bd-e286d97fce92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245172674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1245172674
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2337997002
Short name T1124
Test name
Test status
Simulation time 28315110449 ps
CPU time 139.69 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:16:48 PM PST 24
Peak memory 1052804 kb
Host smart-c99d4330-b1ca-4f55-869b-0fc8ceefceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337997002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2337997002
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1152808892
Short name T520
Test name
Test status
Simulation time 9606813102 ps
CPU time 98.26 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:16:01 PM PST 24
Peak memory 244228 kb
Host smart-dbaff615-0d05-44fd-ae18-57c0cc7bd76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152808892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1152808892
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.371450694
Short name T173
Test name
Test status
Simulation time 160951379 ps
CPU time 0.63 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:22 PM PST 24
Peak memory 202272 kb
Host smart-f9bb2dbc-be6d-4915-9492-446a8e41b905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371450694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.371450694
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3888809442
Short name T904
Test name
Test status
Simulation time 999881057 ps
CPU time 48.15 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:15:11 PM PST 24
Peak memory 211508 kb
Host smart-43aabdd1-66a1-4e12-905d-2f1612ce87f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888809442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3888809442
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_rx_oversample.15845008
Short name T220
Test name
Test status
Simulation time 19592765344 ps
CPU time 203.51 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:17:45 PM PST 24
Peak memory 402388 kb
Host smart-f16afa93-e690-4a68-a124-af287bf97374
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_rx_oversample.15845008
Directory /workspace/7.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3508499492
Short name T657
Test name
Test status
Simulation time 16876405796 ps
CPU time 40.63 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:15:04 PM PST 24
Peak memory 265112 kb
Host smart-da8a5597-15a1-419d-9791-743d609e891e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508499492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3508499492
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.356764557
Short name T31
Test name
Test status
Simulation time 43902612209 ps
CPU time 989.93 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:30:55 PM PST 24
Peak memory 1944480 kb
Host smart-b6f24454-06a6-4837-a4c1-e896b0524dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356764557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.356764557
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.354378158
Short name T1113
Test name
Test status
Simulation time 3871379409 ps
CPU time 14.85 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:39 PM PST 24
Peak memory 219760 kb
Host smart-746ac9d6-b377-4952-a722-cf4a83621b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354378158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.354378158
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.317712193
Short name T782
Test name
Test status
Simulation time 4784917918 ps
CPU time 4.72 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:23 PM PST 24
Peak memory 203432 kb
Host smart-24cf7227-4859-4e35-aed6-abc16da6c0e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317712193 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.317712193
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1124404145
Short name T547
Test name
Test status
Simulation time 10079130918 ps
CPU time 54.25 seconds
Started Feb 21 03:14:19 PM PST 24
Finished Feb 21 03:15:15 PM PST 24
Peak memory 502896 kb
Host smart-9f3ed8fa-a530-4e64-9fb2-daf5704cd784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124404145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1124404145
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3438540986
Short name T282
Test name
Test status
Simulation time 10194506578 ps
CPU time 34.8 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:53 PM PST 24
Peak memory 432896 kb
Host smart-3b9de32e-4b22-4e72-8038-9c0d24e7293b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438540986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3438540986
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2316249944
Short name T50
Test name
Test status
Simulation time 1769615539 ps
CPU time 2.15 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:19 PM PST 24
Peak memory 203400 kb
Host smart-fd4503e2-d540-4f29-be68-3ef84b97ca40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316249944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2316249944
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1800439199
Short name T1025
Test name
Test status
Simulation time 881021767 ps
CPU time 4.7 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 205108 kb
Host smart-d0b11725-7f3a-4a57-bf0e-6f9d0e8f86ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800439199 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1800439199
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.25305502
Short name T589
Test name
Test status
Simulation time 10653660981 ps
CPU time 32 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:58 PM PST 24
Peak memory 647576 kb
Host smart-68158c2f-66c0-4d79-a66b-b1449c35adbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25305502 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.25305502
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.795325582
Short name T825
Test name
Test status
Simulation time 1275734213 ps
CPU time 2.66 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:21 PM PST 24
Peak memory 203388 kb
Host smart-71a294fa-919d-40fe-a14b-57d738d5120e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795325582 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_perf.795325582
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3593971452
Short name T384
Test name
Test status
Simulation time 7651793565 ps
CPU time 12.89 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:40 PM PST 24
Peak memory 203420 kb
Host smart-56e1b9e0-cd16-4ea1-8a6c-c186866d146d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593971452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3593971452
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.1831996515
Short name T743
Test name
Test status
Simulation time 64732474680 ps
CPU time 1034.82 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:31:34 PM PST 24
Peak memory 5383496 kb
Host smart-ef0002ea-8eae-4e24-a4b0-1e39d2ea7bdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831996515 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.1831996515
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.333259945
Short name T1225
Test name
Test status
Simulation time 5643928444 ps
CPU time 58.09 seconds
Started Feb 21 03:14:15 PM PST 24
Finished Feb 21 03:15:13 PM PST 24
Peak memory 203528 kb
Host smart-6c341773-e150-42bb-8ea1-faac38303ab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333259945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.333259945
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.910936466
Short name T379
Test name
Test status
Simulation time 11040586244 ps
CPU time 18.1 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:44 PM PST 24
Peak memory 572672 kb
Host smart-043a14fe-706f-45a0-bb63-b6e1ef549a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910936466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.910936466
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2173345804
Short name T1468
Test name
Test status
Simulation time 41169448998 ps
CPU time 1051.96 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:31:51 PM PST 24
Peak memory 3919436 kb
Host smart-7d45f72a-69cf-43fb-abfb-609ec1bfd8be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173345804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2173345804
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2324325333
Short name T1437
Test name
Test status
Simulation time 3981258444 ps
CPU time 7.58 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203388 kb
Host smart-9314b98c-1f8b-47bf-a888-f67d74ef71f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324325333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2324325333
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_ovf.391724012
Short name T1227
Test name
Test status
Simulation time 13248678635 ps
CPU time 146.06 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:16:42 PM PST 24
Peak memory 440432 kb
Host smart-da64cffc-092b-49ae-8ccc-1e0747b76c72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391724012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_tx_ovf.391724012
Directory /workspace/7.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.3072554990
Short name T1053
Test name
Test status
Simulation time 1607390763 ps
CPU time 7.83 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 203356 kb
Host smart-d6575521-7d14-4918-89c6-dd8a97421399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072554990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.i2c_target_unexp_stop.3072554990
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1605406243
Short name T993
Test name
Test status
Simulation time 17624617 ps
CPU time 0.63 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:28 PM PST 24
Peak memory 202128 kb
Host smart-e1b0bc86-629c-4a6e-a81b-65f590b0f84f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605406243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1605406243
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2493202411
Short name T1488
Test name
Test status
Simulation time 62602175 ps
CPU time 1.56 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 219676 kb
Host smart-8db0f4ad-dabe-444a-8607-24f4af684ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493202411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2493202411
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1617352410
Short name T1373
Test name
Test status
Simulation time 1744139200 ps
CPU time 8.66 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:34 PM PST 24
Peak memory 266944 kb
Host smart-f9b8cea6-ad48-44c9-906c-ee41035622f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617352410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1617352410
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1747174538
Short name T1341
Test name
Test status
Simulation time 5394735085 ps
CPU time 73.08 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:15:35 PM PST 24
Peak memory 728508 kb
Host smart-7918c97f-e359-4509-a95e-924580fc6405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747174538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1747174538
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3934473468
Short name T1199
Test name
Test status
Simulation time 5044630711 ps
CPU time 575.73 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:23:57 PM PST 24
Peak memory 1349580 kb
Host smart-25b3f330-f64f-4690-a89c-b3afd97ed50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934473468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3934473468
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.15952497
Short name T1187
Test name
Test status
Simulation time 404815655 ps
CPU time 0.91 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 202996 kb
Host smart-c10b3309-49f1-44c0-b97b-8982678643e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15952497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.15952497
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.907624203
Short name T305
Test name
Test status
Simulation time 433019079 ps
CPU time 6.76 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:14:31 PM PST 24
Peak memory 245140 kb
Host smart-67a703e5-2cf1-4ff9-8fe4-654a9fd3cac4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907624203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.907624203
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.809355166
Short name T409
Test name
Test status
Simulation time 6350705859 ps
CPU time 372.78 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:20:36 PM PST 24
Peak memory 1696752 kb
Host smart-10496033-b61e-4918-9cc6-d3bb17e6d942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809355166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.809355166
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.836044116
Short name T1479
Test name
Test status
Simulation time 1733463326 ps
CPU time 81.15 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 227656 kb
Host smart-aa75c987-4685-4c23-87e5-3eed32d835f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836044116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.836044116
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.3887512206
Short name T285
Test name
Test status
Simulation time 22397669 ps
CPU time 0.64 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:22 PM PST 24
Peak memory 202272 kb
Host smart-0f8e3f39-8e86-4abb-8dd7-acddc646ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887512206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3887512206
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2591181757
Short name T1008
Test name
Test status
Simulation time 7044149937 ps
CPU time 195.35 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:17:37 PM PST 24
Peak memory 227680 kb
Host smart-8a05cedf-defa-47f3-b370-2ea88faac6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591181757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2591181757
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_rx_oversample.383113049
Short name T1379
Test name
Test status
Simulation time 3548444324 ps
CPU time 62.43 seconds
Started Feb 21 03:14:21 PM PST 24
Finished Feb 21 03:15:24 PM PST 24
Peak memory 279772 kb
Host smart-30d3bac3-5c1f-4919-8fa1-6daa2b1c1ea4
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383113049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_rx_oversample.383113049
Directory /workspace/8.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1813010394
Short name T587
Test name
Test status
Simulation time 2471309029 ps
CPU time 144.36 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:16:46 PM PST 24
Peak memory 267128 kb
Host smart-e7152eda-37c3-43cf-a63b-2ab10cfb4973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813010394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1813010394
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2446551412
Short name T351
Test name
Test status
Simulation time 16956406012 ps
CPU time 152.83 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:16:56 PM PST 24
Peak memory 696616 kb
Host smart-d4c16ca7-3fde-47a8-ab3a-37f19c4cbd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446551412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2446551412
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3308173281
Short name T10
Test name
Test status
Simulation time 952894064 ps
CPU time 21.02 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:45 PM PST 24
Peak memory 211548 kb
Host smart-6d96815c-877d-44ed-afef-3286064a0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308173281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3308173281
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3197666903
Short name T977
Test name
Test status
Simulation time 3536826776 ps
CPU time 3.52 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:31 PM PST 24
Peak memory 203408 kb
Host smart-1fcf8dbf-e10a-41a5-982b-dc7ce3013a1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197666903 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3197666903
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2156409334
Short name T573
Test name
Test status
Simulation time 10398514458 ps
CPU time 15.69 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:42 PM PST 24
Peak memory 317980 kb
Host smart-ecce07d2-f688-488f-8a1c-5b76d22ba100
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156409334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2156409334
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3331650968
Short name T1350
Test name
Test status
Simulation time 10206468825 ps
CPU time 5.16 seconds
Started Feb 21 03:14:28 PM PST 24
Finished Feb 21 03:14:34 PM PST 24
Peak memory 235292 kb
Host smart-9fc8fe33-700b-480e-8975-56ecd6647063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331650968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3331650968
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2473984055
Short name T1353
Test name
Test status
Simulation time 461628043 ps
CPU time 2.42 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203380 kb
Host smart-40e9be74-644d-41ed-aaa1-c2cdf06b63c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473984055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2473984055
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.4119359297
Short name T1242
Test name
Test status
Simulation time 8152202945 ps
CPU time 5 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 209364 kb
Host smart-9f7cfa2f-450e-4f30-9e79-529ebcd6f6a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119359297 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.4119359297
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1636193878
Short name T772
Test name
Test status
Simulation time 23834060468 ps
CPU time 1121.48 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:33:09 PM PST 24
Peak memory 5677680 kb
Host smart-aa909162-a4ff-424b-bc8f-79712674254a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636193878 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1636193878
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.3684678548
Short name T929
Test name
Test status
Simulation time 764889671 ps
CPU time 4.63 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 203384 kb
Host smart-0fd4f36e-4478-4811-9527-52399891f7e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684678548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_perf.3684678548
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2042418365
Short name T724
Test name
Test status
Simulation time 3097489837 ps
CPU time 15.36 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:14:42 PM PST 24
Peak memory 203336 kb
Host smart-6aee4327-4e45-42f6-8674-0b8e9ea60dcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042418365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2042418365
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.795571366
Short name T989
Test name
Test status
Simulation time 14581071220 ps
CPU time 85.58 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:15:52 PM PST 24
Peak memory 1158448 kb
Host smart-41306e75-2596-4dea-a4b9-b53fb04b1303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795571366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.i2c_target_stress_all.795571366
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.4125779084
Short name T1142
Test name
Test status
Simulation time 507544438 ps
CPU time 7.27 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 203368 kb
Host smart-45e8f929-4036-4beb-affe-6f7ed5eab497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125779084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.4125779084
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2755376758
Short name T1413
Test name
Test status
Simulation time 33112397453 ps
CPU time 2114.47 seconds
Started Feb 21 03:14:23 PM PST 24
Finished Feb 21 03:49:39 PM PST 24
Peak memory 3524444 kb
Host smart-e4cbb3e8-3603-4dad-820e-9457b93832ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755376758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2755376758
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3266029075
Short name T625
Test name
Test status
Simulation time 8429815452 ps
CPU time 8.45 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:33 PM PST 24
Peak memory 213992 kb
Host smart-21d90481-d2a9-4b56-854c-c331b95728f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266029075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3266029075
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_ovf.3740825790
Short name T1412
Test name
Test status
Simulation time 2726656694 ps
CPU time 81.29 seconds
Started Feb 21 03:14:27 PM PST 24
Finished Feb 21 03:15:48 PM PST 24
Peak memory 331524 kb
Host smart-88f8c571-3406-4c76-b60a-e598a0f0a576
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740825790 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_tx_ovf.3740825790
Directory /workspace/8.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.3517992100
Short name T398
Test name
Test status
Simulation time 2531892919 ps
CPU time 5.58 seconds
Started Feb 21 03:14:26 PM PST 24
Finished Feb 21 03:14:32 PM PST 24
Peak memory 203756 kb
Host smart-82947358-1d7a-4e92-8e17-706f5c8d4412
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517992100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.3517992100
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2386119852
Short name T1411
Test name
Test status
Simulation time 22105162 ps
CPU time 0.57 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:21 PM PST 24
Peak memory 202120 kb
Host smart-adbcfe82-c853-4a2e-8030-1cc54252528e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386119852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2386119852
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2646949433
Short name T502
Test name
Test status
Simulation time 75761130 ps
CPU time 1.13 seconds
Started Feb 21 03:14:15 PM PST 24
Finished Feb 21 03:14:17 PM PST 24
Peak memory 203272 kb
Host smart-897851ae-8229-43b4-b474-ef8b7e5c685b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646949433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2646949433
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.4258894409
Short name T487
Test name
Test status
Simulation time 1503861398 ps
CPU time 6.24 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:23 PM PST 24
Peak memory 268256 kb
Host smart-dfd7e9ec-997d-46b6-b342-c104568fa04d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258894409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.4258894409
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3505291116
Short name T990
Test name
Test status
Simulation time 6988854113 ps
CPU time 235.92 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:18:18 PM PST 24
Peak memory 899852 kb
Host smart-4cc4a606-0591-4506-a05e-2cd2a72f26a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505291116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3505291116
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.983880943
Short name T1093
Test name
Test status
Simulation time 13360353007 ps
CPU time 442.59 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:21:40 PM PST 24
Peak memory 1660992 kb
Host smart-c249ceaf-704c-4289-bd3f-2739c0ec94dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983880943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.983880943
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.4150667844
Short name T838
Test name
Test status
Simulation time 489338909 ps
CPU time 1 seconds
Started Feb 21 03:14:11 PM PST 24
Finished Feb 21 03:14:14 PM PST 24
Peak memory 203244 kb
Host smart-964fa91d-6440-4704-9445-a0353339e346
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150667844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.4150667844
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2358048184
Short name T1454
Test name
Test status
Simulation time 175357489 ps
CPU time 8.99 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 203292 kb
Host smart-9f844519-4f51-46e3-9672-56ecc22a0c4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358048184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2358048184
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1498322329
Short name T634
Test name
Test status
Simulation time 22769554467 ps
CPU time 259.33 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:18:38 PM PST 24
Peak memory 1325384 kb
Host smart-8fbd0b4b-1f8b-4f79-bbbe-9d3b4bba25a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498322329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1498322329
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.4268433116
Short name T651
Test name
Test status
Simulation time 2329418945 ps
CPU time 86.81 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:15:45 PM PST 24
Peak memory 397992 kb
Host smart-587f8c9b-228f-4298-a4c4-88478844ba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268433116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.4268433116
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2103131964
Short name T330
Test name
Test status
Simulation time 18051713 ps
CPU time 0.66 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 202348 kb
Host smart-4612c461-1722-49dc-a041-8e51bf344aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103131964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2103131964
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2342568765
Short name T1423
Test name
Test status
Simulation time 28892492031 ps
CPU time 338.52 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:19:55 PM PST 24
Peak memory 203372 kb
Host smart-a646162a-6a23-43f4-a89c-cddf22914263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342568765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2342568765
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_rx_oversample.927061551
Short name T930
Test name
Test status
Simulation time 14369428406 ps
CPU time 172.51 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:17:10 PM PST 24
Peak memory 372396 kb
Host smart-39bab303-47e2-4858-a5d8-747419e48eba
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927061551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_rx_oversample.927061551
Directory /workspace/9.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2593394086
Short name T1368
Test name
Test status
Simulation time 4468914109 ps
CPU time 76.06 seconds
Started Feb 21 03:14:24 PM PST 24
Finished Feb 21 03:15:41 PM PST 24
Peak memory 315944 kb
Host smart-c9f950cf-86f3-4709-8ea2-b93deefcdad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593394086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2593394086
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.4062871859
Short name T301
Test name
Test status
Simulation time 2970494162 ps
CPU time 24.83 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:51 PM PST 24
Peak memory 211660 kb
Host smart-92e1d420-0175-465b-8973-b31cf8ae9ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062871859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.4062871859
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.100311791
Short name T859
Test name
Test status
Simulation time 3257799059 ps
CPU time 3.77 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:21 PM PST 24
Peak memory 203644 kb
Host smart-96f28b34-3e8f-4069-972a-6589935a4b68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100311791 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.100311791
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1023403663
Short name T452
Test name
Test status
Simulation time 10056681066 ps
CPU time 67.17 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:15:25 PM PST 24
Peak memory 552508 kb
Host smart-0e3ee8cd-201e-4514-86e1-fcc9f95333f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023403663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1023403663
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1556735590
Short name T1152
Test name
Test status
Simulation time 10225863560 ps
CPU time 28.38 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:14:46 PM PST 24
Peak memory 404560 kb
Host smart-37534c42-e251-4676-a270-08b66f1c0c85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556735590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1556735590
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1699109010
Short name T750
Test name
Test status
Simulation time 1812227079 ps
CPU time 2.68 seconds
Started Feb 21 03:14:22 PM PST 24
Finished Feb 21 03:14:25 PM PST 24
Peak memory 203364 kb
Host smart-22cb4502-2396-4696-89d9-5ae2a53caeb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699109010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1699109010
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1683200435
Short name T720
Test name
Test status
Simulation time 1631668140 ps
CPU time 6.98 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:14:24 PM PST 24
Peak memory 203364 kb
Host smart-031c26b0-36bf-4a15-a51a-94cf63e59ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683200435 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1683200435
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3139977408
Short name T856
Test name
Test status
Simulation time 11399980815 ps
CPU time 91.45 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:15:50 PM PST 24
Peak memory 1347260 kb
Host smart-196996d3-06a5-4035-b605-2f5334393318
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139977408 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3139977408
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.3851545887
Short name T968
Test name
Test status
Simulation time 1674159088 ps
CPU time 2.71 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203392 kb
Host smart-19110edd-93da-4b80-a4f0-ce61aae7e561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851545887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_perf.3851545887
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2081537967
Short name T1378
Test name
Test status
Simulation time 2064802634 ps
CPU time 54.33 seconds
Started Feb 21 03:14:17 PM PST 24
Finished Feb 21 03:15:12 PM PST 24
Peak memory 203344 kb
Host smart-6104082d-84da-4308-84a0-7af6fa61c4a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081537967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2081537967
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_all.1424571094
Short name T1180
Test name
Test status
Simulation time 23095836908 ps
CPU time 1003.13 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:31:01 PM PST 24
Peak memory 622064 kb
Host smart-1a2211e4-4e1d-4d8b-8d34-f9d0d9acf08d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424571094 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.i2c_target_stress_all.1424571094
Directory /workspace/9.i2c_target_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1750283310
Short name T297
Test name
Test status
Simulation time 6571014443 ps
CPU time 70.41 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:15:29 PM PST 24
Peak memory 203452 kb
Host smart-a92b93cf-bd7b-444a-9ab2-3cb10aebaf69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750283310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1750283310
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.4213861335
Short name T1475
Test name
Test status
Simulation time 26195604006 ps
CPU time 785.51 seconds
Started Feb 21 03:14:16 PM PST 24
Finished Feb 21 03:27:22 PM PST 24
Peak memory 5512740 kb
Host smart-1da64d5d-fbcb-4930-ba17-f9e85fc2d5d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213861335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.4213861335
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.1926441339
Short name T48
Test name
Test status
Simulation time 32448286339 ps
CPU time 2689.78 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:59:09 PM PST 24
Peak memory 7215000 kb
Host smart-3fa7d641-6060-419f-8646-75e0effc6593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926441339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.1926441339
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.202425814
Short name T785
Test name
Test status
Simulation time 6511113980 ps
CPU time 7.56 seconds
Started Feb 21 03:14:20 PM PST 24
Finished Feb 21 03:14:29 PM PST 24
Peak memory 203356 kb
Host smart-ef5bb5d8-c723-48eb-8f3c-bf8c7b4081ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202425814 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.202425814
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_ovf.3198966920
Short name T1143
Test name
Test status
Simulation time 5461305835 ps
CPU time 50.76 seconds
Started Feb 21 03:14:25 PM PST 24
Finished Feb 21 03:15:17 PM PST 24
Peak memory 229120 kb
Host smart-c92a3e66-8dee-4d94-ae07-2b66c1623547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198966920 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_tx_ovf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_tx_ovf.3198966920
Directory /workspace/9.i2c_target_tx_ovf/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.1251204643
Short name T1318
Test name
Test status
Simulation time 1583922218 ps
CPU time 7.68 seconds
Started Feb 21 03:14:18 PM PST 24
Finished Feb 21 03:14:26 PM PST 24
Peak memory 208196 kb
Host smart-77b82753-7834-40b8-abac-c7725e364234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251204643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.1251204643
Directory /workspace/9.i2c_target_unexp_stop/latest
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