Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	4196271	1			T1	10		T2	3		T3	3
all_values[1]	4196271	1			T1	10		T2	3		T3	3
all_values[2]	4196271	1			T1	10		T2	3		T3	3
all_values[3]	4196271	1			T1	10		T2	3		T3	3
all_values[4]	4196271	1			T1	10		T2	3		T3	3
all_values[5]	4196271	1			T1	10		T2	3		T3	3
all_values[6]	4196271	1			T1	10		T2	3		T3	3
all_values[7]	4196271	1			T1	10		T2	3		T3	3
all_values[8]	4196271	1			T1	10		T2	3		T3	3
all_values[9]	4196271	1			T1	10		T2	3		T3	3
all_values[10]	4196271	1			T1	10		T2	3		T3	3
all_values[11]	4196271	1			T1	10		T2	3		T3	3
all_values[12]	4196271	1			T1	10		T2	3		T3	3
all_values[13]	4196271	1			T1	10		T2	3		T3	3
all_values[14]	4196271	1			T1	10		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52994226

1

T1

150

T2

39

T3

39

auto[1]

9949839

1

T2

6

T3

6

T14

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62943653

1

T1

150

T2

45

T3

45

auto[1]

412

1

T57

148

T59

42

T60

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	627995	1			T1	10		T14	1		T11	123
all_values[0]	auto[0]	auto[1]	9	1			T57	2		T59	2		T60	1
all_values[0]	auto[1]	auto[0]	3568247	1			T2	3		T3	3		T14	2
all_values[0]	auto[1]	auto[1]	20	1			T57	9		T59	1		T60	2
all_values[1]	auto[0]	auto[0]	4194005	1			T1	10		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	18	1			T57	10		T59	1		T60	2
all_values[1]	auto[1]	auto[0]	2234	1			T15	219		T25	1		T12	51
all_values[1]	auto[1]	auto[1]	14	1			T57	2		T59	3		T60	2
all_values[2]	auto[0]	auto[0]	4196239	1			T1	10		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	19	1			T57	10		T59	2		T198	3
all_values[2]	auto[1]	auto[0]	4	1			T199	2		T200	2		-	-
all_values[2]	auto[1]	auto[1]	9	1			T57	1		T59	1		T198	4
all_values[3]	auto[0]	auto[0]	4196254	1			T1	10		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	10	1			T60	3		T198	3		T201	4
all_values[3]	auto[1]	auto[1]	7	1			T60	1		T198	3		T201	3
all_values[4]	auto[0]	auto[0]	4196185	1			T1	10		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	19	1			T57	11		T198	4		T201	4
all_values[4]	auto[1]	auto[0]	54	1			T34	19		T36	34		T169	1
all_values[4]	auto[1]	auto[1]	13	1			T59	4		T60	3		T198	3
all_values[5]	auto[0]	auto[0]	4196240	1			T1	10		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	19	1			T57	11		T59	2		T201	6
all_values[5]	auto[1]	auto[1]	12	1			T57	1		T59	2		T60	3
all_values[6]	auto[0]	auto[0]	3599019	1			T1	10		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	16	1			T57	9		T59	3		T60	2
all_values[6]	auto[1]	auto[0]	597224	1			T14	1		T11	26		T15	4
all_values[6]	auto[1]	auto[1]	12	1			T57	2		T60	1		T198	5
all_values[7]	auto[0]	auto[0]	3928325	1			T1	10		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	22	1			T57	9		T59	3		T60	2
all_values[7]	auto[1]	auto[0]	267913	1			T14	1		T11	1320		T15	2053
all_values[7]	auto[1]	auto[1]	11	1			T57	3		T60	2		T198	5
all_values[8]	auto[0]	auto[0]	3442795	1			T1	10		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	14	1			T57	6		T198	2		T201	6
all_values[8]	auto[1]	auto[0]	753445	1			T14	1		T11	156		T15	3
all_values[8]	auto[1]	auto[1]	17	1			T57	5		T59	2		T60	4
all_values[9]	auto[0]	auto[0]	3629198	1			T1	10		T2	3		T3	3
all_values[9]	auto[0]	auto[1]	20	1			T57	9		T59	3		T198	4
all_values[9]	auto[1]	auto[0]	567045	1			T14	1		T8	1		T11	26
all_values[9]	auto[1]	auto[1]	8	1			T57	3		T198	3		T201	2
all_values[10]	auto[0]	auto[0]	4196258	1			T1	10		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	7	1			T60	2		T198	3		T201	2
all_values[10]	auto[1]	auto[1]	6	1			T60	2		T198	1		T201	3
all_values[11]	auto[0]	auto[0]	2751	1			T1	10		T14	1		T11	5
all_values[11]	auto[0]	auto[1]	12	1			T57	2		T59	2		T60	2
all_values[11]	auto[1]	auto[0]	4193490	1			T2	3		T3	3		T14	2
all_values[11]	auto[1]	auto[1]	18	1			T57	8		T59	2		T60	2
all_values[12]	auto[0]	auto[0]	4196245	1			T1	10		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	17	1			T57	10		T59	1		T198	3
all_values[12]	auto[1]	auto[1]	9	1			T57	2		T59	1		T198	3
all_values[13]	auto[0]	auto[0]	4196238	1			T1	10		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	13	1			T57	8		T59	2		T201	3
all_values[13]	auto[1]	auto[0]	6	1			T202	1		T203	1		T204	1
all_values[13]	auto[1]	auto[1]	14	1			T57	4		T59	2		T198	6
all_values[14]	auto[0]	auto[0]	4196244	1			T1	10		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	20	1			T57	11		T59	3		T198	3
all_values[14]	auto[1]	auto[1]	7	1			T198	4		T201	3		-	-