Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4196271	1			T1	10		T2	3		T3	3
all_pins[1]	4196271	1			T1	10		T2	3		T3	3
all_pins[2]	4196271	1			T1	10		T2	3		T3	3
all_pins[3]	4196271	1			T1	10		T2	3		T3	3
all_pins[4]	4196271	1			T1	10		T2	3		T3	3
all_pins[5]	4196271	1			T1	10		T2	3		T3	3
all_pins[6]	4196271	1			T1	10		T2	3		T3	3
all_pins[7]	4196271	1			T1	10		T2	3		T3	3
all_pins[8]	4196271	1			T1	10		T2	3		T3	3
all_pins[9]	4196271	1			T1	10		T2	3		T3	3
all_pins[10]	4196271	1			T1	10		T2	3		T3	3
all_pins[11]	4196271	1			T1	10		T2	3		T3	3
all_pins[12]	4196271	1			T1	10		T2	3		T3	3
all_pins[13]	4196271	1			T1	10		T2	3		T3	3
all_pins[14]	4196271	1			T1	10		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	52934559	1			T1	150		T2	39		T3	39
values[0x1]	10009506	1			T2	6		T3	6		T14	8
transitions[0x0=>0x1]	9372210	1			T2	6		T3	6		T14	5
transitions[0x1=>0x0]	9371083	1			T2	5		T3	5		T14	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	628030	1			T1	10		T14	1		T11	124
all_pins[0]	values[0x1]	3568241	1			T2	3		T3	3		T14	2
all_pins[0]	transitions[0x0=>0x1]	3565642	1			T2	3		T3	3		T14	2
all_pins[0]	transitions[0x1=>0x0]	96	1			T220	35		T221	2		T57	1
all_pins[1]	values[0x0]	4193576	1			T1	10		T2	3		T3	3
all_pins[1]	values[0x1]	2695	1			T15	288		T25	1		T12	59
all_pins[1]	transitions[0x0=>0x1]	2694	1			T15	288		T25	1		T12	59
all_pins[1]	transitions[0x1=>0x0]	5	1			T199	2		T200	2		T201	1
all_pins[2]	values[0x0]	4196265	1			T1	10		T2	3		T3	3
all_pins[2]	values[0x1]	6	1			T199	2		T200	2		T198	1
all_pins[2]	transitions[0x0=>0x1]	6	1			T199	2		T200	2		T198	1
all_pins[2]	transitions[0x1=>0x0]	3	1			T201	3		-	-		-	-
all_pins[3]	values[0x0]	4196268	1			T1	10		T2	3		T3	3
all_pins[3]	values[0x1]	3	1			T201	3		-	-		-	-
all_pins[3]	transitions[0x0=>0x1]	2	1			T201	2		-	-		-	-
all_pins[3]	transitions[0x1=>0x0]	73	1			T34	24		T36	44		T169	1
all_pins[4]	values[0x0]	4196197	1			T1	10		T2	3		T3	3
all_pins[4]	values[0x1]	74	1			T34	24		T36	44		T169	1
all_pins[4]	transitions[0x0=>0x1]	72	1			T34	24		T36	44		T169	1
all_pins[4]	transitions[0x1=>0x0]	4	1			T57	1		T59	1		T60	1
all_pins[5]	values[0x0]	4196265	1			T1	10		T2	3		T3	3
all_pins[5]	values[0x1]	6	1			T57	1		T59	1		T60	1
all_pins[5]	transitions[0x0=>0x1]	5	1			T57	1		T59	1		T60	1
all_pins[5]	transitions[0x1=>0x0]	600843	1			T14	1		T11	32		T15	5
all_pins[6]	values[0x0]	3595427	1			T1	10		T2	3		T3	3
all_pins[6]	values[0x1]	600844	1			T14	1		T11	32		T15	5
all_pins[6]	transitions[0x0=>0x1]	583857	1			T11	29		T15	5		T23	2
all_pins[6]	transitions[0x1=>0x0]	283341	1			T11	1487		T15	2357		T23	4
all_pins[7]	values[0x0]	3895943	1			T1	10		T2	3		T3	3
all_pins[7]	values[0x1]	300328	1			T14	1		T11	1490		T15	2357
all_pins[7]	transitions[0x0=>0x1]	242740	1			T11	1454		T15	2353		T23	4
all_pins[7]	transitions[0x1=>0x0]	718292	1			T11	133		T23	2		T25	1444
all_pins[8]	values[0x0]	3420391	1			T1	10		T2	3		T3	3
all_pins[8]	values[0x1]	775880	1			T14	1		T11	169		T15	4
all_pins[8]	transitions[0x0=>0x1]	215769	1			T11	169		T15	4		T23	2
all_pins[8]	transitions[0x1=>0x0]	7792	1			T8	1		T11	32		T15	4
all_pins[9]	values[0x0]	3628368	1			T1	10		T2	3		T3	3
all_pins[9]	values[0x1]	567903	1			T14	1		T8	1		T11	32
all_pins[9]	transitions[0x0=>0x1]	567903	1			T14	1		T8	1		T11	32
all_pins[9]	transitions[0x1=>0x0]	2	1			T60	1		T201	1		-	-
all_pins[10]	values[0x0]	4196269	1			T1	10		T2	3		T3	3
all_pins[10]	values[0x1]	2	1			T60	1		T201	1		-	-
all_pins[10]	transitions[0x0=>0x1]	2	1			T60	1		T201	1		-	-
all_pins[10]	transitions[0x1=>0x0]	4193502	1			T2	3		T3	3		T14	2
all_pins[11]	values[0x0]	2769	1			T1	10		T14	1		T11	5
all_pins[11]	values[0x1]	4193502	1			T2	3		T3	3		T14	2
all_pins[11]	transitions[0x0=>0x1]	4193500	1			T2	3		T3	3		T14	2
all_pins[11]	transitions[0x1=>0x0]	5	1			T57	2		T59	1		T198	1
all_pins[12]	values[0x0]	4196264	1			T1	10		T2	3		T3	3
all_pins[12]	values[0x1]	7	1			T57	2		T59	1		T198	2
all_pins[12]	transitions[0x0=>0x1]	5	1			T57	1		T59	1		T198	1
all_pins[12]	transitions[0x1=>0x0]	9	1			T202	1		T203	1		T204	1
all_pins[13]	values[0x0]	4196260	1			T1	10		T2	3		T3	3
all_pins[13]	values[0x1]	11	1			T202	1		T203	1		T204	1
all_pins[13]	transitions[0x0=>0x1]	9	1			T202	1		T203	1		T204	1
all_pins[13]	transitions[0x1=>0x0]	2	1			T201	2		-	-		-	-
all_pins[14]	values[0x0]	4196267	1			T1	10		T2	3		T3	3
all_pins[14]	values[0x1]	4	1			T198	2		T201	2		-	-
all_pins[14]	transitions[0x0=>0x1]	4	1			T198	2		T201	2		-	-
all_pins[14]	transitions[0x1=>0x0]	3567114	1			T2	2		T3	2		T14	1