Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	3	87	96.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	3	87	96.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	26	1			T57	4		T59	4		T60	4
all_values[1]	26	1			T57	4		T59	4		T60	4
all_values[2]	26	1			T57	4		T59	4		T60	4
all_values[3]	26	1			T57	4		T59	4		T60	4
all_values[4]	26	1			T57	4		T59	4		T60	4
all_values[5]	26	1			T57	4		T59	4		T60	4
all_values[6]	26	1			T57	4		T59	4		T60	4
all_values[7]	26	1			T57	4		T59	4		T60	4
all_values[8]	26	1			T57	4		T59	4		T60	4
all_values[9]	26	1			T57	4		T59	4		T60	4
all_values[10]	26	1			T57	4		T59	4		T60	4
all_values[11]	26	1			T57	4		T59	4		T60	4
all_values[12]	26	1			T57	4		T59	4		T60	4
all_values[13]	26	1			T57	4		T59	4		T60	4
all_values[14]	26	1			T57	4		T59	4		T60	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

214

1

T57

16

T59

42

T60

38

auto[1]

176

1

T57

44

T59

18

T60

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82

1

T57

16

T59

18

T60

24

auto[1]

308

1

T57

44

T59

42

T60

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229

1

T57

38

T59

38

T60

41

auto[1]

161

1

T57

22

T59

22

T60

19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	3	87	96.67	3
Automatically Generated Cross Bins	90	3	87	96.67	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Uncovered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[7]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3	1			T59	1		T198	2		-	-
all_values[0]	auto[0]	auto[0]	auto[1]	4	1			T59	1		T60	1		T198	1
all_values[0]	auto[0]	auto[1]	auto[0]	2	1			T57	1		T60	1		-	-
all_values[0]	auto[0]	auto[1]	auto[1]	4	1			T57	1		T59	1		T198	2
all_values[0]	auto[1]	auto[0]	auto[1]	8	1			T57	1		T59	1		T60	1
all_values[0]	auto[1]	auto[1]	auto[1]	5	1			T57	1		T60	1		T201	3
all_values[1]	auto[0]	auto[0]	auto[0]	2	1			T201	2		-	-		-	-
all_values[1]	auto[0]	auto[0]	auto[1]	6	1			T60	2		T198	2		T201	2
all_values[1]	auto[0]	auto[1]	auto[1]	4	1			T57	2		T59	1		T198	1
all_values[1]	auto[1]	auto[0]	auto[1]	9	1			T59	2		T60	2		T198	2
all_values[1]	auto[1]	auto[1]	auto[1]	5	1			T57	2		T59	1		T198	2
all_values[2]	auto[0]	auto[0]	auto[0]	1	1			T59	1		-	-		-	-
all_values[2]	auto[0]	auto[0]	auto[1]	6	1			T59	2		T198	1		T201	3
all_values[2]	auto[0]	auto[1]	auto[0]	5	1			T57	1		T60	4		-	-
all_values[2]	auto[0]	auto[1]	auto[1]	5	1			T57	2		T198	2		T201	1
all_values[2]	auto[1]	auto[0]	auto[1]	8	1			T57	1		T59	1		T198	3
all_values[2]	auto[1]	auto[1]	auto[1]	1	1			T198	1		-	-		-	-
all_values[3]	auto[0]	auto[0]	auto[0]	5	1			T57	2		T59	2		T198	1
all_values[3]	auto[0]	auto[0]	auto[1]	4	1			T60	2		T198	2		-	-
all_values[3]	auto[0]	auto[1]	auto[0]	4	1			T57	2		T59	2		-	-
all_values[3]	auto[0]	auto[1]	auto[1]	5	1			T198	2		T201	3		-	-
all_values[3]	auto[1]	auto[0]	auto[1]	3	1			T60	2		T198	1		-	-
all_values[3]	auto[1]	auto[1]	auto[1]	5	1			T198	1		T201	4		-	-
all_values[4]	auto[0]	auto[0]	auto[0]	1	1			T60	1		-	-		-	-
all_values[4]	auto[0]	auto[0]	auto[1]	6	1			T59	2		T60	1		T198	2
all_values[4]	auto[0]	auto[1]	auto[0]	1	1			T57	1		-	-		-	-
all_values[4]	auto[0]	auto[1]	auto[1]	7	1			T57	2		T198	2		T201	3
all_values[4]	auto[1]	auto[0]	auto[1]	7	1			T59	2		T60	2		T198	2
all_values[4]	auto[1]	auto[1]	auto[1]	4	1			T57	1		T198	1		T201	2
all_values[5]	auto[0]	auto[0]	auto[0]	3	1			T60	1		T198	2		-	-
all_values[5]	auto[0]	auto[0]	auto[1]	6	1			T59	2		T60	1		T198	1
all_values[5]	auto[0]	auto[1]	auto[1]	6	1			T57	3		T201	3		-	-
all_values[5]	auto[1]	auto[0]	auto[1]	4	1			T60	2		T201	2		-	-
all_values[5]	auto[1]	auto[1]	auto[1]	7	1			T57	1		T59	2		T198	4
all_values[6]	auto[0]	auto[0]	auto[0]	5	1			T59	1		T60	1		T201	3
all_values[6]	auto[0]	auto[0]	auto[1]	6	1			T57	1		T59	1		T198	3
all_values[6]	auto[0]	auto[1]	auto[0]	1	1			T57	1		-	-		-	-
all_values[6]	auto[0]	auto[1]	auto[1]	4	1			T60	2		T198	1		T201	1
all_values[6]	auto[1]	auto[0]	auto[1]	5	1			T57	1		T59	1		T60	1
all_values[6]	auto[1]	auto[1]	auto[1]	5	1			T57	1		T59	1		T198	1
all_values[7]	auto[0]	auto[0]	auto[0]	1	1			T59	1		-	-		-	-
all_values[7]	auto[0]	auto[0]	auto[1]	8	1			T57	1		T59	1		T60	2
all_values[7]	auto[0]	auto[1]	auto[1]	4	1			T59	1		T198	2		T201	1
all_values[7]	auto[1]	auto[0]	auto[1]	9	1			T57	2		T59	1		T60	2
all_values[7]	auto[1]	auto[1]	auto[1]	4	1			T57	1		T198	2		T201	1
all_values[8]	auto[0]	auto[0]	auto[0]	2	1			T59	2		-	-		-	-
all_values[8]	auto[0]	auto[0]	auto[1]	8	1			T57	1		T59	1		T60	2
all_values[8]	auto[0]	auto[1]	auto[0]	1	1			T57	1		-	-		-	-
all_values[8]	auto[0]	auto[1]	auto[1]	2	1			T198	2		-	-		-	-
all_values[8]	auto[1]	auto[0]	auto[1]	9	1			T57	2		T59	1		T60	2
all_values[8]	auto[1]	auto[1]	auto[1]	4	1			T198	2		T201	2		-	-
all_values[9]	auto[0]	auto[0]	auto[0]	5	1			T59	1		T60	4		-	-
all_values[9]	auto[0]	auto[0]	auto[1]	3	1			T59	1		T198	1		T201	1
all_values[9]	auto[0]	auto[1]	auto[0]	1	1			T201	1		-	-		-	-
all_values[9]	auto[0]	auto[1]	auto[1]	6	1			T57	2		T59	1		T198	1
all_values[9]	auto[1]	auto[0]	auto[1]	5	1			T59	1		T198	3		T201	1
all_values[9]	auto[1]	auto[1]	auto[1]	6	1			T57	2		T198	2		T201	2
all_values[10]	auto[0]	auto[0]	auto[0]	4	1			T59	1		T198	2		T201	1
all_values[10]	auto[0]	auto[0]	auto[1]	3	1			T198	1		T201	2		-	-
all_values[10]	auto[0]	auto[1]	auto[0]	9	1			T57	4		T59	3		T198	1
all_values[10]	auto[0]	auto[1]	auto[1]	4	1			T60	2		T198	2		-	-
all_values[10]	auto[1]	auto[0]	auto[1]	4	1			T60	2		T198	1		T201	1
all_values[10]	auto[1]	auto[1]	auto[1]	2	1			T201	2		-	-		-	-
all_values[11]	auto[0]	auto[0]	auto[0]	2	1			T198	2		-	-		-	-
all_values[11]	auto[0]	auto[0]	auto[1]	9	1			T57	1		T59	2		T60	1
all_values[11]	auto[0]	auto[1]	auto[0]	2	1			T57	2		-	-		-	-
all_values[11]	auto[0]	auto[1]	auto[1]	2	1			T60	1		T198	1		-	-
all_values[11]	auto[1]	auto[0]	auto[1]	7	1			T57	1		T59	2		T60	1
all_values[11]	auto[1]	auto[1]	auto[1]	4	1			T60	1		T198	2		T201	1
all_values[12]	auto[0]	auto[0]	auto[0]	1	1			T198	1		-	-		-	-
all_values[12]	auto[0]	auto[0]	auto[1]	3	1			T198	2		T201	1		-	-
all_values[12]	auto[0]	auto[1]	auto[0]	7	1			T59	2		T60	4		T201	1
all_values[12]	auto[0]	auto[1]	auto[1]	6	1			T57	2		T59	1		T198	1
all_values[12]	auto[1]	auto[0]	auto[1]	4	1			T59	1		T198	2		T201	1
all_values[12]	auto[1]	auto[1]	auto[1]	5	1			T57	2		T198	1		T201	2
all_values[13]	auto[0]	auto[0]	auto[0]	4	1			T60	2		T198	1		T201	1
all_values[13]	auto[0]	auto[0]	auto[1]	7	1			T57	1		T59	1		T198	1
all_values[13]	auto[0]	auto[1]	auto[0]	3	1			T60	2		T201	1		-	-
all_values[13]	auto[0]	auto[1]	auto[1]	2	1			T57	1		T198	1		-	-
all_values[13]	auto[1]	auto[0]	auto[1]	4	1			T57	1		T59	1		T198	2
all_values[13]	auto[1]	auto[1]	auto[1]	6	1			T57	1		T59	2		T198	2
all_values[14]	auto[0]	auto[0]	auto[0]	2	1			T59	1		T201	1		-	-
all_values[14]	auto[0]	auto[0]	auto[1]	1	1			T59	1		-	-		-	-
all_values[14]	auto[0]	auto[1]	auto[0]	5	1			T57	1		T60	4		-	-
all_values[14]	auto[0]	auto[1]	auto[1]	6	1			T57	2		T198	2		T201	2
all_values[14]	auto[1]	auto[0]	auto[1]	7	1			T59	2		T198	3		T201	2
all_values[14]	auto[1]	auto[1]	auto[1]	5	1			T57	1		T198	2		T201	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal