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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.49 98.70 95.33 100.00 93.04 97.32 100.00 91.07


Total test records in report: 1408
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T1304 /workspace/coverage/default/27.i2c_target_stress_all.2191561943 Feb 29 02:48:19 PM PST 24 Feb 29 03:43:14 PM PST 24 116201719253 ps
T1305 /workspace/coverage/default/42.i2c_host_stretch_timeout.2708608200 Feb 29 02:50:48 PM PST 24 Feb 29 02:51:00 PM PST 24 779157973 ps
T1306 /workspace/coverage/default/47.i2c_target_hrst.1212834857 Feb 29 02:51:49 PM PST 24 Feb 29 02:51:52 PM PST 24 1521496128 ps
T1307 /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3261451784 Feb 29 02:49:58 PM PST 24 Feb 29 02:50:07 PM PST 24 10317358248 ps
T1308 /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2559907354 Feb 29 02:47:58 PM PST 24 Feb 29 02:48:11 PM PST 24 287036759 ps
T1309 /workspace/coverage/default/31.i2c_host_fifo_full.2377127414 Feb 29 02:48:58 PM PST 24 Feb 29 02:49:55 PM PST 24 1899117963 ps
T1310 /workspace/coverage/default/6.i2c_host_error_intr.1933580498 Feb 29 02:44:23 PM PST 24 Feb 29 02:44:24 PM PST 24 77511966 ps
T1311 /workspace/coverage/default/33.i2c_target_stress_all.1319592388 Feb 29 02:49:15 PM PST 24 Feb 29 02:49:47 PM PST 24 7138642045 ps
T1312 /workspace/coverage/default/44.i2c_host_rx_oversample.1056395314 Feb 29 02:51:13 PM PST 24 Feb 29 02:52:03 PM PST 24 6270383515 ps
T150 /workspace/coverage/default/45.i2c_host_override.4244117598 Feb 29 02:51:18 PM PST 24 Feb 29 02:51:18 PM PST 24 42266323 ps
T1313 /workspace/coverage/default/42.i2c_target_stress_rd.4266451970 Feb 29 02:50:48 PM PST 24 Feb 29 02:51:46 PM PST 24 2848336307 ps
T1314 /workspace/coverage/default/9.i2c_target_intr_stress_wr.1821725286 Feb 29 02:44:56 PM PST 24 Feb 29 02:45:39 PM PST 24 12617928315 ps
T1315 /workspace/coverage/default/11.i2c_target_stretch.1306385207 Feb 29 02:45:30 PM PST 24 Feb 29 02:49:24 PM PST 24 9507718295 ps
T1316 /workspace/coverage/default/39.i2c_host_perf.2216983947 Feb 29 02:50:14 PM PST 24 Feb 29 02:51:07 PM PST 24 2773712000 ps
T1317 /workspace/coverage/default/41.i2c_target_intr_smoke.1497517485 Feb 29 02:50:39 PM PST 24 Feb 29 02:50:46 PM PST 24 5787959961 ps
T1318 /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1486444171 Feb 29 02:49:35 PM PST 24 Feb 29 02:49:40 PM PST 24 212298997 ps
T1319 /workspace/coverage/default/35.i2c_target_hrst.3887034630 Feb 29 02:49:44 PM PST 24 Feb 29 02:49:46 PM PST 24 410694547 ps
T1320 /workspace/coverage/default/8.i2c_target_intr_smoke.1283758106 Feb 29 02:44:56 PM PST 24 Feb 29 02:45:02 PM PST 24 3839607879 ps
T1321 /workspace/coverage/default/30.i2c_target_intr_stress_wr.4252855978 Feb 29 02:48:46 PM PST 24 Feb 29 02:49:11 PM PST 24 10210840905 ps
T1322 /workspace/coverage/default/18.i2c_target_smoke.2197079698 Feb 29 02:46:50 PM PST 24 Feb 29 02:47:28 PM PST 24 8933068068 ps
T1323 /workspace/coverage/default/6.i2c_alert_test.3218045408 Feb 29 02:44:22 PM PST 24 Feb 29 02:44:23 PM PST 24 23700438 ps
T1324 /workspace/coverage/default/41.i2c_target_unexp_stop.3475475807 Feb 29 02:50:35 PM PST 24 Feb 29 02:50:40 PM PST 24 916047577 ps
T1325 /workspace/coverage/default/14.i2c_target_intr_stress_wr.2004072750 Feb 29 02:45:55 PM PST 24 Feb 29 02:46:13 PM PST 24 8600631447 ps
T1326 /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3523432762 Feb 29 02:45:47 PM PST 24 Feb 29 02:46:02 PM PST 24 10170781334 ps
T1327 /workspace/coverage/default/1.i2c_host_rx_oversample.1212668840 Feb 29 02:43:18 PM PST 24 Feb 29 02:45:07 PM PST 24 2509688550 ps
T1328 /workspace/coverage/default/30.i2c_host_error_intr.2614769037 Feb 29 02:48:42 PM PST 24 Feb 29 02:48:43 PM PST 24 46194143 ps
T1329 /workspace/coverage/default/11.i2c_host_fifo_overflow.1647391650 Feb 29 02:45:20 PM PST 24 Feb 29 02:46:59 PM PST 24 7195485148 ps
T1330 /workspace/coverage/default/43.i2c_host_override.162927314 Feb 29 02:50:51 PM PST 24 Feb 29 02:50:52 PM PST 24 26255297 ps
T1331 /workspace/coverage/default/14.i2c_target_stretch.1002380298 Feb 29 02:45:57 PM PST 24 Feb 29 02:48:20 PM PST 24 22304217630 ps
T1332 /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2489806673 Feb 29 02:46:23 PM PST 24 Feb 29 02:46:33 PM PST 24 10177407880 ps
T1333 /workspace/coverage/default/12.i2c_target_unexp_stop.3649153635 Feb 29 02:45:32 PM PST 24 Feb 29 02:45:39 PM PST 24 5578147288 ps
T1334 /workspace/coverage/default/4.i2c_target_hrst.2872776000 Feb 29 02:44:09 PM PST 24 Feb 29 02:44:11 PM PST 24 2077061188 ps
T1335 /workspace/coverage/default/37.i2c_target_timeout.2026102017 Feb 29 02:49:58 PM PST 24 Feb 29 02:50:06 PM PST 24 2079834986 ps
T151 /workspace/coverage/default/36.i2c_host_override.2437064903 Feb 29 02:49:44 PM PST 24 Feb 29 02:49:45 PM PST 24 60524891 ps
T1336 /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3354846814 Feb 29 02:45:17 PM PST 24 Feb 29 02:45:26 PM PST 24 6786778980 ps
T1337 /workspace/coverage/default/46.i2c_target_perf.1618202204 Feb 29 02:51:37 PM PST 24 Feb 29 02:51:43 PM PST 24 955545025 ps
T1338 /workspace/coverage/default/43.i2c_target_intr_smoke.1261941023 Feb 29 02:51:04 PM PST 24 Feb 29 02:51:10 PM PST 24 23070925309 ps
T1339 /workspace/coverage/default/30.i2c_target_stress_wr.2072789570 Feb 29 02:48:45 PM PST 24 Feb 29 03:23:23 PM PST 24 46444545898 ps
T1340 /workspace/coverage/default/46.i2c_host_perf.2963036187 Feb 29 02:51:35 PM PST 24 Feb 29 02:51:40 PM PST 24 202137308 ps
T107 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2126317642 Feb 29 12:48:23 PM PST 24 Feb 29 12:48:24 PM PST 24 26135151 ps
T67 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3654582484 Feb 29 12:48:01 PM PST 24 Feb 29 12:48:03 PM PST 24 100611798 ps
T58 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4014955510 Feb 29 12:47:57 PM PST 24 Feb 29 12:47:58 PM PST 24 27400998 ps
T108 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.453108533 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:03 PM PST 24 133889990 ps
T109 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2395223737 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:52 PM PST 24 50000311 ps
T121 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3425744337 Feb 29 12:48:25 PM PST 24 Feb 29 12:48:26 PM PST 24 74934838 ps
T122 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2739846576 Feb 29 12:47:59 PM PST 24 Feb 29 12:48:00 PM PST 24 53548160 ps
T68 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1476959380 Feb 29 12:48:01 PM PST 24 Feb 29 12:48:04 PM PST 24 465218749 ps
T69 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2088447039 Feb 29 12:47:54 PM PST 24 Feb 29 12:47:57 PM PST 24 164928308 ps
T70 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2684819933 Feb 29 12:48:26 PM PST 24 Feb 29 12:48:29 PM PST 24 217254045 ps
T110 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4188598995 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:56 PM PST 24 18044385 ps
T71 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.427862076 Feb 29 12:47:58 PM PST 24 Feb 29 12:48:00 PM PST 24 42866388 ps
T101 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2762975653 Feb 29 12:48:13 PM PST 24 Feb 29 12:48:15 PM PST 24 86834992 ps
T79 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3579087417 Feb 29 12:47:40 PM PST 24 Feb 29 12:47:41 PM PST 24 56000664 ps
T75 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2225314219 Feb 29 12:48:34 PM PST 24 Feb 29 12:48:37 PM PST 24 82886781 ps
T91 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3290592849 Feb 29 12:48:26 PM PST 24 Feb 29 12:48:27 PM PST 24 780373305 ps
T59 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2555314929 Feb 29 12:48:12 PM PST 24 Feb 29 12:48:13 PM PST 24 17581002 ps
T102 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2229346863 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:56 PM PST 24 45262402 ps
T123 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4187457347 Feb 29 12:47:56 PM PST 24 Feb 29 12:47:57 PM PST 24 25364427 ps
T93 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3575827797 Feb 29 12:48:30 PM PST 24 Feb 29 12:48:32 PM PST 24 109226066 ps
T76 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2850248700 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:56 PM PST 24 268050248 ps
T1341 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1012846248 Feb 29 12:47:40 PM PST 24 Feb 29 12:47:43 PM PST 24 326073313 ps
T103 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.462752316 Feb 29 12:48:07 PM PST 24 Feb 29 12:48:09 PM PST 24 50985008 ps
T77 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3884485797 Feb 29 12:47:57 PM PST 24 Feb 29 12:48:00 PM PST 24 261261791 ps
T78 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2752103143 Feb 29 12:48:05 PM PST 24 Feb 29 12:48:07 PM PST 24 105437407 ps
T94 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.626350491 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:53 PM PST 24 153146752 ps
T1342 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2994285828 Feb 29 12:47:46 PM PST 24 Feb 29 12:47:49 PM PST 24 155573874 ps
T1343 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.632924774 Feb 29 12:48:05 PM PST 24 Feb 29 12:48:06 PM PST 24 117584326 ps
T1344 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3239617484 Feb 29 12:47:39 PM PST 24 Feb 29 12:47:41 PM PST 24 59705775 ps
T88 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.594826942 Feb 29 12:47:57 PM PST 24 Feb 29 12:47:59 PM PST 24 287788165 ps
T80 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2805227819 Feb 29 12:47:59 PM PST 24 Feb 29 12:48:02 PM PST 24 140310181 ps
T111 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1084587451 Feb 29 12:47:38 PM PST 24 Feb 29 12:47:40 PM PST 24 59217718 ps
T126 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1766428735 Feb 29 12:48:21 PM PST 24 Feb 29 12:48:23 PM PST 24 128213425 ps
T1345 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.420387876 Feb 29 12:47:53 PM PST 24 Feb 29 12:47:55 PM PST 24 50856669 ps
T127 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.321822998 Feb 29 12:47:53 PM PST 24 Feb 29 12:47:54 PM PST 24 62618839 ps
T60 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3735969943 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:03 PM PST 24 82883634 ps
T124 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.46677298 Feb 29 12:47:58 PM PST 24 Feb 29 12:47:59 PM PST 24 28038141 ps
T1346 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3651291811 Feb 29 12:48:17 PM PST 24 Feb 29 12:48:20 PM PST 24 157016193 ps
T125 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3309988734 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:57 PM PST 24 61327204 ps
T112 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3626202221 Feb 29 12:47:53 PM PST 24 Feb 29 12:47:54 PM PST 24 57376463 ps
T1347 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1100275710 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:52 PM PST 24 93803054 ps
T1348 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3427269336 Feb 29 12:47:58 PM PST 24 Feb 29 12:47:59 PM PST 24 28307620 ps
T92 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3913157413 Feb 29 12:48:09 PM PST 24 Feb 29 12:48:10 PM PST 24 76470249 ps
T161 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2927112883 Feb 29 12:47:54 PM PST 24 Feb 29 12:47:57 PM PST 24 990581481 ps
T113 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1301252511 Feb 29 12:48:06 PM PST 24 Feb 29 12:48:08 PM PST 24 80562230 ps
T114 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1649333243 Feb 29 12:47:47 PM PST 24 Feb 29 12:47:48 PM PST 24 23356475 ps
T1349 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.288270616 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:56 PM PST 24 35632208 ps
T1350 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.558229078 Feb 29 12:47:50 PM PST 24 Feb 29 12:47:52 PM PST 24 431659519 ps
T1351 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1180198737 Feb 29 12:47:42 PM PST 24 Feb 29 12:47:43 PM PST 24 47886201 ps
T1352 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2733808291 Feb 29 12:48:31 PM PST 24 Feb 29 12:48:33 PM PST 24 17619602 ps
T1353 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2351392176 Feb 29 12:48:05 PM PST 24 Feb 29 12:48:06 PM PST 24 87196808 ps
T1354 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1971328841 Feb 29 12:47:54 PM PST 24 Feb 29 12:47:55 PM PST 24 45550088 ps
T115 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2864848264 Feb 29 12:48:07 PM PST 24 Feb 29 12:48:08 PM PST 24 17977721 ps
T198 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3093890184 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:04 PM PST 24 19521064 ps
T1355 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1555467595 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:05 PM PST 24 243901913 ps
T116 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3602160000 Feb 29 12:47:59 PM PST 24 Feb 29 12:47:59 PM PST 24 125556256 ps
T1356 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4108494841 Feb 29 12:48:01 PM PST 24 Feb 29 12:48:02 PM PST 24 43928906 ps
T1357 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.429352551 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:05 PM PST 24 34058638 ps
T1358 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2122910841 Feb 29 12:48:00 PM PST 24 Feb 29 12:48:02 PM PST 24 171261506 ps
T1359 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.485315293 Feb 29 12:48:16 PM PST 24 Feb 29 12:48:18 PM PST 24 188299930 ps
T1360 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.4188798150 Feb 29 12:47:53 PM PST 24 Feb 29 12:47:53 PM PST 24 24638468 ps
T1361 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1937532745 Feb 29 12:48:01 PM PST 24 Feb 29 12:48:03 PM PST 24 32237565 ps
T1362 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.421745896 Feb 29 12:48:23 PM PST 24 Feb 29 12:48:25 PM PST 24 110754255 ps
T95 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1070347451 Feb 29 12:47:48 PM PST 24 Feb 29 12:47:50 PM PST 24 335452807 ps
T1363 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2112233166 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:57 PM PST 24 67118532 ps
T1364 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3250179581 Feb 29 12:47:58 PM PST 24 Feb 29 12:48:00 PM PST 24 81308028 ps
T1365 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3831642658 Feb 29 12:47:57 PM PST 24 Feb 29 12:48:01 PM PST 24 204034312 ps
T1366 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.863675674 Feb 29 12:48:15 PM PST 24 Feb 29 12:48:16 PM PST 24 41583565 ps
T1367 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.984808412 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:57 PM PST 24 365070930 ps
T1368 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.339764852 Feb 29 12:48:29 PM PST 24 Feb 29 12:48:30 PM PST 24 41386622 ps
T1369 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1944158584 Feb 29 12:48:37 PM PST 24 Feb 29 12:48:39 PM PST 24 21997362 ps
T117 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2321740921 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:52 PM PST 24 49968877 ps
T1370 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3727825897 Feb 29 12:47:58 PM PST 24 Feb 29 12:47:59 PM PST 24 34574241 ps
T89 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3056155589 Feb 29 12:47:43 PM PST 24 Feb 29 12:47:46 PM PST 24 518394275 ps
T1371 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.545504122 Feb 29 12:47:45 PM PST 24 Feb 29 12:47:47 PM PST 24 505864963 ps
T1372 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4055475415 Feb 29 12:47:58 PM PST 24 Feb 29 12:48:00 PM PST 24 77264724 ps
T1373 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.595605429 Feb 29 12:48:13 PM PST 24 Feb 29 12:48:14 PM PST 24 44466675 ps
T1374 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2603479240 Feb 29 12:48:31 PM PST 24 Feb 29 12:48:32 PM PST 24 138352008 ps
T1375 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3921717828 Feb 29 12:47:36 PM PST 24 Feb 29 12:47:38 PM PST 24 244288962 ps
T118 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.66923132 Feb 29 12:47:56 PM PST 24 Feb 29 12:48:02 PM PST 24 39058489 ps
T1376 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3832340449 Feb 29 12:48:16 PM PST 24 Feb 29 12:48:18 PM PST 24 41738389 ps
T120 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2462739081 Feb 29 12:48:04 PM PST 24 Feb 29 12:48:05 PM PST 24 184364589 ps
T1377 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.273091654 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:05 PM PST 24 236888569 ps
T1378 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2097776507 Feb 29 12:48:00 PM PST 24 Feb 29 12:48:02 PM PST 24 53110369 ps
T1379 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2779850633 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:06 PM PST 24 376736653 ps
T119 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3349300482 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:56 PM PST 24 1338029107 ps
T1380 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1464195730 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:57 PM PST 24 219384340 ps
T1381 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.937127094 Feb 29 12:47:49 PM PST 24 Feb 29 12:47:52 PM PST 24 1145441967 ps
T1382 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2431966951 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:56 PM PST 24 29315005 ps
T90 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.450524205 Feb 29 12:48:18 PM PST 24 Feb 29 12:48:20 PM PST 24 379186208 ps
T1383 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3753631444 Feb 29 12:47:57 PM PST 24 Feb 29 12:47:58 PM PST 24 32106590 ps
T1384 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.346345462 Feb 29 12:47:52 PM PST 24 Feb 29 12:47:53 PM PST 24 59542858 ps
T1385 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3234869178 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:55 PM PST 24 24193322 ps
T1386 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.76223885 Feb 29 12:48:05 PM PST 24 Feb 29 12:48:07 PM PST 24 231871779 ps
T1387 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3093265621 Feb 29 12:47:47 PM PST 24 Feb 29 12:47:48 PM PST 24 270226121 ps
T201 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1740236709 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:03 PM PST 24 33986865 ps
T1388 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2037364382 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:04 PM PST 24 155139066 ps
T1389 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.421495029 Feb 29 12:47:56 PM PST 24 Feb 29 12:47:57 PM PST 24 61950999 ps
T84 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2220540521 Feb 29 12:47:59 PM PST 24 Feb 29 12:48:01 PM PST 24 152769211 ps
T85 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2606682326 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:53 PM PST 24 435915126 ps
T1390 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.354821441 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:52 PM PST 24 127571736 ps
T1391 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1742345605 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:05 PM PST 24 80395532 ps
T1392 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.304072885 Feb 29 12:48:13 PM PST 24 Feb 29 12:48:13 PM PST 24 27443584 ps
T1393 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.514661847 Feb 29 12:47:49 PM PST 24 Feb 29 12:47:50 PM PST 24 432325387 ps
T1394 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4123483702 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:03 PM PST 24 64647064 ps
T1395 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2176738902 Feb 29 12:48:13 PM PST 24 Feb 29 12:48:14 PM PST 24 67220119 ps
T1396 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3106084645 Feb 29 12:47:48 PM PST 24 Feb 29 12:47:50 PM PST 24 120594277 ps
T1397 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1050108074 Feb 29 12:48:20 PM PST 24 Feb 29 12:48:23 PM PST 24 51530012 ps
T1398 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.561317771 Feb 29 12:48:00 PM PST 24 Feb 29 12:48:01 PM PST 24 123073072 ps
T1399 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3485485396 Feb 29 12:47:51 PM PST 24 Feb 29 12:47:52 PM PST 24 172743338 ps
T1400 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1305116191 Feb 29 12:47:58 PM PST 24 Feb 29 12:47:58 PM PST 24 22401008 ps
T1401 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2378560180 Feb 29 12:47:55 PM PST 24 Feb 29 12:47:56 PM PST 24 57121326 ps
T1402 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3856127465 Feb 29 12:48:01 PM PST 24 Feb 29 12:48:04 PM PST 24 757781718 ps
T1403 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1589517954 Feb 29 12:48:19 PM PST 24 Feb 29 12:48:20 PM PST 24 207134353 ps
T1404 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3911553169 Feb 29 12:47:53 PM PST 24 Feb 29 12:47:54 PM PST 24 156881153 ps
T1405 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3339608228 Feb 29 12:48:03 PM PST 24 Feb 29 12:48:05 PM PST 24 88882790 ps
T1406 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1732444949 Feb 29 12:48:02 PM PST 24 Feb 29 12:48:03 PM PST 24 139590689 ps
T1407 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.212126021 Feb 29 12:47:34 PM PST 24 Feb 29 12:47:36 PM PST 24 145044650 ps
T1408 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1233131842 Feb 29 12:47:47 PM PST 24 Feb 29 12:47:47 PM PST 24 31205691 ps

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1243305037
Short name T14
Test name
Test status
Simulation time 4748509846 ps
CPU time 88.79 seconds
Started Feb 29 02:48:23 PM PST 24
Finished Feb 29 02:49:52 PM PST 24
Peak memory 783528 kb
Host smart-5c88210f-467a-4569-a323-8ec9f22bb567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243305037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1243305037
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_target_stress_all.350953837
Short name T19
Test name
Test status
Simulation time 13863300265 ps
CPU time 226.59 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:50:48 PM PST 24
Peak memory 2370936 kb
Host smart-e2f07758-658d-4616-a558-69f207e65c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350953837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.i2c_target_stress_all.350953837
Directory /workspace/20.i2c_target_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.8949215
Short name T41
Test name
Test status
Simulation time 2063546616 ps
CPU time 3.87 seconds
Started Feb 29 02:42:52 PM PST 24
Finished Feb 29 02:42:56 PM PST 24
Peak memory 203904 kb
Host smart-df55facc-832a-4672-adc9-9d55f63df9e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8949215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.8949215
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.3854849237
Short name T57
Test name
Test status
Simulation time 27765182628 ps
CPU time 1087.05 seconds
Started Feb 29 02:46:17 PM PST 24
Finished Feb 29 03:04:24 PM PST 24
Peak memory 2178524 kb
Host smart-fd6b4958-80ac-4ded-9dfc-d8ca5d5a2ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854849237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.3854849237
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1192867178
Short name T52
Test name
Test status
Simulation time 141611777114 ps
CPU time 2082.66 seconds
Started Feb 29 02:46:23 PM PST 24
Finished Feb 29 03:21:07 PM PST 24
Peak memory 2814240 kb
Host smart-01a4dd46-7970-4e64-9e05-be8e3a5075ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192867178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1192867178
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1476959380
Short name T68
Test name
Test status
Simulation time 465218749 ps
CPU time 2.13 seconds
Started Feb 29 12:48:01 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 202996 kb
Host smart-3bb730d6-5eb6-41bc-9416-848aad3a3bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476959380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1476959380
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3641862371
Short name T11
Test name
Test status
Simulation time 7087978121 ps
CPU time 104.07 seconds
Started Feb 29 02:43:02 PM PST 24
Finished Feb 29 02:44:46 PM PST 24
Peak memory 247884 kb
Host smart-03e943d3-66ed-43cf-9801-c4a004b16a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641862371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3641862371
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1740236709
Short name T201
Test name
Test status
Simulation time 33986865 ps
CPU time 0.71 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 202704 kb
Host smart-bbfb326f-67ae-4793-b0a8-db5475862cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740236709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1740236709
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/default/14.i2c_host_override.3867405031
Short name T143
Test name
Test status
Simulation time 50228302 ps
CPU time 0.67 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:45:56 PM PST 24
Peak memory 202832 kb
Host smart-6c4b019b-0820-44a1-8a20-f0d1381d78fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867405031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3867405031
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.3800455331
Short name T28
Test name
Test status
Simulation time 7191384451 ps
CPU time 7.68 seconds
Started Feb 29 02:48:45 PM PST 24
Finished Feb 29 02:48:52 PM PST 24
Peak memory 203684 kb
Host smart-b84fa032-b551-42cb-99d5-bb3684f63229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800455331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.3800455331
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3884485797
Short name T77
Test name
Test status
Simulation time 261261791 ps
CPU time 3.02 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:48:00 PM PST 24
Peak memory 203000 kb
Host smart-20023be9-4716-4e9b-b7cf-48fbf702a051
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884485797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3884485797
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1378407401
Short name T73
Test name
Test status
Simulation time 74125045 ps
CPU time 0.81 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:43:39 PM PST 24
Peak memory 220388 kb
Host smart-cc1546d2-485e-4473-ab3c-5ad396286726
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378407401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1378407401
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.546920373
Short name T172
Test name
Test status
Simulation time 10510309085 ps
CPU time 11.13 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:50:49 PM PST 24
Peak memory 258872 kb
Host smart-114776ce-4fe2-4995-9e36-626d109d3304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546920373 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.546920373
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1301252511
Short name T113
Test name
Test status
Simulation time 80562230 ps
CPU time 0.71 seconds
Started Feb 29 12:48:06 PM PST 24
Finished Feb 29 12:48:08 PM PST 24
Peak memory 202788 kb
Host smart-05c0e654-a486-4c56-9080-5bc82b562f6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301252511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1301252511
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3116862723
Short name T246
Test name
Test status
Simulation time 1391235097 ps
CPU time 4.29 seconds
Started Feb 29 02:45:28 PM PST 24
Finished Feb 29 02:45:32 PM PST 24
Peak memory 203628 kb
Host smart-97fdad5e-5c86-4110-8766-91813b160e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116862723 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3116862723
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3093890184
Short name T198
Test name
Test status
Simulation time 19521064 ps
CPU time 0.68 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 202720 kb
Host smart-e2e8aeeb-29a0-441a-95e6-6b874e14668a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093890184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3093890184
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.4132746014
Short name T45
Test name
Test status
Simulation time 29078473419 ps
CPU time 480.84 seconds
Started Feb 29 02:50:26 PM PST 24
Finished Feb 29 02:58:28 PM PST 24
Peak memory 1392132 kb
Host smart-751847fc-34aa-4d97-8952-484727e3dbdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132746014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.4132746014
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.742121215
Short name T34
Test name
Test status
Simulation time 180566580614 ps
CPU time 657.26 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:58:56 PM PST 24
Peak memory 1800408 kb
Host smart-34a523fa-5472-4f70-87f3-47f3a7db58cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742121215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.742121215
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.1227924005
Short name T510
Test name
Test status
Simulation time 672341724 ps
CPU time 3.04 seconds
Started Feb 29 02:43:24 PM PST 24
Finished Feb 29 02:43:27 PM PST 24
Peak memory 203644 kb
Host smart-7d2cc630-4316-4c16-a461-1d53493605dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227924005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.1227924005
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2278229950
Short name T670
Test name
Test status
Simulation time 28437948592 ps
CPU time 486.24 seconds
Started Feb 29 02:50:39 PM PST 24
Finished Feb 29 02:58:45 PM PST 24
Peak memory 211920 kb
Host smart-e97315f3-6200-4720-b5df-6dd18cce7075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278229950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2278229950
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.1193249134
Short name T162
Test name
Test status
Simulation time 15783392874 ps
CPU time 1153.34 seconds
Started Feb 29 02:51:05 PM PST 24
Finished Feb 29 03:10:18 PM PST 24
Peak memory 3593168 kb
Host smart-30d84008-4ae9-499d-bd18-8214a40b0a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193249134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1193249134
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2683195723
Short name T396
Test name
Test status
Simulation time 20094946 ps
CPU time 0.65 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:43:27 PM PST 24
Peak memory 202704 kb
Host smart-499e20bc-eff0-4a72-a226-d78999531b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683195723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2683195723
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1794361724
Short name T9
Test name
Test status
Simulation time 756555114 ps
CPU time 10.63 seconds
Started Feb 29 02:45:27 PM PST 24
Finished Feb 29 02:45:38 PM PST 24
Peak memory 239544 kb
Host smart-3c7bb4ed-9ff2-413c-991a-923f71cbf015
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794361724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1794361724
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2355777282
Short name T40
Test name
Test status
Simulation time 125435833 ps
CPU time 0.86 seconds
Started Feb 29 02:43:25 PM PST 24
Finished Feb 29 02:43:26 PM PST 24
Peak memory 203460 kb
Host smart-83126ca9-9fec-48ad-866b-48ac700f361c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355777282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2355777282
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2555314929
Short name T59
Test name
Test status
Simulation time 17581002 ps
CPU time 0.67 seconds
Started Feb 29 12:48:12 PM PST 24
Finished Feb 29 12:48:13 PM PST 24
Peak memory 202824 kb
Host smart-1a504bd3-1b45-49fd-a40e-799833ddb961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555314929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2555314929
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3913157413
Short name T92
Test name
Test status
Simulation time 76470249 ps
CPU time 1.29 seconds
Started Feb 29 12:48:09 PM PST 24
Finished Feb 29 12:48:10 PM PST 24
Peak memory 203124 kb
Host smart-8dc15e98-cfce-45ee-9679-76e318a85617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913157413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3913157413
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/11.i2c_host_perf.992430289
Short name T184
Test name
Test status
Simulation time 4057081291 ps
CPU time 53.17 seconds
Started Feb 29 02:45:23 PM PST 24
Finished Feb 29 02:46:16 PM PST 24
Peak memory 229156 kb
Host smart-db75c980-d1f3-4519-a639-fa7898861e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992430289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.992430289
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2900862279
Short name T225
Test name
Test status
Simulation time 10056989587 ps
CPU time 73.05 seconds
Started Feb 29 02:47:09 PM PST 24
Finished Feb 29 02:48:23 PM PST 24
Peak memory 601648 kb
Host smart-af045c9a-0bc6-41fa-8335-57a79233c8c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900862279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2900862279
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_stress_all.3380376603
Short name T205
Test name
Test status
Simulation time 30302287066 ps
CPU time 953.18 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 03:01:25 PM PST 24
Peak memory 5157896 kb
Host smart-02be3585-ca96-4f9b-9d07-03e8bc84a419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380376603 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.i2c_target_stress_all.3380376603
Directory /workspace/12.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.4107694672
Short name T202
Test name
Test status
Simulation time 2520577224 ps
CPU time 2.87 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:47:03 PM PST 24
Peak memory 203688 kb
Host smart-16fa48c8-0870-465b-a36b-9eb282b6e3b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107694672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.4107694672
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1006123093
Short name T38
Test name
Test status
Simulation time 907645216 ps
CPU time 0.88 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:47:02 PM PST 24
Peak memory 203388 kb
Host smart-b3eaf5e7-08d0-4022-b8f5-067c3e8dd081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006123093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1006123093
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3575827797
Short name T93
Test name
Test status
Simulation time 109226066 ps
CPU time 2.06 seconds
Started Feb 29 12:48:30 PM PST 24
Finished Feb 29 12:48:32 PM PST 24
Peak memory 203052 kb
Host smart-685d6250-f808-4344-919c-1e7f3caaadd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575827797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3575827797
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.422139387
Short name T200
Test name
Test status
Simulation time 10122601782 ps
CPU time 55.71 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:47:17 PM PST 24
Peak memory 471276 kb
Host smart-b1082809-11b2-44d3-a7e8-0a35ecec8723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422139387 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.422139387
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3735969943
Short name T60
Test name
Test status
Simulation time 82883634 ps
CPU time 0.64 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 202756 kb
Host smart-23762f5c-7566-4cb5-b50e-e07f1071176c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735969943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3735969943
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.211338247
Short name T224
Test name
Test status
Simulation time 10063648671 ps
CPU time 66.1 seconds
Started Feb 29 02:43:24 PM PST 24
Finished Feb 29 02:44:30 PM PST 24
Peak memory 568952 kb
Host smart-7f86e630-82e0-4da0-b949-ad7cb302e080
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211338247 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_acq.211338247
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3158194830
Short name T139
Test name
Test status
Simulation time 859003572 ps
CPU time 15.31 seconds
Started Feb 29 02:45:25 PM PST 24
Finished Feb 29 02:45:41 PM PST 24
Peak memory 219892 kb
Host smart-abcbd205-5365-4de0-b427-930e2a2e440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158194830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3158194830
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_host_rx_oversample.3708141023
Short name T211
Test name
Test status
Simulation time 5918804325 ps
CPU time 215.22 seconds
Started Feb 29 02:45:43 PM PST 24
Finished Feb 29 02:49:18 PM PST 24
Peak memory 406144 kb
Host smart-648b957e-a603-4c9d-b37c-d7dc4d79eec6
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708141023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_rx_oversample
.3708141023
Directory /workspace/13.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1030785167
Short name T190
Test name
Test status
Simulation time 4714895319 ps
CPU time 98.91 seconds
Started Feb 29 02:45:43 PM PST 24
Finished Feb 29 02:47:22 PM PST 24
Peak memory 204916 kb
Host smart-a713f76b-af72-4401-b3a6-a42af65b9a64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030785167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1030785167
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_host_rx_oversample.2913422073
Short name T218
Test name
Test status
Simulation time 2633566758 ps
CPU time 49.03 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 02:46:58 PM PST 24
Peak memory 284304 kb
Host smart-e039c24f-36bc-4755-86ec-fa6f5381dc15
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913422073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_rx_oversample
.2913422073
Directory /workspace/16.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2594078433
Short name T216
Test name
Test status
Simulation time 18528203879 ps
CPU time 130.34 seconds
Started Feb 29 02:47:32 PM PST 24
Finished Feb 29 02:49:43 PM PST 24
Peak memory 1215372 kb
Host smart-3d9a20bf-3688-415a-8563-5daa8f772092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594078433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2594078433
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.450524205
Short name T90
Test name
Test status
Simulation time 379186208 ps
CPU time 1.99 seconds
Started Feb 29 12:48:18 PM PST 24
Finished Feb 29 12:48:20 PM PST 24
Peak memory 203016 kb
Host smart-c26b792b-1b6b-404f-9c56-1e0a7d056f12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450524205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.450524205
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2220540521
Short name T84
Test name
Test status
Simulation time 152769211 ps
CPU time 1.84 seconds
Started Feb 29 12:47:59 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 203104 kb
Host smart-68acf749-3c12-438c-8568-6cb5c2d5235e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220540521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2220540521
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.4051018114
Short name T33
Test name
Test status
Simulation time 2364394167 ps
CPU time 133.81 seconds
Started Feb 29 02:49:13 PM PST 24
Finished Feb 29 02:51:27 PM PST 24
Peak memory 259372 kb
Host smart-9369e6fe-bdef-47c2-b2c3-636e39c57038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051018114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.4051018114
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3921717828
Short name T1375
Test name
Test status
Simulation time 244288962 ps
CPU time 1.57 seconds
Started Feb 29 12:47:36 PM PST 24
Finished Feb 29 12:47:38 PM PST 24
Peak memory 203020 kb
Host smart-c6d4bed0-88c9-4eb5-a2b8-0f82261de162
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921717828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3921717828
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1012846248
Short name T1341
Test name
Test status
Simulation time 326073313 ps
CPU time 2.55 seconds
Started Feb 29 12:47:40 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 203092 kb
Host smart-8e5f196c-e986-409e-a671-ca5f0be8e517
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012846248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1012846248
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3753631444
Short name T1383
Test name
Test status
Simulation time 32106590 ps
CPU time 0.77 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 202832 kb
Host smart-3ce760db-87b7-4f5d-b1de-673e3c77b47b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753631444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3753631444
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3239617484
Short name T1344
Test name
Test status
Simulation time 59705775 ps
CPU time 1.38 seconds
Started Feb 29 12:47:39 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 202956 kb
Host smart-6d2fe73e-019c-4ab3-835d-ddd721801dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239617484 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3239617484
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1233131842
Short name T1408
Test name
Test status
Simulation time 31205691 ps
CPU time 0.68 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 202824 kb
Host smart-26464947-c61d-4c1e-8e98-c3b7898d0cb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233131842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1233131842
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1180198737
Short name T1351
Test name
Test status
Simulation time 47886201 ps
CPU time 0.79 seconds
Started Feb 29 12:47:42 PM PST 24
Finished Feb 29 12:47:43 PM PST 24
Peak memory 202744 kb
Host smart-59c1ccc6-1971-457e-a57b-6dd1d6255a62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180198737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.1180198737
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.937127094
Short name T1381
Test name
Test status
Simulation time 1145441967 ps
CPU time 2.06 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 202960 kb
Host smart-fb719a26-0179-42cd-a91f-7815ffa6534b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937127094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.937127094
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.545504122
Short name T1371
Test name
Test status
Simulation time 505864963 ps
CPU time 1.8 seconds
Started Feb 29 12:47:45 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 202940 kb
Host smart-1e1e66c0-f4f4-434e-aa94-cf9f8cfc0ab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545504122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.545504122
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1084587451
Short name T111
Test name
Test status
Simulation time 59217718 ps
CPU time 1.06 seconds
Started Feb 29 12:47:38 PM PST 24
Finished Feb 29 12:47:40 PM PST 24
Peak memory 203008 kb
Host smart-7ce90a83-fa98-4630-81bb-6525e1d7a127
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084587451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1084587451
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2927112883
Short name T161
Test name
Test status
Simulation time 990581481 ps
CPU time 2.7 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 203096 kb
Host smart-4585f7f1-77b3-49d1-a328-dd65feb10dd0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927112883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2927112883
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.304072885
Short name T1392
Test name
Test status
Simulation time 27443584 ps
CPU time 0.63 seconds
Started Feb 29 12:48:13 PM PST 24
Finished Feb 29 12:48:13 PM PST 24
Peak memory 201812 kb
Host smart-3c80ab64-4568-42e8-a59a-20d223825ae1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304072885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.304072885
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.354821441
Short name T1390
Test name
Test status
Simulation time 127571736 ps
CPU time 0.96 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 202904 kb
Host smart-150523ba-b261-454a-91fa-c8e82d8b7e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354821441 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.354821441
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4187457347
Short name T123
Test name
Test status
Simulation time 25364427 ps
CPU time 0.72 seconds
Started Feb 29 12:47:56 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 202324 kb
Host smart-0de37716-c04e-4428-94d9-55f28a48f026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187457347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.4187457347
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3911553169
Short name T1404
Test name
Test status
Simulation time 156881153 ps
CPU time 1.05 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 202988 kb
Host smart-50bb1a30-3188-48e2-892d-2c8a26301494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911553169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.3911553169
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.462752316
Short name T103
Test name
Test status
Simulation time 50985008 ps
CPU time 1.39 seconds
Started Feb 29 12:48:07 PM PST 24
Finished Feb 29 12:48:09 PM PST 24
Peak memory 203180 kb
Host smart-12ca70e6-2491-494e-8e75-e214318f1344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462752316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.462752316
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2097776507
Short name T1378
Test name
Test status
Simulation time 53110369 ps
CPU time 0.91 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 202884 kb
Host smart-25ceedb0-3737-48bf-805a-40707f9a37c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097776507 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2097776507
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1589517954
Short name T1403
Test name
Test status
Simulation time 207134353 ps
CPU time 0.75 seconds
Started Feb 29 12:48:19 PM PST 24
Finished Feb 29 12:48:20 PM PST 24
Peak memory 202580 kb
Host smart-0ecab75f-13b4-49c3-a174-3d9940d8a9ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589517954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1589517954
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.595605429
Short name T1373
Test name
Test status
Simulation time 44466675 ps
CPU time 1.05 seconds
Started Feb 29 12:48:13 PM PST 24
Finished Feb 29 12:48:14 PM PST 24
Peak memory 203096 kb
Host smart-3bb40522-6f94-4ad2-bfc5-37731568785b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595605429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.595605429
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.984808412
Short name T1367
Test name
Test status
Simulation time 365070930 ps
CPU time 2.13 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 203024 kb
Host smart-89d96fe9-6e72-4490-813a-d3203a4beafe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984808412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.984808412
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3106084645
Short name T1396
Test name
Test status
Simulation time 120594277 ps
CPU time 1.37 seconds
Started Feb 29 12:47:48 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 203048 kb
Host smart-b3228ba0-aeae-440c-94f9-f97a6d3846a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106084645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3106084645
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2229346863
Short name T102
Test name
Test status
Simulation time 45262402 ps
CPU time 1 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 202916 kb
Host smart-c30b0dcf-85b3-42cd-b124-95f1af8a3de6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229346863 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2229346863
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.66923132
Short name T118
Test name
Test status
Simulation time 39058489 ps
CPU time 0.72 seconds
Started Feb 29 12:47:56 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 202660 kb
Host smart-db396433-9484-4884-8849-491929c13a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66923132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.66923132
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.288270616
Short name T1349
Test name
Test status
Simulation time 35632208 ps
CPU time 0.81 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 202824 kb
Host smart-2fdb6d6b-9718-4672-a518-1df6c9ae9dd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288270616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_ou
tstanding.288270616
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1050108074
Short name T1397
Test name
Test status
Simulation time 51530012 ps
CPU time 2.55 seconds
Started Feb 29 12:48:20 PM PST 24
Finished Feb 29 12:48:23 PM PST 24
Peak memory 203032 kb
Host smart-bcc697a7-b3d3-49a3-b4cd-c611d18f01b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050108074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1050108074
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.76223885
Short name T1386
Test name
Test status
Simulation time 231871779 ps
CPU time 1.25 seconds
Started Feb 29 12:48:05 PM PST 24
Finished Feb 29 12:48:07 PM PST 24
Peak memory 203024 kb
Host smart-1bfa6ca4-fe91-4331-9723-9be9600c8d4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76223885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.76223885
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2176738902
Short name T1395
Test name
Test status
Simulation time 67220119 ps
CPU time 0.93 seconds
Started Feb 29 12:48:13 PM PST 24
Finished Feb 29 12:48:14 PM PST 24
Peak memory 202936 kb
Host smart-3ed3925b-eb63-48ea-8fb9-4c2aa2ec8fbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176738902 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2176738902
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2378560180
Short name T1401
Test name
Test status
Simulation time 57121326 ps
CPU time 0.63 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 202196 kb
Host smart-8b455e3a-86ed-42fc-ae11-ae8a8df8ccf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378560180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2378560180
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3425744337
Short name T121
Test name
Test status
Simulation time 74934838 ps
CPU time 0.96 seconds
Started Feb 29 12:48:25 PM PST 24
Finished Feb 29 12:48:26 PM PST 24
Peak memory 202972 kb
Host smart-426d3730-9cc3-4355-a43e-604432eb1f26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425744337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3425744337
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.558229078
Short name T1350
Test name
Test status
Simulation time 431659519 ps
CPU time 2.09 seconds
Started Feb 29 12:47:50 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 203020 kb
Host smart-46993139-4dfb-431c-8ad2-e138976f24e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558229078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.558229078
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2606682326
Short name T85
Test name
Test status
Simulation time 435915126 ps
CPU time 2.05 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 203076 kb
Host smart-df198ff7-97dc-486b-8d96-c482b96f1986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606682326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2606682326
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2112233166
Short name T1363
Test name
Test status
Simulation time 67118532 ps
CPU time 1.52 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 203140 kb
Host smart-46abe154-51fa-4458-96d2-bb12f5a76bb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112233166 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2112233166
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3626202221
Short name T112
Test name
Test status
Simulation time 57376463 ps
CPU time 0.62 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 201988 kb
Host smart-cce58098-7fbd-45dc-a607-b0d66bf94270
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626202221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3626202221
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2037364382
Short name T1388
Test name
Test status
Simulation time 155139066 ps
CPU time 1.13 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 203016 kb
Host smart-4520c215-5be4-493b-b965-8ded1481d52b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037364382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2037364382
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2805227819
Short name T80
Test name
Test status
Simulation time 140310181 ps
CPU time 1.99 seconds
Started Feb 29 12:47:59 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 202824 kb
Host smart-44b29b90-a75f-4141-9ec9-e53c5682d9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805227819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2805227819
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4123483702
Short name T1394
Test name
Test status
Simulation time 64647064 ps
CPU time 1.02 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 202884 kb
Host smart-c16d0362-891d-470b-bb4f-3ed7bd85de74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123483702 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.4123483702
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4188598995
Short name T110
Test name
Test status
Simulation time 18044385 ps
CPU time 0.68 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 202700 kb
Host smart-981cf3ea-949f-4711-a427-2d47deb71f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188598995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4188598995
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3309988734
Short name T125
Test name
Test status
Simulation time 61327204 ps
CPU time 1.14 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 203012 kb
Host smart-b400b7f9-aea8-4f9e-9afa-888aa9546b90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309988734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.3309988734
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1766428735
Short name T126
Test name
Test status
Simulation time 128213425 ps
CPU time 2.39 seconds
Started Feb 29 12:48:21 PM PST 24
Finished Feb 29 12:48:23 PM PST 24
Peak memory 202844 kb
Host smart-444900d9-aa94-4609-807f-c3d8502ae544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766428735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1766428735
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3485485396
Short name T1399
Test name
Test status
Simulation time 172743338 ps
CPU time 1.24 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 202916 kb
Host smart-d1875968-d3a3-487d-a683-c4f80051df0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485485396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3485485396
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.429352551
Short name T1357
Test name
Test status
Simulation time 34058638 ps
CPU time 1.07 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 202800 kb
Host smart-2a4ebb4a-1050-44c7-a621-5f571099fe51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429352551 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.429352551
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1732444949
Short name T1406
Test name
Test status
Simulation time 139590689 ps
CPU time 0.98 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 202992 kb
Host smart-7a415676-ea1b-4dc4-9858-186960993804
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732444949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1732444949
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3651291811
Short name T1346
Test name
Test status
Simulation time 157016193 ps
CPU time 1.97 seconds
Started Feb 29 12:48:17 PM PST 24
Finished Feb 29 12:48:20 PM PST 24
Peak memory 203008 kb
Host smart-f0d7fdd5-cd02-4f91-8db3-24a092276098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651291811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3651291811
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2225314219
Short name T75
Test name
Test status
Simulation time 82886781 ps
CPU time 1.22 seconds
Started Feb 29 12:48:34 PM PST 24
Finished Feb 29 12:48:37 PM PST 24
Peak memory 203176 kb
Host smart-8fe12b4e-37e6-4630-b20b-403492da4de7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225314219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2225314219
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.427862076
Short name T71
Test name
Test status
Simulation time 42866388 ps
CPU time 1.43 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:48:00 PM PST 24
Peak memory 202900 kb
Host smart-42fc2788-d6c5-41d9-8e9e-9f304da79a31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427862076 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.427862076
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1944158584
Short name T1369
Test name
Test status
Simulation time 21997362 ps
CPU time 0.65 seconds
Started Feb 29 12:48:37 PM PST 24
Finished Feb 29 12:48:39 PM PST 24
Peak memory 202812 kb
Host smart-2ca56dde-da45-4f4d-b645-dfd4297b7833
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944158584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1944158584
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.339764852
Short name T1368
Test name
Test status
Simulation time 41386622 ps
CPU time 0.99 seconds
Started Feb 29 12:48:29 PM PST 24
Finished Feb 29 12:48:30 PM PST 24
Peak memory 203212 kb
Host smart-2d2ff866-0d68-4bd9-8d9d-8eb99332f6f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339764852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.339764852
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3856127465
Short name T1402
Test name
Test status
Simulation time 757781718 ps
CPU time 2.76 seconds
Started Feb 29 12:48:01 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 203088 kb
Host smart-00023fff-586c-493b-b8e5-36f6b617ed60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856127465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3856127465
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.594826942
Short name T88
Test name
Test status
Simulation time 287788165 ps
CPU time 1.89 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:59 PM PST 24
Peak memory 203056 kb
Host smart-2836d2f2-6e04-4da0-b809-d8244ba9bf97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594826942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.594826942
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3234869178
Short name T1385
Test name
Test status
Simulation time 24193322 ps
CPU time 0.72 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 202864 kb
Host smart-28253286-d823-4d03-9081-c842339262dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234869178 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3234869178
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.46677298
Short name T124
Test name
Test status
Simulation time 28038141 ps
CPU time 0.7 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:47:59 PM PST 24
Peak memory 202720 kb
Host smart-6f03458e-1a58-446b-ab09-1af91c457a9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46677298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.46677298
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1305116191
Short name T1400
Test name
Test status
Simulation time 22401008 ps
CPU time 0.78 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 202840 kb
Host smart-336e6e02-a2e6-4495-8b96-1d06b89058c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305116191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1305116191
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4055475415
Short name T1372
Test name
Test status
Simulation time 77264724 ps
CPU time 1.65 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:48:00 PM PST 24
Peak memory 203040 kb
Host smart-edb4aa26-104a-4421-9518-af58a4b05ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055475415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.4055475415
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3427269336
Short name T1348
Test name
Test status
Simulation time 28307620 ps
CPU time 0.83 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:47:59 PM PST 24
Peak memory 202892 kb
Host smart-8241c606-aa6e-4410-9e5b-9bb38a844bfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427269336 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3427269336
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.421495029
Short name T1389
Test name
Test status
Simulation time 61950999 ps
CPU time 0.67 seconds
Started Feb 29 12:47:56 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 202772 kb
Host smart-c8d670fb-6d02-40f1-abbf-df07e42e7a69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421495029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.421495029
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.485315293
Short name T1359
Test name
Test status
Simulation time 188299930 ps
CPU time 1.05 seconds
Started Feb 29 12:48:16 PM PST 24
Finished Feb 29 12:48:18 PM PST 24
Peak memory 203008 kb
Host smart-55cdb8db-02ff-4007-adf5-81fabaf16577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485315293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_ou
tstanding.485315293
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.421745896
Short name T1362
Test name
Test status
Simulation time 110754255 ps
CPU time 1.3 seconds
Started Feb 29 12:48:23 PM PST 24
Finished Feb 29 12:48:25 PM PST 24
Peak memory 203000 kb
Host smart-6a198f2f-7005-4461-815f-70713a273e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421745896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.421745896
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3290592849
Short name T91
Test name
Test status
Simulation time 780373305 ps
CPU time 1.31 seconds
Started Feb 29 12:48:26 PM PST 24
Finished Feb 29 12:48:27 PM PST 24
Peak memory 203076 kb
Host smart-4557ad70-cf15-4c3e-b1ef-47e6cd352ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290592849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3290592849
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2603479240
Short name T1374
Test name
Test status
Simulation time 138352008 ps
CPU time 0.92 seconds
Started Feb 29 12:48:31 PM PST 24
Finished Feb 29 12:48:32 PM PST 24
Peak memory 202900 kb
Host smart-ca456e5f-1bd9-4676-891f-e6cd8463d57b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603479240 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2603479240
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2126317642
Short name T107
Test name
Test status
Simulation time 26135151 ps
CPU time 0.81 seconds
Started Feb 29 12:48:23 PM PST 24
Finished Feb 29 12:48:24 PM PST 24
Peak memory 202748 kb
Host smart-2205fa68-abfd-4f9a-8477-d586583942f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126317642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2126317642
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2122910841
Short name T1358
Test name
Test status
Simulation time 171261506 ps
CPU time 0.8 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 202816 kb
Host smart-1ca7d563-f423-4416-a3f1-785139b2e034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122910841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2122910841
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2684819933
Short name T70
Test name
Test status
Simulation time 217254045 ps
CPU time 2.39 seconds
Started Feb 29 12:48:26 PM PST 24
Finished Feb 29 12:48:29 PM PST 24
Peak memory 203068 kb
Host smart-fea4f462-b3da-4436-a1f9-13ebe70cbdac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684819933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2684819933
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.453108533
Short name T108
Test name
Test status
Simulation time 133889990 ps
CPU time 1.48 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 202972 kb
Host smart-5a4ca540-fb10-4113-997c-e2ad3881943e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453108533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.453108533
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3831642658
Short name T1365
Test name
Test status
Simulation time 204034312 ps
CPU time 4.05 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 203096 kb
Host smart-041e1475-a90a-4c9e-9093-22ebae5297f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831642658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3831642658
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3579087417
Short name T79
Test name
Test status
Simulation time 56000664 ps
CPU time 0.77 seconds
Started Feb 29 12:47:40 PM PST 24
Finished Feb 29 12:47:41 PM PST 24
Peak memory 202844 kb
Host smart-b5513a35-9446-4d65-b070-58ff4ef7d946
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579087417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3579087417
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.212126021
Short name T1407
Test name
Test status
Simulation time 145044650 ps
CPU time 1 seconds
Started Feb 29 12:47:34 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 202720 kb
Host smart-4e02d206-7f84-4812-89a7-2ffaf2be4079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212126021 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.212126021
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.4188798150
Short name T1360
Test name
Test status
Simulation time 24638468 ps
CPU time 0.72 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 202808 kb
Host smart-a8c4fbad-b07b-4c32-b2fe-7885c393be0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188798150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.4188798150
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2351392176
Short name T1353
Test name
Test status
Simulation time 87196808 ps
CPU time 0.8 seconds
Started Feb 29 12:48:05 PM PST 24
Finished Feb 29 12:48:06 PM PST 24
Peak memory 202768 kb
Host smart-cdbb5a0c-e6cd-4d85-bcd0-5207bdd4fa5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351392176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2351392176
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1937532745
Short name T1361
Test name
Test status
Simulation time 32237565 ps
CPU time 1.51 seconds
Started Feb 29 12:48:01 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 203032 kb
Host smart-2361992e-72f1-4371-9d0e-906fc1b71719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937532745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1937532745
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.626350491
Short name T94
Test name
Test status
Simulation time 153146752 ps
CPU time 1.8 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 203240 kb
Host smart-95609846-4062-4f2b-add1-430d170e0080
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626350491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.626350491
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3349300482
Short name T119
Test name
Test status
Simulation time 1338029107 ps
CPU time 1.56 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 202988 kb
Host smart-6f0ec052-84d5-42f0-a680-3d680d142848
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349300482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3349300482
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2994285828
Short name T1342
Test name
Test status
Simulation time 155573874 ps
CPU time 2.43 seconds
Started Feb 29 12:47:46 PM PST 24
Finished Feb 29 12:47:49 PM PST 24
Peak memory 203012 kb
Host smart-1d777a9d-d3b7-4881-9f99-9cbbea1c6d6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994285828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2994285828
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.4014955510
Short name T58
Test name
Test status
Simulation time 27400998 ps
CPU time 0.69 seconds
Started Feb 29 12:47:57 PM PST 24
Finished Feb 29 12:47:58 PM PST 24
Peak memory 202856 kb
Host smart-2fa718c5-1fdf-4365-8872-c5df27a31bce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014955510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.4014955510
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.420387876
Short name T1345
Test name
Test status
Simulation time 50856669 ps
CPU time 1.03 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 202840 kb
Host smart-f465a158-64f7-4fb5-9f25-9f0f7f14bd6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420387876 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.420387876
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1649333243
Short name T114
Test name
Test status
Simulation time 23356475 ps
CPU time 0.79 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 202808 kb
Host smart-3da5feb2-8056-4b16-b185-c09151c9e7e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649333243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1649333243
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4108494841
Short name T1356
Test name
Test status
Simulation time 43928906 ps
CPU time 1.02 seconds
Started Feb 29 12:48:01 PM PST 24
Finished Feb 29 12:48:02 PM PST 24
Peak memory 203036 kb
Host smart-2d91c71a-0516-40e9-804a-24a21ad66300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108494841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.4108494841
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3654582484
Short name T67
Test name
Test status
Simulation time 100611798 ps
CPU time 2.16 seconds
Started Feb 29 12:48:01 PM PST 24
Finished Feb 29 12:48:03 PM PST 24
Peak memory 203048 kb
Host smart-05c8caa2-b225-451a-b50a-d954d927774d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654582484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3654582484
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3093265621
Short name T1387
Test name
Test status
Simulation time 270226121 ps
CPU time 1.34 seconds
Started Feb 29 12:47:47 PM PST 24
Finished Feb 29 12:47:48 PM PST 24
Peak memory 203224 kb
Host smart-895be977-65ec-4fc9-85fe-afc67d67f8b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093265621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3093265621
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2321740921
Short name T117
Test name
Test status
Simulation time 49968877 ps
CPU time 1.05 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 203032 kb
Host smart-bfcb0eda-e750-4a87-8a33-c64512325871
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321740921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2321740921
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1555467595
Short name T1355
Test name
Test status
Simulation time 243901913 ps
CPU time 2.75 seconds
Started Feb 29 12:48:02 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 202988 kb
Host smart-e34222b7-3087-40f5-8dd6-eb0fc65cada8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555467595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1555467595
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3602160000
Short name T116
Test name
Test status
Simulation time 125556256 ps
CPU time 0.7 seconds
Started Feb 29 12:47:59 PM PST 24
Finished Feb 29 12:47:59 PM PST 24
Peak memory 202768 kb
Host smart-77bcf270-acb5-4ace-be46-64a778796932
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602160000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3602160000
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1100275710
Short name T1347
Test name
Test status
Simulation time 93803054 ps
CPU time 0.74 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 202840 kb
Host smart-33513f7b-ed4d-49bb-97eb-bbbf2a33c624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100275710 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1100275710
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.632924774
Short name T1343
Test name
Test status
Simulation time 117584326 ps
CPU time 0.7 seconds
Started Feb 29 12:48:05 PM PST 24
Finished Feb 29 12:48:06 PM PST 24
Peak memory 202760 kb
Host smart-3950baa2-33d0-41e8-921f-287c1c0ebd2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632924774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.632924774
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1971328841
Short name T1354
Test name
Test status
Simulation time 45550088 ps
CPU time 1 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 203032 kb
Host smart-84fef741-4360-4895-9ab2-daebe1b52834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971328841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1971328841
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2752103143
Short name T78
Test name
Test status
Simulation time 105437407 ps
CPU time 1.24 seconds
Started Feb 29 12:48:05 PM PST 24
Finished Feb 29 12:48:07 PM PST 24
Peak memory 203084 kb
Host smart-972b9fa0-40a0-45c0-bdcd-4988edb53dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752103143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2752103143
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3056155589
Short name T89
Test name
Test status
Simulation time 518394275 ps
CPU time 1.93 seconds
Started Feb 29 12:47:43 PM PST 24
Finished Feb 29 12:47:46 PM PST 24
Peak memory 203048 kb
Host smart-b309fac5-9f9b-4322-8555-5078767ade35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056155589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3056155589
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.321822998
Short name T127
Test name
Test status
Simulation time 62618839 ps
CPU time 0.73 seconds
Started Feb 29 12:47:53 PM PST 24
Finished Feb 29 12:47:54 PM PST 24
Peak memory 202824 kb
Host smart-a9b2294c-107a-43f3-833c-d54e4170cd37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321822998 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.321822998
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2395223737
Short name T109
Test name
Test status
Simulation time 50000311 ps
CPU time 0.66 seconds
Started Feb 29 12:47:51 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 202808 kb
Host smart-e2facece-6d0d-4648-84e1-01f783c37d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395223737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2395223737
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3250179581
Short name T1364
Test name
Test status
Simulation time 81308028 ps
CPU time 0.98 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:48:00 PM PST 24
Peak memory 202960 kb
Host smart-8b064fcd-c0eb-4014-b7d5-f5982c916737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250179581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3250179581
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2431966951
Short name T1382
Test name
Test status
Simulation time 29315005 ps
CPU time 1.16 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 203136 kb
Host smart-aa9d1032-424e-4e86-a330-de8cbef58ba2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431966951 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2431966951
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.346345462
Short name T1384
Test name
Test status
Simulation time 59542858 ps
CPU time 0.65 seconds
Started Feb 29 12:47:52 PM PST 24
Finished Feb 29 12:47:53 PM PST 24
Peak memory 202756 kb
Host smart-e331e48c-db01-4237-99cf-d62af08016dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346345462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.346345462
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3727825897
Short name T1370
Test name
Test status
Simulation time 34574241 ps
CPU time 0.79 seconds
Started Feb 29 12:47:58 PM PST 24
Finished Feb 29 12:47:59 PM PST 24
Peak memory 202764 kb
Host smart-a0a8b5df-f48d-4db4-aa8f-a6495b99d1a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727825897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3727825897
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2850248700
Short name T76
Test name
Test status
Simulation time 268050248 ps
CPU time 1.58 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:56 PM PST 24
Peak memory 203064 kb
Host smart-e4bc6431-da6b-4758-8f0b-87d93d9558ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850248700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2850248700
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1070347451
Short name T95
Test name
Test status
Simulation time 335452807 ps
CPU time 1.78 seconds
Started Feb 29 12:47:48 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 203012 kb
Host smart-68f6c54f-137a-4360-8f68-593754f98b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070347451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1070347451
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2733808291
Short name T1352
Test name
Test status
Simulation time 17619602 ps
CPU time 0.74 seconds
Started Feb 29 12:48:31 PM PST 24
Finished Feb 29 12:48:33 PM PST 24
Peak memory 202860 kb
Host smart-292c5a67-aaaf-44eb-8417-70b7ae6fe371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733808291 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2733808291
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2462739081
Short name T120
Test name
Test status
Simulation time 184364589 ps
CPU time 0.63 seconds
Started Feb 29 12:48:04 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 202228 kb
Host smart-4e4ce44c-5358-4a85-a3af-c3b5c6dc057a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462739081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2462739081
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2739846576
Short name T122
Test name
Test status
Simulation time 53548160 ps
CPU time 0.79 seconds
Started Feb 29 12:47:59 PM PST 24
Finished Feb 29 12:48:00 PM PST 24
Peak memory 202756 kb
Host smart-bbbd2ac9-a088-4e5b-931b-c6209469ff50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739846576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.2739846576
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.514661847
Short name T1393
Test name
Test status
Simulation time 432325387 ps
CPU time 1.44 seconds
Started Feb 29 12:47:49 PM PST 24
Finished Feb 29 12:47:50 PM PST 24
Peak memory 202976 kb
Host smart-fe51250d-52e5-49ed-b2a9-520fb073c87d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514661847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.514661847
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2088447039
Short name T69
Test name
Test status
Simulation time 164928308 ps
CPU time 1.94 seconds
Started Feb 29 12:47:54 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 203108 kb
Host smart-48ec28ef-33e0-411d-bdd7-695768ae85c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088447039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2088447039
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.273091654
Short name T1377
Test name
Test status
Simulation time 236888569 ps
CPU time 0.96 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 202880 kb
Host smart-dfcc0664-5b14-4460-a8e0-e44915d3b323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273091654 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.273091654
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2864848264
Short name T115
Test name
Test status
Simulation time 17977721 ps
CPU time 0.64 seconds
Started Feb 29 12:48:07 PM PST 24
Finished Feb 29 12:48:08 PM PST 24
Peak memory 202824 kb
Host smart-f775262f-203f-43e0-964e-ab4b76f470f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864848264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2864848264
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3832340449
Short name T1376
Test name
Test status
Simulation time 41738389 ps
CPU time 0.89 seconds
Started Feb 29 12:48:16 PM PST 24
Finished Feb 29 12:48:18 PM PST 24
Peak memory 202832 kb
Host smart-bd08dc24-e6ed-47bc-bfa9-4486893f50ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832340449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3832340449
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2779850633
Short name T1379
Test name
Test status
Simulation time 376736653 ps
CPU time 2.14 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:06 PM PST 24
Peak memory 202984 kb
Host smart-1519acc6-3052-4281-bdd9-1e0fa0fbefc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779850633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2779850633
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3339608228
Short name T1405
Test name
Test status
Simulation time 88882790 ps
CPU time 1.25 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 203028 kb
Host smart-b67b687a-1793-4de1-b6f4-bb901600caa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339608228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3339608228
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2762975653
Short name T101
Test name
Test status
Simulation time 86834992 ps
CPU time 0.87 seconds
Started Feb 29 12:48:13 PM PST 24
Finished Feb 29 12:48:15 PM PST 24
Peak memory 202888 kb
Host smart-0f0d059b-3ddb-402f-85d5-63b958189997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762975653 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2762975653
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.863675674
Short name T1366
Test name
Test status
Simulation time 41583565 ps
CPU time 0.64 seconds
Started Feb 29 12:48:15 PM PST 24
Finished Feb 29 12:48:16 PM PST 24
Peak memory 202756 kb
Host smart-724c1069-9b33-434b-8ea6-2d217a6801b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863675674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.863675674
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.561317771
Short name T1398
Test name
Test status
Simulation time 123073072 ps
CPU time 1.04 seconds
Started Feb 29 12:48:00 PM PST 24
Finished Feb 29 12:48:01 PM PST 24
Peak memory 202980 kb
Host smart-64e6f4fc-739a-4786-aa0c-d292ca758e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561317771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.561317771
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1742345605
Short name T1391
Test name
Test status
Simulation time 80395532 ps
CPU time 1.91 seconds
Started Feb 29 12:48:03 PM PST 24
Finished Feb 29 12:48:05 PM PST 24
Peak memory 203044 kb
Host smart-c22d2728-c27d-4632-af8b-cda725f08933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742345605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1742345605
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1464195730
Short name T1380
Test name
Test status
Simulation time 219384340 ps
CPU time 1.93 seconds
Started Feb 29 12:47:55 PM PST 24
Finished Feb 29 12:47:57 PM PST 24
Peak memory 203020 kb
Host smart-cead045f-6a41-462e-ab05-520aa5a44deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464195730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1464195730
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3134704168
Short name T655
Test name
Test status
Simulation time 39848073 ps
CPU time 0.59 seconds
Started Feb 29 02:43:02 PM PST 24
Finished Feb 29 02:43:03 PM PST 24
Peak memory 202568 kb
Host smart-38167386-6b13-4a78-9ba1-3073fc05ebc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134704168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3134704168
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.906313157
Short name T1098
Test name
Test status
Simulation time 152128977 ps
CPU time 1.47 seconds
Started Feb 29 02:42:51 PM PST 24
Finished Feb 29 02:42:52 PM PST 24
Peak memory 211964 kb
Host smart-718a354f-81aa-489b-9f4b-73bd320adc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906313157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.906313157
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.508152249
Short name T965
Test name
Test status
Simulation time 8456413999 ps
CPU time 12.07 seconds
Started Feb 29 02:42:53 PM PST 24
Finished Feb 29 02:43:06 PM PST 24
Peak memory 362788 kb
Host smart-5c373b95-7a48-4ab3-beb7-dfb6de1647b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508152249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.508152249
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.1542100788
Short name T763
Test name
Test status
Simulation time 3585606888 ps
CPU time 282.06 seconds
Started Feb 29 02:42:54 PM PST 24
Finished Feb 29 02:47:36 PM PST 24
Peak memory 1004656 kb
Host smart-1bb39bbe-6338-4d60-905d-63c1141e1fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542100788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.1542100788
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2895961837
Short name T414
Test name
Test status
Simulation time 6604074732 ps
CPU time 127.05 seconds
Started Feb 29 02:42:52 PM PST 24
Finished Feb 29 02:45:00 PM PST 24
Peak memory 558588 kb
Host smart-ad94dde1-4f8e-4044-ab67-081685416ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895961837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2895961837
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2271552315
Short name T1125
Test name
Test status
Simulation time 731006597 ps
CPU time 11.29 seconds
Started Feb 29 02:42:53 PM PST 24
Finished Feb 29 02:43:05 PM PST 24
Peak memory 240392 kb
Host smart-397c3002-eac7-4326-a1e4-7ba49d7ad5a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271552315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2271552315
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_override.2243237438
Short name T5
Test name
Test status
Simulation time 47620956 ps
CPU time 0.61 seconds
Started Feb 29 02:42:57 PM PST 24
Finished Feb 29 02:42:58 PM PST 24
Peak memory 202720 kb
Host smart-986aba0c-634d-4682-a89a-8dfe8d66de96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243237438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2243237438
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2487046984
Short name T1134
Test name
Test status
Simulation time 602046952 ps
CPU time 10.4 seconds
Started Feb 29 02:42:54 PM PST 24
Finished Feb 29 02:43:05 PM PST 24
Peak memory 224860 kb
Host smart-c9fb2be6-9e3b-4127-ac18-d0014b4ba1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487046984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2487046984
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_rx_oversample.574006444
Short name T790
Test name
Test status
Simulation time 2430769181 ps
CPU time 129.04 seconds
Started Feb 29 02:42:59 PM PST 24
Finished Feb 29 02:45:08 PM PST 24
Peak memory 360292 kb
Host smart-856d0910-d529-4d0e-8641-3fca8799be57
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574006444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_rx_oversample.574006444
Directory /workspace/0.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3236311227
Short name T512
Test name
Test status
Simulation time 1380541430 ps
CPU time 46.45 seconds
Started Feb 29 02:42:53 PM PST 24
Finished Feb 29 02:43:39 PM PST 24
Peak memory 312892 kb
Host smart-a5446af1-32f7-4581-a257-dc76d3984afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236311227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3236311227
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.4020104623
Short name T721
Test name
Test status
Simulation time 662937604 ps
CPU time 27.12 seconds
Started Feb 29 02:42:53 PM PST 24
Finished Feb 29 02:43:21 PM PST 24
Peak memory 211880 kb
Host smart-47c90d45-bd6f-4f79-94ac-449f76dc8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020104623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.4020104623
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1343165372
Short name T98
Test name
Test status
Simulation time 64811238 ps
CPU time 0.96 seconds
Started Feb 29 02:43:02 PM PST 24
Finished Feb 29 02:43:03 PM PST 24
Peak memory 220704 kb
Host smart-ee060b90-f184-48ac-aec6-18cdd0f033c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343165372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1343165372
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3067713594
Short name T344
Test name
Test status
Simulation time 3389933096 ps
CPU time 3.75 seconds
Started Feb 29 02:43:02 PM PST 24
Finished Feb 29 02:43:07 PM PST 24
Peak memory 203780 kb
Host smart-8e583ad1-14de-4f39-b80e-8b1d3d731810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067713594 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3067713594
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1480550436
Short name T987
Test name
Test status
Simulation time 10142450511 ps
CPU time 26.07 seconds
Started Feb 29 02:43:04 PM PST 24
Finished Feb 29 02:43:30 PM PST 24
Peak memory 310980 kb
Host smart-800362e7-a3a7-47fa-96c8-b7a8696e2d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480550436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1480550436
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.138352327
Short name T958
Test name
Test status
Simulation time 10105458183 ps
CPU time 21.96 seconds
Started Feb 29 02:43:04 PM PST 24
Finished Feb 29 02:43:26 PM PST 24
Peak memory 380660 kb
Host smart-4d93fed4-c15d-4c9d-9e50-3113ef172466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138352327 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.138352327
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3846902018
Short name T1016
Test name
Test status
Simulation time 502580945 ps
CPU time 2.5 seconds
Started Feb 29 02:43:03 PM PST 24
Finished Feb 29 02:43:06 PM PST 24
Peak memory 203612 kb
Host smart-16149f9b-4c7a-466c-bb9f-83ce1b07bce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846902018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3846902018
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1764753294
Short name T1185
Test name
Test status
Simulation time 1309098069 ps
CPU time 5.86 seconds
Started Feb 29 02:43:02 PM PST 24
Finished Feb 29 02:43:09 PM PST 24
Peak memory 203708 kb
Host smart-d005ab15-1940-4527-aea5-e399f5e5a658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764753294 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1764753294
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.436523327
Short name T277
Test name
Test status
Simulation time 4107678885 ps
CPU time 5.86 seconds
Started Feb 29 02:43:10 PM PST 24
Finished Feb 29 02:43:16 PM PST 24
Peak memory 308000 kb
Host smart-81755b40-47e9-4780-8029-a51f9ddcf623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436523327 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.436523327
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_perf.1110235885
Short name T444
Test name
Test status
Simulation time 2037002432 ps
CPU time 3.24 seconds
Started Feb 29 02:43:06 PM PST 24
Finished Feb 29 02:43:10 PM PST 24
Peak memory 203704 kb
Host smart-a8c2637c-d2ff-49b8-b8b0-1043be407d49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110235885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_perf.1110235885
Directory /workspace/0.i2c_target_perf/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3841893825
Short name T315
Test name
Test status
Simulation time 12148333981 ps
CPU time 62.88 seconds
Started Feb 29 02:42:58 PM PST 24
Finished Feb 29 02:44:01 PM PST 24
Peak memory 204184 kb
Host smart-30c0f354-cf43-4bd7-a2f8-42eb0a5a67a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841893825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3841893825
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3432723956
Short name T531
Test name
Test status
Simulation time 26432540031 ps
CPU time 630.85 seconds
Started Feb 29 02:42:54 PM PST 24
Finished Feb 29 02:53:26 PM PST 24
Peak memory 5659824 kb
Host smart-f74f9a89-e8fa-4cf2-8147-3c39e28800f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432723956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3432723956
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1533446099
Short name T1101
Test name
Test status
Simulation time 34949521868 ps
CPU time 3431.69 seconds
Started Feb 29 02:42:52 PM PST 24
Finished Feb 29 03:40:04 PM PST 24
Peak memory 8177132 kb
Host smart-e5cb81fe-4cbb-4bb5-91b3-7666bbdd326b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533446099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1533446099
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.692372543
Short name T922
Test name
Test status
Simulation time 3387606068 ps
CPU time 6.98 seconds
Started Feb 29 02:43:02 PM PST 24
Finished Feb 29 02:43:10 PM PST 24
Peak memory 203648 kb
Host smart-2b34065f-c38a-4710-b9f2-d57399a335ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692372543 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.692372543
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_unexp_stop.3696801736
Short name T524
Test name
Test status
Simulation time 1150524382 ps
CPU time 6.42 seconds
Started Feb 29 02:43:02 PM PST 24
Finished Feb 29 02:43:09 PM PST 24
Peak memory 203752 kb
Host smart-0ffcd9ec-ed69-43f3-899c-ff4a3773db74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696801736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.i2c_target_unexp_stop.3696801736
Directory /workspace/0.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2186524223
Short name T239
Test name
Test status
Simulation time 40936228 ps
CPU time 1.2 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 02:43:15 PM PST 24
Peak memory 211772 kb
Host smart-22aba0de-a0d3-4e27-8828-896c7751df58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186524223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2186524223
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.443524891
Short name T535
Test name
Test status
Simulation time 1909436364 ps
CPU time 8.95 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 02:43:23 PM PST 24
Peak memory 294816 kb
Host smart-ff81bbaa-b75f-474d-a822-a3c356348900
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443524891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.443524891
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1734574748
Short name T858
Test name
Test status
Simulation time 7507612138 ps
CPU time 102.6 seconds
Started Feb 29 02:43:14 PM PST 24
Finished Feb 29 02:44:56 PM PST 24
Peak memory 719444 kb
Host smart-f2de3d4a-1a00-4242-9284-f2aa90fa9a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734574748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1734574748
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2743974685
Short name T16
Test name
Test status
Simulation time 5257735159 ps
CPU time 91.36 seconds
Started Feb 29 02:43:12 PM PST 24
Finished Feb 29 02:44:43 PM PST 24
Peak memory 846244 kb
Host smart-e479ba97-662d-4f16-9ef0-cd69f1da7e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743974685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2743974685
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3409603023
Short name T1150
Test name
Test status
Simulation time 194626885 ps
CPU time 5.66 seconds
Started Feb 29 02:43:12 PM PST 24
Finished Feb 29 02:43:18 PM PST 24
Peak memory 239208 kb
Host smart-13537fe9-cbde-40f1-aafa-5dc24d2e44d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409603023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3409603023
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2752653498
Short name T1161
Test name
Test status
Simulation time 24384708263 ps
CPU time 162.48 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 02:45:56 PM PST 24
Peak memory 1618332 kb
Host smart-4770226d-ce6d-4314-8f84-b1ed3da8c1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752653498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2752653498
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2244467226
Short name T1118
Test name
Test status
Simulation time 19224615415 ps
CPU time 47.96 seconds
Started Feb 29 02:43:25 PM PST 24
Finished Feb 29 02:44:13 PM PST 24
Peak memory 281700 kb
Host smart-edfde6f5-7bd6-4de1-be12-79eb45920844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244467226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2244467226
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3235629055
Short name T1004
Test name
Test status
Simulation time 18310421 ps
CPU time 0.65 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 02:43:14 PM PST 24
Peak memory 202688 kb
Host smart-8837a3a8-3d06-44fb-b605-8a57d9e8eb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235629055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3235629055
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1030894823
Short name T860
Test name
Test status
Simulation time 28719238280 ps
CPU time 514.63 seconds
Started Feb 29 02:43:18 PM PST 24
Finished Feb 29 02:51:53 PM PST 24
Peak memory 203700 kb
Host smart-c12c23fe-da47-44ad-938a-20e47e2f3c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030894823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1030894823
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_rx_oversample.1212668840
Short name T1327
Test name
Test status
Simulation time 2509688550 ps
CPU time 109.27 seconds
Started Feb 29 02:43:18 PM PST 24
Finished Feb 29 02:45:07 PM PST 24
Peak memory 334760 kb
Host smart-13db2930-efe7-4de7-be3e-e7b23d53ecc1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212668840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_rx_oversample.
1212668840
Directory /workspace/1.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3063308885
Short name T1295
Test name
Test status
Simulation time 13119944384 ps
CPU time 158.46 seconds
Started Feb 29 02:43:12 PM PST 24
Finished Feb 29 02:45:51 PM PST 24
Peak memory 255180 kb
Host smart-1e319150-5554-40de-9891-ff853838a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063308885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3063308885
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1711714699
Short name T726
Test name
Test status
Simulation time 2614022497 ps
CPU time 8.48 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 02:43:21 PM PST 24
Peak memory 211908 kb
Host smart-ded905ac-5c15-4f00-ae68-abafba5c5ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711714699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1711714699
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2853411458
Short name T74
Test name
Test status
Simulation time 64128619 ps
CPU time 0.97 seconds
Started Feb 29 02:43:25 PM PST 24
Finished Feb 29 02:43:26 PM PST 24
Peak memory 221756 kb
Host smart-be12b97f-6f43-4e5a-9a98-c039b74204d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853411458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2853411458
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3229888874
Short name T458
Test name
Test status
Simulation time 4094578548 ps
CPU time 4.11 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:43:31 PM PST 24
Peak memory 203676 kb
Host smart-9d15c432-1308-4bd0-8389-eb8b569d7714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229888874 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3229888874
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3123089323
Short name T594
Test name
Test status
Simulation time 10536727945 ps
CPU time 13.93 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:43:40 PM PST 24
Peak memory 318228 kb
Host smart-777aa59b-5f83-4aaf-861f-59c4aa35bcbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123089323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3123089323
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3243403003
Short name T42
Test name
Test status
Simulation time 3788588381 ps
CPU time 4.21 seconds
Started Feb 29 02:43:11 PM PST 24
Finished Feb 29 02:43:16 PM PST 24
Peak memory 203816 kb
Host smart-32c1c557-28da-4275-8e47-870bb7c34fc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243403003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3243403003
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1252929513
Short name T1081
Test name
Test status
Simulation time 1260514503 ps
CPU time 5.74 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 02:43:19 PM PST 24
Peak memory 210380 kb
Host smart-a360f9fe-235a-486e-8138-6337c93c6efe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252929513 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1252929513
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2144102149
Short name T266
Test name
Test status
Simulation time 10000206665 ps
CPU time 142.83 seconds
Started Feb 29 02:43:12 PM PST 24
Finished Feb 29 02:45:36 PM PST 24
Peak memory 2184764 kb
Host smart-328ddc96-a4b4-4638-8d0e-96e55b7c6d37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144102149 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2144102149
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_perf.1595248403
Short name T421
Test name
Test status
Simulation time 336643532 ps
CPU time 2.28 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:43:29 PM PST 24
Peak memory 203612 kb
Host smart-be1e22d2-e148-4294-98cf-3df58298e8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595248403 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_perf.1595248403
Directory /workspace/1.i2c_target_perf/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.1583645054
Short name T273
Test name
Test status
Simulation time 69810731622 ps
CPU time 57.97 seconds
Started Feb 29 02:43:25 PM PST 24
Finished Feb 29 02:44:24 PM PST 24
Peak memory 307392 kb
Host smart-387695fe-8d48-4668-b1da-901c60d329ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583645054 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.i2c_target_stress_all.1583645054
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3596669130
Short name T334
Test name
Test status
Simulation time 76510309805 ps
CPU time 2149.09 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 03:19:03 PM PST 24
Peak memory 8907360 kb
Host smart-c9fa9680-f02d-49c3-95bd-16ff45657634
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596669130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3596669130
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2165056501
Short name T593
Test name
Test status
Simulation time 22298517597 ps
CPU time 1362.1 seconds
Started Feb 29 02:43:11 PM PST 24
Finished Feb 29 03:05:53 PM PST 24
Peak memory 5126220 kb
Host smart-542ec44b-96e1-43e0-9d45-8b110a74551a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165056501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2165056501
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2521751823
Short name T21
Test name
Test status
Simulation time 3725010620 ps
CPU time 7.03 seconds
Started Feb 29 02:43:13 PM PST 24
Finished Feb 29 02:43:21 PM PST 24
Peak memory 203664 kb
Host smart-98ad1dac-0e3c-491a-b34d-50d7af9bc1ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521751823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2521751823
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_unexp_stop.2979334946
Short name T991
Test name
Test status
Simulation time 1549030474 ps
CPU time 6.44 seconds
Started Feb 29 02:43:27 PM PST 24
Finished Feb 29 02:43:34 PM PST 24
Peak memory 203648 kb
Host smart-4b8dcd01-a3b9-49fa-a2a4-eab6e8a0f23b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979334946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.i2c_target_unexp_stop.2979334946
Directory /workspace/1.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/10.i2c_alert_test.2430249551
Short name T1223
Test name
Test status
Simulation time 49909409 ps
CPU time 0.6 seconds
Started Feb 29 02:45:19 PM PST 24
Finished Feb 29 02:45:20 PM PST 24
Peak memory 202556 kb
Host smart-689b9089-9daf-4d42-a0f1-e235489e19ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430249551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2430249551
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1932167196
Short name T801
Test name
Test status
Simulation time 34654822 ps
CPU time 1.1 seconds
Started Feb 29 02:45:21 PM PST 24
Finished Feb 29 02:45:23 PM PST 24
Peak memory 213016 kb
Host smart-fa5aa8a8-7e5c-4075-9e23-b544513fdf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932167196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1932167196
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3354846814
Short name T1336
Test name
Test status
Simulation time 6786778980 ps
CPU time 7.98 seconds
Started Feb 29 02:45:17 PM PST 24
Finished Feb 29 02:45:26 PM PST 24
Peak memory 294604 kb
Host smart-c25a147a-d255-4da1-a5f2-851971ade69f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354846814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3354846814
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.745102877
Short name T892
Test name
Test status
Simulation time 10529608207 ps
CPU time 77.97 seconds
Started Feb 29 02:45:16 PM PST 24
Finished Feb 29 02:46:34 PM PST 24
Peak memory 717028 kb
Host smart-5cf965aa-cd49-4d31-9634-06d3c42b1751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745102877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.745102877
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3467856678
Short name T468
Test name
Test status
Simulation time 4492012723 ps
CPU time 69.14 seconds
Started Feb 29 02:45:20 PM PST 24
Finished Feb 29 02:46:29 PM PST 24
Peak memory 763404 kb
Host smart-63c2035a-6c06-474f-91ed-83a0df14b04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467856678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3467856678
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3277581547
Short name T990
Test name
Test status
Simulation time 1067511297 ps
CPU time 14.91 seconds
Started Feb 29 02:45:18 PM PST 24
Finished Feb 29 02:45:33 PM PST 24
Peak memory 260476 kb
Host smart-d00e4cf9-2bc0-4de8-bd8d-782b74bb55e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277581547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3277581547
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2622525659
Short name T222
Test name
Test status
Simulation time 15405387184 ps
CPU time 215.6 seconds
Started Feb 29 02:45:18 PM PST 24
Finished Feb 29 02:48:53 PM PST 24
Peak memory 876136 kb
Host smart-4e41034b-bd26-4c4b-b698-7a06a4668b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622525659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2622525659
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.480467177
Short name T961
Test name
Test status
Simulation time 13036984912 ps
CPU time 89.79 seconds
Started Feb 29 02:45:26 PM PST 24
Finished Feb 29 02:46:56 PM PST 24
Peak memory 317152 kb
Host smart-738b41d7-8852-4d8b-bcff-9ddd3cda73c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480467177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.480467177
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3635666684
Short name T1132
Test name
Test status
Simulation time 35402032 ps
CPU time 0.63 seconds
Started Feb 29 02:45:17 PM PST 24
Finished Feb 29 02:45:18 PM PST 24
Peak memory 202728 kb
Host smart-2886bdbf-47e0-43d4-b8c3-ead3c051e7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635666684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3635666684
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1241956956
Short name T608
Test name
Test status
Simulation time 2779969252 ps
CPU time 54.53 seconds
Started Feb 29 02:45:17 PM PST 24
Finished Feb 29 02:46:12 PM PST 24
Peak memory 309480 kb
Host smart-cc164902-25ed-4f43-a934-d7c4627c7e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241956956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1241956956
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_rx_oversample.2157359803
Short name T472
Test name
Test status
Simulation time 4999390301 ps
CPU time 217.29 seconds
Started Feb 29 02:45:15 PM PST 24
Finished Feb 29 02:48:52 PM PST 24
Peak memory 289688 kb
Host smart-7bd627ae-7e4c-4759-8581-00f9cc986b31
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157359803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_rx_oversample
.2157359803
Directory /workspace/10.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.300018244
Short name T643
Test name
Test status
Simulation time 2346811194 ps
CPU time 133.53 seconds
Started Feb 29 02:45:17 PM PST 24
Finished Feb 29 02:47:30 PM PST 24
Peak memory 246128 kb
Host smart-0f315fb9-751c-4e7e-80a2-4fdcb5f35436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300018244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.300018244
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3703872754
Short name T920
Test name
Test status
Simulation time 2000337597 ps
CPU time 28.92 seconds
Started Feb 29 02:45:18 PM PST 24
Finished Feb 29 02:45:47 PM PST 24
Peak memory 211800 kb
Host smart-660a619a-474e-4ba2-b542-a45f980e5958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703872754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3703872754
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3712594532
Short name T794
Test name
Test status
Simulation time 962022798 ps
CPU time 4.2 seconds
Started Feb 29 02:45:22 PM PST 24
Finished Feb 29 02:45:26 PM PST 24
Peak memory 203624 kb
Host smart-cba93cb8-5ff5-4bbd-95a3-966934decd8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712594532 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3712594532
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2807498940
Short name T1014
Test name
Test status
Simulation time 10070701135 ps
CPU time 54.67 seconds
Started Feb 29 02:45:20 PM PST 24
Finished Feb 29 02:46:15 PM PST 24
Peak memory 457392 kb
Host smart-9d8408ec-be23-4c1f-99f8-c896aea3cece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807498940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2807498940
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1596167431
Short name T613
Test name
Test status
Simulation time 10739139010 ps
CPU time 11.59 seconds
Started Feb 29 02:45:21 PM PST 24
Finished Feb 29 02:45:33 PM PST 24
Peak memory 301808 kb
Host smart-8ec80d69-83a4-477b-9375-6881baa65b05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596167431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1596167431
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3351760148
Short name T1011
Test name
Test status
Simulation time 887301908 ps
CPU time 2.28 seconds
Started Feb 29 02:45:20 PM PST 24
Finished Feb 29 02:45:22 PM PST 24
Peak memory 203696 kb
Host smart-b8615cb6-861d-4426-9f38-168aa30ff580
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351760148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3351760148
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1637050584
Short name T394
Test name
Test status
Simulation time 1196068005 ps
CPU time 3.19 seconds
Started Feb 29 02:45:18 PM PST 24
Finished Feb 29 02:45:21 PM PST 24
Peak memory 203636 kb
Host smart-7b22651d-7ca7-48f4-b9d5-fe53f2d53c78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637050584 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1637050584
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.3221252565
Short name T955
Test name
Test status
Simulation time 7841410005 ps
CPU time 86.88 seconds
Started Feb 29 02:45:18 PM PST 24
Finished Feb 29 02:46:45 PM PST 24
Peak memory 1705856 kb
Host smart-c5febe1c-2109-40e2-936e-8d07548224c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221252565 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3221252565
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_perf.2932756938
Short name T384
Test name
Test status
Simulation time 1959558470 ps
CPU time 3.41 seconds
Started Feb 29 02:45:21 PM PST 24
Finished Feb 29 02:45:25 PM PST 24
Peak memory 203724 kb
Host smart-56b84ee2-3c66-434e-b1cd-af1e14b53035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932756938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_perf.2932756938
Directory /workspace/10.i2c_target_perf/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.2485827385
Short name T833
Test name
Test status
Simulation time 4957449056 ps
CPU time 22.52 seconds
Started Feb 29 02:45:21 PM PST 24
Finished Feb 29 02:45:43 PM PST 24
Peak memory 236068 kb
Host smart-63b20170-75c3-4680-a0e5-a5aed18d55ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485827385 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.2485827385
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.18344718
Short name T736
Test name
Test status
Simulation time 9368073999 ps
CPU time 10.31 seconds
Started Feb 29 02:45:19 PM PST 24
Finished Feb 29 02:45:29 PM PST 24
Peak memory 426728 kb
Host smart-f6ac8b6d-9edb-4eff-b12a-dd8ce03167d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18344718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stress_wr.18344718
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2922331476
Short name T307
Test name
Test status
Simulation time 6116290147 ps
CPU time 458.92 seconds
Started Feb 29 02:45:18 PM PST 24
Finished Feb 29 02:52:58 PM PST 24
Peak memory 1641268 kb
Host smart-3f1ee56c-1394-497f-92dc-6ff7e91d573e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922331476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2922331476
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.6403594
Short name T793
Test name
Test status
Simulation time 1650135018 ps
CPU time 7.69 seconds
Started Feb 29 02:45:21 PM PST 24
Finished Feb 29 02:45:29 PM PST 24
Peak memory 210016 kb
Host smart-f54ca64a-0ce5-424e-822c-17f578c91d4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6403594 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_timeout.6403594
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_unexp_stop.1161087129
Short name T1044
Test name
Test status
Simulation time 1934817338 ps
CPU time 8.8 seconds
Started Feb 29 02:45:19 PM PST 24
Finished Feb 29 02:45:28 PM PST 24
Peak memory 215324 kb
Host smart-34b98665-7233-4efb-81dd-343119b79abe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161087129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.i2c_target_unexp_stop.1161087129
Directory /workspace/10.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/11.i2c_alert_test.410623071
Short name T1292
Test name
Test status
Simulation time 31490803 ps
CPU time 0.57 seconds
Started Feb 29 02:45:28 PM PST 24
Finished Feb 29 02:45:29 PM PST 24
Peak memory 202520 kb
Host smart-0b427e4e-7ba5-45f2-8b2f-9cf069bdbfaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410623071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.410623071
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2504716705
Short name T1232
Test name
Test status
Simulation time 43132955 ps
CPU time 1.14 seconds
Started Feb 29 02:45:25 PM PST 24
Finished Feb 29 02:45:27 PM PST 24
Peak memory 213216 kb
Host smart-61751b33-ea4e-4b58-8294-6637e846e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504716705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2504716705
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1935986336
Short name T1162
Test name
Test status
Simulation time 2035265649 ps
CPU time 10.82 seconds
Started Feb 29 02:45:20 PM PST 24
Finished Feb 29 02:45:31 PM PST 24
Peak memory 320408 kb
Host smart-93dbd0f7-9f93-4ffc-8e50-8ef667b69f77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935986336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1935986336
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1501925167
Short name T560
Test name
Test status
Simulation time 2347134303 ps
CPU time 71.78 seconds
Started Feb 29 02:45:24 PM PST 24
Finished Feb 29 02:46:36 PM PST 24
Peak memory 782280 kb
Host smart-0f00a81b-68df-4b85-bc3b-f90640b6bcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501925167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1501925167
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1647391650
Short name T1329
Test name
Test status
Simulation time 7195485148 ps
CPU time 99.16 seconds
Started Feb 29 02:45:20 PM PST 24
Finished Feb 29 02:46:59 PM PST 24
Peak memory 337064 kb
Host smart-42a61006-81f2-49b5-9bbe-84b9c1d16cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647391650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1647391650
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2015853222
Short name T791
Test name
Test status
Simulation time 271374821 ps
CPU time 4.27 seconds
Started Feb 29 02:45:22 PM PST 24
Finished Feb 29 02:45:26 PM PST 24
Peak memory 225852 kb
Host smart-7964cfb4-1fbb-4fad-b414-0ffebda4810e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015853222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2015853222
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2780781081
Short name T367
Test name
Test status
Simulation time 5935478565 ps
CPU time 201.85 seconds
Started Feb 29 02:45:20 PM PST 24
Finished Feb 29 02:48:42 PM PST 24
Peak memory 1649932 kb
Host smart-b25312b1-9431-4e4a-a6b9-916d0aec8964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780781081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2780781081
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.1556973851
Short name T1066
Test name
Test status
Simulation time 2329087424 ps
CPU time 156.68 seconds
Started Feb 29 02:45:27 PM PST 24
Finished Feb 29 02:48:04 PM PST 24
Peak memory 315288 kb
Host smart-652a44ee-c562-4524-bbe6-09ffdf8ff980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556973851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.1556973851
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.3713293789
Short name T1303
Test name
Test status
Simulation time 17893912 ps
CPU time 0.62 seconds
Started Feb 29 02:45:21 PM PST 24
Finished Feb 29 02:45:22 PM PST 24
Peak memory 202780 kb
Host smart-900a9285-4e11-42d2-8cab-02304825c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713293789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3713293789
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_rx_oversample.633587113
Short name T814
Test name
Test status
Simulation time 2302576108 ps
CPU time 78.64 seconds
Started Feb 29 02:45:25 PM PST 24
Finished Feb 29 02:46:44 PM PST 24
Peak memory 293144 kb
Host smart-63d2ab2e-67ca-4d4e-816c-36815dfe4124
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633587113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_rx_oversample.
633587113
Directory /workspace/11.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.631241734
Short name T441
Test name
Test status
Simulation time 2080900744 ps
CPU time 64.81 seconds
Started Feb 29 02:45:27 PM PST 24
Finished Feb 29 02:46:32 PM PST 24
Peak memory 319756 kb
Host smart-c1751a84-ba3f-49e2-864d-09e0b447f44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631241734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.631241734
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1769947322
Short name T166
Test name
Test status
Simulation time 15626824476 ps
CPU time 2500.77 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 03:27:12 PM PST 24
Peak memory 4087304 kb
Host smart-7933a139-527c-4396-aeb5-c8dea4427e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769947322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1769947322
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2699413562
Short name T65
Test name
Test status
Simulation time 10063566457 ps
CPU time 14.43 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:45:46 PM PST 24
Peak memory 280424 kb
Host smart-def9b4c8-f527-4bca-a236-cdd94246dcb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699413562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2699413562
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.757269059
Short name T583
Test name
Test status
Simulation time 11354007029 ps
CPU time 6.45 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:45:36 PM PST 24
Peak memory 235912 kb
Host smart-125bb424-8b78-4ccb-b76f-8cf1978fb8b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757269059 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.757269059
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3083092031
Short name T1008
Test name
Test status
Simulation time 512289914 ps
CPU time 2.43 seconds
Started Feb 29 02:45:34 PM PST 24
Finished Feb 29 02:45:37 PM PST 24
Peak memory 203644 kb
Host smart-0c717992-1f93-4694-a861-0c04126fe45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083092031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3083092031
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.13021607
Short name T1240
Test name
Test status
Simulation time 1784936071 ps
CPU time 7.04 seconds
Started Feb 29 02:45:28 PM PST 24
Finished Feb 29 02:45:35 PM PST 24
Peak memory 209768 kb
Host smart-d3731d15-7b99-4b5f-8537-58c4d45761f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021607 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.13021607
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.4245821204
Short name T714
Test name
Test status
Simulation time 8412099229 ps
CPU time 115.3 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:47:26 PM PST 24
Peak memory 1907688 kb
Host smart-c1187fa0-c84a-4d6f-9136-0140c99df6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245821204 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.4245821204
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_perf.670836624
Short name T252
Test name
Test status
Simulation time 2217648924 ps
CPU time 2.9 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:45:33 PM PST 24
Peak memory 203696 kb
Host smart-58adb85d-c434-4155-a389-3fec585d5446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670836624 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_perf.670836624
Directory /workspace/11.i2c_target_perf/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.3308758401
Short name T579
Test name
Test status
Simulation time 39891450705 ps
CPU time 43.36 seconds
Started Feb 29 02:45:29 PM PST 24
Finished Feb 29 02:46:13 PM PST 24
Peak memory 221596 kb
Host smart-5edf87bd-2d5a-43ab-801c-10d7cfc46673
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308758401 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.i2c_target_stress_all.3308758401
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.4206755724
Short name T491
Test name
Test status
Simulation time 1852931627 ps
CPU time 16.01 seconds
Started Feb 29 02:45:26 PM PST 24
Finished Feb 29 02:45:43 PM PST 24
Peak memory 203832 kb
Host smart-da4a8ceb-4f47-4d5a-8e78-af6c1ba48161
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206755724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.4206755724
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1306385207
Short name T1315
Test name
Test status
Simulation time 9507718295 ps
CPU time 233.84 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:49:24 PM PST 24
Peak memory 2112908 kb
Host smart-c62beff1-ffd6-4922-a1dc-80151bd97718
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306385207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1306385207
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.4032415895
Short name T1278
Test name
Test status
Simulation time 1531127391 ps
CPU time 6.69 seconds
Started Feb 29 02:45:32 PM PST 24
Finished Feb 29 02:45:39 PM PST 24
Peak memory 203548 kb
Host smart-b66db50b-1068-44e2-807f-61f870efb371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032415895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.4032415895
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_unexp_stop.2685208902
Short name T1135
Test name
Test status
Simulation time 1430386957 ps
CPU time 6.7 seconds
Started Feb 29 02:45:26 PM PST 24
Finished Feb 29 02:45:33 PM PST 24
Peak memory 203636 kb
Host smart-341508df-805f-4ace-b811-bd1f8aca7356
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685208902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.i2c_target_unexp_stop.2685208902
Directory /workspace/11.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/12.i2c_alert_test.1767076118
Short name T83
Test name
Test status
Simulation time 25607119 ps
CPU time 0.63 seconds
Started Feb 29 02:45:42 PM PST 24
Finished Feb 29 02:45:43 PM PST 24
Peak memory 202472 kb
Host smart-b2ff5c8c-ad9b-4f3c-8017-1053efed9478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767076118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1767076118
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2579768591
Short name T37
Test name
Test status
Simulation time 82523927 ps
CPU time 1.93 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:45:32 PM PST 24
Peak memory 211852 kb
Host smart-8e085b8f-b9ba-41a2-9af1-548020098377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579768591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2579768591
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.979987304
Short name T905
Test name
Test status
Simulation time 492959569 ps
CPU time 24.7 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:45:56 PM PST 24
Peak memory 284080 kb
Host smart-a5e13b1f-6016-4882-85b9-f0c504446137
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979987304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.979987304
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1944342037
Short name T288
Test name
Test status
Simulation time 3930813617 ps
CPU time 128.54 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:47:40 PM PST 24
Peak memory 1034280 kb
Host smart-1c7d4d6f-011d-4e7a-8b61-91bcac7dcfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944342037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1944342037
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.420927434
Short name T1302
Test name
Test status
Simulation time 50995905706 ps
CPU time 102.38 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:47:13 PM PST 24
Peak memory 881772 kb
Host smart-87c72d9e-6bdc-437a-8724-14ed15d7f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420927434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.420927434
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.879909089
Short name T459
Test name
Test status
Simulation time 4175500004 ps
CPU time 132.17 seconds
Started Feb 29 02:45:26 PM PST 24
Finished Feb 29 02:47:38 PM PST 24
Peak memory 1242336 kb
Host smart-e5dbadab-271f-428c-9d41-4c6e588c194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879909089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.879909089
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2852388052
Short name T511
Test name
Test status
Simulation time 9938135676 ps
CPU time 97.48 seconds
Started Feb 29 02:45:41 PM PST 24
Finished Feb 29 02:47:19 PM PST 24
Peak memory 375260 kb
Host smart-538bfc0b-75e4-4b11-bf44-41c2b479c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852388052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2852388052
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.2411647443
Short name T432
Test name
Test status
Simulation time 26915299 ps
CPU time 0.63 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:45:31 PM PST 24
Peak memory 202692 kb
Host smart-7939845a-061e-40c9-9469-4568bec45a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411647443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2411647443
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3999319336
Short name T366
Test name
Test status
Simulation time 8224759043 ps
CPU time 116.98 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:47:28 PM PST 24
Peak memory 402528 kb
Host smart-19e2932a-5487-4515-a731-a141dd72b943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999319336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3999319336
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_rx_oversample.1376986690
Short name T542
Test name
Test status
Simulation time 3118673801 ps
CPU time 162.77 seconds
Started Feb 29 02:45:27 PM PST 24
Finished Feb 29 02:48:09 PM PST 24
Peak memory 365772 kb
Host smart-e5cc0348-8ab1-492a-a080-8a1544469588
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376986690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_rx_oversample
.1376986690
Directory /workspace/12.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.358564634
Short name T1210
Test name
Test status
Simulation time 8670289801 ps
CPU time 55.1 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:46:26 PM PST 24
Peak memory 263844 kb
Host smart-d06d652d-eed2-4a86-9780-bd5bc758a425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358564634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.358564634
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2450045662
Short name T548
Test name
Test status
Simulation time 3444374574 ps
CPU time 26 seconds
Started Feb 29 02:45:27 PM PST 24
Finished Feb 29 02:45:54 PM PST 24
Peak memory 211924 kb
Host smart-e8deaa65-dc9e-43c2-b15a-48db66e02404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450045662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2450045662
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1825855779
Short name T1078
Test name
Test status
Simulation time 2178409296 ps
CPU time 4.34 seconds
Started Feb 29 02:45:34 PM PST 24
Finished Feb 29 02:45:38 PM PST 24
Peak memory 203764 kb
Host smart-9cbf9b84-4c97-4ed1-9251-48577eb10653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825855779 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1825855779
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2297190567
Short name T680
Test name
Test status
Simulation time 10512954644 ps
CPU time 13.72 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:45:44 PM PST 24
Peak memory 312296 kb
Host smart-d89c90d5-624b-4cb6-920e-6894ad976dba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297190567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2297190567
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1207389404
Short name T295
Test name
Test status
Simulation time 10024785642 ps
CPU time 55.6 seconds
Started Feb 29 02:45:32 PM PST 24
Finished Feb 29 02:46:28 PM PST 24
Peak memory 539960 kb
Host smart-eb0021e1-53a6-465c-8d25-0219aa34cdf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207389404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1207389404
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.4148164165
Short name T51
Test name
Test status
Simulation time 2591818182 ps
CPU time 3.03 seconds
Started Feb 29 02:45:34 PM PST 24
Finished Feb 29 02:45:37 PM PST 24
Peak memory 203708 kb
Host smart-207e282e-5bc1-4057-aa74-79a33bf60953
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148164165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.4148164165
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1415938000
Short name T900
Test name
Test status
Simulation time 855054629 ps
CPU time 3.94 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:45:35 PM PST 24
Peak memory 203632 kb
Host smart-59b1a1a7-7bb9-4dd7-bbf2-758d74f83ab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415938000 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1415938000
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2050914370
Short name T628
Test name
Test status
Simulation time 4998358717 ps
CPU time 39.95 seconds
Started Feb 29 02:45:29 PM PST 24
Finished Feb 29 02:46:09 PM PST 24
Peak memory 972316 kb
Host smart-1a369362-ab52-4c10-bcb9-1148f9a97d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050914370 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2050914370
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_perf.3132680508
Short name T966
Test name
Test status
Simulation time 3303556345 ps
CPU time 3.52 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:45:33 PM PST 24
Peak memory 203676 kb
Host smart-f9b27788-a32a-4e4b-bacc-9a6b86efe0cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132680508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_perf.3132680508
Directory /workspace/12.i2c_target_perf/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2071423792
Short name T448
Test name
Test status
Simulation time 1949414216 ps
CPU time 47.52 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:46:17 PM PST 24
Peak memory 203692 kb
Host smart-820102e3-a4f2-4a0a-ab07-920ceb24c883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071423792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2071423792
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.614817192
Short name T528
Test name
Test status
Simulation time 7916742220 ps
CPU time 8.37 seconds
Started Feb 29 02:45:26 PM PST 24
Finished Feb 29 02:45:34 PM PST 24
Peak memory 362592 kb
Host smart-6257ab18-d6ed-45b6-bb61-a88ce194ca22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614817192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_wr.614817192
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1792501058
Short name T438
Test name
Test status
Simulation time 27793082464 ps
CPU time 486.09 seconds
Started Feb 29 02:45:30 PM PST 24
Finished Feb 29 02:53:37 PM PST 24
Peak memory 2747484 kb
Host smart-73a3f827-582f-4dd5-916d-0eab10fc1588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792501058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1792501058
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1357044621
Short name T1030
Test name
Test status
Simulation time 7060855510 ps
CPU time 7.45 seconds
Started Feb 29 02:45:31 PM PST 24
Finished Feb 29 02:45:39 PM PST 24
Peak memory 203620 kb
Host smart-d4ad259f-c200-41cb-8947-30fc4124dbfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357044621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1357044621
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.3649153635
Short name T1333
Test name
Test status
Simulation time 5578147288 ps
CPU time 6.49 seconds
Started Feb 29 02:45:32 PM PST 24
Finished Feb 29 02:45:39 PM PST 24
Peak memory 203704 kb
Host smart-7b21bd45-504c-4999-a45e-bf305ee33463
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649153635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.3649153635
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.1711467432
Short name T82
Test name
Test status
Simulation time 16875120 ps
CPU time 0.61 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:45:55 PM PST 24
Peak memory 202520 kb
Host smart-89618dc1-bc5b-4953-8f4d-09a9ef77e332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711467432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1711467432
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.1164800511
Short name T504
Test name
Test status
Simulation time 166869569 ps
CPU time 1.31 seconds
Started Feb 29 02:45:41 PM PST 24
Finished Feb 29 02:45:42 PM PST 24
Peak memory 211792 kb
Host smart-c2b107ac-7f58-48fa-a83b-c5a6e13964c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164800511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1164800511
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2741692821
Short name T1167
Test name
Test status
Simulation time 579154508 ps
CPU time 10.94 seconds
Started Feb 29 02:45:42 PM PST 24
Finished Feb 29 02:45:54 PM PST 24
Peak memory 336528 kb
Host smart-7806acf3-d774-4685-b59f-48135827ac58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741692821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2741692821
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3533459681
Short name T1228
Test name
Test status
Simulation time 8228393172 ps
CPU time 156.97 seconds
Started Feb 29 02:45:45 PM PST 24
Finished Feb 29 02:48:22 PM PST 24
Peak memory 1063080 kb
Host smart-34aaca7f-38a2-4b55-a990-24a042b720c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533459681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3533459681
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.4030170439
Short name T666
Test name
Test status
Simulation time 6696933232 ps
CPU time 116.03 seconds
Started Feb 29 02:45:45 PM PST 24
Finished Feb 29 02:47:42 PM PST 24
Peak memory 865072 kb
Host smart-a9d32948-d108-461c-a8e7-4c7ddce35a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030170439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.4030170439
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3474677009
Short name T518
Test name
Test status
Simulation time 467364574 ps
CPU time 6.78 seconds
Started Feb 29 02:45:43 PM PST 24
Finished Feb 29 02:45:50 PM PST 24
Peak memory 253772 kb
Host smart-0cd9f8c0-66d3-4798-8dcc-a303da04fdee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474677009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3474677009
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1344198534
Short name T129
Test name
Test status
Simulation time 5948731678 ps
CPU time 144.55 seconds
Started Feb 29 02:45:42 PM PST 24
Finished Feb 29 02:48:07 PM PST 24
Peak memory 1551828 kb
Host smart-27b03372-352d-4bec-b602-1d5873706ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344198534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1344198534
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1598855411
Short name T580
Test name
Test status
Simulation time 5720480061 ps
CPU time 154.48 seconds
Started Feb 29 02:45:41 PM PST 24
Finished Feb 29 02:48:16 PM PST 24
Peak memory 255140 kb
Host smart-5b72f7c4-0bb2-4969-9d85-a49729135440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598855411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1598855411
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1524023827
Short name T466
Test name
Test status
Simulation time 18621438 ps
CPU time 0.65 seconds
Started Feb 29 02:45:42 PM PST 24
Finished Feb 29 02:45:43 PM PST 24
Peak memory 202704 kb
Host smart-d3be221b-d0a5-44b7-8fd2-29f3f7194cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524023827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1524023827
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3192160194
Short name T485
Test name
Test status
Simulation time 13831691318 ps
CPU time 212.7 seconds
Started Feb 29 02:45:43 PM PST 24
Finished Feb 29 02:49:15 PM PST 24
Peak memory 297604 kb
Host smart-54a3e819-b920-4e17-bb30-325c1662a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192160194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3192160194
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1763103869
Short name T952
Test name
Test status
Simulation time 5224153389 ps
CPU time 31.75 seconds
Started Feb 29 02:45:45 PM PST 24
Finished Feb 29 02:46:17 PM PST 24
Peak memory 261024 kb
Host smart-01ef0cee-8d41-42e9-af6f-408233fd68bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763103869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1763103869
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.60251514
Short name T1286
Test name
Test status
Simulation time 3770299126 ps
CPU time 23.98 seconds
Started Feb 29 02:45:45 PM PST 24
Finished Feb 29 02:46:09 PM PST 24
Peak memory 211856 kb
Host smart-de8bb790-8863-42ab-b612-6b588237806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60251514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.60251514
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3123785714
Short name T1114
Test name
Test status
Simulation time 794553462 ps
CPU time 3.62 seconds
Started Feb 29 02:45:46 PM PST 24
Finished Feb 29 02:45:50 PM PST 24
Peak memory 203772 kb
Host smart-01663481-815e-44a2-bb6f-bf497fdc884a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123785714 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3123785714
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3523432762
Short name T1326
Test name
Test status
Simulation time 10170781334 ps
CPU time 14.79 seconds
Started Feb 29 02:45:47 PM PST 24
Finished Feb 29 02:46:02 PM PST 24
Peak memory 280424 kb
Host smart-b1c42693-7103-4a9e-b303-a382eb23eedd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523432762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3523432762
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2572721525
Short name T575
Test name
Test status
Simulation time 10035667626 ps
CPU time 59.23 seconds
Started Feb 29 02:45:42 PM PST 24
Finished Feb 29 02:46:42 PM PST 24
Peak memory 524036 kb
Host smart-b61d4117-c0b1-4286-915d-c77a0f7dbd4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572721525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2572721525
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.355780388
Short name T1206
Test name
Test status
Simulation time 278126162 ps
CPU time 2.05 seconds
Started Feb 29 02:45:46 PM PST 24
Finished Feb 29 02:45:48 PM PST 24
Peak memory 203628 kb
Host smart-9fd0ba4f-3cd4-43de-a4ce-afb27b20aba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355780388 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_hrst.355780388
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.746289453
Short name T927
Test name
Test status
Simulation time 2453964022 ps
CPU time 5.21 seconds
Started Feb 29 02:45:43 PM PST 24
Finished Feb 29 02:45:48 PM PST 24
Peak memory 204916 kb
Host smart-b49d7ed2-f373-4aa3-a68b-0857bff35d55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746289453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.746289453
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2697409263
Short name T617
Test name
Test status
Simulation time 9538808070 ps
CPU time 131.03 seconds
Started Feb 29 02:45:44 PM PST 24
Finished Feb 29 02:47:56 PM PST 24
Peak memory 2064000 kb
Host smart-3b56aaf7-6757-434e-97e0-a15af90c0f26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697409263 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2697409263
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_perf.873690923
Short name T780
Test name
Test status
Simulation time 3328642900 ps
CPU time 5.09 seconds
Started Feb 29 02:45:43 PM PST 24
Finished Feb 29 02:45:48 PM PST 24
Peak memory 213452 kb
Host smart-abfbfc4c-73dc-4f15-a02a-d99e032bcf4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873690923 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.i2c_target_perf.873690923
Directory /workspace/13.i2c_target_perf/latest

Test location /workspace/coverage/default/13.i2c_target_stress_all.3635367557
Short name T514
Test name
Test status
Simulation time 36004277578 ps
CPU time 115.81 seconds
Started Feb 29 02:45:45 PM PST 24
Finished Feb 29 02:47:41 PM PST 24
Peak memory 965592 kb
Host smart-e129f669-bfa2-4114-994e-eda946612da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635367557 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.i2c_target_stress_all.3635367557
Directory /workspace/13.i2c_target_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2104653814
Short name T703
Test name
Test status
Simulation time 31774687787 ps
CPU time 315.55 seconds
Started Feb 29 02:45:44 PM PST 24
Finished Feb 29 02:51:00 PM PST 24
Peak memory 3443056 kb
Host smart-1d441f47-5213-4126-859c-300255799288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104653814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2104653814
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.334934041
Short name T764
Test name
Test status
Simulation time 38321356084 ps
CPU time 3426.54 seconds
Started Feb 29 02:45:45 PM PST 24
Finished Feb 29 03:42:52 PM PST 24
Peak memory 8378064 kb
Host smart-db7889bc-65b5-4b83-b294-3495439304d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334934041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.334934041
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.4056001108
Short name T498
Test name
Test status
Simulation time 1818325417 ps
CPU time 7.29 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:46:03 PM PST 24
Peak memory 203684 kb
Host smart-2e15ac72-acee-4167-b732-5de12a8d5672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056001108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.4056001108
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.2868881980
Short name T975
Test name
Test status
Simulation time 1379356025 ps
CPU time 5.83 seconds
Started Feb 29 02:45:44 PM PST 24
Finished Feb 29 02:45:49 PM PST 24
Peak memory 203628 kb
Host smart-740d199d-f26e-43b3-bc2c-cc9bfe422d74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868881980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.2868881980
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2939839161
Short name T712
Test name
Test status
Simulation time 18065444 ps
CPU time 0.64 seconds
Started Feb 29 02:46:00 PM PST 24
Finished Feb 29 02:46:00 PM PST 24
Peak memory 202520 kb
Host smart-a0e42d31-cee3-4743-8b97-03afbd26e19d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939839161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2939839161
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.535494251
Short name T705
Test name
Test status
Simulation time 51063595 ps
CPU time 1.58 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:45:57 PM PST 24
Peak memory 211896 kb
Host smart-11ffa5c0-9409-45b4-9bf3-3591ca547bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535494251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.535494251
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.921468276
Short name T663
Test name
Test status
Simulation time 2681384114 ps
CPU time 14.66 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:46:10 PM PST 24
Peak memory 352616 kb
Host smart-012be245-eecc-4db7-9d9d-63a84c0d5b04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921468276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.921468276
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1266010218
Short name T971
Test name
Test status
Simulation time 4654394597 ps
CPU time 110.68 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:47:48 PM PST 24
Peak memory 981724 kb
Host smart-a7e98d50-2687-4a68-b3c5-604708ce6567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266010218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1266010218
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3887035681
Short name T956
Test name
Test status
Simulation time 10837684999 ps
CPU time 216.96 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:49:35 PM PST 24
Peak memory 852416 kb
Host smart-1d3b3841-3096-4172-81ae-cf577739208c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887035681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3887035681
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.729985632
Short name T849
Test name
Test status
Simulation time 689864938 ps
CPU time 5.36 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:46:02 PM PST 24
Peak memory 236212 kb
Host smart-63023024-dbbc-4fd1-8e04-d084c56d9d92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729985632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
729985632
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1518291791
Short name T132
Test name
Test status
Simulation time 22046439566 ps
CPU time 164.91 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:48:42 PM PST 24
Peak memory 1605308 kb
Host smart-2371682b-c71d-43a5-ac72-915d37101a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518291791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1518291791
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.649679984
Short name T261
Test name
Test status
Simulation time 5622593777 ps
CPU time 61.51 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:59 PM PST 24
Peak memory 299496 kb
Host smart-894e5c18-fac0-4ed5-86bc-1b459b35b8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649679984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.649679984
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3618184589
Short name T167
Test name
Test status
Simulation time 753758119 ps
CPU time 4.28 seconds
Started Feb 29 02:45:56 PM PST 24
Finished Feb 29 02:46:00 PM PST 24
Peak memory 220048 kb
Host smart-51d359ee-c700-4ef9-b4e6-3f685948f072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618184589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3618184589
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_rx_oversample.205019733
Short name T1172
Test name
Test status
Simulation time 11754348215 ps
CPU time 153.84 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:48:32 PM PST 24
Peak memory 368532 kb
Host smart-40e521b6-a1fb-45dd-82f4-2c6dcc915c46
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205019733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_rx_oversample.
205019733
Directory /workspace/14.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3385228798
Short name T739
Test name
Test status
Simulation time 1296728714 ps
CPU time 21.36 seconds
Started Feb 29 02:45:54 PM PST 24
Finished Feb 29 02:46:15 PM PST 24
Peak memory 231676 kb
Host smart-af88104d-36b6-4cf8-9e44-24f77aa0247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385228798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3385228798
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2052220760
Short name T165
Test name
Test status
Simulation time 19906653279 ps
CPU time 1017.6 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 03:02:55 PM PST 24
Peak memory 3416108 kb
Host smart-9d52fecf-4f98-412d-9b50-bbc9f24e5a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052220760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2052220760
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2173610116
Short name T611
Test name
Test status
Simulation time 1936841640 ps
CPU time 17.22 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:46:14 PM PST 24
Peak memory 219304 kb
Host smart-1edd962f-a9b3-4015-bbd3-746d65707db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173610116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2173610116
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2926523496
Short name T1195
Test name
Test status
Simulation time 1012149661 ps
CPU time 4.37 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:03 PM PST 24
Peak memory 203648 kb
Host smart-09e6b21e-af26-44b6-9f29-9ae3f7134efe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926523496 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2926523496
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.824086255
Short name T902
Test name
Test status
Simulation time 10112306022 ps
CPU time 33.6 seconds
Started Feb 29 02:45:54 PM PST 24
Finished Feb 29 02:46:28 PM PST 24
Peak memory 386468 kb
Host smart-7392c425-a916-4a57-8357-29dafe260608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824086255 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.824086255
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3891544598
Short name T972
Test name
Test status
Simulation time 10042138380 ps
CPU time 71.36 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:47:06 PM PST 24
Peak memory 624432 kb
Host smart-3ef9f887-1c5f-41bc-9891-040fff70cbae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891544598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3891544598
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.4104341306
Short name T497
Test name
Test status
Simulation time 403047754 ps
CPU time 2.15 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:00 PM PST 24
Peak memory 203680 kb
Host smart-62d1fdfb-2c3b-4847-814a-37560b43f809
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104341306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.4104341306
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.731100041
Short name T907
Test name
Test status
Simulation time 3590035251 ps
CPU time 4.47 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:46:02 PM PST 24
Peak memory 203832 kb
Host smart-44b6fd34-b343-4d0e-9993-fa3df3e629e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731100041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.731100041
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2004072750
Short name T1325
Test name
Test status
Simulation time 8600631447 ps
CPU time 18.18 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:46:13 PM PST 24
Peak memory 522900 kb
Host smart-695edaf0-96d1-4e7b-8083-0d0524dc2d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004072750 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2004072750
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_perf.3274901173
Short name T153
Test name
Test status
Simulation time 718574130 ps
CPU time 4.58 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:03 PM PST 24
Peak memory 204128 kb
Host smart-da0422fd-b53e-41d8-b50f-f83f60f85ead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274901173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_perf.3274901173
Directory /workspace/14.i2c_target_perf/latest

Test location /workspace/coverage/default/14.i2c_target_stress_all.1753398247
Short name T308
Test name
Test status
Simulation time 55118181564 ps
CPU time 844.93 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 03:00:04 PM PST 24
Peak memory 3571104 kb
Host smart-3474d436-848a-4e20-9d22-2de22807f15b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753398247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.i2c_target_stress_all.1753398247
Directory /workspace/14.i2c_target_stress_all/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.441929609
Short name T513
Test name
Test status
Simulation time 2453330847 ps
CPU time 6.46 seconds
Started Feb 29 02:45:56 PM PST 24
Finished Feb 29 02:46:02 PM PST 24
Peak memory 203700 kb
Host smart-a13011a7-ae3e-4688-a941-2155419b512d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441929609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.441929609
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3871200232
Short name T809
Test name
Test status
Simulation time 38881813178 ps
CPU time 53.27 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:51 PM PST 24
Peak memory 923276 kb
Host smart-c47338ad-6c73-4314-a4c2-d89c4bf8c15b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871200232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3871200232
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1002380298
Short name T1331
Test name
Test status
Simulation time 22304217630 ps
CPU time 142.72 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:48:20 PM PST 24
Peak memory 623016 kb
Host smart-8928cf4d-e9c3-46bd-84bb-8bd6c9e771bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002380298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1002380298
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1828866239
Short name T806
Test name
Test status
Simulation time 1505639023 ps
CPU time 6.66 seconds
Started Feb 29 02:45:56 PM PST 24
Finished Feb 29 02:46:03 PM PST 24
Peak memory 203652 kb
Host smart-a754cf8d-e6ab-40f9-a624-4bd7e00e7dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828866239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1828866239
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.4023340425
Short name T640
Test name
Test status
Simulation time 683473752 ps
CPU time 3.88 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:45:59 PM PST 24
Peak memory 203616 kb
Host smart-e435059a-9e87-4599-8f17-91c0e5182421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023340425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.i2c_target_unexp_stop.4023340425
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.884558695
Short name T1026
Test name
Test status
Simulation time 24719314 ps
CPU time 0.61 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 02:46:10 PM PST 24
Peak memory 202496 kb
Host smart-874cb171-5e10-4655-a84d-b20053812326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884558695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.884558695
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1950005436
Short name T587
Test name
Test status
Simulation time 34512188 ps
CPU time 1.11 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:45:59 PM PST 24
Peak memory 211904 kb
Host smart-b91630b0-f4c0-449d-8c46-4144e70cf5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950005436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1950005436
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2982844675
Short name T1088
Test name
Test status
Simulation time 2136374236 ps
CPU time 9.91 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:08 PM PST 24
Peak memory 321720 kb
Host smart-2d751c92-e2c2-4622-aeec-94139e657183
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982844675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2982844675
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3536882881
Short name T848
Test name
Test status
Simulation time 2500459849 ps
CPU time 103.76 seconds
Started Feb 29 02:45:59 PM PST 24
Finished Feb 29 02:47:43 PM PST 24
Peak memory 557220 kb
Host smart-2fe39aa8-c5c5-4a1e-b4f8-e02ea63c684a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536882881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3536882881
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.4197860473
Short name T350
Test name
Test status
Simulation time 2843974325 ps
CPU time 96.54 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:47:33 PM PST 24
Peak memory 827696 kb
Host smart-fdbc1221-8d0b-4662-b0dc-b3597fe995ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197860473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.4197860473
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.858172315
Short name T656
Test name
Test status
Simulation time 178774243 ps
CPU time 9.15 seconds
Started Feb 29 02:45:59 PM PST 24
Finished Feb 29 02:46:08 PM PST 24
Peak memory 203720 kb
Host smart-e13efbac-28b0-41a0-9362-bb69e2897c4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858172315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
858172315
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2495443265
Short name T130
Test name
Test status
Simulation time 21077502265 ps
CPU time 133.6 seconds
Started Feb 29 02:45:56 PM PST 24
Finished Feb 29 02:48:10 PM PST 24
Peak memory 1447440 kb
Host smart-00ba8a20-86f3-409d-a624-181669db9429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495443265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2495443265
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3862226038
Short name T939
Test name
Test status
Simulation time 5965232926 ps
CPU time 170.87 seconds
Started Feb 29 02:46:10 PM PST 24
Finished Feb 29 02:49:01 PM PST 24
Peak memory 268176 kb
Host smart-1ed5a5de-c949-4a3b-bfd6-3c8f5c258024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862226038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3862226038
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.3044302850
Short name T686
Test name
Test status
Simulation time 72818269 ps
CPU time 0.64 seconds
Started Feb 29 02:45:56 PM PST 24
Finished Feb 29 02:45:57 PM PST 24
Peak memory 202724 kb
Host smart-0ac7937b-f1c0-4c6f-8c91-d786535f4328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044302850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3044302850
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3343067003
Short name T893
Test name
Test status
Simulation time 14396956887 ps
CPU time 71.28 seconds
Started Feb 29 02:46:00 PM PST 24
Finished Feb 29 02:47:12 PM PST 24
Peak memory 227848 kb
Host smart-dacab62d-0232-46e8-8b7d-0eb6ad106c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343067003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3343067003
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_rx_oversample.3047582083
Short name T506
Test name
Test status
Simulation time 7513284343 ps
CPU time 94.23 seconds
Started Feb 29 02:45:55 PM PST 24
Finished Feb 29 02:47:30 PM PST 24
Peak memory 310852 kb
Host smart-349418d4-e1b5-4dfe-940c-0920eb385522
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047582083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_rx_oversample
.3047582083
Directory /workspace/15.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1929508124
Short name T347
Test name
Test status
Simulation time 2058742532 ps
CPU time 36 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:34 PM PST 24
Peak memory 247188 kb
Host smart-c566437a-2b12-4cd3-ba48-9a5892b2e660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929508124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1929508124
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.4210530340
Short name T859
Test name
Test status
Simulation time 15985165266 ps
CPU time 765.13 seconds
Started Feb 29 02:45:57 PM PST 24
Finished Feb 29 02:58:42 PM PST 24
Peak memory 2407660 kb
Host smart-5f85dcd5-2695-4148-aa8c-f41ee9d04564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210530340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.4210530340
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3196338341
Short name T464
Test name
Test status
Simulation time 6600457903 ps
CPU time 52.01 seconds
Started Feb 29 02:46:00 PM PST 24
Finished Feb 29 02:46:52 PM PST 24
Peak memory 212952 kb
Host smart-d4467a52-c9e0-4816-8e72-9a16c4d3eda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196338341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3196338341
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3141777739
Short name T401
Test name
Test status
Simulation time 2792232562 ps
CPU time 5.43 seconds
Started Feb 29 02:46:10 PM PST 24
Finished Feb 29 02:46:16 PM PST 24
Peak memory 203692 kb
Host smart-46c578ee-ad29-4011-aa84-d53751a8dcb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141777739 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3141777739
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3771394490
Short name T1234
Test name
Test status
Simulation time 10106162867 ps
CPU time 56.33 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 02:47:06 PM PST 24
Peak memory 571768 kb
Host smart-a28e5f7d-6049-4f7d-9ee0-7d896d7302d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771394490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3771394490
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2494282663
Short name T612
Test name
Test status
Simulation time 10227562893 ps
CPU time 12.46 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 02:46:22 PM PST 24
Peak memory 348600 kb
Host smart-f2645462-d812-4327-ac35-3e300ee6e8c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494282663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2494282663
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2226954444
Short name T710
Test name
Test status
Simulation time 621299375 ps
CPU time 2.99 seconds
Started Feb 29 02:46:08 PM PST 24
Finished Feb 29 02:46:11 PM PST 24
Peak memory 203644 kb
Host smart-173921c0-3639-4349-8cad-427e322bc000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226954444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2226954444
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1176295999
Short name T796
Test name
Test status
Simulation time 4558677812 ps
CPU time 4.94 seconds
Started Feb 29 02:45:56 PM PST 24
Finished Feb 29 02:46:01 PM PST 24
Peak memory 203764 kb
Host smart-f114b7c6-8de4-43ac-a29d-f64ccc88740b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176295999 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1176295999
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1379957152
Short name T909
Test name
Test status
Simulation time 21600124710 ps
CPU time 5.8 seconds
Started Feb 29 02:45:58 PM PST 24
Finished Feb 29 02:46:04 PM PST 24
Peak memory 203684 kb
Host smart-97775092-2b23-4658-a5b7-93828075f098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379957152 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1379957152
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_perf.1032944073
Short name T648
Test name
Test status
Simulation time 1141839340 ps
CPU time 4.3 seconds
Started Feb 29 02:46:11 PM PST 24
Finished Feb 29 02:46:16 PM PST 24
Peak memory 203716 kb
Host smart-62da910f-26dd-4574-bef5-cd854a66ab41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032944073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_perf.1032944073
Directory /workspace/15.i2c_target_perf/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1425243041
Short name T555
Test name
Test status
Simulation time 17554824408 ps
CPU time 46.49 seconds
Started Feb 29 02:46:01 PM PST 24
Finished Feb 29 02:46:48 PM PST 24
Peak memory 203824 kb
Host smart-a357f51b-ad6d-419c-acd6-d44a0edc0777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425243041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1425243041
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_all.3836503718
Short name T839
Test name
Test status
Simulation time 134488711419 ps
CPU time 209.94 seconds
Started Feb 29 02:46:08 PM PST 24
Finished Feb 29 02:49:38 PM PST 24
Peak memory 1205824 kb
Host smart-74f4de48-bc14-4cae-9ede-fea99bf34a29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836503718 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 15.i2c_target_stress_all.3836503718
Directory /workspace/15.i2c_target_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.2859078386
Short name T1095
Test name
Test status
Simulation time 38790507201 ps
CPU time 175.22 seconds
Started Feb 29 02:45:56 PM PST 24
Finished Feb 29 02:48:52 PM PST 24
Peak memory 2238612 kb
Host smart-d63eb7c5-2302-4556-a50e-00ac4b5a1729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859078386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.2859078386
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1857696890
Short name T540
Test name
Test status
Simulation time 6534599268 ps
CPU time 13.75 seconds
Started Feb 29 02:46:00 PM PST 24
Finished Feb 29 02:46:13 PM PST 24
Peak memory 222208 kb
Host smart-5bf36bfd-9480-4470-9847-cc43781105e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857696890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1857696890
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2140268946
Short name T981
Test name
Test status
Simulation time 3438068575 ps
CPU time 7.19 seconds
Started Feb 29 02:46:12 PM PST 24
Finished Feb 29 02:46:19 PM PST 24
Peak memory 207400 kb
Host smart-a6bf0d09-fc6b-4b4c-be31-5da596a76959
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140268946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2140268946
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.3447782120
Short name T30
Test name
Test status
Simulation time 6433310605 ps
CPU time 7.95 seconds
Started Feb 29 02:46:08 PM PST 24
Finished Feb 29 02:46:17 PM PST 24
Peak memory 208804 kb
Host smart-8034ffee-849f-479a-94a5-dc984d73b5cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447782120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.3447782120
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3179204243
Short name T1009
Test name
Test status
Simulation time 52199972 ps
CPU time 0.58 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:46:21 PM PST 24
Peak memory 202580 kb
Host smart-f9281511-ebcf-43fa-a017-a1d480a6cb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179204243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3179204243
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1861014959
Short name T1272
Test name
Test status
Simulation time 146642760 ps
CPU time 1.95 seconds
Started Feb 29 02:46:12 PM PST 24
Finished Feb 29 02:46:14 PM PST 24
Peak memory 211840 kb
Host smart-ab926c62-9f92-4bba-b654-4bb5249482c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861014959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1861014959
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3425348953
Short name T993
Test name
Test status
Simulation time 1258055910 ps
CPU time 15.28 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 02:46:25 PM PST 24
Peak memory 344956 kb
Host smart-bc0fd61e-5b9e-44a9-94f8-aa740352bcea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425348953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3425348953
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2700184297
Short name T1251
Test name
Test status
Simulation time 3505756243 ps
CPU time 123.11 seconds
Started Feb 29 02:46:14 PM PST 24
Finished Feb 29 02:48:17 PM PST 24
Peak memory 639880 kb
Host smart-127414ad-74fb-4f1e-9dff-b06c08a5f009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700184297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2700184297
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1443542731
Short name T390
Test name
Test status
Simulation time 12977198844 ps
CPU time 104.57 seconds
Started Feb 29 02:46:10 PM PST 24
Finished Feb 29 02:47:55 PM PST 24
Peak memory 981300 kb
Host smart-750fda1e-3954-4e88-808f-c4895da926a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443542731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1443542731
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2353177545
Short name T471
Test name
Test status
Simulation time 236694219 ps
CPU time 4.47 seconds
Started Feb 29 02:46:10 PM PST 24
Finished Feb 29 02:46:15 PM PST 24
Peak memory 203676 kb
Host smart-b1a4e6fd-bf3b-4a1f-9bed-babab3838583
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353177545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2353177545
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2775430447
Short name T899
Test name
Test status
Simulation time 23901684307 ps
CPU time 461.15 seconds
Started Feb 29 02:46:11 PM PST 24
Finished Feb 29 02:53:53 PM PST 24
Peak memory 1558952 kb
Host smart-dc8f978d-f8c3-4127-b7d0-4a3cae869198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775430447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2775430447
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3510856757
Short name T258
Test name
Test status
Simulation time 13021506291 ps
CPU time 119.37 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:48:21 PM PST 24
Peak memory 260196 kb
Host smart-66ed5527-99f5-49e9-a5ee-b022425c544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510856757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3510856757
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.522601701
Short name T745
Test name
Test status
Simulation time 48091145 ps
CPU time 0.69 seconds
Started Feb 29 02:46:11 PM PST 24
Finished Feb 29 02:46:12 PM PST 24
Peak memory 202720 kb
Host smart-1b825590-0f0a-4426-bbb2-d66588ef8575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522601701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.522601701
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1566976868
Short name T588
Test name
Test status
Simulation time 4575381586 ps
CPU time 117.68 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 02:48:07 PM PST 24
Peak memory 213992 kb
Host smart-29503718-f3a7-4181-9be6-a45d32516924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566976868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1566976868
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1740501349
Short name T519
Test name
Test status
Simulation time 2004009383 ps
CPU time 54.61 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 02:47:04 PM PST 24
Peak memory 276816 kb
Host smart-6b117b08-b771-4ea4-b7e3-238a4287ec3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740501349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1740501349
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1801929601
Short name T782
Test name
Test status
Simulation time 1770021103 ps
CPU time 14.88 seconds
Started Feb 29 02:46:08 PM PST 24
Finished Feb 29 02:46:23 PM PST 24
Peak memory 219216 kb
Host smart-74004ae5-4182-45d6-b58b-ad27f350e322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801929601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1801929601
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.269310837
Short name T325
Test name
Test status
Simulation time 4239413205 ps
CPU time 4.4 seconds
Started Feb 29 02:46:21 PM PST 24
Finished Feb 29 02:46:26 PM PST 24
Peak memory 203760 kb
Host smart-f1305854-d37d-425b-b5e6-4ab57ce4c7b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269310837 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.269310837
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2128298666
Short name T263
Test name
Test status
Simulation time 10107375561 ps
CPU time 15.9 seconds
Started Feb 29 02:46:19 PM PST 24
Finished Feb 29 02:46:35 PM PST 24
Peak memory 325752 kb
Host smart-3aa8295e-c98d-4f0a-87c6-489e015be738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128298666 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2128298666
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.182812298
Short name T820
Test name
Test status
Simulation time 4617561059 ps
CPU time 2.59 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:46:24 PM PST 24
Peak memory 203692 kb
Host smart-fc79e5d0-74a6-4e4c-93f8-4d1c4d50b3ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182812298 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.182812298
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3092463608
Short name T867
Test name
Test status
Simulation time 1091280984 ps
CPU time 4.66 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:46:26 PM PST 24
Peak memory 206400 kb
Host smart-ce1a684a-7477-40c9-8231-2699e006b81a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092463608 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3092463608
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3027743070
Short name T1104
Test name
Test status
Simulation time 10374954098 ps
CPU time 171.66 seconds
Started Feb 29 02:46:18 PM PST 24
Finished Feb 29 02:49:10 PM PST 24
Peak memory 2390732 kb
Host smart-1fe9812a-6724-4b82-8b67-fede6a9efcab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027743070 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3027743070
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_perf.1103756692
Short name T1087
Test name
Test status
Simulation time 522880248 ps
CPU time 3.35 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:46:24 PM PST 24
Peak memory 203796 kb
Host smart-9ff4ca4c-1303-4442-87c3-c1343dc6ced2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103756692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_perf.1103756692
Directory /workspace/16.i2c_target_perf/latest

Test location /workspace/coverage/default/16.i2c_target_stress_all.2650889194
Short name T1266
Test name
Test status
Simulation time 28742000981 ps
CPU time 451.47 seconds
Started Feb 29 02:46:21 PM PST 24
Finished Feb 29 02:53:54 PM PST 24
Peak memory 2890364 kb
Host smart-c9cb5391-12c1-4494-8150-a264e3abaae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650889194 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.i2c_target_stress_all.2650889194
Directory /workspace/16.i2c_target_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.812946810
Short name T1247
Test name
Test status
Simulation time 46318535751 ps
CPU time 256.25 seconds
Started Feb 29 02:46:10 PM PST 24
Finished Feb 29 02:50:27 PM PST 24
Peak memory 2667028 kb
Host smart-53747152-3ac0-477c-8175-8768becd05a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812946810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_wr.812946810
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.249399124
Short name T600
Test name
Test status
Simulation time 18653318573 ps
CPU time 2716.1 seconds
Started Feb 29 02:46:09 PM PST 24
Finished Feb 29 03:31:26 PM PST 24
Peak memory 4540848 kb
Host smart-62db15e7-7f9e-4974-b3a8-10d20fdc60bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249399124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.249399124
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2021607639
Short name T1252
Test name
Test status
Simulation time 1556303889 ps
CPU time 6.65 seconds
Started Feb 29 02:46:21 PM PST 24
Finished Feb 29 02:46:29 PM PST 24
Peak memory 211892 kb
Host smart-68eec260-5a81-4f97-b3a1-aa61172aaa98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021607639 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2021607639
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.40260225
Short name T29
Test name
Test status
Simulation time 8566743978 ps
CPU time 7.84 seconds
Started Feb 29 02:46:22 PM PST 24
Finished Feb 29 02:46:30 PM PST 24
Peak memory 204116 kb
Host smart-bdb13e50-9702-448b-a6b0-90858144fa15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40260225 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_unexp_stop.40260225
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.4009173113
Short name T520
Test name
Test status
Simulation time 16434723 ps
CPU time 0.64 seconds
Started Feb 29 02:46:24 PM PST 24
Finished Feb 29 02:46:25 PM PST 24
Peak memory 202504 kb
Host smart-51aac746-6db8-4be9-aa77-2743945fbe36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009173113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.4009173113
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3830284373
Short name T772
Test name
Test status
Simulation time 234118806 ps
CPU time 1.95 seconds
Started Feb 29 02:46:24 PM PST 24
Finished Feb 29 02:46:27 PM PST 24
Peak memory 211856 kb
Host smart-1b147b46-33a4-4188-af0f-5b0ad76a0efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830284373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3830284373
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1583938090
Short name T1047
Test name
Test status
Simulation time 1754969980 ps
CPU time 13.71 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:46:35 PM PST 24
Peak memory 259228 kb
Host smart-da3a7a0b-11e2-49ee-86ed-60933406174d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583938090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1583938090
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1438666053
Short name T1067
Test name
Test status
Simulation time 2554193343 ps
CPU time 136.44 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:48:38 PM PST 24
Peak memory 441060 kb
Host smart-1821e2ae-3535-4ce4-9b09-e48831fcef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438666053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1438666053
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.900419391
Short name T692
Test name
Test status
Simulation time 7307097729 ps
CPU time 57.56 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:47:19 PM PST 24
Peak memory 695728 kb
Host smart-1ae69a8f-0a55-490c-8659-a80cd938901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900419391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.900419391
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2785472016
Short name T876
Test name
Test status
Simulation time 999477096 ps
CPU time 14.19 seconds
Started Feb 29 02:46:22 PM PST 24
Finished Feb 29 02:46:37 PM PST 24
Peak memory 256228 kb
Host smart-8c6328fc-9d14-4dd3-a10b-4d3bab7a8544
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785472016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2785472016
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2448371226
Short name T283
Test name
Test status
Simulation time 6360547863 ps
CPU time 198.02 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:49:39 PM PST 24
Peak memory 1532748 kb
Host smart-ff0d2442-f824-473a-b4ee-98f8cff93718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448371226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2448371226
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2051474040
Short name T733
Test name
Test status
Simulation time 2749946200 ps
CPU time 75.31 seconds
Started Feb 29 02:46:26 PM PST 24
Finished Feb 29 02:47:42 PM PST 24
Peak memory 351488 kb
Host smart-16adabd5-a33d-4795-8673-9f7df85cd8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051474040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2051474040
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3911644868
Short name T1063
Test name
Test status
Simulation time 31977854 ps
CPU time 0.62 seconds
Started Feb 29 02:46:19 PM PST 24
Finished Feb 29 02:46:20 PM PST 24
Peak memory 202760 kb
Host smart-b837b4da-b7a4-4455-8976-ae45a5f3d7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911644868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3911644868
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1490832889
Short name T439
Test name
Test status
Simulation time 12794668744 ps
CPU time 570.35 seconds
Started Feb 29 02:46:22 PM PST 24
Finished Feb 29 02:55:53 PM PST 24
Peak memory 211948 kb
Host smart-2b75a6ea-1be6-4299-bce0-a2a1804ac8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490832889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1490832889
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_rx_oversample.2940214739
Short name T1275
Test name
Test status
Simulation time 8212590432 ps
CPU time 72.38 seconds
Started Feb 29 02:46:22 PM PST 24
Finished Feb 29 02:47:35 PM PST 24
Peak memory 277180 kb
Host smart-48140b14-c6b4-4246-8072-93e85382ba7f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940214739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_rx_oversample
.2940214739
Directory /workspace/17.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1149214683
Short name T877
Test name
Test status
Simulation time 34935819598 ps
CPU time 140.21 seconds
Started Feb 29 02:46:20 PM PST 24
Finished Feb 29 02:48:41 PM PST 24
Peak memory 264016 kb
Host smart-854f53b0-e18b-4acb-89ee-3635b0c6a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149214683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1149214683
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3062430379
Short name T416
Test name
Test status
Simulation time 3769206392 ps
CPU time 43.1 seconds
Started Feb 29 02:46:24 PM PST 24
Finished Feb 29 02:47:08 PM PST 24
Peak memory 213620 kb
Host smart-1dcc18e9-f0d5-4662-8991-401be1aab1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062430379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3062430379
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.701575406
Short name T1244
Test name
Test status
Simulation time 11091879347 ps
CPU time 3.4 seconds
Started Feb 29 02:46:22 PM PST 24
Finished Feb 29 02:46:27 PM PST 24
Peak memory 203680 kb
Host smart-9127dcba-2053-4922-b94f-bd7a920fd0d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701575406 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.701575406
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2489806673
Short name T1332
Test name
Test status
Simulation time 10177407880 ps
CPU time 9.56 seconds
Started Feb 29 02:46:23 PM PST 24
Finished Feb 29 02:46:33 PM PST 24
Peak memory 258208 kb
Host smart-22398422-0b5a-4c4b-9d65-990a60e46e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489806673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2489806673
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1909661797
Short name T397
Test name
Test status
Simulation time 10149818022 ps
CPU time 47.36 seconds
Started Feb 29 02:46:26 PM PST 24
Finished Feb 29 02:47:14 PM PST 24
Peak memory 511012 kb
Host smart-087fb605-6cb5-404c-9310-7a2312299117
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909661797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1909661797
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.4110449300
Short name T753
Test name
Test status
Simulation time 703108367 ps
CPU time 2.98 seconds
Started Feb 29 02:46:26 PM PST 24
Finished Feb 29 02:46:29 PM PST 24
Peak memory 203696 kb
Host smart-38a79add-b1f5-4d30-b433-6812a330407f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110449300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.4110449300
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2748369943
Short name T331
Test name
Test status
Simulation time 2900208266 ps
CPU time 3.68 seconds
Started Feb 29 02:46:25 PM PST 24
Finished Feb 29 02:46:29 PM PST 24
Peak memory 205184 kb
Host smart-ba1b8372-2352-4ee8-96a3-6bf91b07275e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748369943 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2748369943
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1877431359
Short name T423
Test name
Test status
Simulation time 17045679727 ps
CPU time 81.98 seconds
Started Feb 29 02:46:25 PM PST 24
Finished Feb 29 02:47:47 PM PST 24
Peak memory 1118820 kb
Host smart-ff20f59c-e4a4-4d9e-b82f-c1e6c687c3f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877431359 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1877431359
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_perf.4152132681
Short name T1010
Test name
Test status
Simulation time 437810938 ps
CPU time 2.62 seconds
Started Feb 29 02:46:27 PM PST 24
Finished Feb 29 02:46:30 PM PST 24
Peak memory 203644 kb
Host smart-72b848d6-cbe6-48f0-818c-14a8fa33575f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152132681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_perf.4152132681
Directory /workspace/17.i2c_target_perf/latest

Test location /workspace/coverage/default/17.i2c_target_stress_all.2895315908
Short name T1032
Test name
Test status
Simulation time 16161127290 ps
CPU time 123.06 seconds
Started Feb 29 02:46:28 PM PST 24
Finished Feb 29 02:48:32 PM PST 24
Peak memory 1452316 kb
Host smart-0592ae7f-8e64-40da-8489-3be3a24e843f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895315908 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.i2c_target_stress_all.2895315908
Directory /workspace/17.i2c_target_stress_all/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1657121764
Short name T523
Test name
Test status
Simulation time 999829944 ps
CPU time 41.76 seconds
Started Feb 29 02:46:25 PM PST 24
Finished Feb 29 02:47:07 PM PST 24
Peak memory 203632 kb
Host smart-dea9c1c1-7532-4ecf-ad1f-333ca8c5a587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657121764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1657121764
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1857965013
Short name T620
Test name
Test status
Simulation time 13393917421 ps
CPU time 57.41 seconds
Started Feb 29 02:46:22 PM PST 24
Finished Feb 29 02:47:20 PM PST 24
Peak memory 792500 kb
Host smart-0ebe07a3-460f-4c1c-b5c3-c24448d516dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857965013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1857965013
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3134888189
Short name T22
Test name
Test status
Simulation time 21825247770 ps
CPU time 7.43 seconds
Started Feb 29 02:46:25 PM PST 24
Finished Feb 29 02:46:33 PM PST 24
Peak memory 213940 kb
Host smart-5ed3f783-5427-4eb3-b20c-ef57b780c4af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134888189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3134888189
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.1775123443
Short name T1149
Test name
Test status
Simulation time 5584895395 ps
CPU time 7.17 seconds
Started Feb 29 02:46:26 PM PST 24
Finished Feb 29 02:46:34 PM PST 24
Peak memory 204292 kb
Host smart-55d9e3a1-fee9-4252-9b7f-3c1b2985f4f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775123443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.1775123443
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.372733904
Short name T1205
Test name
Test status
Simulation time 47196383 ps
CPU time 0.64 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:46:52 PM PST 24
Peak memory 203516 kb
Host smart-cfc05aca-b127-4234-8ea8-2266949d5daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372733904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.372733904
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1180492313
Short name T1293
Test name
Test status
Simulation time 40189162 ps
CPU time 1.09 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:46:52 PM PST 24
Peak memory 211904 kb
Host smart-e6864ba1-9560-422a-9123-646b63fa142e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180492313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1180492313
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1967319284
Short name T969
Test name
Test status
Simulation time 548322515 ps
CPU time 11.54 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:47:04 PM PST 24
Peak memory 322168 kb
Host smart-99ea7911-0975-4c6c-a4df-da1cc28c8337
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967319284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1967319284
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.4048953914
Short name T62
Test name
Test status
Simulation time 3468664355 ps
CPU time 77.95 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:48:08 PM PST 24
Peak memory 616792 kb
Host smart-2691c9a9-d2a0-4171-80e3-2f9be83cb484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048953914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4048953914
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2010049911
Short name T287
Test name
Test status
Simulation time 1980032446 ps
CPU time 135.66 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:49:08 PM PST 24
Peak memory 635188 kb
Host smart-c83b4200-7784-4cba-8191-9c97d03dac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010049911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2010049911
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2793756923
Short name T630
Test name
Test status
Simulation time 239405408 ps
CPU time 13.92 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:47:05 PM PST 24
Peak memory 251464 kb
Host smart-9ab6e52a-9e9b-436e-8e87-8d8624f26b43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793756923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2793756923
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1308039779
Short name T1050
Test name
Test status
Simulation time 10703552478 ps
CPU time 26.96 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:47:18 PM PST 24
Peak memory 228152 kb
Host smart-d78cb53a-b485-4515-b5a6-696cab97ce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308039779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1308039779
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2117970632
Short name T1199
Test name
Test status
Simulation time 29731083 ps
CPU time 0.63 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:46:52 PM PST 24
Peak memory 202720 kb
Host smart-0c74c532-fa61-494b-be93-e3e120429dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117970632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2117970632
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3795400747
Short name T36
Test name
Test status
Simulation time 10182979081 ps
CPU time 61.66 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:47:53 PM PST 24
Peak memory 220132 kb
Host smart-ba86d2f4-96df-48c6-bfe5-2d91ff35e201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795400747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3795400747
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_rx_oversample.3798052884
Short name T25
Test name
Test status
Simulation time 6692541522 ps
CPU time 135.67 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:49:06 PM PST 24
Peak memory 288172 kb
Host smart-1a0f04ca-c54b-47cc-8b85-3f8705482376
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798052884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_rx_oversample
.3798052884
Directory /workspace/18.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1957335113
Short name T339
Test name
Test status
Simulation time 2388629925 ps
CPU time 55.07 seconds
Started Feb 29 02:46:26 PM PST 24
Finished Feb 29 02:47:22 PM PST 24
Peak memory 294720 kb
Host smart-713e7f01-0440-4465-ab73-e44bd111da85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957335113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1957335113
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3611366740
Short name T1015
Test name
Test status
Simulation time 2414003818 ps
CPU time 8.77 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:47:01 PM PST 24
Peak memory 211892 kb
Host smart-c414638c-27d3-4ff8-8a50-5866b67112fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611366740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3611366740
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.1658125159
Short name T391
Test name
Test status
Simulation time 3120494295 ps
CPU time 3.36 seconds
Started Feb 29 02:46:53 PM PST 24
Finished Feb 29 02:46:56 PM PST 24
Peak memory 204016 kb
Host smart-f5bfcf5c-9a3d-4805-8250-0e93619f8b05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658125159 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1658125159
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.2899079570
Short name T619
Test name
Test status
Simulation time 10080893622 ps
CPU time 30.73 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:47:22 PM PST 24
Peak memory 353856 kb
Host smart-dd60067f-6042-49ec-aa04-0513db3a83f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899079570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.2899079570
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.1302945553
Short name T1229
Test name
Test status
Simulation time 10092221622 ps
CPU time 86.79 seconds
Started Feb 29 02:46:53 PM PST 24
Finished Feb 29 02:48:20 PM PST 24
Peak memory 577568 kb
Host smart-7fe7643c-3e92-4d9c-a497-7f79b254b9fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302945553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.1302945553
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.3817135449
Short name T50
Test name
Test status
Simulation time 1084472656 ps
CPU time 2.41 seconds
Started Feb 29 02:46:49 PM PST 24
Finished Feb 29 02:46:52 PM PST 24
Peak memory 203576 kb
Host smart-283ca715-4593-4146-a847-901a50d63dea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817135449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.3817135449
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2366779909
Short name T624
Test name
Test status
Simulation time 894190360 ps
CPU time 4.54 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:46:57 PM PST 24
Peak memory 209024 kb
Host smart-7c911d31-bf46-4240-9e24-e94c4612088d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366779909 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2366779909
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.637617625
Short name T908
Test name
Test status
Simulation time 17495219274 ps
CPU time 430.72 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:54:01 PM PST 24
Peak memory 3991612 kb
Host smart-3b81ced9-fa1f-4972-bafb-467c4148b275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637617625 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.637617625
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_perf.3646595023
Short name T913
Test name
Test status
Simulation time 14161115124 ps
CPU time 4.22 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:46:54 PM PST 24
Peak memory 204612 kb
Host smart-5459599b-3c1e-45e0-ae39-1bceba4659ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646595023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_perf.3646595023
Directory /workspace/18.i2c_target_perf/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2197079698
Short name T1322
Test name
Test status
Simulation time 8933068068 ps
CPU time 36.97 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:47:28 PM PST 24
Peak memory 203688 kb
Host smart-bd15b3e2-a338-4993-9aa1-6d8824f62524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197079698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2197079698
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2505166330
Short name T919
Test name
Test status
Simulation time 1249836111 ps
CPU time 43.8 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:47:35 PM PST 24
Peak memory 203748 kb
Host smart-d7c03403-d5e2-4d8f-b806-5e14bc7fe968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505166330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2505166330
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.462124514
Short name T650
Test name
Test status
Simulation time 7877077519 ps
CPU time 16 seconds
Started Feb 29 02:46:53 PM PST 24
Finished Feb 29 02:47:09 PM PST 24
Peak memory 549440 kb
Host smart-f9d55780-856b-42d9-9df3-fd1fb5244417
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462124514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.462124514
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3168208334
Short name T1226
Test name
Test status
Simulation time 8563027243 ps
CPU time 191.39 seconds
Started Feb 29 02:46:49 PM PST 24
Finished Feb 29 02:50:01 PM PST 24
Peak memory 1818216 kb
Host smart-b29d3b2b-024d-48ee-a382-59a2a5690add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168208334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3168208334
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.622959785
Short name T897
Test name
Test status
Simulation time 1658860579 ps
CPU time 7.1 seconds
Started Feb 29 02:46:49 PM PST 24
Finished Feb 29 02:46:56 PM PST 24
Peak memory 205792 kb
Host smart-4d765a0a-4778-4f0e-8966-c6c9807e43ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622959785 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.622959785
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.1792738362
Short name T534
Test name
Test status
Simulation time 7762292867 ps
CPU time 6.54 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:46:57 PM PST 24
Peak memory 203696 kb
Host smart-708fb950-dbc4-47b7-9ec9-9f0410185ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792738362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.i2c_target_unexp_stop.1792738362
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1600612398
Short name T380
Test name
Test status
Simulation time 65434628 ps
CPU time 0.62 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:03 PM PST 24
Peak memory 202548 kb
Host smart-f745f4a7-4b59-4a75-94f7-24a5e09da1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600612398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1600612398
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2087570917
Short name T1092
Test name
Test status
Simulation time 125639461 ps
CPU time 1.63 seconds
Started Feb 29 02:47:03 PM PST 24
Finished Feb 29 02:47:04 PM PST 24
Peak memory 211992 kb
Host smart-42f49cf4-b090-4063-b7ea-1a1e60d24646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087570917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2087570917
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3420499923
Short name T811
Test name
Test status
Simulation time 458189899 ps
CPU time 10.15 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:47:03 PM PST 24
Peak memory 302880 kb
Host smart-49198b65-0644-40fd-8092-9452b28740df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420499923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3420499923
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2057236489
Short name T494
Test name
Test status
Simulation time 2153251072 ps
CPU time 67.04 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:47:59 PM PST 24
Peak memory 651784 kb
Host smart-620dd8eb-6ad8-48e9-9389-39cd27993fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057236489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2057236489
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.158027004
Short name T426
Test name
Test status
Simulation time 3098604204 ps
CPU time 211.42 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:50:22 PM PST 24
Peak memory 764944 kb
Host smart-13b1bd58-72b8-47c9-823c-433315fb8816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158027004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.158027004
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.4030748263
Short name T343
Test name
Test status
Simulation time 143692216 ps
CPU time 7.42 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:47:00 PM PST 24
Peak memory 203664 kb
Host smart-7e14e7f4-6fa4-446b-afdd-e54a773015ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030748263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.4030748263
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3200083132
Short name T1136
Test name
Test status
Simulation time 3683632670 ps
CPU time 244.47 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:50:56 PM PST 24
Peak memory 1048212 kb
Host smart-1babdecc-a920-48e8-952e-72eec667b0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200083132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3200083132
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3013657682
Short name T1051
Test name
Test status
Simulation time 4499022294 ps
CPU time 62.55 seconds
Started Feb 29 02:47:04 PM PST 24
Finished Feb 29 02:48:07 PM PST 24
Peak memory 313852 kb
Host smart-d2d69bc2-2cf6-4e4f-b90d-82e16f5735f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013657682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3013657682
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3479336061
Short name T1235
Test name
Test status
Simulation time 40237831 ps
CPU time 0.62 seconds
Started Feb 29 02:46:51 PM PST 24
Finished Feb 29 02:46:52 PM PST 24
Peak memory 202788 kb
Host smart-6a4a2c03-fe9d-4c95-9271-7463ac3084ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479336061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3479336061
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.393308384
Short name T529
Test name
Test status
Simulation time 50649272161 ps
CPU time 246.5 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:51:08 PM PST 24
Peak memory 276096 kb
Host smart-a3eecf4f-a2ad-4215-9584-cc111b63d839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393308384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.393308384
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_rx_oversample.757879379
Short name T1148
Test name
Test status
Simulation time 2590625340 ps
CPU time 156.18 seconds
Started Feb 29 02:46:50 PM PST 24
Finished Feb 29 02:49:26 PM PST 24
Peak memory 362528 kb
Host smart-3615880b-25f7-4db1-a03a-d504cda4f491
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757879379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_rx_oversample.
757879379
Directory /workspace/19.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.737170650
Short name T220
Test name
Test status
Simulation time 9348460102 ps
CPU time 126.9 seconds
Started Feb 29 02:46:52 PM PST 24
Finished Feb 29 02:48:59 PM PST 24
Peak memory 267256 kb
Host smart-3efce6d3-7a93-4f34-a25d-de322a3748b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737170650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.737170650
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.1562878521
Short name T976
Test name
Test status
Simulation time 17524838354 ps
CPU time 3114.91 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 03:38:57 PM PST 24
Peak memory 3465940 kb
Host smart-9f73de67-b3b0-4329-ae27-118cd4be70d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562878521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.1562878521
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1421758559
Short name T481
Test name
Test status
Simulation time 879660009 ps
CPU time 13.53 seconds
Started Feb 29 02:46:58 PM PST 24
Finished Feb 29 02:47:12 PM PST 24
Peak memory 213872 kb
Host smart-97024605-bee6-46e9-b831-582122d10c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421758559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1421758559
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3875454787
Short name T1213
Test name
Test status
Simulation time 5275141664 ps
CPU time 5.5 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:47:06 PM PST 24
Peak memory 203680 kb
Host smart-a6050199-43aa-495f-8c3e-5259a0ffd65f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875454787 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3875454787
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3007119543
Short name T509
Test name
Test status
Simulation time 10131662677 ps
CPU time 54.2 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:56 PM PST 24
Peak memory 537288 kb
Host smart-510fef34-34fd-4dcb-8e76-f98524af7b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007119543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3007119543
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3203457285
Short name T1250
Test name
Test status
Simulation time 10120782211 ps
CPU time 11.92 seconds
Started Feb 29 02:46:57 PM PST 24
Finished Feb 29 02:47:09 PM PST 24
Peak memory 296908 kb
Host smart-0312892b-1cef-4e7d-86b9-e90fc20b242a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203457285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3203457285
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.862579756
Short name T157
Test name
Test status
Simulation time 6340630118 ps
CPU time 6.3 seconds
Started Feb 29 02:46:59 PM PST 24
Finished Feb 29 02:47:05 PM PST 24
Peak memory 209288 kb
Host smart-ba1de93c-d4fc-437c-b831-26b87d544258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862579756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.862579756
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1755213524
Short name T967
Test name
Test status
Simulation time 11083412956 ps
CPU time 121.83 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:49:02 PM PST 24
Peak memory 1873100 kb
Host smart-d76a4266-f19d-4e4b-bb6c-74eff014b06e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755213524 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1755213524
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_perf.1638318836
Short name T294
Test name
Test status
Simulation time 787508670 ps
CPU time 4.67 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:07 PM PST 24
Peak memory 207380 kb
Host smart-e6e84144-3717-40f7-9d74-be15cae0b0c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638318836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_perf.1638318836
Directory /workspace/19.i2c_target_perf/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.698101152
Short name T302
Test name
Test status
Simulation time 4612882279 ps
CPU time 32.35 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:47:33 PM PST 24
Peak memory 203760 kb
Host smart-cf60fe79-f9f6-414d-9cbd-4abc86cf4770
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698101152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.698101152
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_all.3066566583
Short name T873
Test name
Test status
Simulation time 74537260511 ps
CPU time 87.04 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:48:28 PM PST 24
Peak memory 969604 kb
Host smart-baa0cfd4-380b-4d41-b8fe-b04e4ad3fadf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066566583 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_stress_all.3066566583
Directory /workspace/19.i2c_target_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3320769820
Short name T298
Test name
Test status
Simulation time 6116512266 ps
CPU time 64.47 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:48:05 PM PST 24
Peak memory 203712 kb
Host smart-bde4ee6c-41a9-4340-adf2-6eab58dd79cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320769820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3320769820
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1400126754
Short name T1037
Test name
Test status
Simulation time 35521093193 ps
CPU time 411.58 seconds
Started Feb 29 02:47:04 PM PST 24
Finished Feb 29 02:53:56 PM PST 24
Peak memory 3974932 kb
Host smart-20b0f9df-d951-4a67-ad7d-ea8509846166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400126754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1400126754
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.4113161615
Short name T841
Test name
Test status
Simulation time 11720070430 ps
CPU time 1133.12 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 03:05:55 PM PST 24
Peak memory 2687072 kb
Host smart-061b5160-86ae-4656-a813-681ea1fcc000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113161615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.4113161615
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3190483017
Short name T1237
Test name
Test status
Simulation time 3312075574 ps
CPU time 6.8 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:47:07 PM PST 24
Peak memory 209060 kb
Host smart-3d24bcfc-90c7-4aef-8ca0-dacb994fd94a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190483017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3190483017
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.3999349276
Short name T651
Test name
Test status
Simulation time 1204478443 ps
CPU time 6.05 seconds
Started Feb 29 02:46:58 PM PST 24
Finished Feb 29 02:47:04 PM PST 24
Peak memory 206756 kb
Host smart-e693c819-d79d-4edc-ba92-cb1dddb3b2cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999349276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.3999349276
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2467252804
Short name T1069
Test name
Test status
Simulation time 37209787 ps
CPU time 0.58 seconds
Started Feb 29 02:43:44 PM PST 24
Finished Feb 29 02:43:45 PM PST 24
Peak memory 202564 kb
Host smart-18a9711b-11ca-4b1e-8b72-f2e1bb6119df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467252804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2467252804
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1827984493
Short name T317
Test name
Test status
Simulation time 36941689 ps
CPU time 1.09 seconds
Started Feb 29 02:43:45 PM PST 24
Finished Feb 29 02:43:46 PM PST 24
Peak memory 211884 kb
Host smart-ad00e7cc-dcc1-4349-a897-abfaea5ad286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827984493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1827984493
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1306629275
Short name T1238
Test name
Test status
Simulation time 4549438557 ps
CPU time 7.1 seconds
Started Feb 29 02:43:25 PM PST 24
Finished Feb 29 02:43:33 PM PST 24
Peak memory 294900 kb
Host smart-626ad1f8-a746-48dc-9d4a-c2a58aa648f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306629275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1306629275
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1157440061
Short name T354
Test name
Test status
Simulation time 16521412447 ps
CPU time 94.11 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:45:01 PM PST 24
Peak memory 822200 kb
Host smart-1e9c9108-58de-48e3-870b-8f0abf200b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157440061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1157440061
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3664374036
Short name T959
Test name
Test status
Simulation time 3121505065 ps
CPU time 217.73 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:47:04 PM PST 24
Peak memory 771516 kb
Host smart-026b0878-bab6-4253-8f44-7350b20e2681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664374036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3664374036
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.4138945364
Short name T719
Test name
Test status
Simulation time 735222164 ps
CPU time 5.34 seconds
Started Feb 29 02:43:27 PM PST 24
Finished Feb 29 02:43:33 PM PST 24
Peak memory 237484 kb
Host smart-38966df7-001d-4c7d-92b0-ce447fd98199
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138945364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
4138945364
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3583471701
Short name T87
Test name
Test status
Simulation time 20774011458 ps
CPU time 164.4 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:46:11 PM PST 24
Peak memory 1474588 kb
Host smart-b5a28957-1098-4bed-9e78-030ab2e502c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583471701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3583471701
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1345792472
Short name T447
Test name
Test status
Simulation time 8957770500 ps
CPU time 171.7 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:46:31 PM PST 24
Peak memory 377300 kb
Host smart-e8d17e94-837d-4b23-ba5b-e3a111025ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345792472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1345792472
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.4278570302
Short name T6
Test name
Test status
Simulation time 47029904 ps
CPU time 0.62 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:43:27 PM PST 24
Peak memory 202668 kb
Host smart-4223f87c-3e62-4392-bda3-27eda9326892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278570302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.4278570302
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3173748605
Short name T942
Test name
Test status
Simulation time 2982385238 ps
CPU time 60.46 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:44:39 PM PST 24
Peak memory 278176 kb
Host smart-d1f36842-106a-4d42-a90a-020619ac25e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173748605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3173748605
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_rx_oversample.1242325917
Short name T1163
Test name
Test status
Simulation time 4538394477 ps
CPU time 85.9 seconds
Started Feb 29 02:43:26 PM PST 24
Finished Feb 29 02:44:52 PM PST 24
Peak memory 300628 kb
Host smart-b12f7fbc-f93b-412c-b8f1-60cdccc3cce5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242325917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_rx_oversample.
1242325917
Directory /workspace/2.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.2464273608
Short name T798
Test name
Test status
Simulation time 1331281010 ps
CPU time 68.53 seconds
Started Feb 29 02:43:25 PM PST 24
Finished Feb 29 02:44:34 PM PST 24
Peak memory 228700 kb
Host smart-0a390afb-eb6d-41d6-8cd5-2ab53b97e48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464273608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.2464273608
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3593898752
Short name T696
Test name
Test status
Simulation time 1724545633 ps
CPU time 13.98 seconds
Started Feb 29 02:43:44 PM PST 24
Finished Feb 29 02:43:58 PM PST 24
Peak memory 219324 kb
Host smart-7fe4691c-9a10-4c39-8fc2-3d3bdc4e22eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593898752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3593898752
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1476510882
Short name T1021
Test name
Test status
Simulation time 5740599617 ps
CPU time 5.11 seconds
Started Feb 29 02:43:38 PM PST 24
Finished Feb 29 02:43:43 PM PST 24
Peak memory 203696 kb
Host smart-316bced2-c59a-4741-b90d-b504d2570be1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476510882 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1476510882
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2438023
Short name T1224
Test name
Test status
Simulation time 10156983547 ps
CPU time 11.61 seconds
Started Feb 29 02:43:40 PM PST 24
Finished Feb 29 02:43:51 PM PST 24
Peak memory 294440 kb
Host smart-6a860c0c-4d3f-4438-8e8a-404af993205a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438023 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_fifo_reset_acq.2438023
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3602677595
Short name T765
Test name
Test status
Simulation time 10125965677 ps
CPU time 33.05 seconds
Started Feb 29 02:43:37 PM PST 24
Finished Feb 29 02:44:10 PM PST 24
Peak memory 438236 kb
Host smart-014647be-2cfc-49eb-a34a-92f3367e61c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602677595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3602677595
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.317967066
Short name T48
Test name
Test status
Simulation time 470220492 ps
CPU time 2.64 seconds
Started Feb 29 02:43:47 PM PST 24
Finished Feb 29 02:43:50 PM PST 24
Peak memory 203628 kb
Host smart-d93f60c0-7f5c-4b05-b0ba-a17a4d167e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317967066 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.317967066
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2383275610
Short name T1128
Test name
Test status
Simulation time 730770202 ps
CPU time 3.79 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:43:43 PM PST 24
Peak memory 203704 kb
Host smart-e535831b-ddc5-465c-a93d-ad6fba9db040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383275610 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2383275610
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.362473537
Short name T305
Test name
Test status
Simulation time 9918861335 ps
CPU time 19.11 seconds
Started Feb 29 02:43:42 PM PST 24
Finished Feb 29 02:44:01 PM PST 24
Peak memory 487852 kb
Host smart-2ea393c0-adc5-456f-829b-6d56ba24095b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362473537 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.362473537
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_perf.1142811579
Short name T846
Test name
Test status
Simulation time 1176123682 ps
CPU time 5.28 seconds
Started Feb 29 02:43:44 PM PST 24
Finished Feb 29 02:43:50 PM PST 24
Peak memory 205704 kb
Host smart-4fd16cf2-4047-4397-b17f-4520dc6ecbc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142811579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_perf.1142811579
Directory /workspace/2.i2c_target_perf/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.1566083670
Short name T997
Test name
Test status
Simulation time 36142232198 ps
CPU time 1413.52 seconds
Started Feb 29 02:43:40 PM PST 24
Finished Feb 29 03:07:14 PM PST 24
Peak memory 6278940 kb
Host smart-d52ad914-a620-4ca0-bdc4-4771ed8f3bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566083670 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.1566083670
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.167223079
Short name T932
Test name
Test status
Simulation time 438790932 ps
CPU time 18.69 seconds
Started Feb 29 02:43:44 PM PST 24
Finished Feb 29 02:44:03 PM PST 24
Peak memory 203628 kb
Host smart-e524617e-aa5e-4b99-acd3-ce112cade538
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167223079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_rd.167223079
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3522111013
Short name T374
Test name
Test status
Simulation time 28386563342 ps
CPU time 237.74 seconds
Started Feb 29 02:43:44 PM PST 24
Finished Feb 29 02:47:42 PM PST 24
Peak memory 3150044 kb
Host smart-220fd67f-0272-4b15-a4ca-7de2a5893875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522111013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3522111013
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.4024766496
Short name T304
Test name
Test status
Simulation time 12955779966 ps
CPU time 219.76 seconds
Started Feb 29 02:43:37 PM PST 24
Finished Feb 29 02:47:17 PM PST 24
Peak memory 2075300 kb
Host smart-3c4eb71b-f727-433e-aee6-ab6930c6f398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024766496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.4024766496
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3080079377
Short name T898
Test name
Test status
Simulation time 2268014735 ps
CPU time 8.1 seconds
Started Feb 29 02:43:38 PM PST 24
Finished Feb 29 02:43:47 PM PST 24
Peak memory 206572 kb
Host smart-b0d5a3e2-e4bd-43b6-9f14-4394f534cfc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080079377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3080079377
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.411657006
Short name T1048
Test name
Test status
Simulation time 982772484 ps
CPU time 5.63 seconds
Started Feb 29 02:43:48 PM PST 24
Finished Feb 29 02:43:54 PM PST 24
Peak memory 203640 kb
Host smart-6f1a1d2b-3c62-44ed-87b4-6f54036a5815
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411657006 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_unexp_stop.411657006
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.234700502
Short name T539
Test name
Test status
Simulation time 70658501 ps
CPU time 0.61 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:47:06 PM PST 24
Peak memory 203508 kb
Host smart-b7356f7a-0aac-4f76-abc9-0dd01fe4ca64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234700502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.234700502
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3500952583
Short name T1256
Test name
Test status
Simulation time 42336503 ps
CPU time 1.25 seconds
Started Feb 29 02:46:58 PM PST 24
Finished Feb 29 02:46:59 PM PST 24
Peak memory 211968 kb
Host smart-bfb616ce-2640-43f5-8842-e1535265f90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500952583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3500952583
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.879351307
Short name T742
Test name
Test status
Simulation time 2316452281 ps
CPU time 7.57 seconds
Started Feb 29 02:47:03 PM PST 24
Finished Feb 29 02:47:11 PM PST 24
Peak memory 280508 kb
Host smart-316649d1-f552-42c9-b271-34941f0b25ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879351307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.879351307
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.992951983
Short name T376
Test name
Test status
Simulation time 1840470104 ps
CPU time 51.53 seconds
Started Feb 29 02:47:04 PM PST 24
Finished Feb 29 02:47:56 PM PST 24
Peak memory 623836 kb
Host smart-30dade23-b450-4967-8d1c-6390e5edbafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992951983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.992951983
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2596575426
Short name T1287
Test name
Test status
Simulation time 1702366838 ps
CPU time 109.38 seconds
Started Feb 29 02:46:59 PM PST 24
Finished Feb 29 02:48:49 PM PST 24
Peak memory 591452 kb
Host smart-609ea27f-5b50-4555-a072-5e3a653693c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596575426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2596575426
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2723613644
Short name T164
Test name
Test status
Simulation time 763145459 ps
CPU time 9.92 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:47:16 PM PST 24
Peak memory 203376 kb
Host smart-b9008a17-2f6d-4d31-9812-188383e50326
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723613644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2723613644
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3886893747
Short name T1177
Test name
Test status
Simulation time 1516731338 ps
CPU time 84.37 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:48:26 PM PST 24
Peak memory 247888 kb
Host smart-2bcf8db7-b166-41f9-8e6c-2cfd5f1901c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886893747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3886893747
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3381918149
Short name T479
Test name
Test status
Simulation time 24840030 ps
CPU time 0.62 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:47:01 PM PST 24
Peak memory 202732 kb
Host smart-ba70ade2-2a2b-42ed-9951-742d9d64f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381918149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3381918149
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1410299011
Short name T527
Test name
Test status
Simulation time 13816367916 ps
CPU time 58.19 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:48:04 PM PST 24
Peak memory 276552 kb
Host smart-9aeb7901-0070-4c8c-8d13-3628f1383890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410299011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1410299011
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_rx_oversample.1975730979
Short name T319
Test name
Test status
Simulation time 8942492243 ps
CPU time 161.14 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:49:42 PM PST 24
Peak memory 349948 kb
Host smart-a4c09438-ef65-4996-b10f-844b3b24d48e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975730979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_rx_oversample
.1975730979
Directory /workspace/20.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.3045683071
Short name T282
Test name
Test status
Simulation time 4996808264 ps
CPU time 144.28 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:49:27 PM PST 24
Peak memory 244508 kb
Host smart-01bdb932-1217-43f8-8f8b-e160f9e756e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045683071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3045683071
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3312288707
Short name T824
Test name
Test status
Simulation time 610157770 ps
CPU time 29.79 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:47:32 PM PST 24
Peak memory 212020 kb
Host smart-882faddc-37ba-4e5f-afe4-be618d4d0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312288707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3312288707
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.1745140629
Short name T297
Test name
Test status
Simulation time 2195182195 ps
CPU time 4.36 seconds
Started Feb 29 02:47:03 PM PST 24
Finished Feb 29 02:47:07 PM PST 24
Peak memory 203700 kb
Host smart-4e8bc038-a1dd-4f8c-b707-48a4132215fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745140629 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.1745140629
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1449064139
Short name T223
Test name
Test status
Simulation time 10230487751 ps
CPU time 16.04 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:18 PM PST 24
Peak memory 290932 kb
Host smart-c1f78ca5-b0e2-417c-80ff-7c26c602cb1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449064139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1449064139
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2305520664
Short name T175
Test name
Test status
Simulation time 10480689323 ps
CPU time 8.79 seconds
Started Feb 29 02:47:03 PM PST 24
Finished Feb 29 02:47:12 PM PST 24
Peak memory 263888 kb
Host smart-3e69062e-10e6-484f-aafa-2f557e37741c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305520664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2305520664
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1739239920
Short name T204
Test name
Test status
Simulation time 692556582 ps
CPU time 2 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:04 PM PST 24
Peak memory 203632 kb
Host smart-66961e34-57e4-442c-bb07-05f7232693e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739239920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1739239920
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.193333198
Short name T1283
Test name
Test status
Simulation time 5433445579 ps
CPU time 4.67 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:47:06 PM PST 24
Peak memory 203660 kb
Host smart-2a2d223c-3d90-4f44-99d3-e98d54be237f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193333198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.193333198
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.225967361
Short name T741
Test name
Test status
Simulation time 21169707631 ps
CPU time 295.71 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:51:57 PM PST 24
Peak memory 2633424 kb
Host smart-f48f6c2b-9e95-485b-b768-af26a5935258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225967361 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.225967361
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_perf.3675861739
Short name T508
Test name
Test status
Simulation time 2056149114 ps
CPU time 3.62 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:47:05 PM PST 24
Peak memory 203760 kb
Host smart-408abe10-ac57-45a6-bb6c-a4b38aab4d1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675861739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_perf.3675861739
Directory /workspace/20.i2c_target_perf/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.4146647523
Short name T393
Test name
Test status
Simulation time 7126661896 ps
CPU time 16.51 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:47:17 PM PST 24
Peak memory 203772 kb
Host smart-6e2f088b-aef4-49cd-ba40-4dddfb46059d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146647523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.4146647523
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.1018050351
Short name T44
Test name
Test status
Simulation time 12672332783 ps
CPU time 19.85 seconds
Started Feb 29 02:46:56 PM PST 24
Finished Feb 29 02:47:16 PM PST 24
Peak memory 649032 kb
Host smart-ea9fb5cb-e496-483e-95d1-cd9369190b6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018050351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.1018050351
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3090056341
Short name T716
Test name
Test status
Simulation time 40316933340 ps
CPU time 2851.05 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 03:34:33 PM PST 24
Peak memory 7976028 kb
Host smart-87252378-38b8-4843-9ea9-2bc2a2c5d9e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090056341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3090056341
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.478423084
Short name T865
Test name
Test status
Simulation time 1762089620 ps
CPU time 7.22 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:09 PM PST 24
Peak memory 204764 kb
Host smart-95dae178-3726-466e-8a5c-d338d8750270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478423084 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.478423084
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.3272776398
Short name T766
Test name
Test status
Simulation time 6918974159 ps
CPU time 4.9 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:07 PM PST 24
Peak memory 203708 kb
Host smart-b325d266-3f78-43ed-a813-e04331b60490
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272776398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.3272776398
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3488840884
Short name T1006
Test name
Test status
Simulation time 19084908 ps
CPU time 0.64 seconds
Started Feb 29 02:47:07 PM PST 24
Finished Feb 29 02:47:07 PM PST 24
Peak memory 202572 kb
Host smart-7da67213-b8d9-47a2-b49f-19b1b1c70fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488840884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3488840884
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.679663966
Short name T182
Test name
Test status
Simulation time 143199369 ps
CPU time 1.3 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:47:02 PM PST 24
Peak memory 214860 kb
Host smart-0fab40a9-ffce-4b69-8372-4eae070614cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679663966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.679663966
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3773858650
Short name T427
Test name
Test status
Simulation time 2557146952 ps
CPU time 12.6 seconds
Started Feb 29 02:47:01 PM PST 24
Finished Feb 29 02:47:14 PM PST 24
Peak memory 353628 kb
Host smart-d0e107d5-e961-4c46-8267-0f311eade681
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773858650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3773858650
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.458182410
Short name T1231
Test name
Test status
Simulation time 15816067856 ps
CPU time 51 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:47:57 PM PST 24
Peak memory 638496 kb
Host smart-07dd5bcf-ae99-4894-8763-9e9240852d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458182410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.458182410
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3869734730
Short name T1290
Test name
Test status
Simulation time 6605989779 ps
CPU time 124.84 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:49:11 PM PST 24
Peak memory 969616 kb
Host smart-54e4b94c-eb10-4146-8ce0-3e31854df17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869734730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3869734730
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2713945867
Short name T163
Test name
Test status
Simulation time 183794593 ps
CPU time 9.35 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:47:12 PM PST 24
Peak memory 203784 kb
Host smart-d86f3cc0-c6fa-495f-9e87-a48c2a9c85e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713945867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2713945867
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.580155257
Short name T1107
Test name
Test status
Simulation time 7054332278 ps
CPU time 255.8 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:51:22 PM PST 24
Peak memory 1081328 kb
Host smart-fd128b4b-7843-4245-b8a1-bc9a4de24583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580155257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.580155257
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.3341411450
Short name T545
Test name
Test status
Simulation time 13937676155 ps
CPU time 106 seconds
Started Feb 29 02:47:03 PM PST 24
Finished Feb 29 02:48:49 PM PST 24
Peak memory 260796 kb
Host smart-0471f9df-1cda-4311-896a-4db0daa9eca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341411450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.3341411450
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1679773576
Short name T337
Test name
Test status
Simulation time 44836439 ps
CPU time 0.63 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:47:06 PM PST 24
Peak memory 202488 kb
Host smart-635cb18b-6fbb-41f6-844c-22fc14827c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679773576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1679773576
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.191974702
Short name T1220
Test name
Test status
Simulation time 481387004 ps
CPU time 8.68 seconds
Started Feb 29 02:47:04 PM PST 24
Finished Feb 29 02:47:13 PM PST 24
Peak memory 211876 kb
Host smart-014ce2b7-4b01-4dd3-a107-8b871fdcc498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191974702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.191974702
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_rx_oversample.3349024318
Short name T697
Test name
Test status
Simulation time 2982919903 ps
CPU time 113.79 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:48:56 PM PST 24
Peak memory 262116 kb
Host smart-da3a29ca-d8ff-4a09-b505-497481dbed56
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349024318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_rx_oversample
.3349024318
Directory /workspace/21.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3449702849
Short name T272
Test name
Test status
Simulation time 1527570467 ps
CPU time 73.41 seconds
Started Feb 29 02:47:02 PM PST 24
Finished Feb 29 02:48:16 PM PST 24
Peak memory 219944 kb
Host smart-aa2d4243-5589-4e4d-bd99-340c3bf04c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449702849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3449702849
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2893015333
Short name T1086
Test name
Test status
Simulation time 876061536 ps
CPU time 15.58 seconds
Started Feb 29 02:47:07 PM PST 24
Finished Feb 29 02:47:22 PM PST 24
Peak memory 211840 kb
Host smart-b0cafc78-3ef4-4e74-93d3-cfcba5ba38f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893015333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2893015333
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2405882574
Short name T1166
Test name
Test status
Simulation time 1019138048 ps
CPU time 2.64 seconds
Started Feb 29 02:47:10 PM PST 24
Finished Feb 29 02:47:14 PM PST 24
Peak memory 203644 kb
Host smart-be814945-3726-4a72-b3a8-7fdda2ce56c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405882574 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2405882574
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3331141213
Short name T632
Test name
Test status
Simulation time 10073251108 ps
CPU time 66.36 seconds
Started Feb 29 02:47:11 PM PST 24
Finished Feb 29 02:48:17 PM PST 24
Peak memory 597732 kb
Host smart-389793ca-0a42-48a2-a9e3-06742ad02162
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331141213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3331141213
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.4244895344
Short name T522
Test name
Test status
Simulation time 6881206116 ps
CPU time 3.09 seconds
Started Feb 29 02:47:07 PM PST 24
Finished Feb 29 02:47:10 PM PST 24
Peak memory 203708 kb
Host smart-c7648323-44b8-4225-8acc-51539c9a27fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244895344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.4244895344
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1708513176
Short name T797
Test name
Test status
Simulation time 1023343896 ps
CPU time 4.62 seconds
Started Feb 29 02:47:00 PM PST 24
Finished Feb 29 02:47:05 PM PST 24
Peak memory 207168 kb
Host smart-901f1f75-228d-42b6-a8c2-c930b447682c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708513176 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1708513176
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2267169434
Short name T400
Test name
Test status
Simulation time 25084340850 ps
CPU time 146.65 seconds
Started Feb 29 02:47:05 PM PST 24
Finished Feb 29 02:49:32 PM PST 24
Peak memory 1566412 kb
Host smart-59ed3845-59cd-4743-bc3d-2ce386a495a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267169434 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2267169434
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_perf.3049944621
Short name T2
Test name
Test status
Simulation time 3677439011 ps
CPU time 4.2 seconds
Started Feb 29 02:47:07 PM PST 24
Finished Feb 29 02:47:12 PM PST 24
Peak memory 203708 kb
Host smart-b4603071-5fb4-445c-87ad-9a83a3077199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049944621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_perf.3049944621
Directory /workspace/21.i2c_target_perf/latest

Test location /workspace/coverage/default/21.i2c_target_stress_all.3480990032
Short name T303
Test name
Test status
Simulation time 18028811471 ps
CPU time 362.18 seconds
Started Feb 29 02:47:06 PM PST 24
Finished Feb 29 02:53:09 PM PST 24
Peak memory 2350192 kb
Host smart-00d31b09-dac3-4aa3-9c89-350d8423b25a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480990032 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_stress_all.3480990032
Directory /workspace/21.i2c_target_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1507981617
Short name T301
Test name
Test status
Simulation time 1331032432 ps
CPU time 51.94 seconds
Started Feb 29 02:47:07 PM PST 24
Finished Feb 29 02:48:00 PM PST 24
Peak memory 204644 kb
Host smart-ed8d8c91-14da-4060-93a8-e68f9e15820d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507981617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1507981617
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.858018762
Short name T756
Test name
Test status
Simulation time 58586104355 ps
CPU time 3243.14 seconds
Started Feb 29 02:47:07 PM PST 24
Finished Feb 29 03:41:11 PM PST 24
Peak memory 13742696 kb
Host smart-956449d3-b16c-4c28-a2af-6bae66fc7eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858018762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.858018762
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1410732396
Short name T953
Test name
Test status
Simulation time 3755632312 ps
CPU time 94.1 seconds
Started Feb 29 02:47:11 PM PST 24
Finished Feb 29 02:48:45 PM PST 24
Peak memory 1034804 kb
Host smart-709a561b-ef4d-407a-9787-b5648366341f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410732396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1410732396
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2480183706
Short name T229
Test name
Test status
Simulation time 3846513151 ps
CPU time 8.49 seconds
Started Feb 29 02:47:11 PM PST 24
Finished Feb 29 02:47:19 PM PST 24
Peak memory 211612 kb
Host smart-fd013100-ecdd-4d4a-822a-202cf2018eaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480183706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2480183706
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.3333396176
Short name T572
Test name
Test status
Simulation time 3962078079 ps
CPU time 5.36 seconds
Started Feb 29 02:47:03 PM PST 24
Finished Feb 29 02:47:08 PM PST 24
Peak memory 203704 kb
Host smart-bcc91042-49de-4401-a993-1e6081e5292b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333396176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.3333396176
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3634202239
Short name T1060
Test name
Test status
Simulation time 18916951 ps
CPU time 0.6 seconds
Started Feb 29 02:47:16 PM PST 24
Finished Feb 29 02:47:17 PM PST 24
Peak memory 202560 kb
Host smart-f015f642-6832-4cd9-afd6-aef6713f8c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634202239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3634202239
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2386947057
Short name T1294
Test name
Test status
Simulation time 42645668 ps
CPU time 1.11 seconds
Started Feb 29 02:47:13 PM PST 24
Finished Feb 29 02:47:14 PM PST 24
Peak memory 203624 kb
Host smart-c8f221f9-46eb-4f48-ac5d-cee2a7f2037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386947057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2386947057
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.828696544
Short name T1298
Test name
Test status
Simulation time 5532006449 ps
CPU time 23.98 seconds
Started Feb 29 02:47:13 PM PST 24
Finished Feb 29 02:47:37 PM PST 24
Peak memory 304864 kb
Host smart-9d2bfa8c-272b-4a07-92ee-8a901e7d249c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828696544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.828696544
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.407072792
Short name T431
Test name
Test status
Simulation time 3470735886 ps
CPU time 297.71 seconds
Started Feb 29 02:47:13 PM PST 24
Finished Feb 29 02:52:11 PM PST 24
Peak memory 1058716 kb
Host smart-0e39079e-ae49-4d64-b7e7-5f5b50ef805d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407072792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.407072792
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2368659983
Short name T1219
Test name
Test status
Simulation time 11389690473 ps
CPU time 239.57 seconds
Started Feb 29 02:47:15 PM PST 24
Finished Feb 29 02:51:15 PM PST 24
Peak memory 894016 kb
Host smart-fa02fdf6-0673-4f9c-83c0-20ba18bf63da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368659983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2368659983
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.442516951
Short name T1031
Test name
Test status
Simulation time 829807979 ps
CPU time 5.28 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:47:19 PM PST 24
Peak memory 203636 kb
Host smart-1b4a37f9-1527-4a1b-8a35-f1f62392bee1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442516951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
442516951
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1810739538
Short name T128
Test name
Test status
Simulation time 18963715068 ps
CPU time 99.02 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:48:53 PM PST 24
Peak memory 1205820 kb
Host smart-dcafd84e-7a0e-4774-a84f-4ce9253d3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810739538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1810739538
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.1535086419
Short name T906
Test name
Test status
Simulation time 2647846758 ps
CPU time 44.94 seconds
Started Feb 29 02:47:16 PM PST 24
Finished Feb 29 02:48:01 PM PST 24
Peak memory 278588 kb
Host smart-ae1b9c9d-3128-4d40-b67e-ed8c607062a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535086419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.1535086419
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1514872627
Short name T607
Test name
Test status
Simulation time 42079718 ps
CPU time 0.61 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:47:14 PM PST 24
Peak memory 202852 kb
Host smart-d1a12658-2fae-4ae7-a1e0-4f3c7d2779e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514872627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1514872627
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2376680647
Short name T595
Test name
Test status
Simulation time 7374325830 ps
CPU time 303.08 seconds
Started Feb 29 02:47:16 PM PST 24
Finished Feb 29 02:52:19 PM PST 24
Peak memory 211976 kb
Host smart-ce25a86b-cb47-4ec7-9f7e-4d6234eb514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376680647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2376680647
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_rx_oversample.853005247
Short name T568
Test name
Test status
Simulation time 2784188965 ps
CPU time 106.48 seconds
Started Feb 29 02:47:19 PM PST 24
Finished Feb 29 02:49:06 PM PST 24
Peak memory 308752 kb
Host smart-f4466c70-ef18-4994-b5e8-e88c4fbd202d
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853005247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_rx_oversample.
853005247
Directory /workspace/22.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2982877547
Short name T543
Test name
Test status
Simulation time 2307117734 ps
CPU time 75.42 seconds
Started Feb 29 02:47:09 PM PST 24
Finished Feb 29 02:48:25 PM PST 24
Peak memory 347340 kb
Host smart-4412ed22-07ec-4a7f-a400-beff82c9a498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982877547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2982877547
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3598987448
Short name T684
Test name
Test status
Simulation time 5556799713 ps
CPU time 62.33 seconds
Started Feb 29 02:47:15 PM PST 24
Finished Feb 29 02:48:18 PM PST 24
Peak memory 215732 kb
Host smart-3cd42c20-4955-4f17-8011-4029c2e7f364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598987448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3598987448
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1347205593
Short name T644
Test name
Test status
Simulation time 7592075699 ps
CPU time 4.34 seconds
Started Feb 29 02:47:15 PM PST 24
Finished Feb 29 02:47:20 PM PST 24
Peak memory 203724 kb
Host smart-02d6ca86-b64e-46ea-b22e-8d90a9cef316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347205593 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1347205593
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.592212777
Short name T606
Test name
Test status
Simulation time 10187904481 ps
CPU time 12.91 seconds
Started Feb 29 02:47:19 PM PST 24
Finished Feb 29 02:47:32 PM PST 24
Peak memory 291012 kb
Host smart-bf1de187-1472-4567-884d-20d03fc160d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592212777 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_acq.592212777
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1241708718
Short name T737
Test name
Test status
Simulation time 11044768185 ps
CPU time 5.08 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:47:20 PM PST 24
Peak memory 235360 kb
Host smart-8ee67432-bf7e-48e9-bdfe-b46deeed1ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241708718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1241708718
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2041681
Short name T351
Test name
Test status
Simulation time 1563836677 ps
CPU time 2.23 seconds
Started Feb 29 02:47:16 PM PST 24
Finished Feb 29 02:47:18 PM PST 24
Peak memory 203640 kb
Host smart-4b783705-dbfd-446a-ba71-77224a0a7495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041681 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.i2c_target_hrst.2041681
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2005858008
Short name T469
Test name
Test status
Simulation time 6803290864 ps
CPU time 7.53 seconds
Started Feb 29 02:47:15 PM PST 24
Finished Feb 29 02:47:23 PM PST 24
Peak memory 208260 kb
Host smart-661ee433-9878-4047-aaf1-1e8fb1b717d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005858008 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2005858008
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1457103364
Short name T700
Test name
Test status
Simulation time 14842852291 ps
CPU time 300.61 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:52:15 PM PST 24
Peak memory 3449592 kb
Host smart-10394ff2-f504-494c-a8df-d25eeb492df1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457103364 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1457103364
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_perf.1641085821
Short name T453
Test name
Test status
Simulation time 478567906 ps
CPU time 2.98 seconds
Started Feb 29 02:47:16 PM PST 24
Finished Feb 29 02:47:19 PM PST 24
Peak memory 203668 kb
Host smart-f030dd51-e746-45af-8d82-e139e19dd549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641085821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_perf.1641085821
Directory /workspace/22.i2c_target_perf/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.2906928598
Short name T1147
Test name
Test status
Simulation time 92354502369 ps
CPU time 627.44 seconds
Started Feb 29 02:47:19 PM PST 24
Finished Feb 29 02:57:47 PM PST 24
Peak memory 3282340 kb
Host smart-45077e5b-1cc9-4809-a5b0-fdc4f64f2738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906928598 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.2906928598
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.938175030
Short name T256
Test name
Test status
Simulation time 6549523728 ps
CPU time 68.73 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:48:23 PM PST 24
Peak memory 204628 kb
Host smart-b8932a76-e81e-4c06-a04b-9cb4c9b0d877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938175030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.938175030
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3476564743
Short name T1176
Test name
Test status
Simulation time 56189595009 ps
CPU time 1046.03 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 03:04:41 PM PST 24
Peak memory 6481748 kb
Host smart-39406941-4c02-4f0a-9a36-c1dd80740c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476564743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3476564743
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.514891521
Short name T754
Test name
Test status
Simulation time 17661908795 ps
CPU time 309.91 seconds
Started Feb 29 02:47:13 PM PST 24
Finished Feb 29 02:52:23 PM PST 24
Peak memory 1148784 kb
Host smart-99b4aa90-d05b-4002-b617-1026260d7a62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514891521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.514891521
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2676061828
Short name T679
Test name
Test status
Simulation time 7269802368 ps
CPU time 7.56 seconds
Started Feb 29 02:47:15 PM PST 24
Finished Feb 29 02:47:23 PM PST 24
Peak memory 214184 kb
Host smart-38031031-4e06-4e75-ac84-34310762bb3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676061828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2676061828
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.1219046105
Short name T558
Test name
Test status
Simulation time 1034946589 ps
CPU time 5.25 seconds
Started Feb 29 02:47:19 PM PST 24
Finished Feb 29 02:47:25 PM PST 24
Peak memory 203708 kb
Host smart-8a96787d-f46a-4caa-9c9b-c85f0232c9b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219046105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.i2c_target_unexp_stop.1219046105
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.760351313
Short name T1160
Test name
Test status
Simulation time 62189881 ps
CPU time 0.61 seconds
Started Feb 29 02:47:35 PM PST 24
Finished Feb 29 02:47:35 PM PST 24
Peak memory 203524 kb
Host smart-9577965c-5f64-4dc8-a069-0500d58598f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760351313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.760351313
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2674489480
Short name T1184
Test name
Test status
Simulation time 53230055 ps
CPU time 1.47 seconds
Started Feb 29 02:47:26 PM PST 24
Finished Feb 29 02:47:27 PM PST 24
Peak memory 211796 kb
Host smart-4e8f5e7d-eb69-4128-a663-9c5ed23c0989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674489480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2674489480
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2475533684
Short name T598
Test name
Test status
Simulation time 494038851 ps
CPU time 27.1 seconds
Started Feb 29 02:47:27 PM PST 24
Finished Feb 29 02:47:54 PM PST 24
Peak memory 315656 kb
Host smart-c289e3a8-17b9-41a5-aaee-ba5d31677959
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475533684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2475533684
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1114502433
Short name T1202
Test name
Test status
Simulation time 2341676259 ps
CPU time 68.61 seconds
Started Feb 29 02:47:24 PM PST 24
Finished Feb 29 02:48:33 PM PST 24
Peak memory 667340 kb
Host smart-e577621e-fd95-4ff9-b772-b1b8c2c37c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114502433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1114502433
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1300198285
Short name T851
Test name
Test status
Simulation time 12131995491 ps
CPU time 257.83 seconds
Started Feb 29 02:47:19 PM PST 24
Finished Feb 29 02:51:37 PM PST 24
Peak memory 958224 kb
Host smart-08e85858-4285-472f-85cd-9e3c9f7bae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300198285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1300198285
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1422740862
Short name T817
Test name
Test status
Simulation time 159544687 ps
CPU time 9.8 seconds
Started Feb 29 02:47:35 PM PST 24
Finished Feb 29 02:47:45 PM PST 24
Peak memory 232272 kb
Host smart-a34124ce-7964-4f60-9869-317b35e9ffa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422740862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1422740862
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3607681780
Short name T1122
Test name
Test status
Simulation time 7242660859 ps
CPU time 220.98 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:50:55 PM PST 24
Peak memory 2001180 kb
Host smart-9154c201-aa98-4354-be67-6a8aa35a9f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607681780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3607681780
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_override.1393239785
Short name T455
Test name
Test status
Simulation time 43070694 ps
CPU time 0.63 seconds
Started Feb 29 02:47:14 PM PST 24
Finished Feb 29 02:47:15 PM PST 24
Peak memory 202800 kb
Host smart-676f0894-b38e-40a7-a43f-9acb66434561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393239785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1393239785
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1343438975
Short name T1120
Test name
Test status
Simulation time 7580546749 ps
CPU time 97.07 seconds
Started Feb 29 02:47:24 PM PST 24
Finished Feb 29 02:49:02 PM PST 24
Peak memory 211948 kb
Host smart-bb10d9ee-52a9-4ad8-a097-3bf0ac76e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343438975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1343438975
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_rx_oversample.4093670729
Short name T880
Test name
Test status
Simulation time 10773743005 ps
CPU time 75.82 seconds
Started Feb 29 02:47:15 PM PST 24
Finished Feb 29 02:48:31 PM PST 24
Peak memory 326096 kb
Host smart-69e34220-f7ea-44f1-bbd1-3f08a57632b5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093670729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_rx_oversample
.4093670729
Directory /workspace/23.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2336118794
Short name T591
Test name
Test status
Simulation time 5358024155 ps
CPU time 153.36 seconds
Started Feb 29 02:47:19 PM PST 24
Finished Feb 29 02:49:52 PM PST 24
Peak memory 249876 kb
Host smart-428239a9-2bd7-4410-b7a7-4da7db7bc279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336118794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2336118794
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.3035755909
Short name T159
Test name
Test status
Simulation time 38850386205 ps
CPU time 374.85 seconds
Started Feb 29 02:47:24 PM PST 24
Finished Feb 29 02:53:39 PM PST 24
Peak memory 1200000 kb
Host smart-eb01765c-0935-464c-832d-5ea31f710293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035755909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.3035755909
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3989762314
Short name T137
Test name
Test status
Simulation time 695341869 ps
CPU time 10.36 seconds
Started Feb 29 02:47:35 PM PST 24
Finished Feb 29 02:47:45 PM PST 24
Peak memory 219740 kb
Host smart-7d2b5d08-9fbb-48ef-91a2-1df71323a6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989762314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3989762314
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1979350569
Short name T1214
Test name
Test status
Simulation time 773445126 ps
CPU time 3.06 seconds
Started Feb 29 02:47:25 PM PST 24
Finished Feb 29 02:47:28 PM PST 24
Peak memory 203776 kb
Host smart-c2b31786-4116-4af1-8338-aaa652c859bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979350569 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1979350569
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.11554250
Short name T864
Test name
Test status
Simulation time 10294195944 ps
CPU time 13.88 seconds
Started Feb 29 02:47:23 PM PST 24
Finished Feb 29 02:47:37 PM PST 24
Peak memory 253972 kb
Host smart-f63d77a2-5bda-4ae5-83e3-89343b35c942
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11554250 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_acq.11554250
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1575737173
Short name T1140
Test name
Test status
Simulation time 10161295383 ps
CPU time 36.34 seconds
Started Feb 29 02:47:24 PM PST 24
Finished Feb 29 02:48:00 PM PST 24
Peak memory 477256 kb
Host smart-758bf953-5e75-4dd9-93f5-63c4ac277e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575737173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1575737173
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2341043596
Short name T517
Test name
Test status
Simulation time 1805395264 ps
CPU time 2.32 seconds
Started Feb 29 02:47:35 PM PST 24
Finished Feb 29 02:47:38 PM PST 24
Peak memory 203616 kb
Host smart-1ce8ffc4-77fe-49cb-a2f6-c1d44d48834e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341043596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2341043596
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3648949379
Short name T463
Test name
Test status
Simulation time 2622542150 ps
CPU time 5.73 seconds
Started Feb 29 02:47:26 PM PST 24
Finished Feb 29 02:47:32 PM PST 24
Peak memory 203688 kb
Host smart-46eacf9f-3b82-4170-bc95-140ed19e187b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648949379 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3648949379
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3943834700
Short name T1105
Test name
Test status
Simulation time 15200089251 ps
CPU time 46.81 seconds
Started Feb 29 02:47:36 PM PST 24
Finished Feb 29 02:48:23 PM PST 24
Peak memory 819208 kb
Host smart-8c40fb92-2163-4cb8-89c8-08c3d72f2b6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943834700 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3943834700
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_perf.3231523899
Short name T673
Test name
Test status
Simulation time 791298600 ps
CPU time 4.49 seconds
Started Feb 29 02:47:36 PM PST 24
Finished Feb 29 02:47:40 PM PST 24
Peak memory 203624 kb
Host smart-a123f9b7-e820-42d0-861f-5aa682b54536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231523899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_perf.3231523899
Directory /workspace/23.i2c_target_perf/latest

Test location /workspace/coverage/default/23.i2c_target_stress_all.2787093067
Short name T228
Test name
Test status
Simulation time 48684356757 ps
CPU time 139.91 seconds
Started Feb 29 02:47:25 PM PST 24
Finished Feb 29 02:49:45 PM PST 24
Peak memory 899820 kb
Host smart-841b8213-c2c7-4671-a124-da215a1fb4ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787093067 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_stress_all.2787093067
Directory /workspace/23.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1570515719
Short name T808
Test name
Test status
Simulation time 1719734814 ps
CPU time 7.56 seconds
Started Feb 29 02:47:23 PM PST 24
Finished Feb 29 02:47:31 PM PST 24
Peak memory 203664 kb
Host smart-6f8afadf-5bc0-4da2-8a13-fee7e4cae665
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570515719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1570515719
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2692018843
Short name T526
Test name
Test status
Simulation time 43310992173 ps
CPU time 1363.61 seconds
Started Feb 29 02:47:27 PM PST 24
Finished Feb 29 03:10:11 PM PST 24
Peak memory 8714148 kb
Host smart-488a1120-3599-4014-bce0-0fc7ed0a0614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692018843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2692018843
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3803035082
Short name T428
Test name
Test status
Simulation time 9241516268 ps
CPU time 894.47 seconds
Started Feb 29 02:47:24 PM PST 24
Finished Feb 29 03:02:18 PM PST 24
Peak memory 2235304 kb
Host smart-ca4e99b3-0836-4a68-9fcf-858fadabb904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803035082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3803035082
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.601050275
Short name T320
Test name
Test status
Simulation time 7294043857 ps
CPU time 7.29 seconds
Started Feb 29 02:47:35 PM PST 24
Finished Feb 29 02:47:43 PM PST 24
Peak memory 203728 kb
Host smart-cd40ab1d-1f84-4f7e-878b-036419264d8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601050275 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.601050275
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.580744137
Short name T1001
Test name
Test status
Simulation time 28125781133 ps
CPU time 6.5 seconds
Started Feb 29 02:47:24 PM PST 24
Finished Feb 29 02:47:31 PM PST 24
Peak memory 210924 kb
Host smart-a8ad256d-5437-4837-9494-a7041064787e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580744137 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_unexp_stop.580744137
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2668726285
Short name T1089
Test name
Test status
Simulation time 22734053 ps
CPU time 0.6 seconds
Started Feb 29 02:47:50 PM PST 24
Finished Feb 29 02:47:51 PM PST 24
Peak memory 202584 kb
Host smart-169a8435-2727-4ae7-86a5-6ad636571634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668726285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2668726285
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.359496664
Short name T248
Test name
Test status
Simulation time 218142656 ps
CPU time 1.84 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 02:47:36 PM PST 24
Peak memory 211852 kb
Host smart-08a7dc27-297a-45bb-95ad-1cf54b2a1ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359496664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.359496664
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.885383466
Short name T206
Test name
Test status
Simulation time 428115914 ps
CPU time 8.46 seconds
Started Feb 29 02:47:32 PM PST 24
Finished Feb 29 02:47:41 PM PST 24
Peak memory 289704 kb
Host smart-0dd1beb9-645c-451c-85eb-c99c518b0d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885383466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.885383466
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.445109973
Short name T618
Test name
Test status
Simulation time 5232482644 ps
CPU time 340.46 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 02:53:15 PM PST 24
Peak memory 1232544 kb
Host smart-d94b2e3f-6ac1-48de-b95c-25f2646b3cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445109973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.445109973
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2226282558
Short name T1196
Test name
Test status
Simulation time 1545518733 ps
CPU time 109.92 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 02:49:25 PM PST 24
Peak memory 586444 kb
Host smart-0bcdeded-f31a-44ce-9c83-5bc515417922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226282558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2226282558
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.999162699
Short name T894
Test name
Test status
Simulation time 1380540912 ps
CPU time 12.92 seconds
Started Feb 29 02:47:33 PM PST 24
Finished Feb 29 02:47:47 PM PST 24
Peak memory 249264 kb
Host smart-5a700da6-6d31-450f-b2fd-fdca39bc1ab9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999162699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
999162699
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.2888099847
Short name T602
Test name
Test status
Simulation time 1895612789 ps
CPU time 97.26 seconds
Started Feb 29 02:47:46 PM PST 24
Finished Feb 29 02:49:24 PM PST 24
Peak memory 247316 kb
Host smart-3995adb5-3f56-43b5-b4ba-c43ecbc45724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888099847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.2888099847
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3845892818
Short name T552
Test name
Test status
Simulation time 22413692 ps
CPU time 0.66 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 02:47:35 PM PST 24
Peak memory 202780 kb
Host smart-a600b940-741c-4b5b-a31e-9b235d093751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845892818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3845892818
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3455630431
Short name T171
Test name
Test status
Simulation time 8370370889 ps
CPU time 16.54 seconds
Started Feb 29 02:47:33 PM PST 24
Finished Feb 29 02:47:50 PM PST 24
Peak memory 225008 kb
Host smart-479f3e70-03b3-42cf-bc4c-8b8485fe7d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455630431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3455630431
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_rx_oversample.2574753590
Short name T213
Test name
Test status
Simulation time 3550937664 ps
CPU time 72.05 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 02:48:47 PM PST 24
Peak memory 307832 kb
Host smart-e5473c30-2cc9-4752-94ec-65c937be3925
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574753590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_rx_oversample
.2574753590
Directory /workspace/24.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1489904732
Short name T1110
Test name
Test status
Simulation time 6506181381 ps
CPU time 123.81 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 02:49:38 PM PST 24
Peak memory 250144 kb
Host smart-a78661a5-8887-44f3-80d1-6f6f3058087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489904732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1489904732
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3186700016
Short name T449
Test name
Test status
Simulation time 6301222314 ps
CPU time 8.88 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 02:47:43 PM PST 24
Peak memory 211952 kb
Host smart-4f6b857c-35d5-424d-8c99-cb54bdedf751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186700016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3186700016
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4193928859
Short name T1164
Test name
Test status
Simulation time 2247647480 ps
CPU time 4.3 seconds
Started Feb 29 02:47:46 PM PST 24
Finished Feb 29 02:47:51 PM PST 24
Peak memory 203672 kb
Host smart-5c0021be-dc45-4c39-8d02-de9270f6b771
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193928859 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4193928859
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.4023991435
Short name T916
Test name
Test status
Simulation time 10158027425 ps
CPU time 13.22 seconds
Started Feb 29 02:47:47 PM PST 24
Finished Feb 29 02:48:01 PM PST 24
Peak memory 268000 kb
Host smart-e5cc8a37-4ca9-4ef4-b9e9-c97cbcf7a70e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023991435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.4023991435
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3109003834
Short name T687
Test name
Test status
Simulation time 10132510351 ps
CPU time 73.69 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:49:01 PM PST 24
Peak memory 599248 kb
Host smart-900f9fb6-106a-4edb-bd93-3e4f6d247ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109003834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3109003834
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.4237671744
Short name T186
Test name
Test status
Simulation time 617078319 ps
CPU time 2.48 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:47:52 PM PST 24
Peak memory 203708 kb
Host smart-c50e92bf-02fa-4bf7-9ea7-83c33b41f509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237671744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.4237671744
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2513675452
Short name T379
Test name
Test status
Simulation time 2582609268 ps
CPU time 5.18 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:47:54 PM PST 24
Peak memory 207716 kb
Host smart-a6c2988e-38a0-452c-87ea-75de7504c14d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513675452 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2513675452
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.23974502
Short name T155
Test name
Test status
Simulation time 11521188497 ps
CPU time 45.56 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:48:34 PM PST 24
Peak memory 937152 kb
Host smart-8d505fea-0fcd-479e-8857-d0209dc1b455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23974502 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.23974502
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_perf.302311296
Short name T586
Test name
Test status
Simulation time 878922735 ps
CPU time 5.48 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:47:53 PM PST 24
Peak memory 213768 kb
Host smart-d6fbd540-4149-4641-b139-34a46829f182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302311296 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_perf.302311296
Directory /workspace/24.i2c_target_perf/latest

Test location /workspace/coverage/default/24.i2c_target_stress_all.331585193
Short name T819
Test name
Test status
Simulation time 20327137935 ps
CPU time 24.07 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:48:12 PM PST 24
Peak memory 212840 kb
Host smart-6d3c0e3f-c98a-4bf8-baf9-2d743985b3fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331585193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.i2c_target_stress_all.331585193
Directory /workspace/24.i2c_target_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.1723341273
Short name T1097
Test name
Test status
Simulation time 4931050897 ps
CPU time 27.39 seconds
Started Feb 29 02:47:35 PM PST 24
Finished Feb 29 02:48:02 PM PST 24
Peak memory 211900 kb
Host smart-632a7f32-6c6e-4154-a3ec-4852bf9c5ad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723341273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.1723341273
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.4198788835
Short name T253
Test name
Test status
Simulation time 71569649084 ps
CPU time 616.2 seconds
Started Feb 29 02:47:33 PM PST 24
Finished Feb 29 02:57:50 PM PST 24
Peak memory 4374668 kb
Host smart-ed459fdd-ad5b-4bf2-a0fd-a82807a1bd55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198788835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.4198788835
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2936913010
Short name T492
Test name
Test status
Simulation time 44783455953 ps
CPU time 1412.81 seconds
Started Feb 29 02:47:34 PM PST 24
Finished Feb 29 03:11:08 PM PST 24
Peak memory 5134748 kb
Host smart-1099395c-4a63-43af-9a1d-c4aad0fcbac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936913010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2936913010
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1381970304
Short name T1258
Test name
Test status
Simulation time 11035407785 ps
CPU time 7.24 seconds
Started Feb 29 02:47:46 PM PST 24
Finished Feb 29 02:47:54 PM PST 24
Peak memory 203648 kb
Host smart-03ec0706-c443-4480-9876-ac7e86190734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381970304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1381970304
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.632460553
Short name T1129
Test name
Test status
Simulation time 1374680969 ps
CPU time 6.39 seconds
Started Feb 29 02:47:50 PM PST 24
Finished Feb 29 02:47:56 PM PST 24
Peak memory 208940 kb
Host smart-a99952cb-11de-4a4e-bfa0-fa2ba13c8848
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632460553 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_unexp_stop.632460553
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3182452475
Short name T1096
Test name
Test status
Simulation time 18287932 ps
CPU time 0.65 seconds
Started Feb 29 02:48:01 PM PST 24
Finished Feb 29 02:48:02 PM PST 24
Peak memory 202560 kb
Host smart-e4870856-26ed-4a09-8c6b-540a72c1ba00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182452475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3182452475
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.225536265
Short name T410
Test name
Test status
Simulation time 34502457 ps
CPU time 1.59 seconds
Started Feb 29 02:47:50 PM PST 24
Finished Feb 29 02:47:52 PM PST 24
Peak memory 211752 kb
Host smart-c63321c5-2184-45f0-a077-47201081e93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225536265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.225536265
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2075654308
Short name T484
Test name
Test status
Simulation time 3549883731 ps
CPU time 9.95 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:47:59 PM PST 24
Peak memory 301224 kb
Host smart-f6cddfcc-0ea2-46d5-9a79-143fdd3e8f70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075654308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2075654308
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3425671674
Short name T982
Test name
Test status
Simulation time 8832192993 ps
CPU time 142.6 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:50:10 PM PST 24
Peak memory 687964 kb
Host smart-c70a6bce-0aaa-49f2-9764-1c321ba787ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425671674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3425671674
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3232633815
Short name T818
Test name
Test status
Simulation time 9159115459 ps
CPU time 169.98 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:50:38 PM PST 24
Peak memory 751736 kb
Host smart-d2c2c300-ec74-4bcc-8839-7e2f32bd7a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232633815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3232633815
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3679659560
Short name T622
Test name
Test status
Simulation time 379138391 ps
CPU time 3.62 seconds
Started Feb 29 02:47:47 PM PST 24
Finished Feb 29 02:47:51 PM PST 24
Peak memory 203828 kb
Host smart-c043c5ff-7c94-4246-a957-a074d62a09e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679659560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3679659560
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.710824714
Short name T683
Test name
Test status
Simulation time 20186805793 ps
CPU time 312.36 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:53:02 PM PST 24
Peak memory 1152804 kb
Host smart-3a856031-f6f8-41a9-b585-b8a61ad04864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710824714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.710824714
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2948436701
Short name T1218
Test name
Test status
Simulation time 3499307831 ps
CPU time 37.82 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:48:36 PM PST 24
Peak memory 276800 kb
Host smart-749e0b73-0164-47bb-a602-3b976b0a9b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948436701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2948436701
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2403031093
Short name T181
Test name
Test status
Simulation time 50051979 ps
CPU time 0.61 seconds
Started Feb 29 02:47:47 PM PST 24
Finished Feb 29 02:47:48 PM PST 24
Peak memory 202708 kb
Host smart-249cce53-75db-4c51-ad65-2ab37abeeb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403031093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2403031093
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2992500991
Short name T15
Test name
Test status
Simulation time 26534389936 ps
CPU time 537.43 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:56:46 PM PST 24
Peak memory 254284 kb
Host smart-71776563-01a1-4bef-afe2-0810fefe483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992500991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2992500991
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_rx_oversample.3461494539
Short name T816
Test name
Test status
Simulation time 1792836901 ps
CPU time 155.57 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:50:24 PM PST 24
Peak memory 279376 kb
Host smart-f1dc96cb-14f8-4f88-abe6-816f9e1250a1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461494539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_rx_oversample
.3461494539
Directory /workspace/25.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1098391857
Short name T1049
Test name
Test status
Simulation time 7390576358 ps
CPU time 116.19 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:49:46 PM PST 24
Peak memory 260544 kb
Host smart-fb4e8327-d205-4a60-a9c8-aeeaaf382e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098391857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1098391857
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3361995793
Short name T1265
Test name
Test status
Simulation time 2564127301 ps
CPU time 10.21 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:48:00 PM PST 24
Peak memory 220160 kb
Host smart-ec0c4442-1563-41cf-a651-5a7d696725a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361995793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3361995793
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2109736314
Short name T750
Test name
Test status
Simulation time 3243063698 ps
CPU time 5.58 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:47:55 PM PST 24
Peak memory 203716 kb
Host smart-d59d7d35-1e0b-4c40-b7e0-f615041ce43e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109736314 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2109736314
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.604000839
Short name T399
Test name
Test status
Simulation time 10205936269 ps
CPU time 23.13 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:48:13 PM PST 24
Peak memory 337160 kb
Host smart-07f778b6-84f6-47a9-9159-87511b3898bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604000839 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.604000839
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2075582090
Short name T837
Test name
Test status
Simulation time 10190823003 ps
CPU time 29.39 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:48:17 PM PST 24
Peak memory 422600 kb
Host smart-27e2d741-2d65-407d-92ba-a44588424ce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075582090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2075582090
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2787808893
Short name T482
Test name
Test status
Simulation time 595130137 ps
CPU time 2.78 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:47:52 PM PST 24
Peak memory 203600 kb
Host smart-e70138b9-79b1-49b0-9456-abbc5f4d23b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787808893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2787808893
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.369039076
Short name T348
Test name
Test status
Simulation time 3285324893 ps
CPU time 3.61 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:47:53 PM PST 24
Peak memory 204076 kb
Host smart-05e70232-b706-4a4a-8c39-a451d4c9f87b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369039076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.369039076
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.1698192362
Short name T254
Test name
Test status
Simulation time 14192760176 ps
CPU time 118 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:49:47 PM PST 24
Peak memory 1734680 kb
Host smart-bca2f6ee-000b-48c0-98f8-86db27c17fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698192362 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.1698192362
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_perf.892820211
Short name T1035
Test name
Test status
Simulation time 5082769817 ps
CPU time 4.39 seconds
Started Feb 29 02:47:46 PM PST 24
Finished Feb 29 02:47:51 PM PST 24
Peak memory 206048 kb
Host smart-208af052-1124-4e88-8679-c1c5a0afb625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892820211 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_perf.892820211
Directory /workspace/25.i2c_target_perf/latest

Test location /workspace/coverage/default/25.i2c_target_stress_all.2611274140
Short name T1074
Test name
Test status
Simulation time 92661182261 ps
CPU time 1971.31 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 03:20:42 PM PST 24
Peak memory 7217400 kb
Host smart-5653f6a9-b37a-4e48-aa03-dadfd929011b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611274140 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_stress_all.2611274140
Directory /workspace/25.i2c_target_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2053344969
Short name T677
Test name
Test status
Simulation time 32325404887 ps
CPU time 114.94 seconds
Started Feb 29 02:47:48 PM PST 24
Finished Feb 29 02:49:44 PM PST 24
Peak memory 1864324 kb
Host smart-77e83705-84e9-4ab6-ba5e-8ea73c7e4e77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053344969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2053344969
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.490756678
Short name T546
Test name
Test status
Simulation time 16627085907 ps
CPU time 11.36 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:48:01 PM PST 24
Peak memory 278036 kb
Host smart-4adcd83c-b965-47bf-8f99-3970b0b40fcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490756678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.490756678
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3663382759
Short name T299
Test name
Test status
Simulation time 2067994411 ps
CPU time 7.68 seconds
Started Feb 29 02:47:49 PM PST 24
Finished Feb 29 02:47:57 PM PST 24
Peak memory 211048 kb
Host smart-55ab6f42-cd20-4ec9-a03a-8fe01fa558f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663382759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3663382759
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.1542364076
Short name T1143
Test name
Test status
Simulation time 3447325989 ps
CPU time 6.59 seconds
Started Feb 29 02:47:47 PM PST 24
Finished Feb 29 02:47:54 PM PST 24
Peak memory 205180 kb
Host smart-5c7a026b-8773-477f-8159-f3f4c965267d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542364076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.1542364076
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2685473504
Short name T1241
Test name
Test status
Simulation time 43500206 ps
CPU time 0.59 seconds
Started Feb 29 02:48:04 PM PST 24
Finished Feb 29 02:48:05 PM PST 24
Peak memory 202536 kb
Host smart-bd8aa995-fc17-46a1-9ecd-7ae178bf4387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685473504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2685473504
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1826086127
Short name T879
Test name
Test status
Simulation time 56309708 ps
CPU time 1.65 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:48:02 PM PST 24
Peak memory 211896 kb
Host smart-a3b28c33-87ee-418a-9660-1b1940dd76be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826086127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1826086127
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2046682751
Short name T333
Test name
Test status
Simulation time 3775353646 ps
CPU time 18.64 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:48:18 PM PST 24
Peak memory 271744 kb
Host smart-e68e1eb0-1d3e-47eb-9c5a-8b77f92701ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046682751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2046682751
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2026197317
Short name T328
Test name
Test status
Simulation time 7478910466 ps
CPU time 73.37 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:49:12 PM PST 24
Peak memory 355396 kb
Host smart-692b6bd4-fa6a-4dae-be22-4791715028dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026197317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2026197317
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.696762112
Short name T1059
Test name
Test status
Simulation time 24532484186 ps
CPU time 162.69 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:50:43 PM PST 24
Peak memory 722656 kb
Host smart-8f25e623-eb92-4c40-8c2d-6779d9e5f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696762112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.696762112
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1753267264
Short name T807
Test name
Test status
Simulation time 200699326 ps
CPU time 4.9 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:48:03 PM PST 24
Peak memory 242112 kb
Host smart-1cbe112f-aaad-4664-9ed7-64808ac85ff7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753267264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1753267264
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2557444159
Short name T1277
Test name
Test status
Simulation time 14084531215 ps
CPU time 93.59 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:49:32 PM PST 24
Peak memory 1045780 kb
Host smart-0c05c8cb-c79b-4a2b-be69-a59d309f85af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557444159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2557444159
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3495700860
Short name T505
Test name
Test status
Simulation time 12079468344 ps
CPU time 88.78 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:49:27 PM PST 24
Peak memory 350356 kb
Host smart-e0befde8-032a-4c08-a81a-69d432f34f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495700860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3495700860
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2353492915
Short name T1248
Test name
Test status
Simulation time 26739431 ps
CPU time 0.61 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:48:00 PM PST 24
Peak memory 202732 kb
Host smart-d9119ab1-3149-423e-bb14-21432233c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353492915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2353492915
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1961073579
Short name T515
Test name
Test status
Simulation time 9225074073 ps
CPU time 152.69 seconds
Started Feb 29 02:48:01 PM PST 24
Finished Feb 29 02:50:34 PM PST 24
Peak memory 279052 kb
Host smart-4f77dba2-d42b-416f-bfd8-e18e1adced60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961073579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1961073579
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_rx_oversample.3369966947
Short name T549
Test name
Test status
Simulation time 9071656190 ps
CPU time 151.37 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:50:32 PM PST 24
Peak memory 277020 kb
Host smart-e8693d81-1ddb-4a9e-baae-2344f95c9a43
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369966947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_rx_oversample
.3369966947
Directory /workspace/26.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1684591678
Short name T984
Test name
Test status
Simulation time 34348810103 ps
CPU time 75.09 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:49:15 PM PST 24
Peak memory 300148 kb
Host smart-9482468c-f522-4611-a4fa-3b69fe424873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684591678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1684591678
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1469418392
Short name T682
Test name
Test status
Simulation time 1214656166 ps
CPU time 54.42 seconds
Started Feb 29 02:48:03 PM PST 24
Finished Feb 29 02:48:58 PM PST 24
Peak memory 211812 kb
Host smart-bbe8f827-648b-40a2-9ff0-97c058da53a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469418392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1469418392
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4017057243
Short name T861
Test name
Test status
Simulation time 1768261120 ps
CPU time 4.42 seconds
Started Feb 29 02:48:02 PM PST 24
Finished Feb 29 02:48:07 PM PST 24
Peak memory 203620 kb
Host smart-6e52c699-ca88-4db2-9309-b2448bfd97bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017057243 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4017057243
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1073667243
Short name T1212
Test name
Test status
Simulation time 10021928962 ps
CPU time 62.29 seconds
Started Feb 29 02:48:01 PM PST 24
Finished Feb 29 02:49:03 PM PST 24
Peak memory 522276 kb
Host smart-136880d6-7312-4522-8fd2-6bd991b0cfdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073667243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1073667243
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.1226301768
Short name T1055
Test name
Test status
Simulation time 10562567395 ps
CPU time 10.88 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:48:09 PM PST 24
Peak memory 298860 kb
Host smart-e0d52a44-6542-432d-8c70-81d3b44c71ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226301768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.1226301768
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.4023241870
Short name T1045
Test name
Test status
Simulation time 2598328497 ps
CPU time 2.67 seconds
Started Feb 29 02:48:02 PM PST 24
Finished Feb 29 02:48:05 PM PST 24
Peak memory 203776 kb
Host smart-ccf65d87-deba-4a48-b53d-848091be6e96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023241870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.4023241870
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3236245129
Short name T1152
Test name
Test status
Simulation time 3300668641 ps
CPU time 6.5 seconds
Started Feb 29 02:47:59 PM PST 24
Finished Feb 29 02:48:06 PM PST 24
Peak memory 206480 kb
Host smart-7eb78dd4-ee6b-473e-82f2-035284746bda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236245129 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3236245129
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.4066355129
Short name T770
Test name
Test status
Simulation time 23951477645 ps
CPU time 324.96 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:53:23 PM PST 24
Peak memory 2858480 kb
Host smart-c4614061-ff88-46ac-b325-53d81b2db2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066355129 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.4066355129
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_perf.4059469331
Short name T941
Test name
Test status
Simulation time 1540652755 ps
CPU time 3.07 seconds
Started Feb 29 02:47:59 PM PST 24
Finished Feb 29 02:48:02 PM PST 24
Peak memory 203612 kb
Host smart-47cfeff2-8fce-40e2-93a2-df40f45c27d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059469331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_perf.4059469331
Directory /workspace/26.i2c_target_perf/latest

Test location /workspace/coverage/default/26.i2c_target_stress_all.2076080130
Short name T1174
Test name
Test status
Simulation time 30638610417 ps
CPU time 358.01 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:53:58 PM PST 24
Peak memory 2595200 kb
Host smart-2a75014d-4b60-48c2-b7f3-bb10e9471589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076080130 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_stress_all.2076080130
Directory /workspace/26.i2c_target_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.541885595
Short name T715
Test name
Test status
Simulation time 3110713869 ps
CPU time 23.96 seconds
Started Feb 29 02:47:57 PM PST 24
Finished Feb 29 02:48:21 PM PST 24
Peak memory 219728 kb
Host smart-bb7f87d4-f168-4d7e-94a7-73d9d5c15e7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541885595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_rd.541885595
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1836079104
Short name T336
Test name
Test status
Simulation time 54879982473 ps
CPU time 61.65 seconds
Started Feb 29 02:48:01 PM PST 24
Finished Feb 29 02:49:03 PM PST 24
Peak memory 866704 kb
Host smart-f592bf40-7019-4e39-b1f5-a10fd943e8bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836079104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1836079104
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1549631120
Short name T189
Test name
Test status
Simulation time 48960416192 ps
CPU time 245.99 seconds
Started Feb 29 02:47:59 PM PST 24
Finished Feb 29 02:52:06 PM PST 24
Peak memory 722348 kb
Host smart-2707002f-0608-4b68-bdf8-57aabf4706a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549631120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1549631120
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.475278345
Short name T136
Test name
Test status
Simulation time 2892364596 ps
CPU time 6.64 seconds
Started Feb 29 02:48:04 PM PST 24
Finished Feb 29 02:48:10 PM PST 24
Peak memory 210256 kb
Host smart-0cbc0696-accb-4719-8a7f-a65b8b36d896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475278345 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.475278345
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.865376548
Short name T637
Test name
Test status
Simulation time 15150522131 ps
CPU time 8.09 seconds
Started Feb 29 02:48:02 PM PST 24
Finished Feb 29 02:48:10 PM PST 24
Peak memory 203752 kb
Host smart-ecf1019c-3a3a-4afc-a299-876e9e7ecc25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865376548 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_unexp_stop.865376548
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.948791555
Short name T1158
Test name
Test status
Simulation time 19069324 ps
CPU time 0.64 seconds
Started Feb 29 02:48:20 PM PST 24
Finished Feb 29 02:48:21 PM PST 24
Peak memory 202548 kb
Host smart-94e5c91d-9594-4ded-93c1-b5a58997412c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948791555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.948791555
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2071080029
Short name T1036
Test name
Test status
Simulation time 27369961 ps
CPU time 1.19 seconds
Started Feb 29 02:48:04 PM PST 24
Finished Feb 29 02:48:05 PM PST 24
Peak memory 203616 kb
Host smart-229ad74b-605c-4fbb-ad88-c379718e20c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071080029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2071080029
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2743283292
Short name T561
Test name
Test status
Simulation time 403136932 ps
CPU time 9.26 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:48:09 PM PST 24
Peak memory 292468 kb
Host smart-27e96ca5-d663-49db-a50d-a0b4aa851f56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743283292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2743283292
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3237924015
Short name T478
Test name
Test status
Simulation time 5180550054 ps
CPU time 74.84 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:49:15 PM PST 24
Peak memory 714836 kb
Host smart-93fe9082-b918-480a-be8e-2c7cff93c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237924015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3237924015
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.36780039
Short name T1190
Test name
Test status
Simulation time 5161570001 ps
CPU time 195.08 seconds
Started Feb 29 02:48:02 PM PST 24
Finished Feb 29 02:51:17 PM PST 24
Peak memory 820204 kb
Host smart-2742c781-093a-44b7-b12b-d83661abc70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36780039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.36780039
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2559907354
Short name T1308
Test name
Test status
Simulation time 287036759 ps
CPU time 12.27 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:48:11 PM PST 24
Peak memory 203616 kb
Host smart-dae967b8-7767-47e2-b2d7-9e040a4ba153
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559907354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2559907354
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2386996563
Short name T362
Test name
Test status
Simulation time 20981315972 ps
CPU time 103.58 seconds
Started Feb 29 02:48:01 PM PST 24
Finished Feb 29 02:49:44 PM PST 24
Peak memory 1092460 kb
Host smart-8b7b2b24-a94c-4bb4-ab2b-e88e37324727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386996563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2386996563
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.3867922287
Short name T681
Test name
Test status
Simulation time 6388166390 ps
CPU time 83.35 seconds
Started Feb 29 02:48:20 PM PST 24
Finished Feb 29 02:49:44 PM PST 24
Peak memory 244424 kb
Host smart-4eb9a879-d35d-4f16-bc28-c50ffb6eb9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867922287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.3867922287
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.3397279521
Short name T1075
Test name
Test status
Simulation time 114152879 ps
CPU time 0.62 seconds
Started Feb 29 02:47:59 PM PST 24
Finished Feb 29 02:48:00 PM PST 24
Peak memory 202648 kb
Host smart-720f2284-3e76-4c90-a340-44655b6d44f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397279521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3397279521
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1962077571
Short name T1159
Test name
Test status
Simulation time 7058072152 ps
CPU time 142 seconds
Started Feb 29 02:48:01 PM PST 24
Finished Feb 29 02:50:23 PM PST 24
Peak memory 252340 kb
Host smart-3b844a5f-8248-4936-98db-860cd1377efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962077571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1962077571
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_rx_oversample.1245299875
Short name T1257
Test name
Test status
Simulation time 9387492404 ps
CPU time 102.89 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:49:43 PM PST 24
Peak memory 332528 kb
Host smart-27d59c7c-5cef-4f1a-b855-8833abd5c14a
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245299875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_rx_oversample
.1245299875
Directory /workspace/27.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1879130747
Short name T488
Test name
Test status
Simulation time 1684074143 ps
CPU time 42.32 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:48:41 PM PST 24
Peak memory 268552 kb
Host smart-c938075d-24bf-48f0-bb75-9987f4141168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879130747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1879130747
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3294472402
Short name T483
Test name
Test status
Simulation time 1363976502 ps
CPU time 9.65 seconds
Started Feb 29 02:47:59 PM PST 24
Finished Feb 29 02:48:09 PM PST 24
Peak memory 211896 kb
Host smart-494a6818-2430-4664-a6c1-adba2d0e1bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294472402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3294472402
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1247395822
Short name T290
Test name
Test status
Simulation time 1702200622 ps
CPU time 5.66 seconds
Started Feb 29 02:48:10 PM PST 24
Finished Feb 29 02:48:16 PM PST 24
Peak memory 203604 kb
Host smart-73e24289-d169-40dc-89f8-7709e9a49558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247395822 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1247395822
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3233639261
Short name T64
Test name
Test status
Simulation time 10155109160 ps
CPU time 11.29 seconds
Started Feb 29 02:48:11 PM PST 24
Finished Feb 29 02:48:22 PM PST 24
Peak memory 271604 kb
Host smart-5b96a99c-0687-4b2b-a4db-195059fa661d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233639261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3233639261
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2087219245
Short name T760
Test name
Test status
Simulation time 10097200991 ps
CPU time 87.36 seconds
Started Feb 29 02:48:08 PM PST 24
Finished Feb 29 02:49:36 PM PST 24
Peak memory 610336 kb
Host smart-44c753c2-8eef-4759-8adc-ec865ac0259c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087219245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2087219245
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1064798807
Short name T475
Test name
Test status
Simulation time 2006948523 ps
CPU time 2.53 seconds
Started Feb 29 02:48:09 PM PST 24
Finished Feb 29 02:48:12 PM PST 24
Peak memory 203724 kb
Host smart-8e4069b3-17c7-429a-95a1-5d57c844bbb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064798807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1064798807
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2862650700
Short name T871
Test name
Test status
Simulation time 5241799907 ps
CPU time 5.97 seconds
Started Feb 29 02:48:04 PM PST 24
Finished Feb 29 02:48:10 PM PST 24
Peak memory 214024 kb
Host smart-2cf7cc6a-c883-43aa-be72-4348da3a8ac0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862650700 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2862650700
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3958397377
Short name T310
Test name
Test status
Simulation time 6764408103 ps
CPU time 80.64 seconds
Started Feb 29 02:48:08 PM PST 24
Finished Feb 29 02:49:29 PM PST 24
Peak memory 1505892 kb
Host smart-e88e3d67-1ad4-4e64-8bb8-52f3041d4f4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958397377 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3958397377
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_perf.2974105037
Short name T99
Test name
Test status
Simulation time 762005065 ps
CPU time 4.34 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:23 PM PST 24
Peak memory 203604 kb
Host smart-dd6b33f5-7bfa-4585-be17-f852175335e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974105037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_perf.2974105037
Directory /workspace/27.i2c_target_perf/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.2191561943
Short name T1304
Test name
Test status
Simulation time 116201719253 ps
CPU time 3294.24 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 03:43:14 PM PST 24
Peak memory 11169820 kb
Host smart-4167e1d4-ff1f-475c-94dd-14654d13e04d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191561943 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.2191561943
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2694556060
Short name T412
Test name
Test status
Simulation time 71238796243 ps
CPU time 569.72 seconds
Started Feb 29 02:48:00 PM PST 24
Finished Feb 29 02:57:30 PM PST 24
Peak memory 4174008 kb
Host smart-3c6b3eb6-c5ef-4b7a-b8c1-42db79ca560b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694556060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2694556060
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2513486794
Short name T537
Test name
Test status
Simulation time 52510737772 ps
CPU time 64.41 seconds
Started Feb 29 02:47:58 PM PST 24
Finished Feb 29 02:49:03 PM PST 24
Peak memory 551184 kb
Host smart-07512aae-0e49-4401-aa81-ab38079a05bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513486794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2513486794
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3453909101
Short name T259
Test name
Test status
Simulation time 2114779333 ps
CPU time 8.29 seconds
Started Feb 29 02:48:09 PM PST 24
Finished Feb 29 02:48:18 PM PST 24
Peak memory 208480 kb
Host smart-3dee6a01-6408-4642-9520-07054ed1490f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453909101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3453909101
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.1114582233
Short name T1071
Test name
Test status
Simulation time 933086699 ps
CPU time 4.62 seconds
Started Feb 29 02:48:09 PM PST 24
Finished Feb 29 02:48:15 PM PST 24
Peak memory 203704 kb
Host smart-ae0396e2-3743-40db-8689-26ef85dd5165
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114582233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.i2c_target_unexp_stop.1114582233
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3413827655
Short name T433
Test name
Test status
Simulation time 16565989 ps
CPU time 0.64 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:20 PM PST 24
Peak memory 203460 kb
Host smart-2cb82d81-e316-41b3-ba38-b2caf9f2059d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413827655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3413827655
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3487287368
Short name T645
Test name
Test status
Simulation time 37669073 ps
CPU time 1.68 seconds
Started Feb 29 02:48:07 PM PST 24
Finished Feb 29 02:48:09 PM PST 24
Peak memory 211888 kb
Host smart-dff6e30f-a5da-421a-8217-db2a7ea41a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487287368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3487287368
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1432986762
Short name T641
Test name
Test status
Simulation time 2522084424 ps
CPU time 10.31 seconds
Started Feb 29 02:48:12 PM PST 24
Finished Feb 29 02:48:23 PM PST 24
Peak memory 339888 kb
Host smart-46bc9d4c-4446-4c9c-9a45-d238c4bfb872
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432986762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1432986762
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2646548462
Short name T327
Test name
Test status
Simulation time 3841412388 ps
CPU time 157.58 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:50:57 PM PST 24
Peak memory 1122912 kb
Host smart-fe310b59-48b8-4bf2-9f76-9a5ac736f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646548462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2646548462
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3333919597
Short name T142
Test name
Test status
Simulation time 38616942259 ps
CPU time 179.98 seconds
Started Feb 29 02:48:20 PM PST 24
Finished Feb 29 02:51:20 PM PST 24
Peak memory 781828 kb
Host smart-d0288c01-e1b4-4d46-94ed-50d9e1aa0f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333919597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3333919597
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1143065030
Short name T857
Test name
Test status
Simulation time 169951994 ps
CPU time 4.03 seconds
Started Feb 29 02:48:20 PM PST 24
Finished Feb 29 02:48:25 PM PST 24
Peak memory 203600 kb
Host smart-f0921c60-31e2-495b-8aa3-4e72119809db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143065030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1143065030
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3625805477
Short name T685
Test name
Test status
Simulation time 18430261259 ps
CPU time 183.08 seconds
Started Feb 29 02:48:08 PM PST 24
Finished Feb 29 02:51:11 PM PST 24
Peak memory 1569068 kb
Host smart-6f4b8eb1-fb6e-4eec-b7ee-83068224108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625805477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3625805477
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.886433827
Short name T179
Test name
Test status
Simulation time 8745399536 ps
CPU time 53.8 seconds
Started Feb 29 02:48:18 PM PST 24
Finished Feb 29 02:49:11 PM PST 24
Peak memory 264824 kb
Host smart-162663d0-b4b4-479f-9ad9-400a6df127bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886433827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.886433827
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2347950131
Short name T4
Test name
Test status
Simulation time 19308147 ps
CPU time 0.63 seconds
Started Feb 29 02:48:11 PM PST 24
Finished Feb 29 02:48:12 PM PST 24
Peak memory 202784 kb
Host smart-559e0a62-3825-4fdd-92f8-989c2628dc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347950131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2347950131
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.4058743658
Short name T1284
Test name
Test status
Simulation time 6514452558 ps
CPU time 125.7 seconds
Started Feb 29 02:48:11 PM PST 24
Finished Feb 29 02:50:18 PM PST 24
Peak memory 233108 kb
Host smart-37b6f7d5-115d-4fad-92a3-a84d52559b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058743658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4058743658
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_rx_oversample.3820308717
Short name T910
Test name
Test status
Simulation time 10522911245 ps
CPU time 178.23 seconds
Started Feb 29 02:48:10 PM PST 24
Finished Feb 29 02:51:09 PM PST 24
Peak memory 284448 kb
Host smart-475a48d3-dd64-4d44-be55-25d8962cfb14
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820308717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_rx_oversample
.3820308717
Directory /workspace/28.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1041875579
Short name T761
Test name
Test status
Simulation time 5724225260 ps
CPU time 81.34 seconds
Started Feb 29 02:48:08 PM PST 24
Finished Feb 29 02:49:30 PM PST 24
Peak memory 236504 kb
Host smart-6385cfe1-5618-43c7-a2d8-b2a9904ec8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041875579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1041875579
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2993782115
Short name T413
Test name
Test status
Simulation time 2737512582 ps
CPU time 9.35 seconds
Started Feb 29 02:48:09 PM PST 24
Finished Feb 29 02:48:18 PM PST 24
Peak memory 220048 kb
Host smart-ca8ff383-f183-42e7-8b7d-7c5de5b32e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993782115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2993782115
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3576049286
Short name T720
Test name
Test status
Simulation time 2543078401 ps
CPU time 5.01 seconds
Started Feb 29 02:48:28 PM PST 24
Finished Feb 29 02:48:33 PM PST 24
Peak memory 203748 kb
Host smart-48f4c947-dac4-4ca4-8b71-9aeab02361ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576049286 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3576049286
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2061924432
Short name T264
Test name
Test status
Simulation time 10459577013 ps
CPU time 10.61 seconds
Started Feb 29 02:48:21 PM PST 24
Finished Feb 29 02:48:32 PM PST 24
Peak memory 259312 kb
Host smart-68641da7-963d-477b-b441-dc97d540897b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061924432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2061924432
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3191007732
Short name T886
Test name
Test status
Simulation time 10044953617 ps
CPU time 86.33 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:49:45 PM PST 24
Peak memory 707216 kb
Host smart-98a2656f-92c3-42e4-93b0-d9a0c140943d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191007732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3191007732
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.227562039
Short name T1242
Test name
Test status
Simulation time 587287526 ps
CPU time 1.79 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:21 PM PST 24
Peak memory 203620 kb
Host smart-bbd99ddc-3b04-4c1c-826a-01160733a823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227562039 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_hrst.227562039
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.250898069
Short name T436
Test name
Test status
Simulation time 1948514660 ps
CPU time 4.22 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:24 PM PST 24
Peak memory 203604 kb
Host smart-7dccd928-5195-4cd9-b5ec-ee558095b9cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250898069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.250898069
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1446877936
Short name T838
Test name
Test status
Simulation time 24336611676 ps
CPU time 123.66 seconds
Started Feb 29 02:48:18 PM PST 24
Finished Feb 29 02:50:22 PM PST 24
Peak memory 1507832 kb
Host smart-e8422d2e-ff8c-4f87-b643-6b3d77831e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446877936 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1446877936
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_perf.1723845743
Short name T566
Test name
Test status
Simulation time 1767557627 ps
CPU time 4.88 seconds
Started Feb 29 02:48:18 PM PST 24
Finished Feb 29 02:48:23 PM PST 24
Peak memory 210672 kb
Host smart-dfc7fe0f-ec31-44c8-9ba3-1957ecbef650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723845743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_perf.1723845743
Directory /workspace/28.i2c_target_perf/latest

Test location /workspace/coverage/default/28.i2c_target_stress_all.3303446932
Short name T1020
Test name
Test status
Simulation time 39710814487 ps
CPU time 44.91 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:49:04 PM PST 24
Peak memory 220092 kb
Host smart-948a694b-898c-456c-8207-fc9de47e7099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303446932 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.i2c_target_stress_all.3303446932
Directory /workspace/28.i2c_target_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2126614274
Short name T335
Test name
Test status
Simulation time 829281252 ps
CPU time 11.53 seconds
Started Feb 29 02:48:22 PM PST 24
Finished Feb 29 02:48:34 PM PST 24
Peak memory 205964 kb
Host smart-3827c326-583f-4ce3-8b4f-1ee206483762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126614274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2126614274
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.778810367
Short name T1137
Test name
Test status
Simulation time 7468407502 ps
CPU time 30.04 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:49 PM PST 24
Peak memory 829976 kb
Host smart-f056d2e8-cb6a-43f4-aac8-39c0e33a6eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778810367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_wr.778810367
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3378985018
Short name T646
Test name
Test status
Simulation time 10219151656 ps
CPU time 248.05 seconds
Started Feb 29 02:48:18 PM PST 24
Finished Feb 29 02:52:27 PM PST 24
Peak memory 1916520 kb
Host smart-5d4894d3-f787-4261-acfb-a2015bc1bb82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378985018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3378985018
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1764875182
Short name T744
Test name
Test status
Simulation time 1708452508 ps
CPU time 7.11 seconds
Started Feb 29 02:48:17 PM PST 24
Finished Feb 29 02:48:24 PM PST 24
Peak memory 210816 kb
Host smart-d7d2cc5f-23ec-4a11-8947-4af581404cce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764875182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1764875182
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.1345715339
Short name T313
Test name
Test status
Simulation time 4309494666 ps
CPU time 6.6 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:26 PM PST 24
Peak memory 203724 kb
Host smart-ab0399ff-bef0-487c-9d77-152b45717259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345715339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.i2c_target_unexp_stop.1345715339
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1840338989
Short name T1003
Test name
Test status
Simulation time 17208376 ps
CPU time 0.62 seconds
Started Feb 29 02:48:31 PM PST 24
Finished Feb 29 02:48:32 PM PST 24
Peak memory 203512 kb
Host smart-fab53294-9667-4a51-8d3d-1be7cbc6813e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840338989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1840338989
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3592178879
Short name T562
Test name
Test status
Simulation time 68686438 ps
CPU time 1.83 seconds
Started Feb 29 02:48:29 PM PST 24
Finished Feb 29 02:48:31 PM PST 24
Peak memory 211840 kb
Host smart-4fd72158-2cdb-4554-943f-e6811e902e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592178879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3592178879
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1893508568
Short name T236
Test name
Test status
Simulation time 368190301 ps
CPU time 18.63 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:37 PM PST 24
Peak memory 283552 kb
Host smart-ebceac2a-b7b6-4cab-b0dd-872b0de6dbdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893508568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1893508568
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3046383339
Short name T352
Test name
Test status
Simulation time 16851142308 ps
CPU time 369.41 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:54:29 PM PST 24
Peak memory 1211304 kb
Host smart-49d8e53b-5d88-47bc-80e7-981025bde360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046383339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3046383339
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.899470228
Short name T363
Test name
Test status
Simulation time 1040157648 ps
CPU time 5.77 seconds
Started Feb 29 02:48:19 PM PST 24
Finished Feb 29 02:48:25 PM PST 24
Peak memory 203556 kb
Host smart-aad35f27-43b4-4600-926c-fc8db0cf6b29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899470228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
899470228
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1304945465
Short name T590
Test name
Test status
Simulation time 6036190208 ps
CPU time 447.67 seconds
Started Feb 29 02:48:18 PM PST 24
Finished Feb 29 02:55:46 PM PST 24
Peak memory 1468412 kb
Host smart-e21c9e52-860a-4458-9b59-e9fb52874c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304945465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1304945465
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2764191591
Short name T1117
Test name
Test status
Simulation time 2529599460 ps
CPU time 44.86 seconds
Started Feb 29 02:48:30 PM PST 24
Finished Feb 29 02:49:15 PM PST 24
Peak memory 283264 kb
Host smart-5ab211de-1aeb-404c-81cf-43ac76ea5d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764191591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2764191591
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1755933285
Short name T420
Test name
Test status
Simulation time 41077215 ps
CPU time 0.65 seconds
Started Feb 29 02:48:23 PM PST 24
Finished Feb 29 02:48:24 PM PST 24
Peak memory 202684 kb
Host smart-2c95bf32-b0b3-4715-8b1b-313625947b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755933285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1755933285
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.4159745954
Short name T1108
Test name
Test status
Simulation time 394880308 ps
CPU time 9.89 seconds
Started Feb 29 02:48:30 PM PST 24
Finished Feb 29 02:48:40 PM PST 24
Peak memory 203752 kb
Host smart-de4d06bb-ce55-4789-9fd1-593c8a691f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159745954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.4159745954
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_rx_oversample.2019592771
Short name T219
Test name
Test status
Simulation time 1809381781 ps
CPU time 132.6 seconds
Started Feb 29 02:48:18 PM PST 24
Finished Feb 29 02:50:30 PM PST 24
Peak memory 250348 kb
Host smart-0c8108ef-17b0-4761-8b05-15309637bb04
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019592771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_rx_oversample
.2019592771
Directory /workspace/29.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1131044844
Short name T639
Test name
Test status
Simulation time 3002877873 ps
CPU time 43.08 seconds
Started Feb 29 02:48:23 PM PST 24
Finished Feb 29 02:49:06 PM PST 24
Peak memory 260684 kb
Host smart-ddc68e1d-f44e-4dc2-96ef-b401a458686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131044844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1131044844
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3134062531
Short name T158
Test name
Test status
Simulation time 9423417526 ps
CPU time 11.37 seconds
Started Feb 29 02:48:32 PM PST 24
Finished Feb 29 02:48:44 PM PST 24
Peak memory 219980 kb
Host smart-491e65ad-9929-42ff-80bc-49c682cfd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134062531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3134062531
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1994666671
Short name T247
Test name
Test status
Simulation time 556793635 ps
CPU time 2.63 seconds
Started Feb 29 02:48:29 PM PST 24
Finished Feb 29 02:48:32 PM PST 24
Peak memory 203668 kb
Host smart-4dbe8dc9-948b-4c54-889c-011fc5a5ec66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994666671 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1994666671
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2907411108
Short name T18
Test name
Test status
Simulation time 10143686848 ps
CPU time 23.95 seconds
Started Feb 29 02:48:31 PM PST 24
Finished Feb 29 02:48:55 PM PST 24
Peak memory 318728 kb
Host smart-883f54eb-9800-4870-bf99-f45c8b030e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907411108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2907411108
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.4250797646
Short name T174
Test name
Test status
Simulation time 10329843379 ps
CPU time 14.32 seconds
Started Feb 29 02:48:29 PM PST 24
Finished Feb 29 02:48:43 PM PST 24
Peak memory 305924 kb
Host smart-16f80a29-366d-44ae-8b48-4854891799e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250797646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.4250797646
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1757496755
Short name T293
Test name
Test status
Simulation time 1137435663 ps
CPU time 1.93 seconds
Started Feb 29 02:48:29 PM PST 24
Finished Feb 29 02:48:31 PM PST 24
Peak memory 203644 kb
Host smart-0973b6a0-46db-467a-9a46-35bf38e0b9f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757496755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1757496755
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1966053482
Short name T577
Test name
Test status
Simulation time 8295134375 ps
CPU time 6.03 seconds
Started Feb 29 02:48:30 PM PST 24
Finished Feb 29 02:48:36 PM PST 24
Peak memory 212160 kb
Host smart-1e004825-1fe2-4eef-ab96-f4ed323ac425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966053482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1966053482
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.495000580
Short name T621
Test name
Test status
Simulation time 18544415422 ps
CPU time 65.46 seconds
Started Feb 29 02:48:30 PM PST 24
Finished Feb 29 02:49:36 PM PST 24
Peak memory 857424 kb
Host smart-659ed2cf-b7b2-48d0-8705-02a0434078ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495000580 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.495000580
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_perf.1375426042
Short name T589
Test name
Test status
Simulation time 3538029752 ps
CPU time 3.37 seconds
Started Feb 29 02:48:28 PM PST 24
Finished Feb 29 02:48:31 PM PST 24
Peak memory 203720 kb
Host smart-054cbfed-6e03-434b-bdc6-2652e58f59d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375426042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_perf.1375426042
Directory /workspace/29.i2c_target_perf/latest

Test location /workspace/coverage/default/29.i2c_target_stress_all.1625460470
Short name T792
Test name
Test status
Simulation time 53072788721 ps
CPU time 2255.47 seconds
Started Feb 29 02:48:31 PM PST 24
Finished Feb 29 03:26:07 PM PST 24
Peak memory 9940748 kb
Host smart-b86518ed-245a-4de4-a4eb-87945ea90bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625460470 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_stress_all.1625460470
Directory /workspace/29.i2c_target_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.4167671904
Short name T915
Test name
Test status
Simulation time 4712323176 ps
CPU time 32.08 seconds
Started Feb 29 02:48:30 PM PST 24
Finished Feb 29 02:49:02 PM PST 24
Peak memory 203748 kb
Host smart-16d0736b-7199-4d97-906c-655a2e1f0685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167671904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.4167671904
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.3313900249
Short name T1216
Test name
Test status
Simulation time 47668903198 ps
CPU time 750.47 seconds
Started Feb 29 02:48:31 PM PST 24
Finished Feb 29 03:01:02 PM PST 24
Peak memory 5652020 kb
Host smart-ce4145d5-f89c-4e9e-afea-13ae45fb7a06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313900249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.3313900249
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1167641868
Short name T567
Test name
Test status
Simulation time 3726455708 ps
CPU time 46.45 seconds
Started Feb 29 02:48:29 PM PST 24
Finished Feb 29 02:49:15 PM PST 24
Peak memory 650764 kb
Host smart-48884e55-57b7-4aaf-aa3f-1d32300c8294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167641868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1167641868
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3368055517
Short name T850
Test name
Test status
Simulation time 1679753893 ps
CPU time 7.2 seconds
Started Feb 29 02:48:29 PM PST 24
Finished Feb 29 02:48:36 PM PST 24
Peak memory 203724 kb
Host smart-5c84c52a-8042-4de9-a4d0-e2ea3211e992
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368055517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3368055517
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.40651318
Short name T762
Test name
Test status
Simulation time 701341182 ps
CPU time 3.51 seconds
Started Feb 29 02:48:28 PM PST 24
Finished Feb 29 02:48:32 PM PST 24
Peak memory 203636 kb
Host smart-4541216e-e254-4ad5-8933-907403521def
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40651318 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_unexp_stop.40651318
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4272941783
Short name T718
Test name
Test status
Simulation time 43799328 ps
CPU time 0.61 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:43:55 PM PST 24
Peak memory 202560 kb
Host smart-944d8757-081b-4f9a-b027-e84948cdde5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272941783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4272941783
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.701928675
Short name T962
Test name
Test status
Simulation time 127610097 ps
CPU time 1.49 seconds
Started Feb 29 02:43:45 PM PST 24
Finished Feb 29 02:43:46 PM PST 24
Peak memory 211792 kb
Host smart-7028f3cd-58ca-4785-9c68-5cbbcd5a3fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701928675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.701928675
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.480047492
Short name T249
Test name
Test status
Simulation time 2021224980 ps
CPU time 26.35 seconds
Started Feb 29 02:43:44 PM PST 24
Finished Feb 29 02:44:10 PM PST 24
Peak memory 314876 kb
Host smart-fb5dd664-dadb-4113-98bc-15459b07b875
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480047492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.480047492
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2583593835
Short name T1115
Test name
Test status
Simulation time 8767658975 ps
CPU time 117.55 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:45:36 PM PST 24
Peak memory 947604 kb
Host smart-39be7935-4855-46a9-90cf-80047e0b8cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583593835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2583593835
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2046832346
Short name T968
Test name
Test status
Simulation time 2333865060 ps
CPU time 151.66 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:46:11 PM PST 24
Peak memory 644052 kb
Host smart-daaf4fa9-2317-44b6-a2a9-e0a62964c9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046832346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2046832346
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2240736203
Short name T904
Test name
Test status
Simulation time 661505386 ps
CPU time 4.74 seconds
Started Feb 29 02:43:38 PM PST 24
Finished Feb 29 02:43:43 PM PST 24
Peak memory 237608 kb
Host smart-85e535f8-d7e3-44df-b1a3-355beed994d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240736203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2240736203
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1452335356
Short name T133
Test name
Test status
Simulation time 21599514166 ps
CPU time 158.17 seconds
Started Feb 29 02:43:38 PM PST 24
Finished Feb 29 02:46:16 PM PST 24
Peak memory 1577908 kb
Host smart-19ad9746-710c-4cad-9db6-6a1a487db5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452335356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1452335356
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.89382040
Short name T1291
Test name
Test status
Simulation time 3923476674 ps
CPU time 120.51 seconds
Started Feb 29 02:43:51 PM PST 24
Finished Feb 29 02:45:52 PM PST 24
Peak memory 260816 kb
Host smart-3584b8b6-1cbe-4978-9248-daed2673bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89382040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.89382040
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.787180436
Short name T931
Test name
Test status
Simulation time 18530544 ps
CPU time 0.66 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:43:39 PM PST 24
Peak memory 202760 kb
Host smart-3a87da3f-273a-48bc-8d86-fb3515403859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787180436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.787180436
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1121546080
Short name T1268
Test name
Test status
Simulation time 29898158712 ps
CPU time 35.63 seconds
Started Feb 29 02:43:37 PM PST 24
Finished Feb 29 02:44:13 PM PST 24
Peak memory 213756 kb
Host smart-41635325-2e7c-45fc-a4a0-85590c4d7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121546080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1121546080
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_rx_oversample.2733922384
Short name T355
Test name
Test status
Simulation time 1428741241 ps
CPU time 56.77 seconds
Started Feb 29 02:43:45 PM PST 24
Finished Feb 29 02:44:42 PM PST 24
Peak memory 278760 kb
Host smart-168385df-92b9-4f44-872a-8c69c3891477
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733922384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_rx_oversample.
2733922384
Directory /workspace/3.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1891302027
Short name T834
Test name
Test status
Simulation time 9996723082 ps
CPU time 93.33 seconds
Started Feb 29 02:43:37 PM PST 24
Finished Feb 29 02:45:11 PM PST 24
Peak memory 396828 kb
Host smart-fcdad3d6-8e7a-44bd-b0e3-971166c1eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891302027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1891302027
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3433171980
Short name T923
Test name
Test status
Simulation time 9270751158 ps
CPU time 9.45 seconds
Started Feb 29 02:43:39 PM PST 24
Finished Feb 29 02:43:49 PM PST 24
Peak memory 211980 kb
Host smart-a0cd7830-8442-4808-bba7-14c2466ec9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433171980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3433171980
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.970382461
Short name T72
Test name
Test status
Simulation time 76727783 ps
CPU time 0.86 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:43:56 PM PST 24
Peak memory 220396 kb
Host smart-89f6181a-a96c-4a53-a6f4-a29cc13ad6d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970382461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.970382461
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3086127673
Short name T1165
Test name
Test status
Simulation time 1908016259 ps
CPU time 2.98 seconds
Started Feb 29 02:43:52 PM PST 24
Finished Feb 29 02:43:55 PM PST 24
Peak memory 203580 kb
Host smart-ed7edb7a-25c3-4348-ba88-8e7dc6492450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086127673 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3086127673
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1168564708
Short name T417
Test name
Test status
Simulation time 10021669318 ps
CPU time 57.81 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:44:53 PM PST 24
Peak memory 466320 kb
Host smart-de907c19-5bdd-4e5c-acc6-ee396a10511e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168564708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1168564708
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3176705604
Short name T156
Test name
Test status
Simulation time 10276740774 ps
CPU time 6.6 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:44:00 PM PST 24
Peak memory 256724 kb
Host smart-369d9fbf-b1fa-4ed9-8835-8c7b925f239a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176705604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3176705604
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.305396438
Short name T667
Test name
Test status
Simulation time 3004636121 ps
CPU time 3.38 seconds
Started Feb 29 02:43:51 PM PST 24
Finished Feb 29 02:43:55 PM PST 24
Peak memory 204000 kb
Host smart-0e549ffa-f766-4e43-8215-101161cc4017
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305396438 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.305396438
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1486737297
Short name T652
Test name
Test status
Simulation time 8381472507 ps
CPU time 7.03 seconds
Started Feb 29 02:43:52 PM PST 24
Finished Feb 29 02:43:59 PM PST 24
Peak memory 206108 kb
Host smart-44b0d50d-bf95-47f8-abbb-0cf6183f6b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486737297 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1486737297
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2708761323
Short name T1217
Test name
Test status
Simulation time 22871858739 ps
CPU time 151.46 seconds
Started Feb 29 02:43:51 PM PST 24
Finished Feb 29 02:46:23 PM PST 24
Peak memory 1590424 kb
Host smart-3df2bae5-6b7d-4410-89ce-a27f32d7a2f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708761323 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2708761323
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_perf.1631437305
Short name T309
Test name
Test status
Simulation time 3029648858 ps
CPU time 4.28 seconds
Started Feb 29 02:43:52 PM PST 24
Finished Feb 29 02:43:57 PM PST 24
Peak memory 204396 kb
Host smart-baa94e72-79df-4242-904d-67e14d0f2007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631437305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_perf.1631437305
Directory /workspace/3.i2c_target_perf/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1555005798
Short name T238
Test name
Test status
Simulation time 8891520998 ps
CPU time 19.76 seconds
Started Feb 29 02:43:44 PM PST 24
Finished Feb 29 02:44:04 PM PST 24
Peak memory 203668 kb
Host smart-e525ea5f-609f-4a85-b01d-1d223e122449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555005798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1555005798
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_all.1201080572
Short name T1194
Test name
Test status
Simulation time 8007405566 ps
CPU time 31.99 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:44:26 PM PST 24
Peak memory 214288 kb
Host smart-26f4e582-c46e-41d2-a9aa-526252ff0679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201080572 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 3.i2c_target_stress_all.1201080572
Directory /workspace/3.i2c_target_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.505057913
Short name T502
Test name
Test status
Simulation time 3904614966 ps
CPU time 33.53 seconds
Started Feb 29 02:43:45 PM PST 24
Finished Feb 29 02:44:19 PM PST 24
Peak memory 203704 kb
Host smart-e223f292-f559-4abf-bc31-e277d190720e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505057913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.505057913
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2221003427
Short name T503
Test name
Test status
Simulation time 52719555061 ps
CPU time 745.58 seconds
Started Feb 29 02:43:40 PM PST 24
Finished Feb 29 02:56:06 PM PST 24
Peak memory 6068976 kb
Host smart-db101d21-8a17-46cc-b5bd-492b4f27e17c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221003427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2221003427
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2851569274
Short name T768
Test name
Test status
Simulation time 25544029365 ps
CPU time 1172.82 seconds
Started Feb 29 02:43:38 PM PST 24
Finished Feb 29 03:03:12 PM PST 24
Peak memory 5189964 kb
Host smart-db285148-c022-42d1-ab82-e2d1fa6093e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851569274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2851569274
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.5378354
Short name T345
Test name
Test status
Simulation time 1539286956 ps
CPU time 6.74 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:44:00 PM PST 24
Peak memory 203656 kb
Host smart-25030dbf-5c7e-4dd8-a1b4-63bc41e3a497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5378354 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_timeout.5378354
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.3845800234
Short name T691
Test name
Test status
Simulation time 4009556501 ps
CPU time 5.84 seconds
Started Feb 29 02:43:52 PM PST 24
Finished Feb 29 02:43:58 PM PST 24
Peak memory 204216 kb
Host smart-878dc17a-744e-4ab5-a682-f5fec2d22855
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845800234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.3845800234
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2437547477
Short name T803
Test name
Test status
Simulation time 39530091 ps
CPU time 0.61 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:48:44 PM PST 24
Peak memory 202564 kb
Host smart-5d3625ef-6e8c-49a7-aaad-5f261214738e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437547477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2437547477
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2614769037
Short name T1328
Test name
Test status
Simulation time 46194143 ps
CPU time 1.39 seconds
Started Feb 29 02:48:42 PM PST 24
Finished Feb 29 02:48:43 PM PST 24
Peak memory 211780 kb
Host smart-c49cad7d-a258-4dfb-8984-ea2ae5108e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614769037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2614769037
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3509351087
Short name T1054
Test name
Test status
Simulation time 1541078854 ps
CPU time 6.98 seconds
Started Feb 29 02:48:46 PM PST 24
Finished Feb 29 02:48:53 PM PST 24
Peak memory 290284 kb
Host smart-e7c78fce-df1d-4aa0-b319-5b1c8ffabcf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509351087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3509351087
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.63286530
Short name T244
Test name
Test status
Simulation time 11575723350 ps
CPU time 202.29 seconds
Started Feb 29 02:48:46 PM PST 24
Finished Feb 29 02:52:08 PM PST 24
Peak memory 867700 kb
Host smart-ec357097-248d-4c7c-b442-fb22105bd9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63286530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.63286530
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2436758639
Short name T1204
Test name
Test status
Simulation time 2961758267 ps
CPU time 224.51 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:52:28 PM PST 24
Peak memory 825536 kb
Host smart-e98175fb-c6c3-49b7-a3b1-d56ae2e27227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436758639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2436758639
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1500133772
Short name T408
Test name
Test status
Simulation time 1086504963 ps
CPU time 6.68 seconds
Started Feb 29 02:48:41 PM PST 24
Finished Feb 29 02:48:48 PM PST 24
Peak memory 260936 kb
Host smart-67d3fd30-0217-49ac-8080-16e964958358
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500133772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1500133772
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.953476433
Short name T852
Test name
Test status
Simulation time 2718264110 ps
CPU time 134.81 seconds
Started Feb 29 02:48:45 PM PST 24
Finished Feb 29 02:51:00 PM PST 24
Peak memory 244424 kb
Host smart-66ffef92-839e-412f-8cf8-90d31392bb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953476433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.953476433
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1685841258
Short name T146
Test name
Test status
Simulation time 21308273 ps
CPU time 0.64 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:48:44 PM PST 24
Peak memory 202828 kb
Host smart-5f91c70e-2cfd-4c49-9184-987aa7c62d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685841258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1685841258
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3702657968
Short name T183
Test name
Test status
Simulation time 2877405648 ps
CPU time 34.15 seconds
Started Feb 29 02:48:44 PM PST 24
Finished Feb 29 02:49:19 PM PST 24
Peak memory 316500 kb
Host smart-d89ffff8-fef9-44f5-8369-5059c9b61781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702657968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3702657968
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_rx_oversample.1116257999
Short name T911
Test name
Test status
Simulation time 14452049564 ps
CPU time 186.18 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:51:49 PM PST 24
Peak memory 398704 kb
Host smart-51cff35b-8e30-4e58-b3a6-cbeb7833bc14
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116257999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_rx_oversample
.1116257999
Directory /workspace/30.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.143805442
Short name T1153
Test name
Test status
Simulation time 5374766116 ps
CPU time 34.65 seconds
Started Feb 29 02:48:42 PM PST 24
Finished Feb 29 02:49:16 PM PST 24
Peak memory 283716 kb
Host smart-108edf87-9da1-4676-9a1c-9e94003d154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143805442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.143805442
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3056245122
Short name T934
Test name
Test status
Simulation time 6413894736 ps
CPU time 232.24 seconds
Started Feb 29 02:48:41 PM PST 24
Finished Feb 29 02:52:34 PM PST 24
Peak memory 1150444 kb
Host smart-6a047647-60fc-4dc5-a617-3f45b3101be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056245122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3056245122
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3842583763
Short name T563
Test name
Test status
Simulation time 815194412 ps
CPU time 14.43 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:48:57 PM PST 24
Peak memory 211760 kb
Host smart-beac995d-c3cf-4cd7-9a19-68cc490b7463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842583763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3842583763
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.223216600
Short name T467
Test name
Test status
Simulation time 1482133105 ps
CPU time 3.29 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:48:46 PM PST 24
Peak memory 203652 kb
Host smart-3e2aed00-8cce-4858-8543-2ba5098c58f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223216600 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.223216600
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.3474358150
Short name T199
Test name
Test status
Simulation time 10172901916 ps
CPU time 28.59 seconds
Started Feb 29 02:48:42 PM PST 24
Finished Feb 29 02:49:11 PM PST 24
Peak memory 375232 kb
Host smart-cb358338-97d6-49b0-bde1-1a0bc7d33394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474358150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.3474358150
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.254513420
Short name T240
Test name
Test status
Simulation time 11044577056 ps
CPU time 5.9 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:48:49 PM PST 24
Peak memory 246192 kb
Host smart-e981054d-c67e-4965-b319-2695af45779d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254513420 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.254513420
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3465359726
Short name T704
Test name
Test status
Simulation time 2357809424 ps
CPU time 3.23 seconds
Started Feb 29 02:48:46 PM PST 24
Finished Feb 29 02:48:50 PM PST 24
Peak memory 203732 kb
Host smart-d5fe692f-e5ab-4a29-b0f2-84b195bea9c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465359726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3465359726
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2644552370
Short name T605
Test name
Test status
Simulation time 7263273251 ps
CPU time 7.27 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:48:51 PM PST 24
Peak memory 203764 kb
Host smart-e48c9931-8bed-4cff-b628-553de580a15d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644552370 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2644552370
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.4252855978
Short name T1321
Test name
Test status
Simulation time 10210840905 ps
CPU time 24.53 seconds
Started Feb 29 02:48:46 PM PST 24
Finished Feb 29 02:49:11 PM PST 24
Peak memory 629480 kb
Host smart-d3742aa7-e0f5-4c01-866b-0622d11b16f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252855978 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.4252855978
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_perf.1937178526
Short name T556
Test name
Test status
Simulation time 3585943412 ps
CPU time 5.21 seconds
Started Feb 29 02:48:42 PM PST 24
Finished Feb 29 02:48:47 PM PST 24
Peak memory 211984 kb
Host smart-b209f620-a136-43d9-b4df-864c0da6c24b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937178526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_perf.1937178526
Directory /workspace/30.i2c_target_perf/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.307316857
Short name T1130
Test name
Test status
Simulation time 21512042421 ps
CPU time 25.42 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:49:08 PM PST 24
Peak memory 294480 kb
Host smart-fac64fbe-9ebd-4fb1-b755-e89fe989766f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307316857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.i2c_target_stress_all.307316857
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1420700525
Short name T948
Test name
Test status
Simulation time 1410002434 ps
CPU time 57.14 seconds
Started Feb 29 02:48:45 PM PST 24
Finished Feb 29 02:49:42 PM PST 24
Peak memory 203664 kb
Host smart-6642bcea-828f-4014-a6f4-a9722b639ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420700525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1420700525
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2072789570
Short name T1339
Test name
Test status
Simulation time 46444545898 ps
CPU time 2077.49 seconds
Started Feb 29 02:48:45 PM PST 24
Finished Feb 29 03:23:23 PM PST 24
Peak memory 10733568 kb
Host smart-44b2fd5d-c29d-452d-be0e-356619a3c9a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072789570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2072789570
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.804164990
Short name T1065
Test name
Test status
Simulation time 18570580491 ps
CPU time 245.56 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:52:49 PM PST 24
Peak memory 1974176 kb
Host smart-aaf43dd8-eb56-4180-a63b-a086d06b2fe5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804164990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_t
arget_stretch.804164990
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3596594439
Short name T635
Test name
Test status
Simulation time 1803276021 ps
CPU time 7.62 seconds
Started Feb 29 02:48:44 PM PST 24
Finished Feb 29 02:48:52 PM PST 24
Peak memory 215512 kb
Host smart-f41da75f-d614-4a0c-8ba0-5998c06f655b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596594439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3596594439
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.991909480
Short name T385
Test name
Test status
Simulation time 16970380 ps
CPU time 0.65 seconds
Started Feb 29 02:48:57 PM PST 24
Finished Feb 29 02:48:58 PM PST 24
Peak memory 202580 kb
Host smart-6b1aae47-593a-493d-b404-2fc6e3d5db42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991909480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.991909480
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1024374166
Short name T35
Test name
Test status
Simulation time 130756107 ps
CPU time 1.88 seconds
Started Feb 29 02:48:57 PM PST 24
Finished Feb 29 02:48:59 PM PST 24
Peak memory 211884 kb
Host smart-28ac2a85-6455-40d0-a973-d0426c9db1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024374166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1024374166
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.3149707350
Short name T66
Test name
Test status
Simulation time 537982067 ps
CPU time 23.6 seconds
Started Feb 29 02:48:45 PM PST 24
Finished Feb 29 02:49:08 PM PST 24
Peak memory 300124 kb
Host smart-4e40feaa-4d25-4ad0-b080-5021cdfae16e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149707350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.3149707350
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2377127414
Short name T1309
Test name
Test status
Simulation time 1899117963 ps
CPU time 56.58 seconds
Started Feb 29 02:48:58 PM PST 24
Finished Feb 29 02:49:55 PM PST 24
Peak memory 624464 kb
Host smart-b01a3829-e304-4c21-8269-8c29798e16ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377127414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2377127414
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3438907040
Short name T260
Test name
Test status
Simulation time 6980963776 ps
CPU time 120.52 seconds
Started Feb 29 02:48:42 PM PST 24
Finished Feb 29 02:50:43 PM PST 24
Peak memory 1058348 kb
Host smart-d72ff1cf-4a8d-42bb-85c2-5e242dc7fffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438907040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3438907040
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.622841237
Short name T776
Test name
Test status
Simulation time 217974813 ps
CPU time 4.46 seconds
Started Feb 29 02:48:57 PM PST 24
Finished Feb 29 02:49:01 PM PST 24
Peak memory 239460 kb
Host smart-0a312b4d-b892-4974-924c-f24c278b5c91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622841237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
622841237
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3935343272
Short name T131
Test name
Test status
Simulation time 8113785763 ps
CPU time 90.75 seconds
Started Feb 29 02:48:45 PM PST 24
Finished Feb 29 02:50:16 PM PST 24
Peak memory 1232936 kb
Host smart-48b6657f-bf07-43f8-b895-93e985f1e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935343272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3935343272
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.4273805166
Short name T457
Test name
Test status
Simulation time 2944373242 ps
CPU time 71.61 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:50:08 PM PST 24
Peak memory 333880 kb
Host smart-8c0d7d2e-2d1c-4a90-b207-d8c2bee25b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273805166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.4273805166
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1531177283
Short name T804
Test name
Test status
Simulation time 43108168 ps
CPU time 0.61 seconds
Started Feb 29 02:48:44 PM PST 24
Finished Feb 29 02:48:45 PM PST 24
Peak memory 202796 kb
Host smart-7f95f87f-04c7-4252-95dc-b88b4dda3dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531177283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1531177283
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.226682476
Short name T1246
Test name
Test status
Simulation time 7497227667 ps
CPU time 25.62 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:23 PM PST 24
Peak memory 203732 kb
Host smart-f9d9ce47-05f3-421c-8cd2-fc42ed4af6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226682476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.226682476
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_rx_oversample.2222469397
Short name T1201
Test name
Test status
Simulation time 12826853057 ps
CPU time 104.96 seconds
Started Feb 29 02:48:43 PM PST 24
Finished Feb 29 02:50:28 PM PST 24
Peak memory 347372 kb
Host smart-a9f2e266-bfa2-47fa-a082-66a1af974020
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222469397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_rx_oversample
.2222469397
Directory /workspace/31.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2251859163
Short name T889
Test name
Test status
Simulation time 1424623204 ps
CPU time 78.39 seconds
Started Feb 29 02:48:42 PM PST 24
Finished Feb 29 02:50:01 PM PST 24
Peak memory 248764 kb
Host smart-0f5ac918-5b11-4378-978c-6c663d551cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251859163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2251859163
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1548546313
Short name T1211
Test name
Test status
Simulation time 1350295612 ps
CPU time 55.04 seconds
Started Feb 29 02:48:55 PM PST 24
Finished Feb 29 02:49:50 PM PST 24
Peak memory 215760 kb
Host smart-e7f8c0d2-dcc0-46a2-940d-fe9736a0609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548546313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1548546313
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3137334861
Short name T27
Test name
Test status
Simulation time 773050499 ps
CPU time 3.31 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:00 PM PST 24
Peak memory 203612 kb
Host smart-8b235382-aa29-4b5f-96fb-dae9b32d8001
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137334861 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3137334861
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3285362126
Short name T311
Test name
Test status
Simulation time 10363955415 ps
CPU time 12.45 seconds
Started Feb 29 02:49:04 PM PST 24
Finished Feb 29 02:49:16 PM PST 24
Peak memory 297324 kb
Host smart-9f5102ec-8ef6-4964-aa9d-007ab19ac5b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285362126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3285362126
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3157754861
Short name T1039
Test name
Test status
Simulation time 10136664342 ps
CPU time 12.84 seconds
Started Feb 29 02:48:57 PM PST 24
Finished Feb 29 02:49:10 PM PST 24
Peak memory 292600 kb
Host smart-6af94986-4018-4d7a-9d67-b1ca011d15a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157754861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3157754861
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.235735548
Short name T152
Test name
Test status
Simulation time 1640676486 ps
CPU time 2.01 seconds
Started Feb 29 02:48:55 PM PST 24
Finished Feb 29 02:48:58 PM PST 24
Peak memory 203844 kb
Host smart-3954ce2e-e9e6-4698-b28a-ea1ff6149f21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235735548 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.235735548
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.4120889484
Short name T3
Test name
Test status
Simulation time 1492657178 ps
CPU time 6.19 seconds
Started Feb 29 02:48:58 PM PST 24
Finished Feb 29 02:49:04 PM PST 24
Peak memory 205508 kb
Host smart-a397bac1-dbd1-438f-9d76-47bf223a9ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120889484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.4120889484
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.546133322
Short name T324
Test name
Test status
Simulation time 13209507365 ps
CPU time 54.03 seconds
Started Feb 29 02:48:58 PM PST 24
Finished Feb 29 02:49:52 PM PST 24
Peak memory 858188 kb
Host smart-cf2e0874-ceb0-486b-9376-4a366f228979
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546133322 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.546133322
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_perf.1423112408
Short name T1249
Test name
Test status
Simulation time 2449856535 ps
CPU time 3.66 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:00 PM PST 24
Peak memory 203688 kb
Host smart-bae009ed-64ec-4d74-ae4d-8bb018075d56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423112408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_perf.1423112408
Directory /workspace/31.i2c_target_perf/latest

Test location /workspace/coverage/default/31.i2c_target_stress_all.3087284018
Short name T445
Test name
Test status
Simulation time 9110341039 ps
CPU time 36.03 seconds
Started Feb 29 02:49:00 PM PST 24
Finished Feb 29 02:49:36 PM PST 24
Peak memory 219732 kb
Host smart-d226718a-b984-4223-a109-974d57d07b30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087284018 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_stress_all.3087284018
Directory /workspace/31.i2c_target_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2887031119
Short name T708
Test name
Test status
Simulation time 16730327389 ps
CPU time 33.81 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:30 PM PST 24
Peak memory 914892 kb
Host smart-8bc063c4-9fac-43e2-a21f-c81995e375dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887031119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2887031119
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.547590282
Short name T395
Test name
Test status
Simulation time 18334573121 ps
CPU time 1128.89 seconds
Started Feb 29 02:48:57 PM PST 24
Finished Feb 29 03:07:47 PM PST 24
Peak memory 4196816 kb
Host smart-e5f4ab02-8ec0-4c54-94cf-56414043841c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547590282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.547590282
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3415493535
Short name T1192
Test name
Test status
Simulation time 4251909420 ps
CPU time 8.64 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:06 PM PST 24
Peak memory 214052 kb
Host smart-6c314b62-d8ed-4884-94e5-926cac2e032e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415493535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3415493535
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_unexp_stop.951381558
Short name T638
Test name
Test status
Simulation time 1320393352 ps
CPU time 6.78 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:03 PM PST 24
Peak memory 210272 kb
Host smart-c68ea7e8-7ca8-4649-acd7-23cdaa238ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951381558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_unexp_stop.951381558
Directory /workspace/31.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2735127089
Short name T530
Test name
Test status
Simulation time 15691674 ps
CPU time 0.62 seconds
Started Feb 29 02:49:10 PM PST 24
Finished Feb 29 02:49:11 PM PST 24
Peak memory 202532 kb
Host smart-05252798-6947-40fa-b527-3ef82fe2cc22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735127089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2735127089
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3164599015
Short name T375
Test name
Test status
Simulation time 37768460 ps
CPU time 1.11 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:48:58 PM PST 24
Peak memory 212056 kb
Host smart-0ce70351-62d4-4fbc-8368-428e6e833666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164599015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3164599015
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1571991287
Short name T1090
Test name
Test status
Simulation time 1751186314 ps
CPU time 24.05 seconds
Started Feb 29 02:49:00 PM PST 24
Finished Feb 29 02:49:25 PM PST 24
Peak memory 303548 kb
Host smart-bf843b07-7531-4ea7-82f0-d348379bcbb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571991287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1571991287
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2739753639
Short name T1255
Test name
Test status
Simulation time 17982261777 ps
CPU time 255.26 seconds
Started Feb 29 02:49:00 PM PST 24
Finished Feb 29 02:53:17 PM PST 24
Peak memory 820368 kb
Host smart-d488d81f-52d2-4eb9-b27e-35e255023867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739753639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2739753639
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.923966818
Short name T702
Test name
Test status
Simulation time 19717016595 ps
CPU time 100.64 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:50:37 PM PST 24
Peak memory 942760 kb
Host smart-683e27f4-9977-49e6-b19c-923bfaf6fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923966818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.923966818
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.36359784
Short name T957
Test name
Test status
Simulation time 323658950 ps
CPU time 8.65 seconds
Started Feb 29 02:49:00 PM PST 24
Finished Feb 29 02:49:09 PM PST 24
Peak memory 269304 kb
Host smart-293510b7-ad09-4251-a25a-8e07beaa1dba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36359784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.36359784
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3870475483
Short name T729
Test name
Test status
Simulation time 4402220466 ps
CPU time 299.8 seconds
Started Feb 29 02:49:04 PM PST 24
Finished Feb 29 02:54:04 PM PST 24
Peak memory 1199384 kb
Host smart-37ca878d-c953-48e0-a607-218b8fc63508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870475483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3870475483
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_override.847516138
Short name T1056
Test name
Test status
Simulation time 25198416 ps
CPU time 0.63 seconds
Started Feb 29 02:48:58 PM PST 24
Finished Feb 29 02:48:59 PM PST 24
Peak memory 202760 kb
Host smart-29d68a85-ff49-4f86-9321-3c4caf9d9622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847516138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.847516138
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1093283593
Short name T323
Test name
Test status
Simulation time 26862872793 ps
CPU time 111.47 seconds
Started Feb 29 02:48:55 PM PST 24
Finished Feb 29 02:50:47 PM PST 24
Peak memory 203740 kb
Host smart-02432dbc-118f-47d0-854b-f256f28e0c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093283593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1093283593
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_rx_oversample.4294623258
Short name T209
Test name
Test status
Simulation time 1803675115 ps
CPU time 92.4 seconds
Started Feb 29 02:49:00 PM PST 24
Finished Feb 29 02:50:33 PM PST 24
Peak memory 322256 kb
Host smart-ed393a60-40f6-4c29-8bb4-490f77935e52
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294623258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_rx_oversample
.4294623258
Directory /workspace/32.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4233528250
Short name T403
Test name
Test status
Simulation time 4695873467 ps
CPU time 47.34 seconds
Started Feb 29 02:48:59 PM PST 24
Finished Feb 29 02:49:47 PM PST 24
Peak memory 219572 kb
Host smart-b7a03769-5a10-4ef3-8965-f904cec73e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233528250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4233528250
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2748016901
Short name T815
Test name
Test status
Simulation time 946674037 ps
CPU time 15.14 seconds
Started Feb 29 02:48:58 PM PST 24
Finished Feb 29 02:49:14 PM PST 24
Peak memory 220024 kb
Host smart-9f8b8757-78fc-4069-8023-75220b36beff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748016901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2748016901
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.241404588
Short name T26
Test name
Test status
Simulation time 7498718320 ps
CPU time 4.7 seconds
Started Feb 29 02:49:09 PM PST 24
Finished Feb 29 02:49:13 PM PST 24
Peak memory 203700 kb
Host smart-1c3a1ea0-8862-4481-b04e-bfccd01d245e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241404588 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.241404588
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1150940769
Short name T388
Test name
Test status
Simulation time 10261059372 ps
CPU time 31.91 seconds
Started Feb 29 02:49:09 PM PST 24
Finished Feb 29 02:49:41 PM PST 24
Peak memory 385200 kb
Host smart-acef506d-0314-4124-b4dc-6e1ae8f06595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150940769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1150940769
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1162431528
Short name T1062
Test name
Test status
Simulation time 10249933995 ps
CPU time 37.22 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 02:49:49 PM PST 24
Peak memory 457428 kb
Host smart-ba162eb4-d073-4394-8e3a-6504fc65c696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162431528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1162431528
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3976335115
Short name T424
Test name
Test status
Simulation time 2029617889 ps
CPU time 2.59 seconds
Started Feb 29 02:49:10 PM PST 24
Finished Feb 29 02:49:13 PM PST 24
Peak memory 203632 kb
Host smart-f30d0d5f-a611-4296-aebe-b3f8576be38e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976335115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3976335115
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.716528864
Short name T978
Test name
Test status
Simulation time 4802202920 ps
CPU time 5.9 seconds
Started Feb 29 02:49:04 PM PST 24
Finished Feb 29 02:49:10 PM PST 24
Peak memory 206648 kb
Host smart-2c0ca9f6-e6d6-4adf-9e2c-00e1f2ea036a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716528864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.716528864
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3566506320
Short name T853
Test name
Test status
Simulation time 12893750240 ps
CPU time 246.77 seconds
Started Feb 29 02:49:07 PM PST 24
Finished Feb 29 02:53:14 PM PST 24
Peak memory 2862736 kb
Host smart-1d1e38cb-6083-47cd-96b0-c8a247a6207d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566506320 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3566506320
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_perf.908172068
Short name T1145
Test name
Test status
Simulation time 3390917623 ps
CPU time 4.74 seconds
Started Feb 29 02:49:10 PM PST 24
Finished Feb 29 02:49:14 PM PST 24
Peak memory 203696 kb
Host smart-17278749-deeb-4c73-8a09-06d704e35492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908172068 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_perf.908172068
Directory /workspace/32.i2c_target_perf/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3765589393
Short name T795
Test name
Test status
Simulation time 5155675228 ps
CPU time 34.62 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:31 PM PST 24
Peak memory 203672 kb
Host smart-cf012e8e-7f4f-442d-8cc1-5ae47df18693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765589393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3765589393
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_all.1991685272
Short name T55
Test name
Test status
Simulation time 81307664187 ps
CPU time 2822.55 seconds
Started Feb 29 02:49:06 PM PST 24
Finished Feb 29 03:36:10 PM PST 24
Peak memory 11076756 kb
Host smart-f1f612ac-0dfe-42e0-a9c9-7ac7cb02f72d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991685272 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_stress_all.1991685272
Directory /workspace/32.i2c_target_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3315212978
Short name T276
Test name
Test status
Simulation time 2418610376 ps
CPU time 15.88 seconds
Started Feb 29 02:48:57 PM PST 24
Finished Feb 29 02:49:14 PM PST 24
Peak memory 207168 kb
Host smart-0dc41202-405a-4eb9-b967-6993f1543b1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315212978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3315212978
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.791601930
Short name T690
Test name
Test status
Simulation time 36217659979 ps
CPU time 1083.26 seconds
Started Feb 29 02:48:55 PM PST 24
Finished Feb 29 03:06:59 PM PST 24
Peak memory 8053148 kb
Host smart-a38d685a-1c88-4428-9c65-959d7422681f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791601930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_wr.791601930
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.316172434
Short name T100
Test name
Test status
Simulation time 8597607777 ps
CPU time 16.27 seconds
Started Feb 29 02:48:56 PM PST 24
Finished Feb 29 02:49:13 PM PST 24
Peak memory 380076 kb
Host smart-4078f0a4-dded-456a-8551-06350870419a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316172434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.316172434
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3537359580
Short name T411
Test name
Test status
Simulation time 3855716813 ps
CPU time 7.2 seconds
Started Feb 29 02:49:08 PM PST 24
Finished Feb 29 02:49:15 PM PST 24
Peak memory 203748 kb
Host smart-58c15109-bde6-4477-b278-fdaf555e22b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537359580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3537359580
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.3106850011
Short name T723
Test name
Test status
Simulation time 1728901770 ps
CPU time 4.24 seconds
Started Feb 29 02:49:06 PM PST 24
Finished Feb 29 02:49:10 PM PST 24
Peak memory 203828 kb
Host smart-3aacdfd7-2c15-4720-b873-b872b3d1bcd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106850011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.3106850011
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1036712733
Short name T405
Test name
Test status
Simulation time 52560520 ps
CPU time 0.6 seconds
Started Feb 29 02:49:09 PM PST 24
Finished Feb 29 02:49:10 PM PST 24
Peak memory 202560 kb
Host smart-0ef3d3f2-6daf-4dde-b615-5e963caec5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036712733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1036712733
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.39297097
Short name T507
Test name
Test status
Simulation time 41059981 ps
CPU time 2.01 seconds
Started Feb 29 02:49:10 PM PST 24
Finished Feb 29 02:49:12 PM PST 24
Peak memory 211868 kb
Host smart-a63ebc20-d83e-4fc7-acee-8842ce35dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39297097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.39297097
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1649683116
Short name T1222
Test name
Test status
Simulation time 1629581622 ps
CPU time 21.75 seconds
Started Feb 29 02:49:13 PM PST 24
Finished Feb 29 02:49:35 PM PST 24
Peak memory 274072 kb
Host smart-c1d6b056-de90-4694-bd37-c19da850ec2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649683116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1649683116
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3488059913
Short name T1076
Test name
Test status
Simulation time 6799316805 ps
CPU time 145.04 seconds
Started Feb 29 02:49:08 PM PST 24
Finished Feb 29 02:51:33 PM PST 24
Peak memory 1051852 kb
Host smart-92d7ab5e-5a4c-4e5b-8d78-71061c4823b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488059913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3488059913
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.1197031071
Short name T314
Test name
Test status
Simulation time 13443360284 ps
CPU time 88.72 seconds
Started Feb 29 02:49:09 PM PST 24
Finished Feb 29 02:50:38 PM PST 24
Peak memory 827928 kb
Host smart-506e88c9-e01c-4fa1-b182-f053f89d6715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197031071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.1197031071
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2693845694
Short name T477
Test name
Test status
Simulation time 149778361 ps
CPU time 4.1 seconds
Started Feb 29 02:49:09 PM PST 24
Finished Feb 29 02:49:13 PM PST 24
Peak memory 228100 kb
Host smart-24561560-d315-4bd4-99cc-62f62be029eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693845694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2693845694
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3936643367
Short name T134
Test name
Test status
Simulation time 5755477397 ps
CPU time 135.92 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 02:51:28 PM PST 24
Peak memory 1571968 kb
Host smart-768b1c60-88c1-4cfd-8a3f-ed5e0084bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936643367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3936643367
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1061033956
Short name T1028
Test name
Test status
Simulation time 2499277902 ps
CPU time 145.11 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 02:51:37 PM PST 24
Peak memory 268368 kb
Host smart-9bf6514c-9ac4-4f9e-b258-538e50f4ff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061033956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1061033956
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.4110716672
Short name T845
Test name
Test status
Simulation time 27136183 ps
CPU time 0.63 seconds
Started Feb 29 02:49:07 PM PST 24
Finished Feb 29 02:49:08 PM PST 24
Peak memory 202732 kb
Host smart-b234382a-868c-4ad5-a7c7-68eb66f7d92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110716672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.4110716672
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.2062820456
Short name T407
Test name
Test status
Simulation time 3862636083 ps
CPU time 6.55 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 02:49:18 PM PST 24
Peak memory 220136 kb
Host smart-6d684ad6-afcf-47ce-9fb0-58ddd790a9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062820456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2062820456
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_rx_oversample.864784983
Short name T945
Test name
Test status
Simulation time 8776671099 ps
CPU time 189.48 seconds
Started Feb 29 02:49:07 PM PST 24
Finished Feb 29 02:52:16 PM PST 24
Peak memory 278436 kb
Host smart-b5f0bf80-e582-4e8e-a9c7-986a787e521e
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864784983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_rx_oversample.
864784983
Directory /workspace/33.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.246600976
Short name T882
Test name
Test status
Simulation time 2954800308 ps
CPU time 27.72 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 02:49:39 PM PST 24
Peak memory 254588 kb
Host smart-6b782e3a-f018-42fc-8e21-3c153fce5bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246600976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.246600976
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2059297415
Short name T738
Test name
Test status
Simulation time 740885819 ps
CPU time 12.39 seconds
Started Feb 29 02:49:07 PM PST 24
Finished Feb 29 02:49:20 PM PST 24
Peak memory 212844 kb
Host smart-50ae80ee-55c9-46b4-aeb3-9771e5555740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059297415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2059297415
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3115911320
Short name T1269
Test name
Test status
Simulation time 1000020790 ps
CPU time 4.01 seconds
Started Feb 29 02:49:15 PM PST 24
Finished Feb 29 02:49:20 PM PST 24
Peak memory 203576 kb
Host smart-e03ff787-29b7-4a5d-9801-dca32fc1eddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115911320 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3115911320
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3994517776
Short name T176
Test name
Test status
Simulation time 10100768085 ps
CPU time 12.35 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 02:49:24 PM PST 24
Peak memory 298072 kb
Host smart-c3e28a92-640b-4987-970c-d438019248f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994517776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3994517776
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.4083602856
Short name T995
Test name
Test status
Simulation time 10099705035 ps
CPU time 38.66 seconds
Started Feb 29 02:49:10 PM PST 24
Finished Feb 29 02:49:49 PM PST 24
Peak memory 385184 kb
Host smart-88b6b376-f707-46ef-aac2-de792d2e6f49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083602856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.4083602856
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.4256884248
Short name T875
Test name
Test status
Simulation time 721932526 ps
CPU time 2.17 seconds
Started Feb 29 02:49:09 PM PST 24
Finished Feb 29 02:49:11 PM PST 24
Peak memory 203660 kb
Host smart-42923e6f-3a39-4879-9341-f726d8327c37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256884248 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.4256884248
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.1950301065
Short name T291
Test name
Test status
Simulation time 23645367119 ps
CPU time 6.35 seconds
Started Feb 29 02:49:15 PM PST 24
Finished Feb 29 02:49:21 PM PST 24
Peak memory 203636 kb
Host smart-21d53a81-ae4f-42be-bdd0-61c008a43ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950301065 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.1950301065
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3011497678
Short name T368
Test name
Test status
Simulation time 19795460677 ps
CPU time 574.32 seconds
Started Feb 29 02:49:09 PM PST 24
Finished Feb 29 02:58:44 PM PST 24
Peak memory 4641992 kb
Host smart-cd9f9d8f-501f-4851-91b3-a31df4523b25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011497678 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3011497678
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_perf.3577155060
Short name T921
Test name
Test status
Simulation time 1135422819 ps
CPU time 3.33 seconds
Started Feb 29 02:49:12 PM PST 24
Finished Feb 29 02:49:16 PM PST 24
Peak memory 203544 kb
Host smart-23573919-f53a-4876-bc2c-e33b0ca8d945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577155060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_perf.3577155060
Directory /workspace/33.i2c_target_perf/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.1319592388
Short name T1311
Test name
Test status
Simulation time 7138642045 ps
CPU time 31.86 seconds
Started Feb 29 02:49:15 PM PST 24
Finished Feb 29 02:49:47 PM PST 24
Peak memory 249292 kb
Host smart-839465bb-3b0c-45bd-9520-a531e4d1cd70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319592388 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.1319592388
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1137510770
Short name T373
Test name
Test status
Simulation time 10112423568 ps
CPU time 65.39 seconds
Started Feb 29 02:49:07 PM PST 24
Finished Feb 29 02:50:13 PM PST 24
Peak memory 1486324 kb
Host smart-9a8d9c42-7f53-4254-92c9-1639dfdbe273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137510770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1137510770
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.926701516
Short name T454
Test name
Test status
Simulation time 39837720542 ps
CPU time 2792.17 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 03:35:44 PM PST 24
Peak memory 7866248 kb
Host smart-edf1be32-c00d-4f38-9c9b-edfbff3086d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926701516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_t
arget_stretch.926701516
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1618574463
Short name T658
Test name
Test status
Simulation time 3001306696 ps
CPU time 6.49 seconds
Started Feb 29 02:49:11 PM PST 24
Finished Feb 29 02:49:18 PM PST 24
Peak memory 203672 kb
Host smart-de7f57a0-f2dd-41f5-85fb-b1ef32134de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618574463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1618574463
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.4029592822
Short name T855
Test name
Test status
Simulation time 2884370613 ps
CPU time 10.67 seconds
Started Feb 29 02:49:10 PM PST 24
Finished Feb 29 02:49:22 PM PST 24
Peak memory 203680 kb
Host smart-af59a060-c62b-408a-9d2a-5827b4ac43fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029592822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.i2c_target_unexp_stop.4029592822
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2934347187
Short name T779
Test name
Test status
Simulation time 126220795 ps
CPU time 0.63 seconds
Started Feb 29 02:49:30 PM PST 24
Finished Feb 29 02:49:31 PM PST 24
Peak memory 202420 kb
Host smart-cad92b32-c592-4d9c-8c52-1b31d2f83a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934347187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2934347187
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2317051186
Short name T231
Test name
Test status
Simulation time 142972751 ps
CPU time 1.3 seconds
Started Feb 29 02:49:21 PM PST 24
Finished Feb 29 02:49:22 PM PST 24
Peak memory 214044 kb
Host smart-b92d94de-502d-4b5f-8749-ba0c2899a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317051186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2317051186
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1517286383
Short name T938
Test name
Test status
Simulation time 299567125 ps
CPU time 15.27 seconds
Started Feb 29 02:49:21 PM PST 24
Finished Feb 29 02:49:36 PM PST 24
Peak memory 265144 kb
Host smart-5bb0db1e-f922-4add-9b7e-89a46a6edc3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517286383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1517286383
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2915535367
Short name T1180
Test name
Test status
Simulation time 5580726410 ps
CPU time 86.94 seconds
Started Feb 29 02:49:20 PM PST 24
Finished Feb 29 02:50:47 PM PST 24
Peak memory 705520 kb
Host smart-8324c34e-513d-48eb-a56e-45362805de7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915535367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2915535367
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.785213113
Short name T289
Test name
Test status
Simulation time 2438257048 ps
CPU time 69.85 seconds
Started Feb 29 02:49:20 PM PST 24
Finished Feb 29 02:50:30 PM PST 24
Peak memory 786348 kb
Host smart-59639b90-867b-4c5c-a38c-3d401afd3e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785213113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.785213113
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.569641011
Short name T665
Test name
Test status
Simulation time 1150420068 ps
CPU time 5.3 seconds
Started Feb 29 02:49:22 PM PST 24
Finished Feb 29 02:49:27 PM PST 24
Peak memory 203696 kb
Host smart-e0396d74-9816-41fe-921c-94abd1e061f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569641011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
569641011
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3025738870
Short name T316
Test name
Test status
Simulation time 6206290538 ps
CPU time 209.67 seconds
Started Feb 29 02:49:21 PM PST 24
Finished Feb 29 02:52:51 PM PST 24
Peak memory 1699952 kb
Host smart-53751bbb-abe9-403d-8d96-7678e602f744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025738870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3025738870
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3175632581
Short name T1225
Test name
Test status
Simulation time 30576903834 ps
CPU time 61.56 seconds
Started Feb 29 02:49:32 PM PST 24
Finished Feb 29 02:50:34 PM PST 24
Peak memory 335044 kb
Host smart-3b57f4fc-010c-4e6e-976d-f9c4fca75888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175632581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3175632581
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.2102480427
Short name T145
Test name
Test status
Simulation time 27516462 ps
CPU time 0.72 seconds
Started Feb 29 02:49:20 PM PST 24
Finished Feb 29 02:49:21 PM PST 24
Peak memory 202780 kb
Host smart-218313f3-84fc-45af-a482-deddf354605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102480427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2102480427
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3346457629
Short name T1058
Test name
Test status
Simulation time 263127423 ps
CPU time 1.85 seconds
Started Feb 29 02:49:21 PM PST 24
Finished Feb 29 02:49:23 PM PST 24
Peak memory 221388 kb
Host smart-518fd4e7-4dd4-4fcc-b918-80570264330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346457629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3346457629
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_rx_oversample.4197910242
Short name T943
Test name
Test status
Simulation time 2788188524 ps
CPU time 186.62 seconds
Started Feb 29 02:49:22 PM PST 24
Finished Feb 29 02:52:29 PM PST 24
Peak memory 385764 kb
Host smart-a6824256-5da5-49de-852d-57b510464647
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197910242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_rx_oversample
.4197910242
Directory /workspace/34.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.230867028
Short name T358
Test name
Test status
Simulation time 4989460203 ps
CPU time 148.71 seconds
Started Feb 29 02:49:20 PM PST 24
Finished Feb 29 02:51:48 PM PST 24
Peak memory 260000 kb
Host smart-f457d266-f482-4a98-a997-6520e0e20572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230867028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.230867028
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.458346455
Short name T823
Test name
Test status
Simulation time 17200946501 ps
CPU time 21.85 seconds
Started Feb 29 02:49:20 PM PST 24
Finished Feb 29 02:49:42 PM PST 24
Peak memory 219888 kb
Host smart-0de6940c-2c15-4d82-94c4-b75f55556e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458346455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.458346455
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.3556808131
Short name T626
Test name
Test status
Simulation time 1014074947 ps
CPU time 3.94 seconds
Started Feb 29 02:49:31 PM PST 24
Finished Feb 29 02:49:35 PM PST 24
Peak memory 203692 kb
Host smart-85e51a77-55b1-46ed-a7aa-fc64aa5a1699
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556808131 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3556808131
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2076295812
Short name T364
Test name
Test status
Simulation time 10088046515 ps
CPU time 69.95 seconds
Started Feb 29 02:49:32 PM PST 24
Finished Feb 29 02:50:42 PM PST 24
Peak memory 617336 kb
Host smart-d214f6db-d853-4999-b3b7-36674072c02f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076295812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2076295812
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2079440837
Short name T970
Test name
Test status
Simulation time 10068193036 ps
CPU time 54.03 seconds
Started Feb 29 02:49:30 PM PST 24
Finished Feb 29 02:50:25 PM PST 24
Peak memory 561900 kb
Host smart-e7bce068-6340-4d0d-9c46-cbac2a993be9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079440837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2079440837
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1918524644
Short name T495
Test name
Test status
Simulation time 1782101715 ps
CPU time 2.29 seconds
Started Feb 29 02:49:31 PM PST 24
Finished Feb 29 02:49:34 PM PST 24
Peak memory 203704 kb
Host smart-b2a216c9-990a-446e-88c8-d536307bbef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918524644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1918524644
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.614860124
Short name T195
Test name
Test status
Simulation time 1902772916 ps
CPU time 6.2 seconds
Started Feb 29 02:49:21 PM PST 24
Finished Feb 29 02:49:28 PM PST 24
Peak memory 203776 kb
Host smart-6acca6e6-839f-4b91-bbe5-355669437e5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614860124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.614860124
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1944698298
Short name T711
Test name
Test status
Simulation time 14089233280 ps
CPU time 57.36 seconds
Started Feb 29 02:49:24 PM PST 24
Finished Feb 29 02:50:22 PM PST 24
Peak memory 916140 kb
Host smart-b71283a6-7321-4651-8c08-fb2802a399cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944698298 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1944698298
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_perf.2352954209
Short name T452
Test name
Test status
Simulation time 810920563 ps
CPU time 4.86 seconds
Started Feb 29 02:49:34 PM PST 24
Finished Feb 29 02:49:39 PM PST 24
Peak memory 203696 kb
Host smart-4a1f760c-590a-4266-8552-d42e18947619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352954209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_perf.2352954209
Directory /workspace/34.i2c_target_perf/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.3596480865
Short name T596
Test name
Test status
Simulation time 118262920225 ps
CPU time 249.14 seconds
Started Feb 29 02:49:30 PM PST 24
Finished Feb 29 02:53:40 PM PST 24
Peak memory 1804004 kb
Host smart-ff1ef69b-5c62-42ad-acda-e075d5a07102
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596480865 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.3596480865
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2006210308
Short name T1093
Test name
Test status
Simulation time 78639165386 ps
CPU time 704.36 seconds
Started Feb 29 02:49:20 PM PST 24
Finished Feb 29 03:01:04 PM PST 24
Peak memory 4808292 kb
Host smart-1a036143-6bb0-4dfc-bd97-dc39bca297b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006210308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2006210308
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.4184649663
Short name T1151
Test name
Test status
Simulation time 6216191182 ps
CPU time 25.53 seconds
Started Feb 29 02:49:19 PM PST 24
Finished Feb 29 02:49:45 PM PST 24
Peak memory 500780 kb
Host smart-3097161a-2a31-41c8-b8c0-bbc74494b56d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184649663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.4184649663
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.3935366075
Short name T553
Test name
Test status
Simulation time 4859923667 ps
CPU time 7.66 seconds
Started Feb 29 02:49:23 PM PST 24
Finished Feb 29 02:49:30 PM PST 24
Peak memory 207880 kb
Host smart-b03e351e-e198-4b34-abe8-c127f9744c4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935366075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.3935366075
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.1403460409
Short name T784
Test name
Test status
Simulation time 1740321109 ps
CPU time 8.11 seconds
Started Feb 29 02:49:21 PM PST 24
Finished Feb 29 02:49:29 PM PST 24
Peak memory 203624 kb
Host smart-d14391d8-e87b-4945-a50f-d7f19639bde3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403460409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.1403460409
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2182673956
Short name T771
Test name
Test status
Simulation time 73725156 ps
CPU time 0.63 seconds
Started Feb 29 02:49:45 PM PST 24
Finished Feb 29 02:49:46 PM PST 24
Peak memory 202448 kb
Host smart-96e4ce6f-1de2-42fd-819f-826c007e2213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182673956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2182673956
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2274932443
Short name T234
Test name
Test status
Simulation time 80981718 ps
CPU time 1.46 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:49:37 PM PST 24
Peak memory 211892 kb
Host smart-b364bb01-c1e9-49f1-8590-b80c006ef53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274932443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2274932443
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2579597456
Short name T601
Test name
Test status
Simulation time 1712109218 ps
CPU time 8.32 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:49:43 PM PST 24
Peak memory 232360 kb
Host smart-ff6a5549-1b8b-4f27-9f9e-836366fbc4bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579597456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2579597456
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.938480827
Short name T521
Test name
Test status
Simulation time 15262150703 ps
CPU time 187.33 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:52:43 PM PST 24
Peak memory 1157028 kb
Host smart-dba633c2-a160-48ba-a082-e1862da88065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938480827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.938480827
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3514889241
Short name T17
Test name
Test status
Simulation time 2545617732 ps
CPU time 90.11 seconds
Started Feb 29 02:49:34 PM PST 24
Finished Feb 29 02:51:04 PM PST 24
Peak memory 784948 kb
Host smart-8ebdaec8-4349-44bc-9244-e0c78a656c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514889241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3514889241
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1486444171
Short name T1318
Test name
Test status
Simulation time 212298997 ps
CPU time 5.18 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:49:40 PM PST 24
Peak memory 243192 kb
Host smart-e73568b2-10f0-4576-9a6b-f5184fb75b06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486444171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1486444171
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.700077805
Short name T135
Test name
Test status
Simulation time 10925491632 ps
CPU time 212.72 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:53:08 PM PST 24
Peak memory 1892364 kb
Host smart-1fcf1987-e950-4d12-8ca2-877520fdd9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700077805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.700077805
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3778512024
Short name T178
Test name
Test status
Simulation time 1642132293 ps
CPU time 82.14 seconds
Started Feb 29 02:49:43 PM PST 24
Finished Feb 29 02:51:05 PM PST 24
Peak memory 234200 kb
Host smart-772545e2-c463-4687-9058-7b3e4dabe32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778512024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3778512024
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.978584394
Short name T960
Test name
Test status
Simulation time 18224194 ps
CPU time 0.66 seconds
Started Feb 29 02:49:32 PM PST 24
Finished Feb 29 02:49:33 PM PST 24
Peak memory 202720 kb
Host smart-0d79774b-cb30-40a3-a17d-444388923fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978584394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.978584394
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_rx_oversample.1347948110
Short name T255
Test name
Test status
Simulation time 3235711411 ps
CPU time 265.37 seconds
Started Feb 29 02:49:31 PM PST 24
Finished Feb 29 02:53:57 PM PST 24
Peak memory 311488 kb
Host smart-77efd8c9-38d0-4248-9a05-d8664282ff3c
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347948110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_rx_oversample
.1347948110
Directory /workspace/35.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1975647356
Short name T1282
Test name
Test status
Simulation time 2328657762 ps
CPU time 58.85 seconds
Started Feb 29 02:49:31 PM PST 24
Finished Feb 29 02:50:30 PM PST 24
Peak memory 283880 kb
Host smart-c7f1f53e-78c9-42c8-8295-ba745e69dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975647356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1975647356
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.1676789067
Short name T828
Test name
Test status
Simulation time 1292442485 ps
CPU time 10.76 seconds
Started Feb 29 02:49:33 PM PST 24
Finished Feb 29 02:49:44 PM PST 24
Peak memory 213712 kb
Host smart-7c3e058e-7ebb-44de-aa42-5238da17441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676789067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1676789067
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1990320848
Short name T227
Test name
Test status
Simulation time 767446868 ps
CPU time 3.58 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:49:38 PM PST 24
Peak memory 203648 kb
Host smart-673a54ae-da9d-4c1c-a8ae-e8f669ea704a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990320848 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1990320848
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2805964067
Short name T1236
Test name
Test status
Simulation time 10078428688 ps
CPU time 58.72 seconds
Started Feb 29 02:49:34 PM PST 24
Finished Feb 29 02:50:33 PM PST 24
Peak memory 544608 kb
Host smart-dbcc4a84-a61f-4b53-a9a2-a6e6b995dc65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805964067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2805964067
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.411846254
Short name T8
Test name
Test status
Simulation time 10215314650 ps
CPU time 14.27 seconds
Started Feb 29 02:49:34 PM PST 24
Finished Feb 29 02:49:48 PM PST 24
Peak memory 332268 kb
Host smart-40d2e1a8-8e5d-48f8-a4a5-038b7582fbaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411846254 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.411846254
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3887034630
Short name T1319
Test name
Test status
Simulation time 410694547 ps
CPU time 2.52 seconds
Started Feb 29 02:49:44 PM PST 24
Finished Feb 29 02:49:46 PM PST 24
Peak memory 203608 kb
Host smart-eae9a23d-ed58-4d6a-a501-d5d2c11dda72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887034630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3887034630
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.367921709
Short name T1253
Test name
Test status
Simulation time 2009210314 ps
CPU time 7.59 seconds
Started Feb 29 02:49:32 PM PST 24
Finished Feb 29 02:49:40 PM PST 24
Peak memory 207804 kb
Host smart-bbe84049-10f3-481e-9318-bf8ccc50873a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367921709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.367921709
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2446521042
Short name T805
Test name
Test status
Simulation time 15361326708 ps
CPU time 152.66 seconds
Started Feb 29 02:49:31 PM PST 24
Finished Feb 29 02:52:04 PM PST 24
Peak memory 1849692 kb
Host smart-400f3f3a-b6b8-41fa-acac-ceb5d4c8801f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446521042 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2446521042
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_perf.3717602917
Short name T1072
Test name
Test status
Simulation time 864717770 ps
CPU time 4.64 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:49:39 PM PST 24
Peak memory 209736 kb
Host smart-fe0a266e-ed14-43ef-b27a-d6ef5774ab0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717602917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_perf.3717602917
Directory /workspace/35.i2c_target_perf/latest

Test location /workspace/coverage/default/35.i2c_target_stress_all.1977144738
Short name T1271
Test name
Test status
Simulation time 32910014848 ps
CPU time 21.54 seconds
Started Feb 29 02:49:34 PM PST 24
Finished Feb 29 02:49:56 PM PST 24
Peak memory 214324 kb
Host smart-87b31ace-a930-4a8e-a7af-2653d7fb3023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977144738 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.i2c_target_stress_all.1977144738
Directory /workspace/35.i2c_target_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2055814139
Short name T928
Test name
Test status
Simulation time 1556359055 ps
CPU time 15.95 seconds
Started Feb 29 02:49:35 PM PST 24
Finished Feb 29 02:49:51 PM PST 24
Peak memory 203708 kb
Host smart-2fa31a9c-b1ce-4574-a980-8ae9f9ce7d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055814139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2055814139
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2983610323
Short name T1187
Test name
Test status
Simulation time 47966417894 ps
CPU time 72.52 seconds
Started Feb 29 02:49:34 PM PST 24
Finished Feb 29 02:50:47 PM PST 24
Peak memory 1007040 kb
Host smart-31e26d6d-af1d-4013-815e-e8390e2560fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983610323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2983610323
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2332732937
Short name T759
Test name
Test status
Simulation time 6167567347 ps
CPU time 11.77 seconds
Started Feb 29 02:49:33 PM PST 24
Finished Feb 29 02:49:45 PM PST 24
Peak memory 320780 kb
Host smart-2f538a9a-2116-4551-86b5-a7adf44d1eed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332732937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2332732937
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1519713047
Short name T1124
Test name
Test status
Simulation time 1593390834 ps
CPU time 7.3 seconds
Started Feb 29 02:49:31 PM PST 24
Finished Feb 29 02:49:39 PM PST 24
Peak memory 212652 kb
Host smart-31b7de1a-1be2-41a8-9442-bba7d31c7fcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519713047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1519713047
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.1547305929
Short name T1230
Test name
Test status
Simulation time 6414556387 ps
CPU time 8.92 seconds
Started Feb 29 02:49:34 PM PST 24
Finished Feb 29 02:49:43 PM PST 24
Peak memory 203600 kb
Host smart-c4c00c7d-b583-4204-80e6-909c5a2da5fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547305929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.1547305929
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2747019951
Short name T81
Test name
Test status
Simulation time 16323374 ps
CPU time 0.62 seconds
Started Feb 29 02:49:55 PM PST 24
Finished Feb 29 02:49:56 PM PST 24
Peak memory 202580 kb
Host smart-da95efda-38af-4b4f-9d19-5167a82c7fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747019951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2747019951
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2794567967
Short name T1057
Test name
Test status
Simulation time 86659588 ps
CPU time 1.58 seconds
Started Feb 29 02:49:47 PM PST 24
Finished Feb 29 02:49:49 PM PST 24
Peak memory 213536 kb
Host smart-4a8d8914-0cef-4bfd-964c-2d18a2d98527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794567967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2794567967
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.4191714256
Short name T574
Test name
Test status
Simulation time 1347948143 ps
CPU time 10.14 seconds
Started Feb 29 02:49:46 PM PST 24
Finished Feb 29 02:49:56 PM PST 24
Peak memory 305132 kb
Host smart-6c5452dc-3b40-43c4-9d1c-ccd7d4943ed7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191714256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.4191714256
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2685904780
Short name T689
Test name
Test status
Simulation time 11066439736 ps
CPU time 138.67 seconds
Started Feb 29 02:49:44 PM PST 24
Finished Feb 29 02:52:03 PM PST 24
Peak memory 1060780 kb
Host smart-420e65ec-895c-4dd7-b95f-117e42f7be9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685904780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2685904780
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2785158343
Short name T1103
Test name
Test status
Simulation time 11167319491 ps
CPU time 102.37 seconds
Started Feb 29 02:49:44 PM PST 24
Finished Feb 29 02:51:26 PM PST 24
Peak memory 868596 kb
Host smart-dce895b8-d90e-4646-a6dc-4e7708f6afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785158343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2785158343
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.567497200
Short name T1273
Test name
Test status
Simulation time 1523225271 ps
CPU time 3.42 seconds
Started Feb 29 02:49:43 PM PST 24
Finished Feb 29 02:49:46 PM PST 24
Peak memory 203608 kb
Host smart-e15d78aa-0f89-415f-ac72-663a54e03bda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567497200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
567497200
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.483924280
Short name T1285
Test name
Test status
Simulation time 5453113396 ps
CPU time 187.89 seconds
Started Feb 29 02:49:43 PM PST 24
Finished Feb 29 02:52:51 PM PST 24
Peak memory 1550096 kb
Host smart-12b44264-e39d-4192-87ef-edf9a5ec01e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483924280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.483924280
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3997127251
Short name T141
Test name
Test status
Simulation time 6395608053 ps
CPU time 91.24 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:51:30 PM PST 24
Peak memory 244176 kb
Host smart-68264999-34b0-460f-8733-a19e42568f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997127251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3997127251
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2437064903
Short name T151
Test name
Test status
Simulation time 60524891 ps
CPU time 0.64 seconds
Started Feb 29 02:49:44 PM PST 24
Finished Feb 29 02:49:45 PM PST 24
Peak memory 202692 kb
Host smart-6616945d-4366-47b4-bb4f-d730acab0c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437064903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2437064903
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.274010971
Short name T188
Test name
Test status
Simulation time 6429186141 ps
CPU time 58.46 seconds
Started Feb 29 02:49:44 PM PST 24
Finished Feb 29 02:50:42 PM PST 24
Peak memory 312376 kb
Host smart-1ea01358-249b-4a03-89c9-9b20dfc2847c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274010971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.274010971
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_rx_oversample.3277085784
Short name T208
Test name
Test status
Simulation time 7371074312 ps
CPU time 140.94 seconds
Started Feb 29 02:49:45 PM PST 24
Finished Feb 29 02:52:06 PM PST 24
Peak memory 267288 kb
Host smart-aca8bb62-bf86-4635-bcc1-420aa8257b32
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277085784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_rx_oversample
.3277085784
Directory /workspace/36.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2408957015
Short name T728
Test name
Test status
Simulation time 4094254824 ps
CPU time 115.03 seconds
Started Feb 29 02:49:44 PM PST 24
Finished Feb 29 02:51:39 PM PST 24
Peak memory 251940 kb
Host smart-841e223d-7b55-4d42-9277-2ea60713fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408957015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2408957015
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3024039232
Short name T603
Test name
Test status
Simulation time 590269624 ps
CPU time 10.51 seconds
Started Feb 29 02:49:45 PM PST 24
Finished Feb 29 02:49:55 PM PST 24
Peak memory 211848 kb
Host smart-293f1b55-1ec3-4133-991a-5ec05432ee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024039232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3024039232
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2234327805
Short name T609
Test name
Test status
Simulation time 914610297 ps
CPU time 3.65 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:01 PM PST 24
Peak memory 203560 kb
Host smart-b4e1f294-aa36-48e6-ab1d-ada2bc83b57b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234327805 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2234327805
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.619483865
Short name T1175
Test name
Test status
Simulation time 10426820553 ps
CPU time 12.16 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:11 PM PST 24
Peak memory 296460 kb
Host smart-13fa9f29-6d1f-4f3e-b40a-dd4329aa704b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619483865 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.619483865
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2498097545
Short name T1301
Test name
Test status
Simulation time 10873475217 ps
CPU time 6.23 seconds
Started Feb 29 02:49:56 PM PST 24
Finished Feb 29 02:50:03 PM PST 24
Peak memory 261540 kb
Host smart-55498ed9-04d2-4ca4-8f35-3689e80eac3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498097545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2498097545
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.4027696052
Short name T434
Test name
Test status
Simulation time 589777512 ps
CPU time 1.86 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:00 PM PST 24
Peak memory 203652 kb
Host smart-824edc1d-604f-4ebb-a2dd-46c2caf36ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027696052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.4027696052
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2096860769
Short name T674
Test name
Test status
Simulation time 1482299734 ps
CPU time 3.94 seconds
Started Feb 29 02:49:45 PM PST 24
Finished Feb 29 02:49:49 PM PST 24
Peak memory 206128 kb
Host smart-c3bc76f8-208b-42cc-a084-814539620358
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096860769 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2096860769
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.112693612
Short name T425
Test name
Test status
Simulation time 22918288871 ps
CPU time 83.14 seconds
Started Feb 29 02:49:43 PM PST 24
Finished Feb 29 02:51:06 PM PST 24
Peak memory 1000456 kb
Host smart-14e4787c-d503-4815-bc05-a391928acce0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112693612 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.112693612
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_perf.3923946996
Short name T914
Test name
Test status
Simulation time 886338357 ps
CPU time 4.83 seconds
Started Feb 29 02:49:56 PM PST 24
Finished Feb 29 02:50:01 PM PST 24
Peak memory 203640 kb
Host smart-c14d8224-af52-404a-bc81-20651a6c545a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923946996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_perf.3923946996
Directory /workspace/36.i2c_target_perf/latest

Test location /workspace/coverage/default/36.i2c_target_stress_all.2442610440
Short name T985
Test name
Test status
Simulation time 57286925020 ps
CPU time 276.51 seconds
Started Feb 29 02:49:56 PM PST 24
Finished Feb 29 02:54:32 PM PST 24
Peak memory 2288896 kb
Host smart-4f80c061-4dfe-4226-bef9-3fbcc5802ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442610440 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_stress_all.2442610440
Directory /workspace/36.i2c_target_stress_all/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1351115500
Short name T193
Test name
Test status
Simulation time 18189539378 ps
CPU time 42.68 seconds
Started Feb 29 02:49:46 PM PST 24
Finished Feb 29 02:50:29 PM PST 24
Peak memory 986088 kb
Host smart-866ec719-c817-4db1-aa2a-ee3ad738d653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351115500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1351115500
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3533044923
Short name T636
Test name
Test status
Simulation time 38830956949 ps
CPU time 3450.49 seconds
Started Feb 29 02:49:45 PM PST 24
Finished Feb 29 03:47:16 PM PST 24
Peak memory 8495688 kb
Host smart-b10c2dd7-80df-4184-80aa-408d4855748d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533044923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3533044923
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2302583847
Short name T1183
Test name
Test status
Simulation time 1872390724 ps
CPU time 7.47 seconds
Started Feb 29 02:49:45 PM PST 24
Finished Feb 29 02:49:52 PM PST 24
Peak memory 207144 kb
Host smart-d1fd30fc-d500-4c99-a5db-a2504b73111f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302583847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2302583847
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.4228921555
Short name T322
Test name
Test status
Simulation time 1287414170 ps
CPU time 6.81 seconds
Started Feb 29 02:49:56 PM PST 24
Finished Feb 29 02:50:03 PM PST 24
Peak memory 203656 kb
Host smart-013b0042-f0a3-4737-a9af-f6f3a5f07715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228921555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.4228921555
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3947331248
Short name T581
Test name
Test status
Simulation time 15060289 ps
CPU time 0.6 seconds
Started Feb 29 02:49:56 PM PST 24
Finished Feb 29 02:49:57 PM PST 24
Peak memory 202572 kb
Host smart-57764e92-3903-4aeb-9e9e-c94f32488761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947331248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3947331248
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.4172867673
Short name T1141
Test name
Test status
Simulation time 38900387 ps
CPU time 1.09 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:00 PM PST 24
Peak memory 203648 kb
Host smart-b8f95ad0-a1d2-449b-a8ce-218b01167607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172867673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.4172867673
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3435747801
Short name T863
Test name
Test status
Simulation time 607789541 ps
CPU time 4.19 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:50:02 PM PST 24
Peak memory 234812 kb
Host smart-7db04043-5f1d-44d7-881a-3af1a0ba074d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435747801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3435747801
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1459667411
Short name T446
Test name
Test status
Simulation time 2505794660 ps
CPU time 97.72 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:51:36 PM PST 24
Peak memory 820924 kb
Host smart-b91afa4c-5721-4622-bec7-6f75e111e00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459667411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1459667411
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2524027252
Short name T230
Test name
Test status
Simulation time 7469280269 ps
CPU time 283.69 seconds
Started Feb 29 02:49:59 PM PST 24
Finished Feb 29 02:54:44 PM PST 24
Peak memory 1002580 kb
Host smart-4fc3d6ad-a05e-4662-ac46-5ddc9bd4b85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524027252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2524027252
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.228288932
Short name T743
Test name
Test status
Simulation time 223426148 ps
CPU time 6.16 seconds
Started Feb 29 02:49:59 PM PST 24
Finished Feb 29 02:50:06 PM PST 24
Peak memory 244688 kb
Host smart-f983c367-698f-46a0-ba9a-8debe7159b17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228288932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
228288932
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1448310124
Short name T544
Test name
Test status
Simulation time 3608324862 ps
CPU time 46.81 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:50:44 PM PST 24
Peak memory 279176 kb
Host smart-1b76e23d-a2b9-47ed-9625-44a3f7a714da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448310124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1448310124
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1066134639
Short name T404
Test name
Test status
Simulation time 14854132 ps
CPU time 0.62 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:49:58 PM PST 24
Peak memory 202772 kb
Host smart-eead53b9-5e55-4526-a66a-cd88ce85b8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066134639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1066134639
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1714950274
Short name T1133
Test name
Test status
Simulation time 27358734999 ps
CPU time 428.4 seconds
Started Feb 29 02:50:00 PM PST 24
Finished Feb 29 02:57:08 PM PST 24
Peak memory 211792 kb
Host smart-9c493852-5b31-4316-a789-91be3718e70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714950274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1714950274
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_rx_oversample.1848324129
Short name T951
Test name
Test status
Simulation time 3217557795 ps
CPU time 202.22 seconds
Started Feb 29 02:50:18 PM PST 24
Finished Feb 29 02:53:40 PM PST 24
Peak memory 418176 kb
Host smart-6adf49c4-526e-4efa-9f0a-bd150060d989
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848324129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_rx_oversample
.1848324129
Directory /workspace/37.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1899510990
Short name T242
Test name
Test status
Simulation time 3434321332 ps
CPU time 48.64 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:50:46 PM PST 24
Peak memory 287504 kb
Host smart-fd0af054-e3ee-4fc7-99bc-ed54eb287a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899510990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1899510990
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2803903701
Short name T1113
Test name
Test status
Simulation time 1088514925 ps
CPU time 47.57 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:50:44 PM PST 24
Peak memory 211940 kb
Host smart-5092c999-0493-4df2-822a-30cdfe244219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803903701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2803903701
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1065505184
Short name T296
Test name
Test status
Simulation time 4868073524 ps
CPU time 5.67 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:50:03 PM PST 24
Peak memory 203692 kb
Host smart-3c16fc3b-f12c-4020-a7ce-bc981c1d2145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065505184 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1065505184
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3261451784
Short name T1307
Test name
Test status
Simulation time 10317358248 ps
CPU time 8.19 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:07 PM PST 24
Peak memory 246728 kb
Host smart-0b9880d6-eae2-4f11-af0d-3f6886ccdacc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261451784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3261451784
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1323926275
Short name T342
Test name
Test status
Simulation time 10074508713 ps
CPU time 60.61 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:50:58 PM PST 24
Peak memory 514812 kb
Host smart-b618a0e3-fa3e-4363-8049-e0816d6ab74d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323926275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1323926275
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1858971029
Short name T104
Test name
Test status
Simulation time 1589329528 ps
CPU time 3.39 seconds
Started Feb 29 02:50:00 PM PST 24
Finished Feb 29 02:50:04 PM PST 24
Peak memory 203660 kb
Host smart-ac2e29c7-50b9-4685-aaf4-0acc4722acac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858971029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1858971029
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2024173639
Short name T516
Test name
Test status
Simulation time 1452876135 ps
CPU time 6.12 seconds
Started Feb 29 02:49:56 PM PST 24
Finished Feb 29 02:50:03 PM PST 24
Peak memory 203616 kb
Host smart-e968180a-1924-4da4-8d2c-798313672477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024173639 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2024173639
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.2102502593
Short name T418
Test name
Test status
Simulation time 13250692448 ps
CPU time 5.29 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:50:02 PM PST 24
Peak memory 203628 kb
Host smart-b808f786-1f8a-4e6f-b0f5-6cb6893f28ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102502593 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.2102502593
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_perf.1688911667
Short name T559
Test name
Test status
Simulation time 631176105 ps
CPU time 3.92 seconds
Started Feb 29 02:49:59 PM PST 24
Finished Feb 29 02:50:04 PM PST 24
Peak memory 203584 kb
Host smart-9b8b52dd-929b-47ff-a276-36acc8e5b371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688911667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_perf.1688911667
Directory /workspace/37.i2c_target_perf/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.3104577204
Short name T698
Test name
Test status
Simulation time 61315116224 ps
CPU time 81.92 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:51:20 PM PST 24
Peak memory 559376 kb
Host smart-f69b32a8-7bd0-4b12-8702-79cb1506b65c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104577204 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.3104577204
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.2110802698
Short name T279
Test name
Test status
Simulation time 16138856717 ps
CPU time 71.02 seconds
Started Feb 29 02:49:59 PM PST 24
Finished Feb 29 02:51:11 PM PST 24
Peak memory 204204 kb
Host smart-ab27939f-b788-479a-be7b-8e882ae13cb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110802698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.2110802698
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4227322642
Short name T1254
Test name
Test status
Simulation time 55424792441 ps
CPU time 1054.96 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 03:07:33 PM PST 24
Peak memory 6644216 kb
Host smart-cf6a3589-865e-4477-a85f-45cbfdf8f5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227322642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4227322642
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2026102017
Short name T1335
Test name
Test status
Simulation time 2079834986 ps
CPU time 8.51 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:06 PM PST 24
Peak memory 213536 kb
Host smart-31dd89a0-410e-42c0-8243-96980ea310fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026102017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2026102017
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.257867468
Short name T896
Test name
Test status
Simulation time 4910166314 ps
CPU time 6.22 seconds
Started Feb 29 02:50:00 PM PST 24
Finished Feb 29 02:50:07 PM PST 24
Peak memory 205804 kb
Host smart-0a458631-2053-4d0a-b3d3-1ff61d25e366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257867468 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_unexp_stop.257867468
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3735857293
Short name T378
Test name
Test status
Simulation time 67794581 ps
CPU time 0.62 seconds
Started Feb 29 02:50:09 PM PST 24
Finished Feb 29 02:50:10 PM PST 24
Peak memory 202564 kb
Host smart-4e55f401-fe60-4466-a7bc-f3dd9da8a08d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735857293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3735857293
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2916361542
Short name T53
Test name
Test status
Simulation time 79943341 ps
CPU time 1.27 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:49:59 PM PST 24
Peak memory 203612 kb
Host smart-e6668ec4-6369-40fa-942a-3b70bbdc9a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916361542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2916361542
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.67627248
Short name T662
Test name
Test status
Simulation time 1593300329 ps
CPU time 21.6 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:19 PM PST 24
Peak memory 292640 kb
Host smart-97002926-c480-4222-9fc5-7fb8c5bc63cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67627248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty
.67627248
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2538131293
Short name T61
Test name
Test status
Simulation time 7673124037 ps
CPU time 317.82 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:55:16 PM PST 24
Peak memory 1073600 kb
Host smart-f707602a-8083-4b00-b381-ccc2f95637f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538131293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2538131293
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2180964264
Short name T533
Test name
Test status
Simulation time 14197505734 ps
CPU time 141.26 seconds
Started Feb 29 02:49:57 PM PST 24
Finished Feb 29 02:52:18 PM PST 24
Peak memory 1054384 kb
Host smart-69e94e69-2d82-449e-9663-bfa9aab56f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180964264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2180964264
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.913761037
Short name T39
Test name
Test status
Simulation time 302678449 ps
CPU time 0.81 seconds
Started Feb 29 02:49:59 PM PST 24
Finished Feb 29 02:50:00 PM PST 24
Peak memory 203364 kb
Host smart-1c6e008f-7705-4ea5-bb3b-360fa8713059
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913761037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.913761037
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1134659325
Short name T1080
Test name
Test status
Simulation time 690097981 ps
CPU time 6.36 seconds
Started Feb 29 02:50:00 PM PST 24
Finished Feb 29 02:50:06 PM PST 24
Peak memory 257208 kb
Host smart-8b068394-80d7-48d3-a4d6-107a047aed5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134659325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1134659325
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2171422433
Short name T1025
Test name
Test status
Simulation time 7605955692 ps
CPU time 244.01 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:54:03 PM PST 24
Peak memory 1000172 kb
Host smart-9706f4e0-3436-40c5-af2a-497c9c159128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171422433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2171422433
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.3722790607
Short name T180
Test name
Test status
Simulation time 1900226174 ps
CPU time 35.42 seconds
Started Feb 29 02:50:15 PM PST 24
Finished Feb 29 02:50:51 PM PST 24
Peak memory 248512 kb
Host smart-3b0fc5b9-7f21-4b28-b54a-2f9773be94de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722790607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.3722790607
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.762175928
Short name T709
Test name
Test status
Simulation time 23437498 ps
CPU time 0.67 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:00 PM PST 24
Peak memory 202796 kb
Host smart-2814ed6c-1f21-4b11-b5b1-8422224cbacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762175928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.762175928
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1381139485
Short name T292
Test name
Test status
Simulation time 4781581257 ps
CPU time 33.86 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:50:32 PM PST 24
Peak memory 203768 kb
Host smart-471bb1a1-ac01-4fc4-9988-10965b262434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381139485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1381139485
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_rx_oversample.3221321549
Short name T207
Test name
Test status
Simulation time 11259360598 ps
CPU time 93.48 seconds
Started Feb 29 02:49:58 PM PST 24
Finished Feb 29 02:51:32 PM PST 24
Peak memory 305484 kb
Host smart-970ab2d2-ccf9-4aff-a142-53aecdf21981
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221321549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_rx_oversample
.3221321549
Directory /workspace/38.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1031041173
Short name T160
Test name
Test status
Simulation time 11762659373 ps
CPU time 109.44 seconds
Started Feb 29 02:50:00 PM PST 24
Finished Feb 29 02:51:50 PM PST 24
Peak memory 266680 kb
Host smart-93e3571c-bb51-473c-a614-18c398e0f839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031041173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1031041173
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1908306340
Short name T866
Test name
Test status
Simulation time 6289003219 ps
CPU time 32.92 seconds
Started Feb 29 02:49:59 PM PST 24
Finished Feb 29 02:50:33 PM PST 24
Peak memory 211884 kb
Host smart-79dc72c2-fa8d-45d0-8994-9f791a815007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908306340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1908306340
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2460673753
Short name T340
Test name
Test status
Simulation time 2771819828 ps
CPU time 4.83 seconds
Started Feb 29 02:50:09 PM PST 24
Finished Feb 29 02:50:14 PM PST 24
Peak memory 203772 kb
Host smart-66ac15ea-d912-4fa8-a693-38956478f234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460673753 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2460673753
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3362166812
Short name T1019
Test name
Test status
Simulation time 10031447144 ps
CPU time 60.84 seconds
Started Feb 29 02:50:10 PM PST 24
Finished Feb 29 02:51:11 PM PST 24
Peak memory 474136 kb
Host smart-380b03bb-0ba9-4e0c-9ace-df63b5bbc9d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362166812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3362166812
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3864238683
Short name T241
Test name
Test status
Simulation time 10464030999 ps
CPU time 13.04 seconds
Started Feb 29 02:50:16 PM PST 24
Finished Feb 29 02:50:29 PM PST 24
Peak memory 314800 kb
Host smart-82be743d-d019-4bb4-bce2-06ce4304abc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864238683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3864238683
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3984054792
Short name T49
Test name
Test status
Simulation time 1014989437 ps
CPU time 2.72 seconds
Started Feb 29 02:50:12 PM PST 24
Finished Feb 29 02:50:15 PM PST 24
Peak memory 203600 kb
Host smart-35b13337-3b0e-461d-b2ac-eeca548b176d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984054792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3984054792
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.724893494
Short name T963
Test name
Test status
Simulation time 1213523220 ps
CPU time 5.25 seconds
Started Feb 29 02:50:16 PM PST 24
Finished Feb 29 02:50:21 PM PST 24
Peak memory 203684 kb
Host smart-67cb557e-f489-49f9-b522-c837bf6d8c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724893494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.724893494
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3318747397
Short name T836
Test name
Test status
Simulation time 9448937560 ps
CPU time 51.83 seconds
Started Feb 29 02:50:15 PM PST 24
Finished Feb 29 02:51:07 PM PST 24
Peak memory 1096344 kb
Host smart-15520a14-9414-422a-a34c-851e1d9993a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318747397 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3318747397
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_perf.811929267
Short name T1170
Test name
Test status
Simulation time 4131214163 ps
CPU time 5.81 seconds
Started Feb 29 02:50:12 PM PST 24
Finished Feb 29 02:50:18 PM PST 24
Peak memory 203724 kb
Host smart-cbabcf0f-6650-4b64-b96d-23195437cc64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811929267 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_perf.811929267
Directory /workspace/38.i2c_target_perf/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.777355572
Short name T785
Test name
Test status
Simulation time 31288615580 ps
CPU time 541.72 seconds
Started Feb 29 02:50:08 PM PST 24
Finished Feb 29 02:59:10 PM PST 24
Peak memory 5086532 kb
Host smart-1cbdda8c-0752-4f00-ab25-4bc4dec0f7a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777355572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.i2c_target_stress_all.777355572
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1281995132
Short name T615
Test name
Test status
Simulation time 5026713669 ps
CPU time 15.5 seconds
Started Feb 29 02:50:11 PM PST 24
Finished Feb 29 02:50:27 PM PST 24
Peak memory 206964 kb
Host smart-5b8c290b-6fde-4c16-8979-4d19e9ff003c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281995132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1281995132
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3346809288
Short name T46
Test name
Test status
Simulation time 30285691871 ps
CPU time 207.44 seconds
Started Feb 29 02:50:13 PM PST 24
Finished Feb 29 02:53:41 PM PST 24
Peak memory 1660520 kb
Host smart-6297d9c7-ed4d-458d-9d15-b8293863b4d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346809288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3346809288
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.481869677
Short name T346
Test name
Test status
Simulation time 1796305047 ps
CPU time 7.42 seconds
Started Feb 29 02:50:16 PM PST 24
Finished Feb 29 02:50:24 PM PST 24
Peak memory 212036 kb
Host smart-3e79c82c-9ed8-466e-81d7-9825c12eceeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481869677 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.481869677
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.3164902899
Short name T1288
Test name
Test status
Simulation time 748343894 ps
CPU time 3.81 seconds
Started Feb 29 02:50:14 PM PST 24
Finished Feb 29 02:50:18 PM PST 24
Peak memory 203684 kb
Host smart-bb614689-8f0e-43d9-ba3b-4c778e7d5582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164902899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.3164902899
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1841299391
Short name T1139
Test name
Test status
Simulation time 15951685 ps
CPU time 0.59 seconds
Started Feb 29 02:50:24 PM PST 24
Finished Feb 29 02:50:25 PM PST 24
Peak memory 202572 kb
Host smart-3398b25f-6d31-406d-9606-8e3ac10f5f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841299391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1841299391
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2209106638
Short name T422
Test name
Test status
Simulation time 139320326 ps
CPU time 1.18 seconds
Started Feb 29 02:50:09 PM PST 24
Finished Feb 29 02:50:10 PM PST 24
Peak memory 211848 kb
Host smart-e15fe093-45aa-455f-b1e9-e0ec7a171617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209106638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2209106638
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.4206211856
Short name T318
Test name
Test status
Simulation time 1279668525 ps
CPU time 16.56 seconds
Started Feb 29 02:50:15 PM PST 24
Finished Feb 29 02:50:32 PM PST 24
Peak memory 273396 kb
Host smart-c7db5709-b500-4c0a-8a8e-bca6d607ae73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206211856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.4206211856
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3746796356
Short name T490
Test name
Test status
Simulation time 7472240948 ps
CPU time 55.38 seconds
Started Feb 29 02:50:11 PM PST 24
Finished Feb 29 02:51:06 PM PST 24
Peak memory 651308 kb
Host smart-91678c18-d076-4791-ad3f-f4b8560cd5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746796356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3746796356
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1603810400
Short name T1260
Test name
Test status
Simulation time 4105371208 ps
CPU time 70.44 seconds
Started Feb 29 02:50:11 PM PST 24
Finished Feb 29 02:51:21 PM PST 24
Peak memory 694648 kb
Host smart-6b3a7d5d-61bd-48f5-b4a8-a41332f76796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603810400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1603810400
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.840158914
Short name T773
Test name
Test status
Simulation time 226808774 ps
CPU time 5.61 seconds
Started Feb 29 02:50:10 PM PST 24
Finished Feb 29 02:50:16 PM PST 24
Peak memory 203824 kb
Host smart-022928de-ca2d-4df9-b36f-30a16dea8f18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840158914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
840158914
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.794139876
Short name T569
Test name
Test status
Simulation time 5096891489 ps
CPU time 25.95 seconds
Started Feb 29 02:50:21 PM PST 24
Finished Feb 29 02:50:48 PM PST 24
Peak memory 231384 kb
Host smart-e33b9dac-2a82-41ce-a01e-7831493fa9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794139876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.794139876
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1093861340
Short name T576
Test name
Test status
Simulation time 17457844 ps
CPU time 0.63 seconds
Started Feb 29 02:50:16 PM PST 24
Finished Feb 29 02:50:17 PM PST 24
Peak memory 202776 kb
Host smart-1d89ab55-1178-4944-b9e3-207505f47144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093861340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1093861340
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2216983947
Short name T1316
Test name
Test status
Simulation time 2773712000 ps
CPU time 52.84 seconds
Started Feb 29 02:50:14 PM PST 24
Finished Feb 29 02:51:07 PM PST 24
Peak memory 222764 kb
Host smart-94771513-d09c-4052-a649-5d87767d8808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216983947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2216983947
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_rx_oversample.2109500304
Short name T925
Test name
Test status
Simulation time 2987714873 ps
CPU time 138.85 seconds
Started Feb 29 02:50:10 PM PST 24
Finished Feb 29 02:52:29 PM PST 24
Peak memory 317476 kb
Host smart-88a78006-379e-4945-9cbb-2c95c3b5ee86
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109500304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_rx_oversample
.2109500304
Directory /workspace/39.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1912879466
Short name T950
Test name
Test status
Simulation time 2543631701 ps
CPU time 70.9 seconds
Started Feb 29 02:50:09 PM PST 24
Finished Feb 29 02:51:20 PM PST 24
Peak memory 334664 kb
Host smart-6a0711f3-a916-4b26-880c-ecc84849b21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912879466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1912879466
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1045282266
Short name T1002
Test name
Test status
Simulation time 749591201 ps
CPU time 34.01 seconds
Started Feb 29 02:50:08 PM PST 24
Finished Feb 29 02:50:42 PM PST 24
Peak memory 211796 kb
Host smart-7680c576-f1dd-46a9-b94f-01bc438610f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045282266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1045282266
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3697865715
Short name T813
Test name
Test status
Simulation time 973580038 ps
CPU time 3.79 seconds
Started Feb 29 02:50:23 PM PST 24
Finished Feb 29 02:50:27 PM PST 24
Peak memory 203704 kb
Host smart-13f617f7-22e1-4310-9b0c-49bb73387381
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697865715 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3697865715
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.4176098971
Short name T1138
Test name
Test status
Simulation time 10170406330 ps
CPU time 36.2 seconds
Started Feb 29 02:50:24 PM PST 24
Finished Feb 29 02:51:01 PM PST 24
Peak memory 403124 kb
Host smart-cef5c83b-dc08-4768-b01f-24331c8d29c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176098971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.4176098971
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3400794555
Short name T280
Test name
Test status
Simulation time 10175722835 ps
CPU time 23.78 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 02:50:46 PM PST 24
Peak memory 354292 kb
Host smart-4d22f997-9135-420c-a719-02fb42a41f4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400794555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3400794555
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2057034962
Short name T740
Test name
Test status
Simulation time 704653355 ps
CPU time 2.08 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 02:50:25 PM PST 24
Peak memory 203684 kb
Host smart-0906390a-0fc5-4737-a8f5-a37cb2ee2ce4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057034962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2057034962
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1998702327
Short name T625
Test name
Test status
Simulation time 3283558370 ps
CPU time 7.23 seconds
Started Feb 29 02:50:23 PM PST 24
Finished Feb 29 02:50:31 PM PST 24
Peak memory 215820 kb
Host smart-b6c011f2-b92f-489e-a9cf-54b740ca1221
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998702327 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1998702327
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1361712959
Short name T278
Test name
Test status
Simulation time 15718560198 ps
CPU time 150.34 seconds
Started Feb 29 02:50:23 PM PST 24
Finished Feb 29 02:52:54 PM PST 24
Peak memory 1796840 kb
Host smart-86431ec8-b70b-4e1c-a8d7-8b4873f47263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361712959 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1361712959
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_perf.983928196
Short name T1182
Test name
Test status
Simulation time 5655212242 ps
CPU time 4.18 seconds
Started Feb 29 02:50:24 PM PST 24
Finished Feb 29 02:50:29 PM PST 24
Peak memory 203600 kb
Host smart-6ac17e16-6b00-4e1c-a064-d9e9d6619b9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983928196 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_perf.983928196
Directory /workspace/39.i2c_target_perf/latest

Test location /workspace/coverage/default/39.i2c_target_stress_all.2634598700
Short name T825
Test name
Test status
Simulation time 29965138070 ps
CPU time 33.7 seconds
Started Feb 29 02:50:26 PM PST 24
Finished Feb 29 02:51:01 PM PST 24
Peak memory 219900 kb
Host smart-50485809-4322-4c80-b4cd-0396479a2f75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634598700 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_stress_all.2634598700
Directory /workspace/39.i2c_target_stress_all/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2332160322
Short name T699
Test name
Test status
Simulation time 2762712878 ps
CPU time 49.93 seconds
Started Feb 29 02:50:23 PM PST 24
Finished Feb 29 02:51:14 PM PST 24
Peak memory 203784 kb
Host smart-c73bed53-ac45-453c-8da7-ec10992be183
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332160322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2332160322
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.559762528
Short name T1112
Test name
Test status
Simulation time 36730940623 ps
CPU time 415.28 seconds
Started Feb 29 02:50:16 PM PST 24
Finished Feb 29 02:57:11 PM PST 24
Peak memory 4112136 kb
Host smart-a28b8554-7d03-4201-bb13-f4ca39377de0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559762528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.559762528
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1093963839
Short name T767
Test name
Test status
Simulation time 17612570231 ps
CPU time 266.91 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 02:54:49 PM PST 24
Peak memory 1064156 kb
Host smart-0a1cb85b-1ce5-4503-b724-34d81e01e679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093963839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1093963839
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2860321995
Short name T499
Test name
Test status
Simulation time 7746826135 ps
CPU time 8.86 seconds
Started Feb 29 02:50:21 PM PST 24
Finished Feb 29 02:50:31 PM PST 24
Peak memory 215896 kb
Host smart-f28e290f-6945-4d17-bf8f-23f263901142
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860321995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2860321995
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.1958714014
Short name T657
Test name
Test status
Simulation time 816917110 ps
CPU time 4.42 seconds
Started Feb 29 02:50:21 PM PST 24
Finished Feb 29 02:50:27 PM PST 24
Peak memory 203708 kb
Host smart-703babce-e9fe-495e-a0be-623b27ea41b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958714014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.1958714014
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2501784641
Short name T597
Test name
Test status
Simulation time 45531392 ps
CPU time 0.6 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:44:08 PM PST 24
Peak memory 203544 kb
Host smart-84769a1b-fada-4568-9b4e-b4d6bd87a266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501784641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2501784641
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1339303062
Short name T1198
Test name
Test status
Simulation time 271136663 ps
CPU time 1.2 seconds
Started Feb 29 02:43:50 PM PST 24
Finished Feb 29 02:43:52 PM PST 24
Peak memory 211848 kb
Host smart-f2647225-10e3-4e63-ad90-77815c7e107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339303062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1339303062
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.542950735
Short name T473
Test name
Test status
Simulation time 1635302197 ps
CPU time 7.89 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:44:02 PM PST 24
Peak memory 271400 kb
Host smart-f680c346-206b-4592-b261-93b6f8fe1586
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542950735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.542950735
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.798082449
Short name T257
Test name
Test status
Simulation time 3863291102 ps
CPU time 125.15 seconds
Started Feb 29 02:43:50 PM PST 24
Finished Feb 29 02:45:55 PM PST 24
Peak memory 826640 kb
Host smart-09971441-c98b-40c7-9892-dc6389bdf74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798082449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.798082449
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.552695900
Short name T1209
Test name
Test status
Simulation time 5363411351 ps
CPU time 83.4 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:45:19 PM PST 24
Peak memory 785748 kb
Host smart-e97aa14e-2a32-4df0-9af9-5ba869ea6cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552695900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.552695900
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.247741209
Short name T386
Test name
Test status
Simulation time 1543064910 ps
CPU time 3.44 seconds
Started Feb 29 02:43:54 PM PST 24
Finished Feb 29 02:43:57 PM PST 24
Peak memory 203680 kb
Host smart-61116964-327c-41ae-be59-9ad1693c89b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247741209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.247741209
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1963938481
Short name T13
Test name
Test status
Simulation time 8450162237 ps
CPU time 66.63 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:45:16 PM PST 24
Peak memory 322324 kb
Host smart-308ccdfc-094b-4ffc-9258-3176117f4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963938481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1963938481
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2769908369
Short name T149
Test name
Test status
Simulation time 45616739 ps
CPU time 0.63 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:43:54 PM PST 24
Peak memory 202752 kb
Host smart-e9044f3d-6d0a-4fe8-a5f3-34932d7d5ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769908369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2769908369
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3083575825
Short name T541
Test name
Test status
Simulation time 967272581 ps
CPU time 13.23 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:44:08 PM PST 24
Peak memory 211248 kb
Host smart-dfa01a75-6f93-4e0d-8913-a15e2c4c4a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083575825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3083575825
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_rx_oversample.1010502662
Short name T1023
Test name
Test status
Simulation time 2368937913 ps
CPU time 231.12 seconds
Started Feb 29 02:43:51 PM PST 24
Finished Feb 29 02:47:42 PM PST 24
Peak memory 300800 kb
Host smart-d5275e23-565d-4f9b-9494-d3bd37e300a1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010502662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_rx_oversample.
1010502662
Directory /workspace/4.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.89618627
Short name T233
Test name
Test status
Simulation time 9697965199 ps
CPU time 52.95 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:44:48 PM PST 24
Peak memory 317056 kb
Host smart-2b7438bf-39cb-40c4-a311-6e43d9399a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89618627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.89618627
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3599591837
Short name T154
Test name
Test status
Simulation time 5850634060 ps
CPU time 635.26 seconds
Started Feb 29 02:43:54 PM PST 24
Finished Feb 29 02:54:29 PM PST 24
Peak memory 912944 kb
Host smart-b41e374a-8ce3-4208-8056-184949c39a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599591837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3599591837
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2931508089
Short name T480
Test name
Test status
Simulation time 4137405505 ps
CPU time 18.39 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:44:12 PM PST 24
Peak memory 220008 kb
Host smart-66929fb1-e39f-4c29-ac7c-e23edf4467ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931508089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2931508089
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1616103530
Short name T97
Test name
Test status
Simulation time 45729075 ps
CPU time 0.87 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:09 PM PST 24
Peak memory 220392 kb
Host smart-47ce50cf-7a5f-4a7c-af5b-a24cae5979e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616103530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1616103530
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.4206953690
Short name T1189
Test name
Test status
Simulation time 1605546928 ps
CPU time 3.54 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:44:12 PM PST 24
Peak memory 203700 kb
Host smart-3b078ef4-3635-4afb-83a2-188c54d8a487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206953690 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.4206953690
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2037944213
Short name T1013
Test name
Test status
Simulation time 10043373151 ps
CPU time 60.26 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:44:55 PM PST 24
Peak memory 488464 kb
Host smart-132cd64b-2134-4883-9e69-49fd9b3a7256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037944213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2037944213
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2852928494
Short name T883
Test name
Test status
Simulation time 10058528248 ps
CPU time 75.31 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:45:08 PM PST 24
Peak memory 654904 kb
Host smart-935d7bcf-d56b-4772-bfcc-181bfab2a74f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852928494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2852928494
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2872776000
Short name T1334
Test name
Test status
Simulation time 2077061188 ps
CPU time 2.72 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:44:11 PM PST 24
Peak memory 203696 kb
Host smart-dea2372f-d921-4ebe-af66-38f2c26e06a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872776000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2872776000
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.258610307
Short name T1034
Test name
Test status
Simulation time 1677348011 ps
CPU time 6.92 seconds
Started Feb 29 02:43:54 PM PST 24
Finished Feb 29 02:44:01 PM PST 24
Peak memory 203608 kb
Host smart-7f3d4e05-1c19-4e0f-b9ed-bdff8de6a225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258610307 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.258610307
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3963227288
Short name T937
Test name
Test status
Simulation time 21839747432 ps
CPU time 774.36 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:56:50 PM PST 24
Peak memory 5211152 kb
Host smart-4311c364-f6f1-4684-893f-3cbcf2749d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963227288 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3963227288
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_perf.2931107121
Short name T547
Test name
Test status
Simulation time 767467908 ps
CPU time 5.11 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:13 PM PST 24
Peak memory 209872 kb
Host smart-cb93185a-841b-42d7-9d9e-15487fcb9ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931107121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_perf.2931107121
Directory /workspace/4.i2c_target_perf/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1102713962
Short name T232
Test name
Test status
Simulation time 1653931740 ps
CPU time 45.54 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:44:40 PM PST 24
Peak memory 203604 kb
Host smart-788ba4f6-7e5e-4918-a044-a1e6f04c743e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102713962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1102713962
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_all.4079581402
Short name T1106
Test name
Test status
Simulation time 21688768491 ps
CPU time 26.32 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:35 PM PST 24
Peak memory 219184 kb
Host smart-508f9482-e8f6-40ee-9c78-2b0784f66357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079581402 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.i2c_target_stress_all.4079581402
Directory /workspace/4.i2c_target_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.2604579354
Short name T1046
Test name
Test status
Simulation time 1432428839 ps
CPU time 55 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:44:49 PM PST 24
Peak memory 203640 kb
Host smart-45c2ca0f-3c23-4419-9035-3f7bca24ae56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604579354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.2604579354
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1629130468
Short name T551
Test name
Test status
Simulation time 17247300604 ps
CPU time 248.11 seconds
Started Feb 29 02:43:55 PM PST 24
Finished Feb 29 02:48:03 PM PST 24
Peak memory 3344132 kb
Host smart-959c233a-fdb1-475a-86cc-5e41cba40123
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629130468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1629130468
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2755500850
Short name T47
Test name
Test status
Simulation time 37984967052 ps
CPU time 2720.52 seconds
Started Feb 29 02:43:51 PM PST 24
Finished Feb 29 03:29:13 PM PST 24
Peak memory 4273320 kb
Host smart-97fc19c1-34e4-4450-a8ca-143f75aa031f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755500850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2755500850
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3443722969
Short name T557
Test name
Test status
Simulation time 3791465661 ps
CPU time 7.44 seconds
Started Feb 29 02:43:51 PM PST 24
Finished Feb 29 02:43:59 PM PST 24
Peak memory 203764 kb
Host smart-1db2cd9b-4854-4394-b28e-2de402dc2021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443722969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3443722969
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.1061474346
Short name T713
Test name
Test status
Simulation time 11310981064 ps
CPU time 8.51 seconds
Started Feb 29 02:43:53 PM PST 24
Finished Feb 29 02:44:02 PM PST 24
Peak memory 210264 kb
Host smart-fe85e1f1-53f9-411f-b7bb-098da853c567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061474346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.1061474346
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2759710455
Short name T678
Test name
Test status
Simulation time 27632944 ps
CPU time 0.6 seconds
Started Feb 29 02:50:39 PM PST 24
Finished Feb 29 02:50:39 PM PST 24
Peak memory 202556 kb
Host smart-e3f9677b-4b7f-4363-bd47-4aef7496156e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759710455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2759710455
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1525730800
Short name T884
Test name
Test status
Simulation time 44507615 ps
CPU time 1.06 seconds
Started Feb 29 02:50:23 PM PST 24
Finished Feb 29 02:50:24 PM PST 24
Peak memory 214132 kb
Host smart-fb43e71d-77f2-478c-8d4f-ee45307fd207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525730800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1525730800
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1432758981
Short name T462
Test name
Test status
Simulation time 25802471880 ps
CPU time 135.22 seconds
Started Feb 29 02:50:24 PM PST 24
Finished Feb 29 02:52:40 PM PST 24
Peak memory 977372 kb
Host smart-abf0aab6-0ade-4b02-b95b-c3b523f7f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432758981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1432758981
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1698483142
Short name T1123
Test name
Test status
Simulation time 7557989129 ps
CPU time 154.15 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 02:52:57 PM PST 24
Peak memory 712564 kb
Host smart-ba21687e-30c8-4350-be57-4f662f7cde44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698483142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1698483142
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1313466168
Short name T571
Test name
Test status
Simulation time 563577879 ps
CPU time 4.19 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 02:50:27 PM PST 24
Peak memory 227980 kb
Host smart-1394133d-7d37-4c3c-bc36-6698aaa7da39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313466168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1313466168
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.843240696
Short name T1267
Test name
Test status
Simulation time 4097621354 ps
CPU time 119.32 seconds
Started Feb 29 02:50:25 PM PST 24
Finished Feb 29 02:52:24 PM PST 24
Peak memory 1181036 kb
Host smart-a72feb4f-8659-4273-8ac6-4bac2f7cab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843240696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.843240696
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.2012450131
Short name T285
Test name
Test status
Simulation time 11733800964 ps
CPU time 79.72 seconds
Started Feb 29 02:50:35 PM PST 24
Finished Feb 29 02:51:55 PM PST 24
Peak memory 307304 kb
Host smart-13af42b9-a4cb-43f8-9455-8d2f0415dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012450131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.2012450131
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1618297607
Short name T1091
Test name
Test status
Simulation time 51314576 ps
CPU time 0.73 seconds
Started Feb 29 02:50:23 PM PST 24
Finished Feb 29 02:50:24 PM PST 24
Peak memory 202800 kb
Host smart-3f52a36f-75fb-4fbc-baff-fc15ad5d9e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618297607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1618297607
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2058422950
Short name T23
Test name
Test status
Simulation time 5078831299 ps
CPU time 224.29 seconds
Started Feb 29 02:50:24 PM PST 24
Finished Feb 29 02:54:09 PM PST 24
Peak memory 221200 kb
Host smart-8e7d1f7f-e64a-43c1-9a67-dff63369b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058422950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2058422950
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_rx_oversample.32634880
Short name T1155
Test name
Test status
Simulation time 2039450288 ps
CPU time 48.47 seconds
Started Feb 29 02:50:21 PM PST 24
Finished Feb 29 02:51:10 PM PST 24
Peak memory 262720 kb
Host smart-6f23d31f-5d8a-4951-8b94-8c6dba056cc5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32634880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversample
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_rx_oversample.32634880
Directory /workspace/40.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1478459459
Short name T862
Test name
Test status
Simulation time 2444424963 ps
CPU time 66.24 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 02:51:29 PM PST 24
Peak memory 284844 kb
Host smart-8d503725-eb7f-4e6b-93e5-3c05d4eb9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478459459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1478459459
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.418379349
Short name T649
Test name
Test status
Simulation time 729245188 ps
CPU time 33.77 seconds
Started Feb 29 02:50:23 PM PST 24
Finished Feb 29 02:50:57 PM PST 24
Peak memory 211828 kb
Host smart-2c56c410-c90c-4c41-9aaf-108034365826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418379349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.418379349
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.102557440
Short name T7
Test name
Test status
Simulation time 4955772873 ps
CPU time 4.62 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:50:42 PM PST 24
Peak memory 203732 kb
Host smart-78f00aab-a106-4e56-a899-4ecb70385a79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102557440 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.102557440
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2620563739
Short name T830
Test name
Test status
Simulation time 10059830725 ps
CPU time 13.31 seconds
Started Feb 29 02:50:38 PM PST 24
Finished Feb 29 02:50:51 PM PST 24
Peak memory 297176 kb
Host smart-7ee18967-544e-48de-a31a-a2d973e9e468
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620563739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2620563739
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2357257236
Short name T1109
Test name
Test status
Simulation time 10399551555 ps
CPU time 13.75 seconds
Started Feb 29 02:50:40 PM PST 24
Finished Feb 29 02:50:54 PM PST 24
Peak memory 287024 kb
Host smart-e3bc3593-8ca1-4084-a837-4cc6f515215d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357257236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2357257236
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3670525294
Short name T946
Test name
Test status
Simulation time 694883494 ps
CPU time 2.86 seconds
Started Feb 29 02:50:36 PM PST 24
Finished Feb 29 02:50:39 PM PST 24
Peak memory 203652 kb
Host smart-cb970038-1095-4040-8e48-fccbb7edb211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670525294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3670525294
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1551167330
Short name T929
Test name
Test status
Simulation time 2159435223 ps
CPU time 4.89 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 02:50:27 PM PST 24
Peak memory 204488 kb
Host smart-f8e57d2c-f20d-4b64-87d6-1877c775ff4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551167330 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1551167330
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.4283863035
Short name T827
Test name
Test status
Simulation time 10134497255 ps
CPU time 26.8 seconds
Started Feb 29 02:50:24 PM PST 24
Finished Feb 29 02:50:52 PM PST 24
Peak memory 636148 kb
Host smart-151b203d-2e7c-4d85-90be-ba97ffd3af50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283863035 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.4283863035
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_perf.2800360548
Short name T810
Test name
Test status
Simulation time 12297691670 ps
CPU time 4.57 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:50:41 PM PST 24
Peak memory 203704 kb
Host smart-be563be7-fe79-481a-bcee-b9a025ec19ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800360548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_perf.2800360548
Directory /workspace/40.i2c_target_perf/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.3736574654
Short name T885
Test name
Test status
Simulation time 73617612484 ps
CPU time 837 seconds
Started Feb 29 02:50:34 PM PST 24
Finished Feb 29 03:04:32 PM PST 24
Peak memory 5432304 kb
Host smart-05760481-9ce5-40f0-97cf-c43a4f788e70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736574654 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.3736574654
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.4269572566
Short name T1000
Test name
Test status
Simulation time 55554055449 ps
CPU time 2983.36 seconds
Started Feb 29 02:50:22 PM PST 24
Finished Feb 29 03:40:07 PM PST 24
Peak memory 12724780 kb
Host smart-638edcf1-9bfe-4080-abf9-85abcd2c1b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269572566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.4269572566
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.4017079360
Short name T751
Test name
Test status
Simulation time 1832732943 ps
CPU time 6.81 seconds
Started Feb 29 02:50:38 PM PST 24
Finished Feb 29 02:50:45 PM PST 24
Peak memory 203776 kb
Host smart-15917709-53ac-4a50-8cfc-8184d6a4e29b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017079360 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.4017079360
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_unexp_stop.187025561
Short name T270
Test name
Test status
Simulation time 800067967 ps
CPU time 4.8 seconds
Started Feb 29 02:50:35 PM PST 24
Finished Feb 29 02:50:40 PM PST 24
Peak memory 203708 kb
Host smart-2e9bb508-e0ab-427b-a106-1a0a4512af66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187025561 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_unexp_stop.187025561
Directory /workspace/40.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/41.i2c_alert_test.474738082
Short name T1142
Test name
Test status
Simulation time 16984609 ps
CPU time 0.67 seconds
Started Feb 29 02:50:40 PM PST 24
Finished Feb 29 02:50:41 PM PST 24
Peak memory 202548 kb
Host smart-bd0afb13-6c4f-4cc8-913e-3e35231ff8a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474738082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.474738082
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3822473929
Short name T1
Test name
Test status
Simulation time 134070934 ps
CPU time 1.77 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:50:40 PM PST 24
Peak memory 211796 kb
Host smart-9a7bf60e-ae9a-4d26-a057-642ab521ad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822473929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3822473929
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3342644879
Short name T330
Test name
Test status
Simulation time 413320005 ps
CPU time 20.09 seconds
Started Feb 29 02:50:36 PM PST 24
Finished Feb 29 02:50:57 PM PST 24
Peak memory 291888 kb
Host smart-d63a3df4-f73e-4f21-bdcc-e5fa716c1288
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342644879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3342644879
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2162691085
Short name T1094
Test name
Test status
Simulation time 14531119094 ps
CPU time 124.01 seconds
Started Feb 29 02:50:33 PM PST 24
Finished Feb 29 02:52:38 PM PST 24
Peak memory 637924 kb
Host smart-1921af94-4ceb-4d50-a63d-a1d879ef814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162691085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2162691085
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2878944784
Short name T843
Test name
Test status
Simulation time 2029688707 ps
CPU time 128.02 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:52:45 PM PST 24
Peak memory 643400 kb
Host smart-ddd80f91-54f1-4942-96c1-b60eb49a489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878944784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2878944784
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.2189107443
Short name T1082
Test name
Test status
Simulation time 593280121 ps
CPU time 15.05 seconds
Started Feb 29 02:50:36 PM PST 24
Finished Feb 29 02:50:51 PM PST 24
Peak memory 203684 kb
Host smart-20f79478-c1cd-46e7-be5d-f480d7cfd789
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189107443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.2189107443
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1078705996
Short name T1279
Test name
Test status
Simulation time 3839364773 ps
CPU time 88.63 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:52:06 PM PST 24
Peak memory 965324 kb
Host smart-5b5d203c-9dcc-4c65-9dd6-234347294921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078705996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1078705996
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.3121670129
Short name T1259
Test name
Test status
Simulation time 5151361712 ps
CPU time 133.65 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:52:51 PM PST 24
Peak memory 413508 kb
Host smart-d00c4349-0ebb-4b77-ade7-e9e29793beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121670129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.3121670129
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3741818261
Short name T734
Test name
Test status
Simulation time 80045136 ps
CPU time 0.63 seconds
Started Feb 29 02:50:35 PM PST 24
Finished Feb 29 02:50:35 PM PST 24
Peak memory 202724 kb
Host smart-1e4f6bed-a1a8-44d8-86b3-fa77aed90a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741818261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3741818261
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_rx_oversample.4171590376
Short name T748
Test name
Test status
Simulation time 7113546621 ps
CPU time 58.78 seconds
Started Feb 29 02:50:35 PM PST 24
Finished Feb 29 02:51:34 PM PST 24
Peak memory 291396 kb
Host smart-b0e926e5-875e-4aac-a8a7-b210b0b2a638
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171590376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_rx_oversample
.4171590376
Directory /workspace/41.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1547270639
Short name T735
Test name
Test status
Simulation time 8690595561 ps
CPU time 46.89 seconds
Started Feb 29 02:50:36 PM PST 24
Finished Feb 29 02:51:23 PM PST 24
Peak memory 282452 kb
Host smart-e5cb4eb4-bce4-46e4-9d25-ec823071d773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547270639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1547270639
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2685934433
Short name T1042
Test name
Test status
Simulation time 2863518039 ps
CPU time 10.24 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:50:48 PM PST 24
Peak memory 219304 kb
Host smart-5df8a5f5-d40c-4c4a-8c18-407f735bbb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685934433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2685934433
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2001084268
Short name T664
Test name
Test status
Simulation time 786640882 ps
CPU time 3.95 seconds
Started Feb 29 02:50:38 PM PST 24
Finished Feb 29 02:50:42 PM PST 24
Peak memory 203628 kb
Host smart-792f79a9-da22-48c9-9dcc-a0bd6742d619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001084268 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2001084268
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1544425751
Short name T707
Test name
Test status
Simulation time 10164017785 ps
CPU time 28.41 seconds
Started Feb 29 02:50:39 PM PST 24
Finished Feb 29 02:51:07 PM PST 24
Peak memory 405144 kb
Host smart-a705acbe-1ec3-4bb0-ac41-752b7127bb68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544425751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1544425751
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3194704112
Short name T688
Test name
Test status
Simulation time 896504408 ps
CPU time 2.38 seconds
Started Feb 29 02:50:39 PM PST 24
Finished Feb 29 02:50:41 PM PST 24
Peak memory 203648 kb
Host smart-a56003c3-01de-4e57-b2ae-dd594f3f5bf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194704112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3194704112
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1497517485
Short name T1317
Test name
Test status
Simulation time 5787959961 ps
CPU time 6.5 seconds
Started Feb 29 02:50:39 PM PST 24
Finished Feb 29 02:50:46 PM PST 24
Peak memory 203888 kb
Host smart-8a5723fe-d67e-47f2-bb8f-5bb866124c12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497517485 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1497517485
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2616768944
Short name T831
Test name
Test status
Simulation time 10259936711 ps
CPU time 31.95 seconds
Started Feb 29 02:50:40 PM PST 24
Finished Feb 29 02:51:13 PM PST 24
Peak memory 675388 kb
Host smart-0a276c7a-3e84-4f53-9005-5c09fba3ea17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616768944 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2616768944
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_perf.163806963
Short name T1116
Test name
Test status
Simulation time 5188792080 ps
CPU time 5.01 seconds
Started Feb 29 02:50:36 PM PST 24
Finished Feb 29 02:50:42 PM PST 24
Peak memory 208700 kb
Host smart-f02ad537-6a63-457b-861f-7bbc5c0f8349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163806963 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_perf.163806963
Directory /workspace/41.i2c_target_perf/latest

Test location /workspace/coverage/default/41.i2c_target_stress_all.3783990250
Short name T1178
Test name
Test status
Simulation time 14897346200 ps
CPU time 31.45 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:51:09 PM PST 24
Peak memory 212084 kb
Host smart-09740c2a-a6fe-4129-9095-df422c36f7e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783990250 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.i2c_target_stress_all.3783990250
Directory /workspace/41.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3587206156
Short name T1040
Test name
Test status
Simulation time 1195559952 ps
CPU time 48.52 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:51:26 PM PST 24
Peak memory 203640 kb
Host smart-2ad9561c-fd91-48e6-a598-30216a19147f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587206156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3587206156
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.2703522069
Short name T451
Test name
Test status
Simulation time 8740359728 ps
CPU time 9.05 seconds
Started Feb 29 02:50:36 PM PST 24
Finished Feb 29 02:50:45 PM PST 24
Peak memory 411676 kb
Host smart-b329d3c4-45cf-4d4b-9b26-62269534bbb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703522069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.2703522069
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2042981287
Short name T752
Test name
Test status
Simulation time 49577142434 ps
CPU time 111.5 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:52:28 PM PST 24
Peak memory 1146976 kb
Host smart-3cdeb0b7-a673-4510-ab9c-5ab33fd986c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042981287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2042981287
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2082526626
Short name T1084
Test name
Test status
Simulation time 2668260318 ps
CPU time 6.57 seconds
Started Feb 29 02:50:37 PM PST 24
Finished Feb 29 02:50:44 PM PST 24
Peak memory 208488 kb
Host smart-855ed96c-fdc5-4c0e-94ff-8cf201938112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082526626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2082526626
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.3475475807
Short name T1324
Test name
Test status
Simulation time 916047577 ps
CPU time 4.87 seconds
Started Feb 29 02:50:35 PM PST 24
Finished Feb 29 02:50:40 PM PST 24
Peak memory 203636 kb
Host smart-9da31dda-91c5-4c2e-ba3a-13fb45434adb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475475807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_target_unexp_stop.3475475807
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3263291681
Short name T986
Test name
Test status
Simulation time 16066200 ps
CPU time 0.63 seconds
Started Feb 29 02:50:51 PM PST 24
Finished Feb 29 02:50:52 PM PST 24
Peak memory 202504 kb
Host smart-e8cfb874-1129-40ae-ab9c-9aa45d4eca7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263291681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3263291681
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.38042486
Short name T1121
Test name
Test status
Simulation time 40153393 ps
CPU time 1.2 seconds
Started Feb 29 02:50:53 PM PST 24
Finished Feb 29 02:50:55 PM PST 24
Peak memory 211876 kb
Host smart-e42b1e3e-cd1d-457e-840d-83ee968553ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38042486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.38042486
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.502845723
Short name T353
Test name
Test status
Simulation time 1342898663 ps
CPU time 12.51 seconds
Started Feb 29 02:50:51 PM PST 24
Finished Feb 29 02:51:04 PM PST 24
Peak memory 351992 kb
Host smart-b7828386-5ca5-4649-a11c-29877868fc13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502845723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.502845723
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3749667205
Short name T470
Test name
Test status
Simulation time 2757796644 ps
CPU time 199.95 seconds
Started Feb 29 02:50:53 PM PST 24
Finished Feb 29 02:54:13 PM PST 24
Peak memory 861344 kb
Host smart-3f3643a8-477a-4ca5-8a55-f5c38f3e9796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749667205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3749667205
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3031335193
Short name T398
Test name
Test status
Simulation time 7935430945 ps
CPU time 91.12 seconds
Started Feb 29 02:50:51 PM PST 24
Finished Feb 29 02:52:23 PM PST 24
Peak memory 817416 kb
Host smart-e981d28f-b130-47db-822c-cb8a476ad83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031335193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3031335193
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.374008610
Short name T1007
Test name
Test status
Simulation time 592804337 ps
CPU time 4.32 seconds
Started Feb 29 02:50:51 PM PST 24
Finished Feb 29 02:50:55 PM PST 24
Peak memory 229424 kb
Host smart-1dc28b74-bd55-4a1e-8337-1db1b69dee66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374008610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
374008610
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1145908076
Short name T86
Test name
Test status
Simulation time 26309687954 ps
CPU time 631.17 seconds
Started Feb 29 02:50:49 PM PST 24
Finished Feb 29 03:01:20 PM PST 24
Peak memory 1870312 kb
Host smart-a31c787a-e3f6-4d01-bfa3-0c6d762de0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145908076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1145908076
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3290925516
Short name T274
Test name
Test status
Simulation time 9213974254 ps
CPU time 56.6 seconds
Started Feb 29 02:50:50 PM PST 24
Finished Feb 29 02:51:47 PM PST 24
Peak memory 320756 kb
Host smart-643ecc28-6333-49d8-a4b9-26e69e2b4b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290925516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3290925516
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.238743426
Short name T429
Test name
Test status
Simulation time 28816281 ps
CPU time 0.64 seconds
Started Feb 29 02:50:48 PM PST 24
Finished Feb 29 02:50:49 PM PST 24
Peak memory 202740 kb
Host smart-708e92e9-5ece-4fec-bb87-d9881a19a281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238743426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.238743426
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2468566740
Short name T844
Test name
Test status
Simulation time 5544129619 ps
CPU time 96.11 seconds
Started Feb 29 02:50:51 PM PST 24
Finished Feb 29 02:52:28 PM PST 24
Peak memory 246084 kb
Host smart-a7705f97-9eb5-46e8-8e51-ac25e704b0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468566740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2468566740
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_rx_oversample.1328108300
Short name T936
Test name
Test status
Simulation time 8650208773 ps
CPU time 156.63 seconds
Started Feb 29 02:50:47 PM PST 24
Finished Feb 29 02:53:24 PM PST 24
Peak memory 267880 kb
Host smart-3661589b-9ceb-47a1-84a6-c11617254c5b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328108300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_rx_oversample
.1328108300
Directory /workspace/42.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2224096181
Short name T105
Test name
Test status
Simulation time 5926272694 ps
CPU time 140.37 seconds
Started Feb 29 02:50:39 PM PST 24
Finished Feb 29 02:52:59 PM PST 24
Peak memory 260544 kb
Host smart-0f8c50bc-3eb9-4612-9a06-62ed167db644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224096181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2224096181
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2708608200
Short name T1305
Test name
Test status
Simulation time 779157973 ps
CPU time 11.35 seconds
Started Feb 29 02:50:48 PM PST 24
Finished Feb 29 02:51:00 PM PST 24
Peak memory 216084 kb
Host smart-5826b42b-e007-4cac-b188-6d008c7c06ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708608200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2708608200
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3411423748
Short name T370
Test name
Test status
Simulation time 5613665078 ps
CPU time 5.25 seconds
Started Feb 29 02:50:54 PM PST 24
Finished Feb 29 02:50:59 PM PST 24
Peak memory 203772 kb
Host smart-5edb9638-9a63-480f-b3a2-122368e96b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411423748 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3411423748
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3900010296
Short name T1263
Test name
Test status
Simulation time 10185050643 ps
CPU time 8.05 seconds
Started Feb 29 02:50:49 PM PST 24
Finished Feb 29 02:50:57 PM PST 24
Peak memory 258312 kb
Host smart-7c2f0a2e-2cdd-4641-bdc2-9ea9c0b04f6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900010296 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3900010296
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1072696517
Short name T461
Test name
Test status
Simulation time 10032920481 ps
CPU time 60.33 seconds
Started Feb 29 02:50:48 PM PST 24
Finished Feb 29 02:51:49 PM PST 24
Peak memory 517812 kb
Host smart-eb7484c5-ca90-42c8-a23e-220ba24d48c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072696517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1072696517
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2525300497
Short name T1126
Test name
Test status
Simulation time 913111466 ps
CPU time 1.68 seconds
Started Feb 29 02:50:52 PM PST 24
Finished Feb 29 02:50:54 PM PST 24
Peak memory 203652 kb
Host smart-50f75aeb-0b66-4342-b50f-8f134c1bdf85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525300497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2525300497
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1129922420
Short name T435
Test name
Test status
Simulation time 8388380820 ps
CPU time 7.58 seconds
Started Feb 29 02:50:51 PM PST 24
Finished Feb 29 02:50:59 PM PST 24
Peak memory 209888 kb
Host smart-c6f32b3b-ba94-45c3-aff2-596a7e45638f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129922420 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1129922420
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2545880469
Short name T443
Test name
Test status
Simulation time 4899107996 ps
CPU time 8.47 seconds
Started Feb 29 02:50:47 PM PST 24
Finished Feb 29 02:50:56 PM PST 24
Peak memory 367816 kb
Host smart-79bcc109-5eb1-421a-b647-7caef9c19a05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545880469 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2545880469
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_perf.4148778302
Short name T456
Test name
Test status
Simulation time 820693860 ps
CPU time 4.53 seconds
Started Feb 29 02:50:53 PM PST 24
Finished Feb 29 02:50:58 PM PST 24
Peak memory 208192 kb
Host smart-eaaee34f-d927-404f-a8d7-27f2b496c24f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148778302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_perf.4148778302
Directory /workspace/42.i2c_target_perf/latest

Test location /workspace/coverage/default/42.i2c_target_stress_all.3714128535
Short name T732
Test name
Test status
Simulation time 65194205642 ps
CPU time 149.18 seconds
Started Feb 29 02:50:47 PM PST 24
Finished Feb 29 02:53:16 PM PST 24
Peak memory 1267776 kb
Host smart-31ffee40-6fa3-493f-aeaf-d738e851f44a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714128535 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.i2c_target_stress_all.3714128535
Directory /workspace/42.i2c_target_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.4266451970
Short name T1313
Test name
Test status
Simulation time 2848336307 ps
CPU time 57.94 seconds
Started Feb 29 02:50:48 PM PST 24
Finished Feb 29 02:51:46 PM PST 24
Peak memory 204624 kb
Host smart-31416459-8046-4921-a996-2b463f6c5c09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266451970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.4266451970
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.846034318
Short name T341
Test name
Test status
Simulation time 20682113150 ps
CPU time 36.34 seconds
Started Feb 29 02:50:48 PM PST 24
Finished Feb 29 02:51:24 PM PST 24
Peak memory 950080 kb
Host smart-0fa0979c-855d-45f9-a2de-f478eb3dc106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846034318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.846034318
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1025312300
Short name T96
Test name
Test status
Simulation time 7910755688 ps
CPU time 8.58 seconds
Started Feb 29 02:50:47 PM PST 24
Finished Feb 29 02:50:56 PM PST 24
Peak memory 206240 kb
Host smart-02fd8d4e-05f4-425d-95dd-80cb96323b8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025312300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1025312300
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.1815553402
Short name T749
Test name
Test status
Simulation time 1641480378 ps
CPU time 6.5 seconds
Started Feb 29 02:50:54 PM PST 24
Finished Feb 29 02:51:00 PM PST 24
Peak memory 205604 kb
Host smart-46974741-eba2-44a3-806e-965187a4c344
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815553402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.1815553402
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1600420571
Short name T437
Test name
Test status
Simulation time 22540624 ps
CPU time 0.62 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:16 PM PST 24
Peak memory 202580 kb
Host smart-5a6d247b-1073-43d2-99fc-ebf094a1c6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600420571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1600420571
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.957968255
Short name T1289
Test name
Test status
Simulation time 222043445 ps
CPU time 1.31 seconds
Started Feb 29 02:51:06 PM PST 24
Finished Feb 29 02:51:08 PM PST 24
Peak memory 211880 kb
Host smart-27ef31c6-943b-4384-92d0-04bf39726731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957968255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.957968255
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.311930552
Short name T271
Test name
Test status
Simulation time 1784476408 ps
CPU time 20.48 seconds
Started Feb 29 02:50:47 PM PST 24
Finished Feb 29 02:51:08 PM PST 24
Peak memory 287456 kb
Host smart-ba863654-c5e7-4e81-a753-1582e36a6c06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311930552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.311930552
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3058100587
Short name T1207
Test name
Test status
Simulation time 4263055709 ps
CPU time 162.65 seconds
Started Feb 29 02:51:04 PM PST 24
Finished Feb 29 02:53:47 PM PST 24
Peak memory 734296 kb
Host smart-42c0dbf1-c84b-4512-928f-e7052559c649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058100587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3058100587
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.4221115812
Short name T610
Test name
Test status
Simulation time 18215959436 ps
CPU time 78.4 seconds
Started Feb 29 02:50:53 PM PST 24
Finished Feb 29 02:52:12 PM PST 24
Peak memory 762300 kb
Host smart-6770c010-9b88-4ca0-9700-6b8515e5bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221115812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.4221115812
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1438384196
Short name T874
Test name
Test status
Simulation time 939938362 ps
CPU time 7.3 seconds
Started Feb 29 02:51:04 PM PST 24
Finished Feb 29 02:51:11 PM PST 24
Peak memory 254732 kb
Host smart-b1f7fc9d-e76e-4f54-afa3-d8d472ae81c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438384196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1438384196
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1005482820
Short name T999
Test name
Test status
Simulation time 16724285961 ps
CPU time 118.99 seconds
Started Feb 29 02:50:53 PM PST 24
Finished Feb 29 02:52:52 PM PST 24
Peak memory 1203224 kb
Host smart-049182ca-8c59-4309-8746-e96e2decf225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005482820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1005482820
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2936776136
Short name T964
Test name
Test status
Simulation time 10533067804 ps
CPU time 70.95 seconds
Started Feb 29 02:51:08 PM PST 24
Finished Feb 29 02:52:19 PM PST 24
Peak memory 301008 kb
Host smart-87b062df-9b7a-428e-b1d1-2eaf9d907306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936776136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2936776136
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.162927314
Short name T1330
Test name
Test status
Simulation time 26255297 ps
CPU time 0.64 seconds
Started Feb 29 02:50:51 PM PST 24
Finished Feb 29 02:50:52 PM PST 24
Peak memory 202892 kb
Host smart-23e6d20c-51a6-4279-864b-2012827aa1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162927314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.162927314
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1013234489
Short name T268
Test name
Test status
Simulation time 2944289806 ps
CPU time 135.64 seconds
Started Feb 29 02:51:03 PM PST 24
Finished Feb 29 02:53:19 PM PST 24
Peak memory 212012 kb
Host smart-1c964ccb-45b4-495f-80e7-09424617a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013234489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1013234489
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_rx_oversample.707112828
Short name T856
Test name
Test status
Simulation time 2241634229 ps
CPU time 87.98 seconds
Started Feb 29 02:50:50 PM PST 24
Finished Feb 29 02:52:18 PM PST 24
Peak memory 277272 kb
Host smart-97afa579-68ea-4145-8aac-b230b8cb3d03
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707112828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_rx_oversample.
707112828
Directory /workspace/43.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3430679336
Short name T267
Test name
Test status
Simulation time 2404803674 ps
CPU time 77.6 seconds
Started Feb 29 02:50:53 PM PST 24
Finished Feb 29 02:52:11 PM PST 24
Peak memory 322180 kb
Host smart-50f3c9da-23a1-4c97-b6f7-fb893c28e091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430679336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3430679336
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2460059078
Short name T215
Test name
Test status
Simulation time 712568637 ps
CPU time 11.65 seconds
Started Feb 29 02:51:05 PM PST 24
Finished Feb 29 02:51:17 PM PST 24
Peak memory 211812 kb
Host smart-c9b08113-6420-4342-bcf1-356ea860f2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460059078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2460059078
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2375846225
Short name T671
Test name
Test status
Simulation time 4608725137 ps
CPU time 4.25 seconds
Started Feb 29 02:51:04 PM PST 24
Finished Feb 29 02:51:09 PM PST 24
Peak memory 203744 kb
Host smart-4af149e0-fd7c-46aa-aab0-ed6a2b5b1d5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375846225 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2375846225
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.169412700
Short name T173
Test name
Test status
Simulation time 10168360066 ps
CPU time 13.43 seconds
Started Feb 29 02:51:04 PM PST 24
Finished Feb 29 02:51:17 PM PST 24
Peak memory 280976 kb
Host smart-f54b6c8f-adf6-4261-8ec3-6507d1f4fbd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169412700 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.169412700
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3900080726
Short name T821
Test name
Test status
Simulation time 10146233938 ps
CPU time 80.44 seconds
Started Feb 29 02:51:05 PM PST 24
Finished Feb 29 02:52:25 PM PST 24
Peak memory 663420 kb
Host smart-8bd70251-faa8-4716-8f37-5899cab2c6c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900080726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3900080726
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3237768656
Short name T930
Test name
Test status
Simulation time 633192902 ps
CPU time 2.94 seconds
Started Feb 29 02:51:05 PM PST 24
Finished Feb 29 02:51:08 PM PST 24
Peak memory 203600 kb
Host smart-2777018d-0d2f-41d0-be3f-b359a2cb1995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237768656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3237768656
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1261941023
Short name T1338
Test name
Test status
Simulation time 23070925309 ps
CPU time 5.14 seconds
Started Feb 29 02:51:04 PM PST 24
Finished Feb 29 02:51:10 PM PST 24
Peak memory 207164 kb
Host smart-43ebb847-d350-4684-8f3f-6e0ce93de562
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261941023 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1261941023
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_perf.122122782
Short name T918
Test name
Test status
Simulation time 651284805 ps
CPU time 4.02 seconds
Started Feb 29 02:51:06 PM PST 24
Finished Feb 29 02:51:11 PM PST 24
Peak memory 203644 kb
Host smart-3f680dfd-55c8-4089-8720-8ce1153998db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122122782 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_perf.122122782
Directory /workspace/43.i2c_target_perf/latest

Test location /workspace/coverage/default/43.i2c_target_stress_all.1392461362
Short name T947
Test name
Test status
Simulation time 10750414340 ps
CPU time 18.56 seconds
Started Feb 29 02:51:04 PM PST 24
Finished Feb 29 02:51:23 PM PST 24
Peak memory 228828 kb
Host smart-6b5f96fe-65f5-41d6-b6f3-0a3dde49cf1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392461362 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_stress_all.1392461362
Directory /workspace/43.i2c_target_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2576429436
Short name T1017
Test name
Test status
Simulation time 1607567158 ps
CPU time 15.83 seconds
Started Feb 29 02:51:07 PM PST 24
Finished Feb 29 02:51:23 PM PST 24
Peak memory 203648 kb
Host smart-f925f153-eb46-465e-86e7-5eddd001d216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576429436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2576429436
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3421077404
Short name T642
Test name
Test status
Simulation time 54616571975 ps
CPU time 842.98 seconds
Started Feb 29 02:51:04 PM PST 24
Finished Feb 29 03:05:08 PM PST 24
Peak memory 6521980 kb
Host smart-4001c4b1-a08e-4e94-8dce-93d7cc0a06a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421077404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3421077404
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2962353550
Short name T500
Test name
Test status
Simulation time 36416369263 ps
CPU time 296.79 seconds
Started Feb 29 02:51:09 PM PST 24
Finished Feb 29 02:56:05 PM PST 24
Peak memory 1803696 kb
Host smart-02f1d9f6-421a-404a-b959-100edd2dea47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962353550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2962353550
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3102976882
Short name T496
Test name
Test status
Simulation time 5325429515 ps
CPU time 6.85 seconds
Started Feb 29 02:51:06 PM PST 24
Finished Feb 29 02:51:13 PM PST 24
Peak memory 209244 kb
Host smart-051e886f-6658-46ff-944b-8e9b3dc06f45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102976882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3102976882
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_unexp_stop.2229774319
Short name T895
Test name
Test status
Simulation time 4533821244 ps
CPU time 6.81 seconds
Started Feb 29 02:51:05 PM PST 24
Finished Feb 29 02:51:12 PM PST 24
Peak memory 209176 kb
Host smart-32c111a1-5182-4166-8818-68a030036561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229774319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.i2c_target_unexp_stop.2229774319
Directory /workspace/43.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3659437094
Short name T474
Test name
Test status
Simulation time 32088237 ps
CPU time 0.57 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:16 PM PST 24
Peak memory 202480 kb
Host smart-e62f8116-d2ee-40ed-a7eb-5a71ce58bb0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659437094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3659437094
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.232771030
Short name T829
Test name
Test status
Simulation time 139286242 ps
CPU time 1.3 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:17 PM PST 24
Peak memory 203520 kb
Host smart-ca4ab03f-8294-442c-aa82-1e84e27f4bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232771030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.232771030
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.4038600611
Short name T1173
Test name
Test status
Simulation time 2742147554 ps
CPU time 7.07 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:51:22 PM PST 24
Peak memory 273252 kb
Host smart-5edd0b47-4078-483e-bbab-5bb5c55b02fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038600611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.4038600611
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3623530672
Short name T724
Test name
Test status
Simulation time 2673637166 ps
CPU time 91.96 seconds
Started Feb 29 02:51:19 PM PST 24
Finished Feb 29 02:52:51 PM PST 24
Peak memory 809796 kb
Host smart-fa0b101e-a19b-44b8-bb0b-8afbf332a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623530672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3623530672
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.726782993
Short name T430
Test name
Test status
Simulation time 10714070681 ps
CPU time 52.28 seconds
Started Feb 29 02:51:18 PM PST 24
Finished Feb 29 02:52:11 PM PST 24
Peak memory 604620 kb
Host smart-e0e56982-d3b6-44bb-a9a9-d410dc0e3bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726782993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.726782993
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3070886636
Short name T789
Test name
Test status
Simulation time 844337736 ps
CPU time 4.67 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:20 PM PST 24
Peak memory 203548 kb
Host smart-6ff423fa-8d45-4e1e-9874-7125d6ab6286
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070886636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3070886636
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1107836217
Short name T1243
Test name
Test status
Simulation time 32574468473 ps
CPU time 401.04 seconds
Started Feb 29 02:51:16 PM PST 24
Finished Feb 29 02:57:57 PM PST 24
Peak memory 1336764 kb
Host smart-c52b3aa5-12fd-481c-804e-eea3694dae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107836217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1107836217
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3543398489
Short name T1038
Test name
Test status
Simulation time 2178134937 ps
CPU time 57.53 seconds
Started Feb 29 02:51:17 PM PST 24
Finished Feb 29 02:52:15 PM PST 24
Peak memory 271448 kb
Host smart-1dd20cd1-1222-43eb-91cc-71e315a97937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543398489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3543398489
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3982617680
Short name T1068
Test name
Test status
Simulation time 45712495 ps
CPU time 0.63 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:15 PM PST 24
Peak memory 202740 kb
Host smart-5d78efce-f51b-4d2b-b09f-56903def22d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982617680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3982617680
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.94536378
Short name T185
Test name
Test status
Simulation time 6569360885 ps
CPU time 30.39 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:51:44 PM PST 24
Peak memory 236404 kb
Host smart-471f398b-a1e1-4145-ae96-8510a926b314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94536378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.94536378
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_rx_oversample.1056395314
Short name T1312
Test name
Test status
Simulation time 6270383515 ps
CPU time 49.67 seconds
Started Feb 29 02:51:13 PM PST 24
Finished Feb 29 02:52:03 PM PST 24
Peak memory 279176 kb
Host smart-51b59b1d-c3cc-4c81-9a9c-33d7c5d7ff43
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056395314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_rx_oversample
.1056395314
Directory /workspace/44.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2789844796
Short name T717
Test name
Test status
Simulation time 1979488259 ps
CPU time 45.19 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:52:00 PM PST 24
Peak memory 292292 kb
Host smart-77c900f3-430b-46c7-b77f-51994216f015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789844796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2789844796
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.388375327
Short name T800
Test name
Test status
Simulation time 20112287841 ps
CPU time 1520.46 seconds
Started Feb 29 02:51:16 PM PST 24
Finished Feb 29 03:16:36 PM PST 24
Peak memory 1995696 kb
Host smart-7c08c57f-ca9c-4e04-86a7-e8809a8e14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388375327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.388375327
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1912187691
Short name T210
Test name
Test status
Simulation time 2835527978 ps
CPU time 25.8 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:41 PM PST 24
Peak memory 227456 kb
Host smart-77bb6396-d0b0-4539-8857-c2c4cdfb515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912187691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1912187691
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2285907879
Short name T1146
Test name
Test status
Simulation time 4690684964 ps
CPU time 4.79 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:20 PM PST 24
Peak memory 203704 kb
Host smart-5ed87a60-87c3-43c4-96a7-e9988b2d5d3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285907879 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2285907879
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.4116246920
Short name T10
Test name
Test status
Simulation time 10186476861 ps
CPU time 19.41 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:51:34 PM PST 24
Peak memory 317080 kb
Host smart-b0bc13c2-c63a-4f78-ab1c-2c39dfe811da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116246920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.4116246920
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1591584088
Short name T265
Test name
Test status
Simulation time 10110983613 ps
CPU time 26.17 seconds
Started Feb 29 02:51:16 PM PST 24
Finished Feb 29 02:51:43 PM PST 24
Peak memory 370788 kb
Host smart-386538ba-a417-4ddd-a4b0-6720330c7b31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591584088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1591584088
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1562045719
Short name T312
Test name
Test status
Simulation time 410289831 ps
CPU time 2.18 seconds
Started Feb 29 02:51:13 PM PST 24
Finished Feb 29 02:51:16 PM PST 24
Peak memory 203644 kb
Host smart-d6ae2426-3bf9-4286-94c4-02c4932078ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562045719 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1562045719
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2834666513
Short name T675
Test name
Test status
Simulation time 3196446343 ps
CPU time 6.63 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:22 PM PST 24
Peak memory 203688 kb
Host smart-67732216-3b33-4b7f-b433-2fb24eb2186b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834666513 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2834666513
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3814218785
Short name T1297
Test name
Test status
Simulation time 17773222627 ps
CPU time 500.03 seconds
Started Feb 29 02:51:13 PM PST 24
Finished Feb 29 02:59:34 PM PST 24
Peak memory 4105428 kb
Host smart-6b2f7a97-799c-43a4-ab52-df1882287213
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814218785 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3814218785
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_perf.1262678460
Short name T822
Test name
Test status
Simulation time 614005975 ps
CPU time 3.58 seconds
Started Feb 29 02:51:19 PM PST 24
Finished Feb 29 02:51:22 PM PST 24
Peak memory 203688 kb
Host smart-164f1765-0248-4261-b67a-547837b30b52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262678460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_perf.1262678460
Directory /workspace/44.i2c_target_perf/latest

Test location /workspace/coverage/default/44.i2c_target_stress_all.714154053
Short name T194
Test name
Test status
Simulation time 66835901538 ps
CPU time 3116.25 seconds
Started Feb 29 02:51:16 PM PST 24
Finished Feb 29 03:43:13 PM PST 24
Peak memory 11048664 kb
Host smart-e013c291-ca0f-4aaa-a9df-c16384fd3a28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714154053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.i2c_target_stress_all.714154053
Directory /workspace/44.i2c_target_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3705301561
Short name T1300
Test name
Test status
Simulation time 451156872 ps
CPU time 18.07 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:34 PM PST 24
Peak memory 203592 kb
Host smart-961d862d-607d-49bd-be68-5c78d4b5f1d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705301561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3705301561
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.1731192411
Short name T43
Test name
Test status
Simulation time 35727136522 ps
CPU time 53.89 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:52:08 PM PST 24
Peak memory 1006144 kb
Host smart-e89b3f19-0cf3-497e-8889-cba4d2770fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731192411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.1731192411
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.3854467860
Short name T1276
Test name
Test status
Simulation time 22326946329 ps
CPU time 343.62 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:56:58 PM PST 24
Peak memory 1164324 kb
Host smart-4d5acc5d-b1e1-4775-95c9-1802eeb5a5d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854467860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.3854467860
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2612422247
Short name T935
Test name
Test status
Simulation time 2529876543 ps
CPU time 8.55 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:51:23 PM PST 24
Peak memory 208680 kb
Host smart-d8c3c9c3-8e33-48db-8c3c-43da85292d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612422247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2612422247
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.2075082554
Short name T783
Test name
Test status
Simulation time 2719642319 ps
CPU time 6.32 seconds
Started Feb 29 02:51:18 PM PST 24
Finished Feb 29 02:51:25 PM PST 24
Peak memory 203728 kb
Host smart-7878345b-54ab-4627-9a18-1fd2cedd0210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075082554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.2075082554
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2736176816
Short name T890
Test name
Test status
Simulation time 112686023 ps
CPU time 0.64 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:51:25 PM PST 24
Peak memory 203520 kb
Host smart-2c9efbe1-6b06-457f-aeb3-b8aef063b8ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736176816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2736176816
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1941698705
Short name T781
Test name
Test status
Simulation time 172137193 ps
CPU time 1.32 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:51:27 PM PST 24
Peak memory 211888 kb
Host smart-d351436b-9b06-48fd-b0f0-ad27cb1d820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941698705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1941698705
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.26266518
Short name T944
Test name
Test status
Simulation time 933204110 ps
CPU time 10.65 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:51:24 PM PST 24
Peak memory 309764 kb
Host smart-c3056918-82db-421d-b7c0-67107d139651
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26266518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty
.26266518
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.205330908
Short name T1029
Test name
Test status
Simulation time 12511700933 ps
CPU time 75.49 seconds
Started Feb 29 02:51:18 PM PST 24
Finished Feb 29 02:52:34 PM PST 24
Peak memory 734520 kb
Host smart-18ac55db-6cac-4113-aef6-ab73e74b0a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205330908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.205330908
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.290916403
Short name T788
Test name
Test status
Simulation time 4830504204 ps
CPU time 120.03 seconds
Started Feb 29 02:51:19 PM PST 24
Finished Feb 29 02:53:19 PM PST 24
Peak memory 1055264 kb
Host smart-0a0e8dd1-781f-4446-93f9-2d354066d5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290916403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.290916403
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2806794104
Short name T1280
Test name
Test status
Simulation time 1770991672 ps
CPU time 6.44 seconds
Started Feb 29 02:51:17 PM PST 24
Finished Feb 29 02:51:24 PM PST 24
Peak memory 203556 kb
Host smart-6d06b97e-3d5f-4177-a5f0-2fbb1d00b6d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806794104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2806794104
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.3984969124
Short name T1041
Test name
Test status
Simulation time 24241903041 ps
CPU time 312.28 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:56:27 PM PST 24
Peak memory 1229844 kb
Host smart-94cedcd2-026e-4d14-a58a-e2c38c6e0f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984969124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3984969124
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3612268712
Short name T901
Test name
Test status
Simulation time 5960949649 ps
CPU time 96.74 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:53:01 PM PST 24
Peak memory 338932 kb
Host smart-01c65df6-a196-4b22-b9b9-0d2fa28d02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612268712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3612268712
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.4244117598
Short name T150
Test name
Test status
Simulation time 42266323 ps
CPU time 0.67 seconds
Started Feb 29 02:51:18 PM PST 24
Finished Feb 29 02:51:18 PM PST 24
Peak memory 202764 kb
Host smart-15f9e5ba-cda9-4096-8656-d73f17c0ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244117598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.4244117598
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1299665074
Short name T402
Test name
Test status
Simulation time 6536244148 ps
CPU time 338.05 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:56:53 PM PST 24
Peak memory 252204 kb
Host smart-e3214a6f-a8b3-4709-8f00-3477ebdd438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299665074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1299665074
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_rx_oversample.4289270360
Short name T550
Test name
Test status
Simulation time 3270488308 ps
CPU time 120.5 seconds
Started Feb 29 02:51:18 PM PST 24
Finished Feb 29 02:53:18 PM PST 24
Peak memory 276492 kb
Host smart-eb4cd0ac-5ea4-4927-8c3b-998a2c36c59b
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289270360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_rx_oversample
.4289270360
Directory /workspace/45.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.456619105
Short name T826
Test name
Test status
Simulation time 5170554640 ps
CPU time 72.47 seconds
Started Feb 29 02:51:14 PM PST 24
Finished Feb 29 02:52:26 PM PST 24
Peak memory 228064 kb
Host smart-ef8cd5ce-48e6-4e1a-a496-aef640ec7947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456619105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.456619105
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3479581634
Short name T887
Test name
Test status
Simulation time 550154542 ps
CPU time 10.55 seconds
Started Feb 29 02:51:15 PM PST 24
Finished Feb 29 02:51:25 PM PST 24
Peak memory 219256 kb
Host smart-4fcfa26a-a909-4a2a-897d-94b37cc5ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479581634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3479581634
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.692029
Short name T998
Test name
Test status
Simulation time 2000161737 ps
CPU time 4.26 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:51:31 PM PST 24
Peak memory 203644 kb
Host smart-8bb4fc5a-7bfb-471c-b4ee-e2d19c1bc273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692029 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.i2c_target_bad_addr.692029
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.252898823
Short name T786
Test name
Test status
Simulation time 10244775703 ps
CPU time 25.16 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:51:51 PM PST 24
Peak memory 318560 kb
Host smart-5fd08fec-6438-4d22-bf77-8a9a12b08963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252898823 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.252898823
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1425264676
Short name T332
Test name
Test status
Simulation time 10126798756 ps
CPU time 11.43 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:51:38 PM PST 24
Peak memory 316788 kb
Host smart-0ebf316c-78f3-42f1-994a-53bf2f2f5be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425264676 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1425264676
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.644643448
Short name T243
Test name
Test status
Simulation time 441230130 ps
CPU time 2.32 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:51:27 PM PST 24
Peak memory 203820 kb
Host smart-1b244675-02e6-4024-9232-700d8fe30e84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644643448 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.644643448
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3155765858
Short name T1197
Test name
Test status
Simulation time 2229404928 ps
CPU time 5.86 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:51:31 PM PST 24
Peak memory 203716 kb
Host smart-ad7b785f-2bf8-44c7-bdc3-4c0bd4da8d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155765858 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3155765858
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2546487923
Short name T917
Test name
Test status
Simulation time 9093170940 ps
CPU time 14.66 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:51:39 PM PST 24
Peak memory 474744 kb
Host smart-7955dbbf-2ea7-4e28-82e4-6f1c201971f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546487923 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2546487923
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_perf.3689405200
Short name T988
Test name
Test status
Simulation time 1226422061 ps
CPU time 4.55 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:51:30 PM PST 24
Peak memory 203644 kb
Host smart-9698d15c-0e47-4b30-81f7-5a5c61e663fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689405200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_perf.3689405200
Directory /workspace/45.i2c_target_perf/latest

Test location /workspace/coverage/default/45.i2c_target_stress_all.1359713968
Short name T525
Test name
Test status
Simulation time 51841016890 ps
CPU time 57.06 seconds
Started Feb 29 02:51:27 PM PST 24
Finished Feb 29 02:52:24 PM PST 24
Peak memory 222460 kb
Host smart-34a78000-7764-4cab-8007-5fd4de6ddc36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359713968 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.i2c_target_stress_all.1359713968
Directory /workspace/45.i2c_target_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.954566885
Short name T196
Test name
Test status
Simulation time 48804179826 ps
CPU time 755.74 seconds
Started Feb 29 02:51:25 PM PST 24
Finished Feb 29 03:04:01 PM PST 24
Peak memory 5699864 kb
Host smart-66ac3285-effd-4136-9582-8d629da19fc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954566885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.954566885
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3293069386
Short name T321
Test name
Test status
Simulation time 2054008440 ps
CPU time 8.48 seconds
Started Feb 29 02:51:25 PM PST 24
Finished Feb 29 02:51:34 PM PST 24
Peak memory 210724 kb
Host smart-ed980201-7831-4b2a-9ef5-38079c54f9ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293069386 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3293069386
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.805800455
Short name T486
Test name
Test status
Simulation time 2478351057 ps
CPU time 5.72 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:51:31 PM PST 24
Peak memory 204604 kb
Host smart-3947349d-183b-47c7-9a2a-d15da18456d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805800455 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_unexp_stop.805800455
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2078872763
Short name T383
Test name
Test status
Simulation time 15499660 ps
CPU time 0.6 seconds
Started Feb 29 02:51:37 PM PST 24
Finished Feb 29 02:51:38 PM PST 24
Peak memory 202716 kb
Host smart-21f1c604-0862-4bd5-9fe1-36228f2c11ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078872763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2078872763
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3635446292
Short name T1012
Test name
Test status
Simulation time 23213897 ps
CPU time 1.02 seconds
Started Feb 29 02:51:36 PM PST 24
Finished Feb 29 02:51:37 PM PST 24
Peak memory 203604 kb
Host smart-ca0c0ded-fbba-44c6-a9b6-633eb4355ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635446292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3635446292
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.1752994743
Short name T731
Test name
Test status
Simulation time 1734200941 ps
CPU time 8.3 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:51:33 PM PST 24
Peak memory 300252 kb
Host smart-8c622a36-9cce-4aaf-8060-11567bd92890
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752994743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.1752994743
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1818995672
Short name T706
Test name
Test status
Simulation time 5063796471 ps
CPU time 56.93 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:52:22 PM PST 24
Peak memory 441268 kb
Host smart-9b957356-9393-447a-b27a-76345b53f2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818995672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1818995672
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.167379027
Short name T565
Test name
Test status
Simulation time 1866606785 ps
CPU time 64.51 seconds
Started Feb 29 02:51:24 PM PST 24
Finished Feb 29 02:52:29 PM PST 24
Peak memory 662100 kb
Host smart-c4ad17db-d993-4fda-8acb-dbaaea6b1e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167379027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.167379027
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.4053942539
Short name T1061
Test name
Test status
Simulation time 970753802 ps
CPU time 6.82 seconds
Started Feb 29 02:51:23 PM PST 24
Finished Feb 29 02:51:30 PM PST 24
Peak memory 251620 kb
Host smart-1fb0e8d3-a60d-4feb-b92d-9291da935ea4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053942539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.4053942539
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.540623800
Short name T578
Test name
Test status
Simulation time 3329714780 ps
CPU time 239.84 seconds
Started Feb 29 02:51:25 PM PST 24
Finished Feb 29 02:55:25 PM PST 24
Peak memory 1031216 kb
Host smart-b6095ac9-d5f9-4fa6-92c7-0907154d36aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540623800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.540623800
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.67738591
Short name T623
Test name
Test status
Simulation time 3361856528 ps
CPU time 42.39 seconds
Started Feb 29 02:51:35 PM PST 24
Finished Feb 29 02:52:18 PM PST 24
Peak memory 248348 kb
Host smart-9e306250-3f46-4ddb-bcaf-181a0944a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67738591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.67738591
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3776253301
Short name T148
Test name
Test status
Simulation time 28569209 ps
CPU time 0.62 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:51:27 PM PST 24
Peak memory 202924 kb
Host smart-30726fcc-1b8f-4ec2-b7fb-4fea796c58e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776253301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3776253301
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2963036187
Short name T1340
Test name
Test status
Simulation time 202137308 ps
CPU time 4.48 seconds
Started Feb 29 02:51:35 PM PST 24
Finished Feb 29 02:51:40 PM PST 24
Peak memory 226960 kb
Host smart-6b1f1dee-3ed3-4e69-b2c2-60720d06293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963036187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2963036187
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_rx_oversample.3272986825
Short name T212
Test name
Test status
Simulation time 3896763856 ps
CPU time 167.6 seconds
Started Feb 29 02:51:26 PM PST 24
Finished Feb 29 02:54:13 PM PST 24
Peak memory 363648 kb
Host smart-8b68dceb-c996-4937-b74f-f8fb2fd09cf5
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272986825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_rx_oversample
.3272986825
Directory /workspace/46.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2204021251
Short name T672
Test name
Test status
Simulation time 3864252984 ps
CPU time 108.25 seconds
Started Feb 29 02:51:25 PM PST 24
Finished Feb 29 02:53:14 PM PST 24
Peak memory 244492 kb
Host smart-1c9aed4c-5fcf-46d5-ac2c-0392f0b85467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204021251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2204021251
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.229245679
Short name T979
Test name
Test status
Simulation time 1923478408 ps
CPU time 9.12 seconds
Started Feb 29 02:51:37 PM PST 24
Finished Feb 29 02:51:47 PM PST 24
Peak memory 211848 kb
Host smart-5f62912f-7ba6-453f-a983-eb844554f023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229245679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.229245679
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3741004892
Short name T389
Test name
Test status
Simulation time 1315874989 ps
CPU time 5.2 seconds
Started Feb 29 02:51:33 PM PST 24
Finished Feb 29 02:51:39 PM PST 24
Peak memory 203624 kb
Host smart-65a71e7d-6399-4e0e-8ab4-6cc8348205cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741004892 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3741004892
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.824950107
Short name T226
Test name
Test status
Simulation time 10112432904 ps
CPU time 34.44 seconds
Started Feb 29 02:51:37 PM PST 24
Finished Feb 29 02:52:12 PM PST 24
Peak memory 398788 kb
Host smart-d0d83e79-8985-4223-ac28-370519915569
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824950107 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.824950107
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.720697412
Short name T654
Test name
Test status
Simulation time 10070202290 ps
CPU time 80.79 seconds
Started Feb 29 02:51:36 PM PST 24
Finished Feb 29 02:52:58 PM PST 24
Peak memory 681684 kb
Host smart-c8c0e990-0556-42be-beb6-578c983b91d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720697412 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.720697412
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1146933926
Short name T983
Test name
Test status
Simulation time 2095841471 ps
CPU time 2.22 seconds
Started Feb 29 02:51:35 PM PST 24
Finished Feb 29 02:51:38 PM PST 24
Peak memory 203640 kb
Host smart-3669395e-ee23-41bb-8007-340a921d102e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146933926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1146933926
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1180545790
Short name T661
Test name
Test status
Simulation time 6225603682 ps
CPU time 6.32 seconds
Started Feb 29 02:51:37 PM PST 24
Finished Feb 29 02:51:44 PM PST 24
Peak memory 207440 kb
Host smart-477c9c36-59c7-4432-98a9-90acc022914a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180545790 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1180545790
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.3101197914
Short name T949
Test name
Test status
Simulation time 11241619997 ps
CPU time 24.34 seconds
Started Feb 29 02:51:34 PM PST 24
Finished Feb 29 02:51:59 PM PST 24
Peak memory 559196 kb
Host smart-4aa38d18-2398-4879-9c0f-ed7beb28b629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101197914 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.3101197914
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_perf.1618202204
Short name T1337
Test name
Test status
Simulation time 955545025 ps
CPU time 5.53 seconds
Started Feb 29 02:51:37 PM PST 24
Finished Feb 29 02:51:43 PM PST 24
Peak memory 214320 kb
Host smart-04da6bdb-afc4-4454-8e36-3bb67cc75393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618202204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_perf.1618202204
Directory /workspace/46.i2c_target_perf/latest

Test location /workspace/coverage/default/46.i2c_target_stress_all.1618748375
Short name T1111
Test name
Test status
Simulation time 24778851752 ps
CPU time 27.2 seconds
Started Feb 29 02:51:35 PM PST 24
Finished Feb 29 02:52:03 PM PST 24
Peak memory 269124 kb
Host smart-317618a3-94e8-45ed-9596-d7c15b9c4114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618748375 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 46.i2c_target_stress_all.1618748375
Directory /workspace/46.i2c_target_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3030953849
Short name T450
Test name
Test status
Simulation time 43744607280 ps
CPU time 3057.45 seconds
Started Feb 29 02:51:37 PM PST 24
Finished Feb 29 03:42:35 PM PST 24
Peak memory 4246012 kb
Host smart-5a47dbe5-5864-4bd6-94ac-14f2e01c2083
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030953849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3030953849
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.1359631670
Short name T755
Test name
Test status
Simulation time 6013872716 ps
CPU time 6.19 seconds
Started Feb 29 02:51:39 PM PST 24
Finished Feb 29 02:51:45 PM PST 24
Peak memory 203668 kb
Host smart-45dd2a89-1ba7-44c5-8837-0603906abc9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359631670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.1359631670
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.966217523
Short name T192
Test name
Test status
Simulation time 6739361021 ps
CPU time 8.61 seconds
Started Feb 29 02:51:38 PM PST 24
Finished Feb 29 02:51:47 PM PST 24
Peak memory 203772 kb
Host smart-caa7b5c5-74ad-4546-b258-70f9a8bc7d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966217523 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_unexp_stop.966217523
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2058838123
Short name T349
Test name
Test status
Simulation time 33983997 ps
CPU time 0.62 seconds
Started Feb 29 02:51:47 PM PST 24
Finished Feb 29 02:51:48 PM PST 24
Peak memory 202556 kb
Host smart-36644475-7c2b-43eb-887e-06f5e9192abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058838123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2058838123
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.703230791
Short name T361
Test name
Test status
Simulation time 75712330 ps
CPU time 1.32 seconds
Started Feb 29 02:51:45 PM PST 24
Finished Feb 29 02:51:46 PM PST 24
Peak memory 211800 kb
Host smart-a74e3f76-f641-4b91-a695-25b2f2c4d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703230791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.703230791
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1201187070
Short name T140
Test name
Test status
Simulation time 616483770 ps
CPU time 10.15 seconds
Started Feb 29 02:51:36 PM PST 24
Finished Feb 29 02:51:46 PM PST 24
Peak memory 317808 kb
Host smart-343cbdab-54ae-40a0-a2d5-b198353ca946
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201187070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1201187070
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.575752010
Short name T20
Test name
Test status
Simulation time 20774781056 ps
CPU time 94.72 seconds
Started Feb 29 02:51:34 PM PST 24
Finished Feb 29 02:53:09 PM PST 24
Peak memory 805696 kb
Host smart-dc40bdcb-0110-4be0-bdcc-8576b4216ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575752010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.575752010
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3515915040
Short name T1079
Test name
Test status
Simulation time 10252728104 ps
CPU time 188.88 seconds
Started Feb 29 02:51:39 PM PST 24
Finished Feb 29 02:54:48 PM PST 24
Peak memory 765684 kb
Host smart-e29f4286-1205-4bc2-bd13-e433408d5602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515915040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3515915040
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.675710417
Short name T599
Test name
Test status
Simulation time 192095461 ps
CPU time 4.84 seconds
Started Feb 29 02:51:35 PM PST 24
Finished Feb 29 02:51:40 PM PST 24
Peak memory 235056 kb
Host smart-309d3603-4844-440c-829e-453ad0d0a394
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675710417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
675710417
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.348837564
Short name T306
Test name
Test status
Simulation time 5582584276 ps
CPU time 442.43 seconds
Started Feb 29 02:51:35 PM PST 24
Finished Feb 29 02:58:58 PM PST 24
Peak memory 1620880 kb
Host smart-034c8a76-41be-4428-963e-485ccb6e4040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348837564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.348837564
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.300716202
Short name T392
Test name
Test status
Simulation time 18827425123 ps
CPU time 54.47 seconds
Started Feb 29 02:51:49 PM PST 24
Finished Feb 29 02:52:44 PM PST 24
Peak memory 331960 kb
Host smart-4120ede6-d527-4783-bdd1-f0cfc9fcaf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300716202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.300716202
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.1024313687
Short name T994
Test name
Test status
Simulation time 103548198 ps
CPU time 0.64 seconds
Started Feb 29 02:51:37 PM PST 24
Finished Feb 29 02:51:38 PM PST 24
Peak memory 202924 kb
Host smart-ac0ebe42-254c-4529-8d53-de2bd72ec319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024313687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1024313687
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2310084860
Short name T1154
Test name
Test status
Simulation time 20281609525 ps
CPU time 78.97 seconds
Started Feb 29 02:51:46 PM PST 24
Finished Feb 29 02:53:05 PM PST 24
Peak memory 212008 kb
Host smart-dfc7d3fd-4a4c-4cd6-9306-a430f358b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310084860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2310084860
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_rx_oversample.508418641
Short name T1203
Test name
Test status
Simulation time 4670223477 ps
CPU time 174.41 seconds
Started Feb 29 02:51:36 PM PST 24
Finished Feb 29 02:54:31 PM PST 24
Peak memory 267920 kb
Host smart-c6bfe0a4-18b0-4f90-9353-4f4dab5130ef
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508418641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversampl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_rx_oversample.
508418641
Directory /workspace/47.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.4216293973
Short name T912
Test name
Test status
Simulation time 9432162612 ps
CPU time 57.65 seconds
Started Feb 29 02:51:36 PM PST 24
Finished Feb 29 02:52:35 PM PST 24
Peak memory 260296 kb
Host smart-8ad49e95-e646-4669-a207-214c6715bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216293973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.4216293973
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3328858044
Short name T1262
Test name
Test status
Simulation time 4196553449 ps
CPU time 15.33 seconds
Started Feb 29 02:51:48 PM PST 24
Finished Feb 29 02:52:04 PM PST 24
Peak memory 220076 kb
Host smart-dd4bbb3d-03fa-4895-ac77-7f04079f48aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328858044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3328858044
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2220487972
Short name T878
Test name
Test status
Simulation time 7032703775 ps
CPU time 6.1 seconds
Started Feb 29 02:51:49 PM PST 24
Finished Feb 29 02:51:56 PM PST 24
Peak memory 203712 kb
Host smart-d6b08445-5221-4f3a-a1da-60d321233617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220487972 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2220487972
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1908667973
Short name T881
Test name
Test status
Simulation time 10187030056 ps
CPU time 26 seconds
Started Feb 29 02:51:45 PM PST 24
Finished Feb 29 02:52:12 PM PST 24
Peak memory 350472 kb
Host smart-a20af754-b42a-4292-9621-ac05d3dfe9f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908667973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1908667973
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3232104125
Short name T387
Test name
Test status
Simulation time 10158199089 ps
CPU time 12.6 seconds
Started Feb 29 02:51:49 PM PST 24
Finished Feb 29 02:52:02 PM PST 24
Peak memory 301312 kb
Host smart-9412c7ef-ebaa-404c-8597-020e17e37f98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232104125 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3232104125
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1212834857
Short name T1306
Test name
Test status
Simulation time 1521496128 ps
CPU time 2.34 seconds
Started Feb 29 02:51:49 PM PST 24
Finished Feb 29 02:51:52 PM PST 24
Peak memory 203632 kb
Host smart-7027f80e-60dc-4dde-ad57-19fd1b01bc00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212834857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1212834857
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.4131605137
Short name T538
Test name
Test status
Simulation time 4030570841 ps
CPU time 5.07 seconds
Started Feb 29 02:51:47 PM PST 24
Finished Feb 29 02:51:52 PM PST 24
Peak memory 204984 kb
Host smart-000b39d7-df55-4fd3-a01a-0caca96d749a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131605137 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.4131605137
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.4151645737
Short name T659
Test name
Test status
Simulation time 10996985798 ps
CPU time 83.83 seconds
Started Feb 29 02:51:48 PM PST 24
Finished Feb 29 02:53:13 PM PST 24
Peak memory 1734036 kb
Host smart-a69dd981-704f-4843-8347-6a2673c305ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151645737 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.4151645737
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_perf.1896110683
Short name T1053
Test name
Test status
Simulation time 970226019 ps
CPU time 2.95 seconds
Started Feb 29 02:51:49 PM PST 24
Finished Feb 29 02:51:53 PM PST 24
Peak memory 203664 kb
Host smart-d9a54c6f-efd4-4c12-b002-cb209e552c3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896110683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_perf.1896110683
Directory /workspace/47.i2c_target_perf/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2313084272
Short name T536
Test name
Test status
Simulation time 53933399161 ps
CPU time 869.99 seconds
Started Feb 29 02:51:47 PM PST 24
Finished Feb 29 03:06:18 PM PST 24
Peak memory 6327312 kb
Host smart-adad85f6-b31f-4a6c-a020-4e8db1c89c26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313084272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2313084272
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1750468234
Short name T573
Test name
Test status
Simulation time 8237781408 ps
CPU time 249.61 seconds
Started Feb 29 02:51:49 PM PST 24
Finished Feb 29 02:56:00 PM PST 24
Peak memory 1034076 kb
Host smart-6f83cb87-d899-49d9-9073-44b66b5419aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750468234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1750468234
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2852016033
Short name T359
Test name
Test status
Simulation time 7805491570 ps
CPU time 7.52 seconds
Started Feb 29 02:51:46 PM PST 24
Finished Feb 29 02:51:54 PM PST 24
Peak memory 212484 kb
Host smart-db9b3572-8c06-45ad-8e05-598f8c46fa03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852016033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2852016033
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.2116846087
Short name T501
Test name
Test status
Simulation time 2428836038 ps
CPU time 5.6 seconds
Started Feb 29 02:51:45 PM PST 24
Finished Feb 29 02:51:51 PM PST 24
Peak memory 208404 kb
Host smart-3c2443bf-2aa6-4c65-8a0e-56f6ac012f12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116846087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.2116846087
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2836822538
Short name T1215
Test name
Test status
Simulation time 47667231 ps
CPU time 0.6 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:51:59 PM PST 24
Peak memory 202600 kb
Host smart-f24f8cdf-514a-43e8-aaa7-ebeb8389f9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836822538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2836822538
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1352040913
Short name T775
Test name
Test status
Simulation time 56500562 ps
CPU time 1.36 seconds
Started Feb 29 02:51:56 PM PST 24
Finished Feb 29 02:51:57 PM PST 24
Peak memory 213288 kb
Host smart-938406c5-0ba7-4772-9c7f-5d44c3ad0599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352040913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1352040913
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2957490039
Short name T460
Test name
Test status
Simulation time 1409451080 ps
CPU time 17.33 seconds
Started Feb 29 02:51:46 PM PST 24
Finished Feb 29 02:52:03 PM PST 24
Peak memory 277452 kb
Host smart-29ee8855-755a-45d8-a499-07c9d53912bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957490039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2957490039
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.959318497
Short name T217
Test name
Test status
Simulation time 10966325562 ps
CPU time 95.61 seconds
Started Feb 29 02:51:45 PM PST 24
Finished Feb 29 02:53:21 PM PST 24
Peak memory 800848 kb
Host smart-a1848fbd-a7db-482e-8244-d447c16454c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959318497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.959318497
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1917940383
Short name T835
Test name
Test status
Simulation time 5145914804 ps
CPU time 80.75 seconds
Started Feb 29 02:51:47 PM PST 24
Finished Feb 29 02:53:08 PM PST 24
Peak memory 702572 kb
Host smart-1d8c89bb-0822-4e1f-b214-36399410fbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917940383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1917940383
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3517588272
Short name T177
Test name
Test status
Simulation time 175242924 ps
CPU time 4.34 seconds
Started Feb 29 02:51:46 PM PST 24
Finished Feb 29 02:51:51 PM PST 24
Peak memory 234396 kb
Host smart-9d3242e5-b38a-47f3-aa1a-738d1840243d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517588272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3517588272
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2064079650
Short name T758
Test name
Test status
Simulation time 7183108917 ps
CPU time 240.09 seconds
Started Feb 29 02:51:46 PM PST 24
Finished Feb 29 02:55:46 PM PST 24
Peak memory 1738000 kb
Host smart-b5c366a7-1244-4a22-81ab-33171f579537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064079650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2064079650
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3542859974
Short name T381
Test name
Test status
Simulation time 3827977033 ps
CPU time 105.02 seconds
Started Feb 29 02:51:58 PM PST 24
Finished Feb 29 02:53:44 PM PST 24
Peak memory 235592 kb
Host smart-805e9660-ed52-43dc-b134-65fca208cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542859974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3542859974
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2095097609
Short name T144
Test name
Test status
Simulation time 20513481 ps
CPU time 0.67 seconds
Started Feb 29 02:51:47 PM PST 24
Finished Feb 29 02:51:48 PM PST 24
Peak memory 202672 kb
Host smart-f4cf5a4e-eeb8-44ce-9542-e8446334d677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095097609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2095097609
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1428420492
Short name T24
Test name
Test status
Simulation time 52276022925 ps
CPU time 810.73 seconds
Started Feb 29 02:51:45 PM PST 24
Finished Feb 29 03:05:16 PM PST 24
Peak memory 405436 kb
Host smart-05d2b2db-5ed9-4df6-a95d-2fe652a8838a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428420492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1428420492
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_rx_oversample.2380155726
Short name T787
Test name
Test status
Simulation time 1778269090 ps
CPU time 45.18 seconds
Started Feb 29 02:51:46 PM PST 24
Finished Feb 29 02:52:31 PM PST 24
Peak memory 261600 kb
Host smart-1dd7765b-ec14-4eac-994e-19260a4b6a4f
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380155726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_rx_oversample
.2380155726
Directory /workspace/48.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.4101091665
Short name T1064
Test name
Test status
Simulation time 3841732193 ps
CPU time 92.45 seconds
Started Feb 29 02:51:46 PM PST 24
Finished Feb 29 02:53:19 PM PST 24
Peak memory 395980 kb
Host smart-cc47a44d-d8a6-4232-bd26-976e0d524691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101091665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.4101091665
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.485742201
Short name T769
Test name
Test status
Simulation time 10559867042 ps
CPU time 58.15 seconds
Started Feb 29 02:51:58 PM PST 24
Finished Feb 29 02:52:56 PM PST 24
Peak memory 220124 kb
Host smart-aec894f0-71e0-41a9-aa5a-025387ab95c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485742201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.485742201
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3686912445
Short name T281
Test name
Test status
Simulation time 2010625886 ps
CPU time 7.2 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:06 PM PST 24
Peak memory 203612 kb
Host smart-6883b958-3b96-4be1-ab6e-7b897135eb0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686912445 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3686912445
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3086840525
Short name T977
Test name
Test status
Simulation time 10143205720 ps
CPU time 20.73 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:20 PM PST 24
Peak memory 344928 kb
Host smart-adf41199-d5bd-43d4-af73-1c573b1a69c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086840525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3086840525
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2366266198
Short name T357
Test name
Test status
Simulation time 10049347554 ps
CPU time 29.46 seconds
Started Feb 29 02:52:00 PM PST 24
Finished Feb 29 02:52:29 PM PST 24
Peak memory 407168 kb
Host smart-bd66bb65-b1c0-468e-a28e-522ba199837e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366266198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2366266198
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.2575972142
Short name T187
Test name
Test status
Simulation time 2691527509 ps
CPU time 2.73 seconds
Started Feb 29 02:51:57 PM PST 24
Finished Feb 29 02:52:00 PM PST 24
Peak memory 203712 kb
Host smart-6f2a5958-4518-49a4-9f5e-37edfa18df32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575972142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.2575972142
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.745514980
Short name T1005
Test name
Test status
Simulation time 4772015722 ps
CPU time 5.04 seconds
Started Feb 29 02:51:56 PM PST 24
Finished Feb 29 02:52:02 PM PST 24
Peak memory 203672 kb
Host smart-c50ac1ad-72a2-43d9-b5e2-5d819a996b9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745514980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.745514980
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.3162465210
Short name T634
Test name
Test status
Simulation time 18802393947 ps
CPU time 77.58 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:53:17 PM PST 24
Peak memory 1078292 kb
Host smart-ebc20a82-28fc-4b07-85ad-dd875988cd85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162465210 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.3162465210
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_perf.4222006312
Short name T676
Test name
Test status
Simulation time 9865910255 ps
CPU time 3.64 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:03 PM PST 24
Peak memory 207052 kb
Host smart-463d1f6a-ab49-443e-980a-ae96e4b8ee46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222006312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_perf.4222006312
Directory /workspace/48.i2c_target_perf/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.493793633
Short name T1200
Test name
Test status
Simulation time 47444483268 ps
CPU time 360.19 seconds
Started Feb 29 02:51:58 PM PST 24
Finished Feb 29 02:57:58 PM PST 24
Peak memory 3076800 kb
Host smart-9b019d03-b90e-4821-99fb-7d38f1154f36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493793633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_target_stress_all.493793633
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2641109339
Short name T419
Test name
Test status
Simulation time 463610638 ps
CPU time 6.73 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:06 PM PST 24
Peak memory 203748 kb
Host smart-b0e5b2e2-b424-471d-81c5-bb0e589bba58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641109339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2641109339
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2919233774
Short name T868
Test name
Test status
Simulation time 9177885427 ps
CPU time 10.61 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:09 PM PST 24
Peak memory 437940 kb
Host smart-22074783-7e28-4d39-babd-29c73370d5fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919233774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2919233774
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.4147187552
Short name T1179
Test name
Test status
Simulation time 40815152169 ps
CPU time 282.72 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:56:42 PM PST 24
Peak memory 1850096 kb
Host smart-5f87059f-9b31-4a28-9f46-922cea26e56e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147187552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.4147187552
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2275970414
Short name T693
Test name
Test status
Simulation time 3275195456 ps
CPU time 7.19 seconds
Started Feb 29 02:51:58 PM PST 24
Finished Feb 29 02:52:06 PM PST 24
Peak memory 203752 kb
Host smart-3d9c03ab-c254-4284-b102-4f7822bf09bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275970414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2275970414
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.3397474459
Short name T440
Test name
Test status
Simulation time 1452387413 ps
CPU time 6.98 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:06 PM PST 24
Peak memory 203608 kb
Host smart-5c37434a-6819-4d92-9a5a-2ba320f620e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397474459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.3397474459
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.700055265
Short name T365
Test name
Test status
Simulation time 26760116 ps
CPU time 0.61 seconds
Started Feb 29 02:52:09 PM PST 24
Finished Feb 29 02:52:09 PM PST 24
Peak memory 202568 kb
Host smart-bd4600fa-9a91-4dce-8c81-19c28f23cfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700055265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.700055265
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2856793734
Short name T1052
Test name
Test status
Simulation time 131835698 ps
CPU time 1.07 seconds
Started Feb 29 02:51:57 PM PST 24
Finished Feb 29 02:51:58 PM PST 24
Peak memory 211840 kb
Host smart-11926fb5-d94a-4295-97f3-ce708a9af68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856793734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2856793734
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2932152445
Short name T1245
Test name
Test status
Simulation time 1124754193 ps
CPU time 4.99 seconds
Started Feb 29 02:51:58 PM PST 24
Finished Feb 29 02:52:03 PM PST 24
Peak memory 257784 kb
Host smart-4fa33203-41d7-4db4-8609-6fbba65cbcca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932152445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2932152445
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3782524790
Short name T1239
Test name
Test status
Simulation time 12835564552 ps
CPU time 265.08 seconds
Started Feb 29 02:51:56 PM PST 24
Finished Feb 29 02:56:21 PM PST 24
Peak memory 1003732 kb
Host smart-6554c5f4-60ea-40ef-be03-e5edc22193ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782524790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3782524790
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.195903228
Short name T269
Test name
Test status
Simulation time 1721611200 ps
CPU time 52.01 seconds
Started Feb 29 02:51:55 PM PST 24
Finished Feb 29 02:52:48 PM PST 24
Peak memory 548436 kb
Host smart-d596325a-1e9b-4817-9768-5c867c927871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195903228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.195903228
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1142054422
Short name T532
Test name
Test status
Simulation time 773929455 ps
CPU time 4.54 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:03 PM PST 24
Peak memory 238164 kb
Host smart-324a2124-1969-4301-92d6-9ff4149f6d2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142054422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1142054422
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.408210307
Short name T356
Test name
Test status
Simulation time 23724466624 ps
CPU time 390.2 seconds
Started Feb 29 02:51:56 PM PST 24
Finished Feb 29 02:58:27 PM PST 24
Peak memory 1385616 kb
Host smart-cdc24c64-bb64-4134-ae63-d8b8e540a245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408210307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.408210307
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3801054954
Short name T1296
Test name
Test status
Simulation time 4481929814 ps
CPU time 104.32 seconds
Started Feb 29 02:52:09 PM PST 24
Finished Feb 29 02:53:54 PM PST 24
Peak memory 228120 kb
Host smart-6db93ee2-a0bd-46bd-8d6a-e58bb143dd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801054954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3801054954
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1554521208
Short name T730
Test name
Test status
Simulation time 49844527 ps
CPU time 0.61 seconds
Started Feb 29 02:51:57 PM PST 24
Finished Feb 29 02:51:58 PM PST 24
Peak memory 202756 kb
Host smart-a6c16597-c98a-4a48-b7de-ef3094c1b91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554521208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1554521208
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2995260567
Short name T1157
Test name
Test status
Simulation time 55863842576 ps
CPU time 269.74 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:56:29 PM PST 24
Peak memory 442584 kb
Host smart-7f6e7434-5607-4118-8b72-1a2855f483a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995260567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2995260567
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_rx_oversample.3289252850
Short name T701
Test name
Test status
Simulation time 8783827735 ps
CPU time 78.26 seconds
Started Feb 29 02:52:00 PM PST 24
Finished Feb 29 02:53:18 PM PST 24
Peak memory 319416 kb
Host smart-dbb52ddf-2ddf-4c5e-9623-74a1a5e57faa
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289252850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_rx_oversample
.3289252850
Directory /workspace/49.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.549857718
Short name T888
Test name
Test status
Simulation time 2494748257 ps
CPU time 59.75 seconds
Started Feb 29 02:51:59 PM PST 24
Finished Feb 29 02:52:59 PM PST 24
Peak memory 284872 kb
Host smart-e4b40c59-b70f-4b68-a984-82dabe4c3c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549857718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.549857718
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3788164427
Short name T1102
Test name
Test status
Simulation time 2898593909 ps
CPU time 18.25 seconds
Started Feb 29 02:51:57 PM PST 24
Finished Feb 29 02:52:16 PM PST 24
Peak memory 211920 kb
Host smart-953547a3-5197-46fa-beb2-b808ebc86a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788164427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3788164427
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1506882348
Short name T326
Test name
Test status
Simulation time 7449287130 ps
CPU time 4.06 seconds
Started Feb 29 02:52:09 PM PST 24
Finished Feb 29 02:52:13 PM PST 24
Peak memory 203624 kb
Host smart-757d4a5a-c535-4e7a-ab86-5849c6092c91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506882348 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1506882348
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3407822592
Short name T360
Test name
Test status
Simulation time 10055160758 ps
CPU time 50.94 seconds
Started Feb 29 02:52:09 PM PST 24
Finished Feb 29 02:53:00 PM PST 24
Peak memory 467928 kb
Host smart-0f5e276d-181e-47cf-b4dc-a842e5966243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407822592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3407822592
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.8630879
Short name T974
Test name
Test status
Simulation time 10137398753 ps
CPU time 27.03 seconds
Started Feb 29 02:52:08 PM PST 24
Finished Feb 29 02:52:35 PM PST 24
Peak memory 383252 kb
Host smart-ff4bfdad-bd02-44f5-86c2-88bf245b2507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8630879 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.i2c_target_fifo_reset_tx.8630879
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.4070544773
Short name T802
Test name
Test status
Simulation time 638131927 ps
CPU time 2.94 seconds
Started Feb 29 02:52:07 PM PST 24
Finished Feb 29 02:52:11 PM PST 24
Peak memory 203640 kb
Host smart-12864ab0-614b-41e9-b172-7f28a0c63475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070544773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.4070544773
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2433136327
Short name T56
Test name
Test status
Simulation time 5628246213 ps
CPU time 4.2 seconds
Started Feb 29 02:52:09 PM PST 24
Finished Feb 29 02:52:14 PM PST 24
Peak memory 203884 kb
Host smart-e31522dc-d0a2-4fef-b2e2-50182596ddcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433136327 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2433136327
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.694427078
Short name T1022
Test name
Test status
Simulation time 3802850957 ps
CPU time 11.47 seconds
Started Feb 29 02:52:06 PM PST 24
Finished Feb 29 02:52:18 PM PST 24
Peak memory 444620 kb
Host smart-4c1116b0-f407-4d5a-b05d-0829f49a1a45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694427078 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.694427078
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_perf.1132847221
Short name T996
Test name
Test status
Simulation time 1700225481 ps
CPU time 4.73 seconds
Started Feb 29 02:52:07 PM PST 24
Finished Feb 29 02:52:13 PM PST 24
Peak memory 203624 kb
Host smart-6122f77a-6357-4dc4-8af8-8c0790c929b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132847221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_perf.1132847221
Directory /workspace/49.i2c_target_perf/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.1869841128
Short name T992
Test name
Test status
Simulation time 759539364 ps
CPU time 19.51 seconds
Started Feb 29 02:52:09 PM PST 24
Finished Feb 29 02:52:29 PM PST 24
Peak memory 203580 kb
Host smart-bbccecfc-1e67-4cd0-931b-aaf167cd6b75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869841128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.1869841128
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.2365488329
Short name T774
Test name
Test status
Simulation time 58157369102 ps
CPU time 42.59 seconds
Started Feb 29 02:52:09 PM PST 24
Finished Feb 29 02:52:52 PM PST 24
Peak memory 652968 kb
Host smart-826564a6-c634-471b-926d-7481e8bc7c93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365488329 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.2365488329
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1860078605
Short name T812
Test name
Test status
Simulation time 1025932383 ps
CPU time 41.6 seconds
Started Feb 29 02:52:10 PM PST 24
Finished Feb 29 02:52:52 PM PST 24
Peak memory 203632 kb
Host smart-f30221fb-e706-4ffc-baff-368d5c05ebd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860078605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1860078605
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3861138529
Short name T197
Test name
Test status
Simulation time 28774557336 ps
CPU time 700.56 seconds
Started Feb 29 02:52:12 PM PST 24
Finished Feb 29 03:03:53 PM PST 24
Peak memory 6323240 kb
Host smart-ec88947d-2922-4805-9266-31b7aa2af054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861138529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3861138529
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2654272966
Short name T245
Test name
Test status
Simulation time 9395901861 ps
CPU time 476.81 seconds
Started Feb 29 02:52:12 PM PST 24
Finished Feb 29 03:00:09 PM PST 24
Peak memory 1667592 kb
Host smart-cd167c28-4059-4203-8ac3-b231cbcb2dc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654272966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2654272966
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2478090423
Short name T694
Test name
Test status
Simulation time 2321867451 ps
CPU time 8.06 seconds
Started Feb 29 02:52:11 PM PST 24
Finished Feb 29 02:52:19 PM PST 24
Peak memory 208064 kb
Host smart-0a79635e-6da8-480f-8779-420dcef0df85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478090423 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2478090423
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.2095880977
Short name T604
Test name
Test status
Simulation time 2184490338 ps
CPU time 5.24 seconds
Started Feb 29 02:52:13 PM PST 24
Finished Feb 29 02:52:18 PM PST 24
Peak memory 203632 kb
Host smart-ce86cc87-8e7c-46f7-a2a5-bd020833a314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095880977 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.i2c_target_unexp_stop.2095880977
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.848946118
Short name T465
Test name
Test status
Simulation time 15260450 ps
CPU time 0.57 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:23 PM PST 24
Peak memory 203508 kb
Host smart-e21f5eff-60c8-4adf-8627-920098476a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848946118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.848946118
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1257396894
Short name T31
Test name
Test status
Simulation time 103718165 ps
CPU time 1.41 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:44:09 PM PST 24
Peak memory 214152 kb
Host smart-0d7d4281-d1f9-4611-9d4e-cc9493811d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257396894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1257396894
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3165847409
Short name T251
Test name
Test status
Simulation time 578007133 ps
CPU time 17.19 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:26 PM PST 24
Peak memory 266704 kb
Host smart-47ed4472-b644-4507-adce-97cfd5388fa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165847409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3165847409
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2568776378
Short name T980
Test name
Test status
Simulation time 11125784803 ps
CPU time 103.78 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:45:53 PM PST 24
Peak memory 870220 kb
Host smart-cfa60bd8-b8d8-47ae-baac-893cd8099b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568776378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2568776378
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1157716907
Short name T940
Test name
Test status
Simulation time 10869871984 ps
CPU time 121.68 seconds
Started Feb 29 02:44:06 PM PST 24
Finished Feb 29 02:46:08 PM PST 24
Peak memory 874884 kb
Host smart-6c0c6742-2b79-4790-b1b4-4ae410f683f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157716907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1157716907
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2214213743
Short name T647
Test name
Test status
Simulation time 174988789 ps
CPU time 9.55 seconds
Started Feb 29 02:44:05 PM PST 24
Finished Feb 29 02:44:15 PM PST 24
Peak memory 233984 kb
Host smart-d98f5a3a-29b7-4eba-8635-2e4058913dc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214213743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2214213743
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.935684049
Short name T1083
Test name
Test status
Simulation time 32622709556 ps
CPU time 650.97 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:54:59 PM PST 24
Peak memory 1899132 kb
Host smart-b19936c8-c3a9-43b5-80af-c8e6fb8bf8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935684049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.935684049
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2932957750
Short name T409
Test name
Test status
Simulation time 2268583163 ps
CPU time 137.74 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:46:27 PM PST 24
Peak memory 261764 kb
Host smart-19f8063b-bb2c-406a-9ee7-3d08595f2c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932957750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2932957750
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.1074608025
Short name T989
Test name
Test status
Simulation time 42978299 ps
CPU time 0.63 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:44:09 PM PST 24
Peak memory 202712 kb
Host smart-0bab22d9-0ffc-477e-a3f4-9a9a44f67d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074608025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1074608025
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.2005476581
Short name T653
Test name
Test status
Simulation time 12219708265 ps
CPU time 179 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:47:06 PM PST 24
Peak memory 212008 kb
Host smart-28a8db03-7128-4b7f-945f-65a5ff5a17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005476581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2005476581
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_rx_oversample.2746310397
Short name T1018
Test name
Test status
Simulation time 10875700867 ps
CPU time 103.82 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:45:51 PM PST 24
Peak memory 298948 kb
Host smart-392cfcb0-d818-4b18-bf10-97f8f78babfe
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746310397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_rx_oversample.
2746310397
Directory /workspace/5.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.491758817
Short name T1227
Test name
Test status
Simulation time 4875077796 ps
CPU time 71.8 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:45:19 PM PST 24
Peak memory 236136 kb
Host smart-d1e4f0ca-48b8-48e7-b839-db43f6592d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491758817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.491758817
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2395290622
Short name T1070
Test name
Test status
Simulation time 997298598 ps
CPU time 9.34 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:18 PM PST 24
Peak memory 211960 kb
Host smart-c586ac60-bc22-482a-9ab0-8835a35f0fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395290622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2395290622
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1372336948
Short name T382
Test name
Test status
Simulation time 2847030969 ps
CPU time 3.23 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:11 PM PST 24
Peak memory 203684 kb
Host smart-97bf3ddb-c19a-4631-b14b-24bcb1ae5087
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372336948 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1372336948
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2901727556
Short name T633
Test name
Test status
Simulation time 10168007068 ps
CPU time 12.16 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:21 PM PST 24
Peak memory 281412 kb
Host smart-112c5458-b284-4863-bcaa-51333dd6d097
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901727556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2901727556
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.276837682
Short name T1100
Test name
Test status
Simulation time 10119112992 ps
CPU time 73.54 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:45:21 PM PST 24
Peak memory 564416 kb
Host smart-8ede8713-3393-44af-92d2-d7ec98725248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276837682 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.276837682
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3255338104
Short name T1208
Test name
Test status
Simulation time 1211494431 ps
CPU time 2.78 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:11 PM PST 24
Peak memory 203644 kb
Host smart-65828649-d09a-418a-98e8-7f1b030e861e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255338104 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3255338104
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.387434137
Short name T138
Test name
Test status
Simulation time 6742079170 ps
CPU time 6.7 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:44:14 PM PST 24
Peak memory 203736 kb
Host smart-1708c582-71f7-4377-ae5b-586b536ca576
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387434137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.387434137
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3308312420
Short name T1127
Test name
Test status
Simulation time 26995018921 ps
CPU time 752.17 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:56:40 PM PST 24
Peak memory 5680888 kb
Host smart-7a472345-55e5-4218-952b-b78f569ac5e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308312420 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3308312420
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_perf.4065696550
Short name T869
Test name
Test status
Simulation time 741469436 ps
CPU time 4.45 seconds
Started Feb 29 02:44:08 PM PST 24
Finished Feb 29 02:44:13 PM PST 24
Peak memory 204904 kb
Host smart-2a9c690c-98cf-49ae-9fce-c1d0b5f34328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065696550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_perf.4065696550
Directory /workspace/5.i2c_target_perf/latest

Test location /workspace/coverage/default/5.i2c_target_stress_all.971550534
Short name T1261
Test name
Test status
Simulation time 64068865420 ps
CPU time 137.68 seconds
Started Feb 29 02:44:11 PM PST 24
Finished Feb 29 02:46:28 PM PST 24
Peak memory 969568 kb
Host smart-3925939a-cb7e-4a36-a743-72afaceaee2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971550534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.i2c_target_stress_all.971550534
Directory /workspace/5.i2c_target_stress_all/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2595998393
Short name T1027
Test name
Test status
Simulation time 48423357155 ps
CPU time 2266.57 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 03:21:54 PM PST 24
Peak memory 11233040 kb
Host smart-00f34526-03f4-4f5a-bbb7-654015f75052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595998393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2595998393
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1124755523
Short name T570
Test name
Test status
Simulation time 27874011984 ps
CPU time 130.26 seconds
Started Feb 29 02:44:07 PM PST 24
Finished Feb 29 02:46:18 PM PST 24
Peak memory 1096576 kb
Host smart-b38735c2-e258-4fcc-86c7-8b801428fbaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124755523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1124755523
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1438612686
Short name T1131
Test name
Test status
Simulation time 2961498679 ps
CPU time 6.07 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:44:16 PM PST 24
Peak memory 203696 kb
Host smart-e6473b3d-4378-459b-8c3b-e3fcd5e83068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438612686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1438612686
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.1162553379
Short name T842
Test name
Test status
Simulation time 5265145823 ps
CPU time 6.63 seconds
Started Feb 29 02:44:09 PM PST 24
Finished Feb 29 02:44:16 PM PST 24
Peak memory 203696 kb
Host smart-bea581fb-183c-4403-8440-d2f50adc9755
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162553379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.1162553379
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3218045408
Short name T1323
Test name
Test status
Simulation time 23700438 ps
CPU time 0.61 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:23 PM PST 24
Peak memory 202568 kb
Host smart-4d217f39-26eb-4fdb-b08f-aef30912c072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218045408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3218045408
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1933580498
Short name T1310
Test name
Test status
Simulation time 77511966 ps
CPU time 1.44 seconds
Started Feb 29 02:44:23 PM PST 24
Finished Feb 29 02:44:24 PM PST 24
Peak memory 211816 kb
Host smart-918dec11-d26c-4da1-b19f-b2a658377a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933580498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1933580498
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3199740724
Short name T616
Test name
Test status
Simulation time 3710284677 ps
CPU time 15.9 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:38 PM PST 24
Peak memory 267860 kb
Host smart-08d96664-4a1d-44c4-aadb-97aeeb4f345e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199740724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3199740724
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2009896502
Short name T746
Test name
Test status
Simulation time 13195382405 ps
CPU time 165.67 seconds
Started Feb 29 02:44:21 PM PST 24
Finished Feb 29 02:47:08 PM PST 24
Peak memory 651896 kb
Host smart-69c3ce12-6d4c-48da-8932-e00a8a6fdba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009896502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2009896502
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3085600695
Short name T1073
Test name
Test status
Simulation time 2480104146 ps
CPU time 88.79 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:45:51 PM PST 24
Peak memory 802296 kb
Host smart-fde351ee-15a2-4138-add1-bf9d3a71eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085600695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3085600695
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3970702984
Short name T1144
Test name
Test status
Simulation time 458911520 ps
CPU time 6.32 seconds
Started Feb 29 02:44:24 PM PST 24
Finished Feb 29 02:44:30 PM PST 24
Peak memory 251432 kb
Host smart-07cf7d73-5ded-4ec1-a609-b6de319f5c22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970702984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3970702984
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3728752253
Short name T924
Test name
Test status
Simulation time 19392250866 ps
CPU time 153.38 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:46:56 PM PST 24
Peak memory 1363220 kb
Host smart-ea5c9d10-e1bb-42ce-9ef7-e6221b2626b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728752253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3728752253
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3498560025
Short name T415
Test name
Test status
Simulation time 10606044185 ps
CPU time 93.28 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:45:56 PM PST 24
Peak memory 365452 kb
Host smart-750e34d5-6ea1-46c7-a452-818d784fc671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498560025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3498560025
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2907208341
Short name T891
Test name
Test status
Simulation time 47017325 ps
CPU time 0.62 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:23 PM PST 24
Peak memory 202724 kb
Host smart-4b35b065-0885-40ff-8a1c-38e8265e84a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907208341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2907208341
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1972022513
Short name T170
Test name
Test status
Simulation time 27176377272 ps
CPU time 441.91 seconds
Started Feb 29 02:44:21 PM PST 24
Finished Feb 29 02:51:44 PM PST 24
Peak memory 212948 kb
Host smart-16aa99fe-0b89-4906-9514-ce99f1562de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972022513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1972022513
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_rx_oversample.1367900078
Short name T442
Test name
Test status
Simulation time 2313570586 ps
CPU time 91.48 seconds
Started Feb 29 02:44:23 PM PST 24
Finished Feb 29 02:45:54 PM PST 24
Peak memory 298856 kb
Host smart-07ccea98-5b16-40e5-88e9-26363d5186bc
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367900078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_rx_oversample.
1367900078
Directory /workspace/6.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1577969722
Short name T106
Test name
Test status
Simulation time 1681533068 ps
CPU time 79.12 seconds
Started Feb 29 02:44:21 PM PST 24
Finished Feb 29 02:45:40 PM PST 24
Peak memory 227484 kb
Host smart-ab37c428-6c39-494d-8bfd-a3fe59eb88a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577969722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1577969722
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3546494697
Short name T722
Test name
Test status
Simulation time 811630542 ps
CPU time 11 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:33 PM PST 24
Peak memory 219176 kb
Host smart-851d42e6-742c-41ff-a330-95f66ebec692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546494697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3546494697
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4204334551
Short name T1077
Test name
Test status
Simulation time 1911585786 ps
CPU time 5.5 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:27 PM PST 24
Peak memory 203724 kb
Host smart-28235d4a-9183-46d9-9952-a378e682b4b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204334551 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4204334551
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.973767694
Short name T372
Test name
Test status
Simulation time 10545245669 ps
CPU time 13.19 seconds
Started Feb 29 02:44:21 PM PST 24
Finished Feb 29 02:44:35 PM PST 24
Peak memory 294296 kb
Host smart-b1b6a36a-db65-4798-9ce6-9694c7015e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973767694 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.973767694
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3141257851
Short name T847
Test name
Test status
Simulation time 10092872014 ps
CPU time 25.58 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:48 PM PST 24
Peak memory 373692 kb
Host smart-5babdbd8-3678-4f23-baa5-f38652c2e71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141257851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3141257851
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1317554234
Short name T614
Test name
Test status
Simulation time 2324758661 ps
CPU time 3.04 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:25 PM PST 24
Peak memory 203672 kb
Host smart-5a7436d7-caff-4d54-bf70-5182793d6e57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317554234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1317554234
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3976254400
Short name T1299
Test name
Test status
Simulation time 1335469176 ps
CPU time 4.86 seconds
Started Feb 29 02:44:23 PM PST 24
Finished Feb 29 02:44:28 PM PST 24
Peak memory 206788 kb
Host smart-01fa1f8f-b5c5-4f13-b16c-61ffe38b92db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976254400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3976254400
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.4182637821
Short name T840
Test name
Test status
Simulation time 12235543649 ps
CPU time 218.55 seconds
Started Feb 29 02:44:21 PM PST 24
Finished Feb 29 02:48:00 PM PST 24
Peak memory 2859644 kb
Host smart-85c6c9d1-78e5-4f86-9d25-094a4e15dbd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182637821 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.4182637821
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_perf.1125924340
Short name T487
Test name
Test status
Simulation time 2504317345 ps
CPU time 3.72 seconds
Started Feb 29 02:44:21 PM PST 24
Finished Feb 29 02:44:25 PM PST 24
Peak memory 203772 kb
Host smart-3456b6f3-5238-48e3-8fb5-5c8a198f4db9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125924340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_perf.1125924340
Directory /workspace/6.i2c_target_perf/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.898481369
Short name T377
Test name
Test status
Simulation time 30345761873 ps
CPU time 33.56 seconds
Started Feb 29 02:44:23 PM PST 24
Finished Feb 29 02:44:56 PM PST 24
Peak memory 253584 kb
Host smart-752884cc-42b4-4f07-850b-3432431c00e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898481369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_target_stress_all.898481369
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1802738515
Short name T284
Test name
Test status
Simulation time 26446791234 ps
CPU time 92.92 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:45:56 PM PST 24
Peak memory 1546648 kb
Host smart-06f0e373-fc4d-4cb4-9739-30fee304784c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802738515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1802738515
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.424532195
Short name T191
Test name
Test status
Simulation time 44305063544 ps
CPU time 128.46 seconds
Started Feb 29 02:44:23 PM PST 24
Finished Feb 29 02:46:31 PM PST 24
Peak memory 1179708 kb
Host smart-1065b398-339f-4150-9167-791723437360
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424532195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.424532195
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3185436883
Short name T371
Test name
Test status
Simulation time 3391994553 ps
CPU time 7.27 seconds
Started Feb 29 02:44:22 PM PST 24
Finished Feb 29 02:44:30 PM PST 24
Peak memory 206904 kb
Host smart-683ee53b-d288-4cbd-8f8a-c34a9ac2ee69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185436883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3185436883
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_unexp_stop.895367638
Short name T54
Test name
Test status
Simulation time 1036378312 ps
CPU time 5.02 seconds
Started Feb 29 02:44:21 PM PST 24
Finished Feb 29 02:44:26 PM PST 24
Peak memory 210416 kb
Host smart-79b92254-854d-4ed7-b5be-e051b24c47ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895367638 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_unexp_stop.895367638
Directory /workspace/6.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1962939417
Short name T582
Test name
Test status
Simulation time 37303628 ps
CPU time 0.6 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:44:39 PM PST 24
Peak memory 202528 kb
Host smart-977d6209-65af-4f97-abf7-dd7e6fb685e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962939417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1962939417
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3816481889
Short name T235
Test name
Test status
Simulation time 53703264 ps
CPU time 1.34 seconds
Started Feb 29 02:44:42 PM PST 24
Finished Feb 29 02:44:43 PM PST 24
Peak memory 211752 kb
Host smart-d070ed7c-cfcd-4fe7-82a7-6bd451e003b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816481889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3816481889
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.46746325
Short name T592
Test name
Test status
Simulation time 1919894349 ps
CPU time 26.99 seconds
Started Feb 29 02:44:38 PM PST 24
Finished Feb 29 02:45:06 PM PST 24
Peak memory 313720 kb
Host smart-5ecc86ba-2cd6-46f7-91f5-b7c78239c366
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46746325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.46746325
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2410744585
Short name T725
Test name
Test status
Simulation time 15004501067 ps
CPU time 126.76 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:46:46 PM PST 24
Peak memory 927160 kb
Host smart-8105a33e-0ba8-4ac4-8e4d-fced0cb1b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410744585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2410744585
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.358073264
Short name T493
Test name
Test status
Simulation time 12874908469 ps
CPU time 266.04 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:49:05 PM PST 24
Peak memory 973664 kb
Host smart-8b266e7a-7549-4493-b0f6-125e7e6b1ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358073264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.358073264
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1530327633
Short name T1233
Test name
Test status
Simulation time 262089386 ps
CPU time 13.41 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:44:53 PM PST 24
Peak memory 203636 kb
Host smart-a1f6db15-8315-449f-85af-4b6bc4e7570b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530327633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1530327633
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2852722813
Short name T262
Test name
Test status
Simulation time 21166814033 ps
CPU time 514.17 seconds
Started Feb 29 02:44:38 PM PST 24
Finished Feb 29 02:53:13 PM PST 24
Peak memory 1655508 kb
Host smart-340123bd-4cc9-4903-81b7-560d3cc07bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852722813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2852722813
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.905401494
Short name T12
Test name
Test status
Simulation time 9709651411 ps
CPU time 63.18 seconds
Started Feb 29 02:44:40 PM PST 24
Finished Feb 29 02:45:43 PM PST 24
Peak memory 311036 kb
Host smart-23707eb2-f54c-4dc3-b7eb-58170e697ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905401494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.905401494
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1253036150
Short name T147
Test name
Test status
Simulation time 20308634 ps
CPU time 0.65 seconds
Started Feb 29 02:44:40 PM PST 24
Finished Feb 29 02:44:40 PM PST 24
Peak memory 202768 kb
Host smart-bd5ab4ea-2351-47a2-b288-36748000efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253036150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1253036150
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.51890229
Short name T169
Test name
Test status
Simulation time 688032703 ps
CPU time 3.52 seconds
Started Feb 29 02:44:42 PM PST 24
Finished Feb 29 02:44:45 PM PST 24
Peak memory 211792 kb
Host smart-06c9445e-e411-487e-a04a-90ad81244a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51890229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.51890229
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_rx_oversample.3217387683
Short name T214
Test name
Test status
Simulation time 2254738174 ps
CPU time 114.15 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:46:34 PM PST 24
Peak memory 335488 kb
Host smart-f5f478a0-d1bb-48d8-949c-3b015309c5e1
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217387683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_rx_oversample.
3217387683
Directory /workspace/7.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2172030685
Short name T1188
Test name
Test status
Simulation time 5039712637 ps
CPU time 137.96 seconds
Started Feb 29 02:44:40 PM PST 24
Finished Feb 29 02:46:58 PM PST 24
Peak memory 244700 kb
Host smart-90413f2c-b073-4182-92f3-28e5799d738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172030685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2172030685
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3783372023
Short name T777
Test name
Test status
Simulation time 3889284126 ps
CPU time 18.57 seconds
Started Feb 29 02:44:42 PM PST 24
Finished Feb 29 02:45:01 PM PST 24
Peak memory 216668 kb
Host smart-bf6c73aa-31a8-4d01-a04e-eea2f9fa899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783372023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3783372023
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1376973621
Short name T870
Test name
Test status
Simulation time 1836063895 ps
CPU time 4.25 seconds
Started Feb 29 02:44:42 PM PST 24
Finished Feb 29 02:44:46 PM PST 24
Peak memory 203604 kb
Host smart-113d9260-b23a-4d4f-9fd4-0ecf022d0099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376973621 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1376973621
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3387986655
Short name T564
Test name
Test status
Simulation time 10198123949 ps
CPU time 16.14 seconds
Started Feb 29 02:44:40 PM PST 24
Finished Feb 29 02:44:56 PM PST 24
Peak memory 282844 kb
Host smart-13df7053-a5f8-4c59-b039-194f6a21065d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387986655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3387986655
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3113819343
Short name T903
Test name
Test status
Simulation time 10323516306 ps
CPU time 15.05 seconds
Started Feb 29 02:44:40 PM PST 24
Finished Feb 29 02:44:55 PM PST 24
Peak memory 326424 kb
Host smart-477472e3-d883-44d8-9b86-6d8129896d0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113819343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3113819343
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2646996617
Short name T1274
Test name
Test status
Simulation time 453054372 ps
CPU time 2.67 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:44:41 PM PST 24
Peak memory 203648 kb
Host smart-21385b50-c790-4831-b5af-1353c13629c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646996617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2646996617
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.4239004704
Short name T286
Test name
Test status
Simulation time 2946047152 ps
CPU time 5.89 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:44:45 PM PST 24
Peak memory 208132 kb
Host smart-e2abba44-ab1b-40f2-9eff-0711437eeba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239004704 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.4239004704
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.988001322
Short name T669
Test name
Test status
Simulation time 7174546444 ps
CPU time 59.46 seconds
Started Feb 29 02:44:41 PM PST 24
Finished Feb 29 02:45:41 PM PST 24
Peak memory 1178184 kb
Host smart-80ecf0b1-5a10-49f8-8891-f676afd9a7c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988001322 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.988001322
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_perf.502811359
Short name T832
Test name
Test status
Simulation time 2728160248 ps
CPU time 3.76 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:44:43 PM PST 24
Peak memory 205888 kb
Host smart-cf01d1cf-6790-47fa-a9b5-a2b330513068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502811359 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_perf.502811359
Directory /workspace/7.i2c_target_perf/latest

Test location /workspace/coverage/default/7.i2c_target_stress_all.2046395297
Short name T854
Test name
Test status
Simulation time 26274256944 ps
CPU time 422.01 seconds
Started Feb 29 02:44:38 PM PST 24
Finished Feb 29 02:51:41 PM PST 24
Peak memory 2285412 kb
Host smart-794b02d7-ac16-41b3-a2b5-1250ca86ce23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046395297 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.i2c_target_stress_all.2046395297
Directory /workspace/7.i2c_target_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2862191974
Short name T695
Test name
Test status
Simulation time 8461945740 ps
CPU time 77.58 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:45:56 PM PST 24
Peak memory 204940 kb
Host smart-b4074120-1cca-4de4-a75a-f6662d38a3af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862191974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2862191974
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.1529496854
Short name T1193
Test name
Test status
Simulation time 26738164102 ps
CPU time 1536.23 seconds
Started Feb 29 02:44:41 PM PST 24
Finished Feb 29 03:10:18 PM PST 24
Peak memory 5672404 kb
Host smart-c158c47a-9511-4269-bb47-791ffc90ae79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529496854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.1529496854
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.275529669
Short name T1181
Test name
Test status
Simulation time 1232591812 ps
CPU time 6.47 seconds
Started Feb 29 02:44:40 PM PST 24
Finished Feb 29 02:44:46 PM PST 24
Peak memory 203600 kb
Host smart-04620fd7-4a57-466a-9eb0-cbdd647d7890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275529669 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.275529669
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_unexp_stop.1909401528
Short name T203
Test name
Test status
Simulation time 1070281218 ps
CPU time 5.3 seconds
Started Feb 29 02:44:41 PM PST 24
Finished Feb 29 02:44:46 PM PST 24
Peak memory 203616 kb
Host smart-e51598ff-d04e-4274-a5d9-1a60c72c97ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909401528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.i2c_target_unexp_stop.1909401528
Directory /workspace/7.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3425919158
Short name T1099
Test name
Test status
Simulation time 18734245 ps
CPU time 0.62 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:44:58 PM PST 24
Peak memory 203520 kb
Host smart-7781c1c9-9591-4113-84e4-839cfd4b4dae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425919158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3425919158
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1960205036
Short name T954
Test name
Test status
Simulation time 156644773 ps
CPU time 1.77 seconds
Started Feb 29 02:44:59 PM PST 24
Finished Feb 29 02:45:01 PM PST 24
Peak memory 211816 kb
Host smart-d008a415-9a18-426b-80cd-6b630e000dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960205036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1960205036
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.561773854
Short name T627
Test name
Test status
Simulation time 735212578 ps
CPU time 12.75 seconds
Started Feb 29 02:44:59 PM PST 24
Finished Feb 29 02:45:12 PM PST 24
Peak memory 367756 kb
Host smart-db473501-deb0-47cd-a8df-bc5ab5533ac3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561773854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.561773854
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2573483360
Short name T1085
Test name
Test status
Simulation time 49502197591 ps
CPU time 132.16 seconds
Started Feb 29 02:44:51 PM PST 24
Finished Feb 29 02:47:04 PM PST 24
Peak memory 362692 kb
Host smart-1e1f4379-5ce3-464a-a10a-00700a011a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573483360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2573483360
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.791226464
Short name T237
Test name
Test status
Simulation time 4896508556 ps
CPU time 85.62 seconds
Started Feb 29 02:44:40 PM PST 24
Finished Feb 29 02:46:06 PM PST 24
Peak memory 775116 kb
Host smart-7f1f5895-aa87-49ee-ac6e-5f44e7ebf8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791226464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.791226464
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1268577782
Short name T585
Test name
Test status
Simulation time 795768569 ps
CPU time 5.73 seconds
Started Feb 29 02:45:00 PM PST 24
Finished Feb 29 02:45:06 PM PST 24
Peak memory 241728 kb
Host smart-0dd9487a-7717-4f4a-bb4b-ad8f49951068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268577782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1268577782
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1696796794
Short name T631
Test name
Test status
Simulation time 3751269377 ps
CPU time 94.63 seconds
Started Feb 29 02:44:39 PM PST 24
Finished Feb 29 02:46:13 PM PST 24
Peak memory 980144 kb
Host smart-72a32f6d-0d6f-472d-b443-596a9058a910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696796794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1696796794
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.150164223
Short name T32
Test name
Test status
Simulation time 1298215643 ps
CPU time 62.39 seconds
Started Feb 29 02:45:01 PM PST 24
Finished Feb 29 02:46:05 PM PST 24
Peak memory 219968 kb
Host smart-1c1bd1ac-9297-415d-8db0-8e5e27d1ca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150164223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.150164223
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2567223698
Short name T757
Test name
Test status
Simulation time 52277396 ps
CPU time 0.65 seconds
Started Feb 29 02:44:43 PM PST 24
Finished Feb 29 02:44:44 PM PST 24
Peak memory 202768 kb
Host smart-b4e4ecbc-ddd0-4260-9439-6c78a3da4258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567223698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2567223698
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1200038336
Short name T168
Test name
Test status
Simulation time 13265952214 ps
CPU time 95.44 seconds
Started Feb 29 02:45:00 PM PST 24
Finished Feb 29 02:46:36 PM PST 24
Peak memory 211940 kb
Host smart-04c8180f-0c23-4c65-a02c-acc1f327f893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200038336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1200038336
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_rx_oversample.2202560330
Short name T1043
Test name
Test status
Simulation time 6000763795 ps
CPU time 113.61 seconds
Started Feb 29 02:44:41 PM PST 24
Finished Feb 29 02:46:35 PM PST 24
Peak memory 318972 kb
Host smart-4a618a2f-8bc0-4db6-a1f2-d41180015657
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202560330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_rx_oversample.
2202560330
Directory /workspace/8.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.3369508580
Short name T629
Test name
Test status
Simulation time 2649050639 ps
CPU time 24.47 seconds
Started Feb 29 02:44:41 PM PST 24
Finished Feb 29 02:45:06 PM PST 24
Peak memory 247320 kb
Host smart-e6d6ef2a-e0af-4408-8b97-7c1bbff7fbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369508580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3369508580
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.3881595228
Short name T221
Test name
Test status
Simulation time 12824152500 ps
CPU time 1557.11 seconds
Started Feb 29 02:44:58 PM PST 24
Finished Feb 29 03:10:55 PM PST 24
Peak memory 2197208 kb
Host smart-4cdea704-53cd-4329-b7fc-3c26dd5a22b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881595228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.3881595228
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3974601059
Short name T338
Test name
Test status
Simulation time 5670269097 ps
CPU time 14.33 seconds
Started Feb 29 02:45:00 PM PST 24
Finished Feb 29 02:45:15 PM PST 24
Peak memory 228260 kb
Host smart-eff20887-171f-4aba-a772-14ac5407df0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974601059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3974601059
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3001138581
Short name T1169
Test name
Test status
Simulation time 593287119 ps
CPU time 2.69 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:44:59 PM PST 24
Peak memory 203612 kb
Host smart-127514d5-d5d8-44cb-8415-289c02304932
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001138581 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3001138581
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.270615319
Short name T63
Test name
Test status
Simulation time 10278447389 ps
CPU time 29.59 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:45:26 PM PST 24
Peak memory 398844 kb
Host smart-3de08079-dec8-461c-b368-e2d1bd57f319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270615319 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.270615319
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.4221402135
Short name T872
Test name
Test status
Simulation time 10212682403 ps
CPU time 9.74 seconds
Started Feb 29 02:44:58 PM PST 24
Finished Feb 29 02:45:08 PM PST 24
Peak memory 263464 kb
Host smart-2dc20b90-e7cb-4f85-b80a-f49416494050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221402135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.4221402135
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.149923201
Short name T778
Test name
Test status
Simulation time 1655867436 ps
CPU time 2.28 seconds
Started Feb 29 02:44:58 PM PST 24
Finished Feb 29 02:45:00 PM PST 24
Peak memory 203628 kb
Host smart-93422370-d59f-460d-af05-75bed35893fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149923201 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.149923201
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1283758106
Short name T1320
Test name
Test status
Simulation time 3839607879 ps
CPU time 5.12 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:45:02 PM PST 24
Peak memory 207760 kb
Host smart-37d27023-6e3d-4663-9780-9f81f708ebb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283758106 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1283758106
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2472473531
Short name T406
Test name
Test status
Simulation time 13018843377 ps
CPU time 240.74 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:48:58 PM PST 24
Peak memory 2985444 kb
Host smart-4bd8fad8-63df-4a7a-bda2-4bfbdf726a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472473531 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2472473531
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_perf.784133619
Short name T300
Test name
Test status
Simulation time 1044268286 ps
CPU time 5.78 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:45:02 PM PST 24
Peak memory 206864 kb
Host smart-7d03d0f6-7e6f-4bb8-af8f-fa08d1fbd981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784133619 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_perf.784133619
Directory /workspace/8.i2c_target_perf/latest

Test location /workspace/coverage/default/8.i2c_target_stress_all.3090777541
Short name T1270
Test name
Test status
Simulation time 63650170607 ps
CPU time 669.81 seconds
Started Feb 29 02:45:01 PM PST 24
Finished Feb 29 02:56:12 PM PST 24
Peak memory 5104840 kb
Host smart-2b78ebc3-f1d0-4132-89e0-21b938b712c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090777541 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.i2c_target_stress_all.3090777541
Directory /workspace/8.i2c_target_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3280610744
Short name T668
Test name
Test status
Simulation time 2085130018 ps
CPU time 37.85 seconds
Started Feb 29 02:44:58 PM PST 24
Finished Feb 29 02:45:36 PM PST 24
Peak memory 227836 kb
Host smart-d7a49ba3-41c3-42e1-80b6-4f5f8fbb6e45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280610744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3280610744
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.2507251403
Short name T369
Test name
Test status
Simulation time 53935052366 ps
CPU time 917.09 seconds
Started Feb 29 02:45:00 PM PST 24
Finished Feb 29 03:00:17 PM PST 24
Peak memory 6438456 kb
Host smart-683016e2-eb57-46d0-b87f-1cb61ab51832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507251403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.2507251403
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2489964785
Short name T747
Test name
Test status
Simulation time 1372428499 ps
CPU time 6.11 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:45:03 PM PST 24
Peak memory 203672 kb
Host smart-6a5be07a-bd4f-4661-97c3-8707994fdb21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489964785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2489964785
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.2825745967
Short name T584
Test name
Test status
Simulation time 4063017438 ps
CPU time 4.99 seconds
Started Feb 29 02:44:59 PM PST 24
Finished Feb 29 02:45:04 PM PST 24
Peak memory 203764 kb
Host smart-f93c23d2-bc66-4ec5-b3a7-0ada713c1f52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825745967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.2825745967
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1622314092
Short name T1186
Test name
Test status
Simulation time 81887569 ps
CPU time 0.59 seconds
Started Feb 29 02:45:19 PM PST 24
Finished Feb 29 02:45:20 PM PST 24
Peak memory 203512 kb
Host smart-166c24a8-05d0-4011-8f66-56c193e940c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622314092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1622314092
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1974566113
Short name T489
Test name
Test status
Simulation time 49242797 ps
CPU time 1.29 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:44:58 PM PST 24
Peak memory 203608 kb
Host smart-74b0f73f-602a-4ffb-8a98-aa7a689113e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974566113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1974566113
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3527582581
Short name T1221
Test name
Test status
Simulation time 183578689 ps
CPU time 3.92 seconds
Started Feb 29 02:45:02 PM PST 24
Finished Feb 29 02:45:06 PM PST 24
Peak memory 227792 kb
Host smart-b4e55dc6-a553-488e-9813-ad2daebc09a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527582581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3527582581
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2292018645
Short name T554
Test name
Test status
Simulation time 2246312426 ps
CPU time 67.12 seconds
Started Feb 29 02:44:58 PM PST 24
Finished Feb 29 02:46:06 PM PST 24
Peak memory 588120 kb
Host smart-7ea95af2-a79e-416f-b925-d5f966a64ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292018645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2292018645
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1711301188
Short name T1119
Test name
Test status
Simulation time 1691508713 ps
CPU time 110.82 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:46:47 PM PST 24
Peak memory 542576 kb
Host smart-eefa2b92-c3b8-4df7-af84-8caafd8fd3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711301188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1711301188
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.4251649505
Short name T1264
Test name
Test status
Simulation time 224267608 ps
CPU time 5.58 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:45:02 PM PST 24
Peak memory 247376 kb
Host smart-a966046e-2628-4bf6-9ada-7e60072e2887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251649505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
4251649505
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2803947677
Short name T727
Test name
Test status
Simulation time 5860304763 ps
CPU time 432.87 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:52:09 PM PST 24
Peak memory 1514856 kb
Host smart-c45d4c81-c794-4a22-8ba4-39be5f49ea97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803947677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2803947677
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.1623365000
Short name T250
Test name
Test status
Simulation time 18647444571 ps
CPU time 146.64 seconds
Started Feb 29 02:45:16 PM PST 24
Finished Feb 29 02:47:43 PM PST 24
Peak memory 344088 kb
Host smart-b9a5411d-138d-4871-a1a1-acc22cc38b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623365000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1623365000
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.1734151176
Short name T1191
Test name
Test status
Simulation time 49340480 ps
CPU time 0.63 seconds
Started Feb 29 02:44:58 PM PST 24
Finished Feb 29 02:44:59 PM PST 24
Peak memory 202816 kb
Host smart-d84e2967-fa2f-49e6-9050-500c141bd210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734151176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1734151176
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.284239938
Short name T1168
Test name
Test status
Simulation time 658890940 ps
CPU time 5.06 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:45:02 PM PST 24
Peak memory 228316 kb
Host smart-b2d84113-3465-4781-8cac-a3de141ab58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284239938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.284239938
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_rx_oversample.2422779996
Short name T926
Test name
Test status
Simulation time 3046471079 ps
CPU time 47.12 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:45:45 PM PST 24
Peak memory 260916 kb
Host smart-45f0300e-e264-4cef-a4dd-893ba2f56274
User root
Command /workspace/default/simv +test_timeout_ns=80_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422779996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_rx_oversamp
le_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_rx_oversample.
2422779996
Directory /workspace/9.i2c_host_rx_oversample/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1939265357
Short name T1024
Test name
Test status
Simulation time 4787984281 ps
CPU time 113.15 seconds
Started Feb 29 02:44:59 PM PST 24
Finished Feb 29 02:46:53 PM PST 24
Peak memory 253108 kb
Host smart-29c5446e-c8ee-43b3-9038-be3d46215ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939265357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1939265357
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3946130765
Short name T275
Test name
Test status
Simulation time 2635153704 ps
CPU time 7.46 seconds
Started Feb 29 02:45:02 PM PST 24
Finished Feb 29 02:45:10 PM PST 24
Peak memory 217764 kb
Host smart-ec8b8e83-484c-4b60-8c82-5ea89cef297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946130765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3946130765
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.312199646
Short name T1156
Test name
Test status
Simulation time 3166324573 ps
CPU time 4.22 seconds
Started Feb 29 02:44:59 PM PST 24
Finished Feb 29 02:45:03 PM PST 24
Peak memory 203764 kb
Host smart-7cc8ee28-75d3-43be-b300-4b5e3244de10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312199646 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.312199646
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1491305251
Short name T1171
Test name
Test status
Simulation time 10208152320 ps
CPU time 27.26 seconds
Started Feb 29 02:45:00 PM PST 24
Finished Feb 29 02:45:27 PM PST 24
Peak memory 364292 kb
Host smart-9d1ec226-e7ff-4c0d-867b-c9a9f2f4af12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491305251 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1491305251
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2313493243
Short name T476
Test name
Test status
Simulation time 10096208668 ps
CPU time 26.63 seconds
Started Feb 29 02:45:01 PM PST 24
Finished Feb 29 02:45:29 PM PST 24
Peak memory 359500 kb
Host smart-c766c047-6503-4ecd-b376-a24a3b0c9d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313493243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2313493243
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2832747019
Short name T329
Test name
Test status
Simulation time 551143088 ps
CPU time 2.53 seconds
Started Feb 29 02:45:02 PM PST 24
Finished Feb 29 02:45:05 PM PST 24
Peak memory 203400 kb
Host smart-f7326b14-94c3-471b-ad95-a0b8c90f0dce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832747019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2832747019
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3783662735
Short name T660
Test name
Test status
Simulation time 1614264347 ps
CPU time 6.9 seconds
Started Feb 29 02:44:59 PM PST 24
Finished Feb 29 02:45:06 PM PST 24
Peak memory 203656 kb
Host smart-2b29c872-2e53-4043-acdc-f81159e247d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783662735 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3783662735
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1821725286
Short name T1314
Test name
Test status
Simulation time 12617928315 ps
CPU time 42.91 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:45:39 PM PST 24
Peak memory 824932 kb
Host smart-b672fe31-ed46-4da5-b487-ae6f16f3cb5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821725286 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1821725286
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_perf.371839443
Short name T933
Test name
Test status
Simulation time 734758859 ps
CPU time 4.22 seconds
Started Feb 29 02:45:01 PM PST 24
Finished Feb 29 02:45:05 PM PST 24
Peak memory 211052 kb
Host smart-25d5b7b5-30e1-4e38-808d-fae370729ee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371839443 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_perf.371839443
Directory /workspace/9.i2c_target_perf/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.216022213
Short name T1033
Test name
Test status
Simulation time 28565308945 ps
CPU time 100.74 seconds
Started Feb 29 02:45:00 PM PST 24
Finished Feb 29 02:46:40 PM PST 24
Peak memory 1616400 kb
Host smart-d2ebec69-7c73-46fb-b118-446ed413ebfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216022213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.216022213
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.4167528555
Short name T973
Test name
Test status
Simulation time 3506393629 ps
CPU time 122.09 seconds
Started Feb 29 02:44:59 PM PST 24
Finished Feb 29 02:47:02 PM PST 24
Peak memory 683864 kb
Host smart-4a4fa8a3-7d8b-418b-af1b-37c1abb16cf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167528555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.4167528555
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2155108271
Short name T799
Test name
Test status
Simulation time 1204107509 ps
CPU time 6.76 seconds
Started Feb 29 02:44:56 PM PST 24
Finished Feb 29 02:45:03 PM PST 24
Peak memory 213624 kb
Host smart-1603b254-3519-4811-b9e8-caf218fb5964
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155108271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2155108271
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.1288988991
Short name T1281
Test name
Test status
Simulation time 6148640372 ps
CPU time 7.97 seconds
Started Feb 29 02:44:57 PM PST 24
Finished Feb 29 02:45:05 PM PST 24
Peak memory 206372 kb
Host smart-f1afe505-88b6-462a-9f24-5bdc90e47dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288988991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.1288988991
Directory /workspace/9.i2c_target_unexp_stop/latest
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