Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	5717800	1			T7	2		T1	3		T8	3
all_values[1]	5717800	1			T7	2		T1	3		T8	3
all_values[2]	5717800	1			T7	2		T1	3		T8	3
all_values[3]	5717800	1			T7	2		T1	3		T8	3
all_values[4]	5717800	1			T7	2		T1	3		T8	3
all_values[5]	5717800	1			T7	2		T1	3		T8	3
all_values[6]	5717800	1			T7	2		T1	3		T8	3
all_values[7]	5717800	1			T7	2		T1	3		T8	3
all_values[8]	5717800	1			T7	2		T1	3		T8	3
all_values[9]	5717800	1			T7	2		T1	3		T8	3
all_values[10]	5717800	1			T7	2		T1	3		T8	3
all_values[11]	5717800	1			T7	2		T1	3		T8	3
all_values[12]	5717800	1			T7	2		T1	3		T8	3
all_values[13]	5717800	1			T7	2		T1	3		T8	3
all_values[14]	5717800	1			T7	2		T1	3		T8	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73375364

1

T7

30

T1

37

T8

44

auto[1]

12391636

1

T1

8

T8

1

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77572083

1

T7

30

T1

45

T8

45

auto[1]

8194917

1

T31

224990

T37

364657

T68

129277

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1515080	1			T7	2		T1	1		T8	3
all_values[0]	auto[0]	auto[1]	130630	1			T31	9695		T37	1077		T68	1668
all_values[0]	auto[1]	auto[0]	3620730	1			T1	2		T4	2		T2	12274
all_values[0]	auto[1]	auto[1]	451360	1			T31	5304		T37	23232		T68	84516
all_values[1]	auto[0]	auto[0]	5174882	1			T7	2		T1	3		T8	3
all_values[1]	auto[0]	auto[1]	540936	1			T31	14998		T37	24295		T68	86180
all_values[1]	auto[1]	auto[0]	1544	1			T31	24		T53	15		T194	41
all_values[1]	auto[1]	auto[1]	438	1			T31	2		T37	17		T68	6
all_values[2]	auto[0]	auto[0]	5115605	1			T7	2		T1	3		T8	3
all_values[2]	auto[0]	auto[1]	601990	1			T31	14998		T37	24307		T68	86182
all_values[2]	auto[1]	auto[1]	205	1			T31	2		T37	5		T68	4
all_values[3]	auto[0]	auto[0]	5296128	1			T7	2		T1	3		T8	3
all_values[3]	auto[0]	auto[1]	421426	1			T31	14994		T37	24302		T68	86182
all_values[3]	auto[1]	auto[1]	246	1			T31	6		T37	6		T68	4
all_values[4]	auto[0]	auto[0]	5119884	1			T7	2		T1	3		T8	3
all_values[4]	auto[0]	auto[1]	597580	1			T31	14992		T37	24305		T68	86177
all_values[4]	auto[1]	auto[0]	77	1			T34	24		T195	1		T157	52
all_values[4]	auto[1]	auto[1]	259	1			T31	8		T37	7		T68	9
all_values[5]	auto[0]	auto[0]	5299948	1			T7	2		T1	3		T8	3
all_values[5]	auto[0]	auto[1]	417007	1			T31	14992		T37	24308		T68	86180
all_values[5]	auto[1]	auto[0]	605	1			T28	605		-	-		-	-
all_values[5]	auto[1]	auto[1]	240	1			T31	8		T37	2		T68	6
all_values[6]	auto[0]	auto[0]	4486353	1			T7	2		T1	2		T8	2
all_values[6]	auto[0]	auto[1]	475240	1			T31	14952		T37	24272		T68	76881
all_values[6]	auto[1]	auto[0]	649464	1			T1	1		T8	1		T2	27
all_values[6]	auto[1]	auto[1]	106743	1			T31	47		T37	40		T68	9305
all_values[7]	auto[0]	auto[0]	5073833	1			T7	2		T1	2		T8	3
all_values[7]	auto[0]	auto[1]	371740	1			T31	14044		T37	22100		T68	81457
all_values[7]	auto[1]	auto[0]	244176	1			T1	1		T2	893		T3	104
all_values[7]	auto[1]	auto[1]	28051	1			T31	955		T37	2212		T68	4727
all_values[8]	auto[0]	auto[0]	4414494	1			T7	2		T1	2		T8	3
all_values[8]	auto[0]	auto[1]	475125	1			T31	14328		T37	23967		T68	75368
all_values[8]	auto[1]	auto[0]	701104	1			T1	1		T2	367		T3	3186
all_values[8]	auto[1]	auto[1]	127077	1			T31	671		T37	341		T68	10818
all_values[9]	auto[0]	auto[0]	4485306	1			T7	2		T1	2		T8	3
all_values[9]	auto[0]	auto[1]	488368	1			T31	14963		T37	24271		T68	75898
all_values[9]	auto[1]	auto[0]	630298	1			T1	1		T2	28		T3	3130
all_values[9]	auto[1]	auto[1]	113828	1			T31	35		T37	40		T68	10288
all_values[10]	auto[0]	auto[0]	5180809	1			T7	2		T1	3		T8	3
all_values[10]	auto[0]	auto[1]	536781	1			T31	14997		T37	24307		T68	86179
all_values[10]	auto[1]	auto[1]	210	1			T31	3		T37	4		T68	4
all_values[11]	auto[0]	auto[0]	2840	1			T7	2		T1	1		T8	3
all_values[11]	auto[0]	auto[1]	637	1			T31	11		T37	10		T68	36
all_values[11]	auto[1]	auto[0]	5112787	1			T1	2		T4	2		T2	12274
all_values[11]	auto[1]	auto[1]	601536	1			T31	14988		T37	24300		T68	86149
all_values[12]	auto[0]	auto[0]	5164177	1			T7	2		T1	3		T8	3
all_values[12]	auto[0]	auto[1]	553438	1			T31	14995		T37	24306		T68	86177
all_values[12]	auto[1]	auto[1]	185	1			T31	5		T37	3		T68	4
all_values[13]	auto[0]	auto[0]	5115597	1			T7	2		T1	3		T8	3
all_values[13]	auto[0]	auto[1]	601959	1			T31	14996		T37	24307		T68	86182
all_values[13]	auto[1]	auto[0]	12	1			T25	1		T26	1		T189	1
all_values[13]	auto[1]	auto[1]	232	1			T31	2		T37	4		T68	4
all_values[14]	auto[0]	auto[0]	5166350	1			T7	2		T1	3		T8	3
all_values[14]	auto[0]	auto[1]	551221	1			T31	14998		T37	24308		T68	86181
all_values[14]	auto[1]	auto[1]	229	1			T31	1		T37	2		T68	5