Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5717800	1			T7	2		T1	3		T8	3
all_pins[1]	5717800	1			T7	2		T1	3		T8	3
all_pins[2]	5717800	1			T7	2		T1	3		T8	3
all_pins[3]	5717800	1			T7	2		T1	3		T8	3
all_pins[4]	5717800	1			T7	2		T1	3		T8	3
all_pins[5]	5717800	1			T7	2		T1	3		T8	3
all_pins[6]	5717800	1			T7	2		T1	3		T8	3
all_pins[7]	5717800	1			T7	2		T1	3		T8	3
all_pins[8]	5717800	1			T7	2		T1	3		T8	3
all_pins[9]	5717800	1			T7	2		T1	3		T8	3
all_pins[10]	5717800	1			T7	2		T1	3		T8	3
all_pins[11]	5717800	1			T7	2		T1	3		T8	3
all_pins[12]	5717800	1			T7	2		T1	3		T8	3
all_pins[13]	5717800	1			T7	2		T1	3		T8	3
all_pins[14]	5717800	1			T7	2		T1	3		T8	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	73337133	1			T7	30		T1	37		T8	44
values[0x1]	12429867	1			T1	8		T8	1		T4	4
transitions[0x0=>0x1]	11633362	1			T1	5		T8	1		T4	4
transitions[0x1=>0x0]	11632451	1			T1	4		T8	1		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1645882	1			T7	2		T1	1		T8	3
all_pins[0]	values[0x1]	4071918	1			T1	2		T4	2		T2	12274
all_pins[0]	transitions[0x0=>0x1]	4069819	1			T1	2		T4	2		T2	12274
all_pins[0]	transitions[0x1=>0x0]	94	1			T37	1		T68	1		T13	3
all_pins[1]	values[0x0]	5715607	1			T7	2		T1	3		T8	3
all_pins[1]	values[0x1]	2193	1			T31	26		T53	17		T37	20
all_pins[1]	transitions[0x0=>0x1]	2172	1			T31	26		T53	17		T37	19
all_pins[1]	transitions[0x1=>0x0]	65	1			T37	2		T68	3		T13	3
all_pins[2]	values[0x0]	5717714	1			T7	2		T1	3		T8	3
all_pins[2]	values[0x1]	86	1			T37	3		T68	3		T13	5
all_pins[2]	transitions[0x0=>0x1]	62	1			T37	3		T68	2		T13	3
all_pins[2]	transitions[0x1=>0x0]	104	1			T31	5		T37	1		T68	2
all_pins[3]	values[0x0]	5717672	1			T7	2		T1	3		T8	3
all_pins[3]	values[0x1]	128	1			T31	5		T37	1		T68	3
all_pins[3]	transitions[0x0=>0x1]	92	1			T31	5		T68	1		T13	7
all_pins[3]	transitions[0x1=>0x0]	180	1			T31	2		T37	6		T68	1
all_pins[4]	values[0x0]	5717584	1			T7	2		T1	3		T8	3
all_pins[4]	values[0x1]	216	1			T31	2		T37	7		T68	3
all_pins[4]	transitions[0x0=>0x1]	185	1			T37	7		T68	1		T13	2
all_pins[4]	transitions[0x1=>0x0]	722	1			T31	4		T37	1		T68	1
all_pins[5]	values[0x0]	5717047	1			T7	2		T1	3		T8	3
all_pins[5]	values[0x1]	753	1			T31	6		T37	1		T68	3
all_pins[5]	transitions[0x0=>0x1]	724	1			T31	6		T37	1		T68	1
all_pins[5]	transitions[0x1=>0x0]	757193	1			T1	1		T8	1		T2	30
all_pins[6]	values[0x0]	4960578	1			T7	2		T1	2		T8	2
all_pins[6]	values[0x1]	757222	1			T1	1		T8	1		T2	30
all_pins[6]	transitions[0x0=>0x1]	738933	1			T8	1		T2	30		T3	3019
all_pins[6]	transitions[0x1=>0x0]	283129	1			T2	1042		T3	5		T52	3
all_pins[7]	values[0x0]	5416382	1			T7	2		T1	2		T8	3
all_pins[7]	values[0x1]	301418	1			T1	1		T2	1042		T3	116
all_pins[7]	transitions[0x0=>0x1]	265370	1			T2	955		T20	623		T31	2590
all_pins[7]	transitions[0x1=>0x0]	800808	1			T2	342		T3	3070		T11	1
all_pins[8]	values[0x0]	4880944	1			T7	2		T1	2		T8	3
all_pins[8]	values[0x1]	836856	1			T1	1		T2	429		T3	3186
all_pins[8]	transitions[0x0=>0x1]	97082	1			T2	429		T3	56		T52	24
all_pins[8]	transitions[0x1=>0x0]	4695	1			T2	30		T5	1		T12	2
all_pins[9]	values[0x0]	4973331	1			T7	2		T1	2		T8	3
all_pins[9]	values[0x1]	744469	1			T1	1		T2	30		T3	3130
all_pins[9]	transitions[0x0=>0x1]	744448	1			T1	1		T2	30		T3	3130
all_pins[9]	transitions[0x1=>0x0]	71	1			T31	1		T37	1		T68	2
all_pins[10]	values[0x0]	5717708	1			T7	2		T1	3		T8	3
all_pins[10]	values[0x1]	92	1			T31	1		T37	1		T68	4
all_pins[10]	transitions[0x0=>0x1]	70	1			T68	2		T13	8		T50	1
all_pins[10]	transitions[0x1=>0x0]	5714169	1			T1	2		T4	2		T2	12274
all_pins[11]	values[0x0]	3609	1			T7	2		T1	1		T8	3
all_pins[11]	values[0x1]	5714191	1			T1	2		T4	2		T2	12274
all_pins[11]	transitions[0x0=>0x1]	5714169	1			T1	2		T4	2		T2	12274
all_pins[11]	transitions[0x1=>0x0]	64	1			T31	2		T37	2		T50	3
all_pins[12]	values[0x0]	5717714	1			T7	2		T1	3		T8	3
all_pins[12]	values[0x1]	86	1			T31	3		T37	3		T68	1
all_pins[12]	transitions[0x0=>0x1]	67	1			T31	3		T37	3		T68	1
all_pins[12]	transitions[0x1=>0x0]	105	1			T25	1		T26	1		T37	2
all_pins[13]	values[0x0]	5717676	1			T7	2		T1	3		T8	3
all_pins[13]	values[0x1]	124	1			T25	1		T26	1		T37	2
all_pins[13]	transitions[0x0=>0x1]	98	1			T25	1		T26	1		T37	2
all_pins[13]	transitions[0x1=>0x0]	89	1			T31	1		T37	1		T68	1
all_pins[14]	values[0x0]	5717685	1			T7	2		T1	3		T8	3
all_pins[14]	values[0x1]	115	1			T31	1		T37	1		T68	1
all_pins[14]	transitions[0x0=>0x1]	71	1			T31	1		T13	2		T50	1
all_pins[14]	transitions[0x1=>0x0]	4070963	1			T1	1		T4	1		T2	12273