Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	500	1			T31	8		T37	11		T68	11
all_values[1]	500	1			T31	8		T37	11		T68	11
all_values[2]	500	1			T31	8		T37	11		T68	11
all_values[3]	500	1			T31	8		T37	11		T68	11
all_values[4]	500	1			T31	8		T37	11		T68	11
all_values[5]	500	1			T31	8		T37	11		T68	11
all_values[6]	500	1			T31	8		T37	11		T68	11
all_values[7]	500	1			T31	8		T37	11		T68	11
all_values[8]	500	1			T31	8		T37	11		T68	11
all_values[9]	500	1			T31	8		T37	11		T68	11
all_values[10]	500	1			T31	8		T37	11		T68	11
all_values[11]	500	1			T31	8		T37	11		T68	11
all_values[12]	500	1			T31	8		T37	11		T68	11
all_values[13]	500	1			T31	8		T37	11		T68	11
all_values[14]	500	1			T31	8		T37	11		T68	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3963

1

T31

57

T37

80

T68

87

auto[1]

3537

1

T31

63

T37

85

T68

78

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T31

10

T37

23

T68

13

auto[1]

6335

1

T31

110

T37

142

T68

152

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4457

1

T31

75

T37

107

T68

90

auto[1]

3043

1

T31

45

T37

58

T68

75

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	28	1			T31	1		T37	1		T68	1
all_values[0]	auto[0]	auto[0]	auto[1]	122	1			T31	2		T37	3		T68	2
all_values[0]	auto[0]	auto[1]	auto[0]	44	1			T37	2		T68	1		T206	1
all_values[0]	auto[0]	auto[1]	auto[1]	102	1			T31	1		T37	2		T68	1
all_values[0]	auto[1]	auto[0]	auto[1]	97	1			T31	1		T68	3		T13	7
all_values[0]	auto[1]	auto[1]	auto[1]	107	1			T31	3		T37	3		T68	3
all_values[1]	auto[0]	auto[0]	auto[0]	48	1			T206	1		T140	4		T142	2
all_values[1]	auto[0]	auto[0]	auto[1]	105	1			T31	4		T37	6		T68	5
all_values[1]	auto[0]	auto[1]	auto[0]	24	1			T13	2		T206	2		T200	1
all_values[1]	auto[0]	auto[1]	auto[1]	109	1			T31	2		T37	2		T13	4
all_values[1]	auto[1]	auto[0]	auto[1]	113	1			T31	2		T37	1		T68	4
all_values[1]	auto[1]	auto[1]	auto[1]	101	1			T37	2		T68	2		T13	9
all_values[2]	auto[0]	auto[0]	auto[0]	38	1			T142	1		T208	1		T35	2
all_values[2]	auto[0]	auto[0]	auto[1]	127	1			T31	1		T37	2		T68	5
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T50	1		T142	1		T200	1
all_values[2]	auto[0]	auto[1]	auto[1]	99	1			T31	5		T37	4		T68	2
all_values[2]	auto[1]	auto[0]	auto[1]	117	1			T31	2		T37	2		T68	1
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T37	3		T68	3		T13	7
all_values[3]	auto[0]	auto[0]	auto[0]	45	1			T37	2		T50	2		T140	3
all_values[3]	auto[0]	auto[0]	auto[1]	106	1			T31	1		T37	2		T68	4
all_values[3]	auto[0]	auto[1]	auto[0]	31	1			T37	2		T13	1		T206	1
all_values[3]	auto[0]	auto[1]	auto[1]	114	1			T31	3		T68	2		T13	5
all_values[3]	auto[1]	auto[0]	auto[1]	111	1			T31	1		T37	4		T68	2
all_values[3]	auto[1]	auto[1]	auto[1]	93	1			T31	3		T37	1		T68	3
all_values[4]	auto[0]	auto[0]	auto[0]	42	1			T212	1		T188	1		T144	1
all_values[4]	auto[0]	auto[0]	auto[1]	97	1			T31	3		T68	1		T13	9
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T13	1		T50	1		T140	4
all_values[4]	auto[0]	auto[1]	auto[1]	113	1			T37	6		T68	3		T13	6
all_values[4]	auto[1]	auto[0]	auto[1]	107	1			T31	3		T37	1		T68	5
all_values[4]	auto[1]	auto[1]	auto[1]	108	1			T31	2		T37	4		T68	2
all_values[5]	auto[0]	auto[0]	auto[0]	36	1			T37	1		T13	1		T206	1
all_values[5]	auto[0]	auto[0]	auto[1]	117	1			T31	1		T37	4		T68	5
all_values[5]	auto[0]	auto[1]	auto[0]	34	1			T37	1		T13	4		T50	2
all_values[5]	auto[0]	auto[1]	auto[1]	105	1			T31	2		T37	4		T68	1
all_values[5]	auto[1]	auto[0]	auto[1]	115	1			T68	2		T13	7		T50	2
all_values[5]	auto[1]	auto[1]	auto[1]	93	1			T31	5		T37	1		T68	3
all_values[6]	auto[0]	auto[0]	auto[0]	44	1			T31	1		T50	1		T213	1
all_values[6]	auto[0]	auto[0]	auto[1]	113	1			T31	4		T37	2		T68	3
all_values[6]	auto[0]	auto[1]	auto[0]	35	1			T50	1		T206	1		T213	2
all_values[6]	auto[0]	auto[1]	auto[1]	113	1			T31	1		T37	5		T68	3
all_values[6]	auto[1]	auto[0]	auto[1]	104	1			T31	2		T37	1		T68	2
all_values[6]	auto[1]	auto[1]	auto[1]	91	1			T37	3		T68	3		T13	7
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T31	1		T68	1		T140	2
all_values[7]	auto[0]	auto[0]	auto[1]	116	1			T31	3		T37	2		T68	5
all_values[7]	auto[0]	auto[1]	auto[0]	40	1			T68	1		T206	1		T213	1
all_values[7]	auto[0]	auto[1]	auto[1]	88	1			T31	2		T37	3		T13	11
all_values[7]	auto[1]	auto[0]	auto[1]	116	1			T31	1		T37	3		T68	2
all_values[7]	auto[1]	auto[1]	auto[1]	99	1			T31	1		T37	3		T68	2
all_values[8]	auto[0]	auto[0]	auto[0]	43	1			T37	4		T13	1		T50	1
all_values[8]	auto[0]	auto[0]	auto[1]	110	1			T31	2		T37	2		T68	3
all_values[8]	auto[0]	auto[1]	auto[0]	20	1			T31	1		T13	1		T213	2
all_values[8]	auto[0]	auto[1]	auto[1]	121	1			T31	1		T37	1		T68	4
all_values[8]	auto[1]	auto[0]	auto[1]	114	1			T31	2		T37	1		T68	1
all_values[8]	auto[1]	auto[1]	auto[1]	92	1			T31	2		T37	3		T68	3
all_values[9]	auto[0]	auto[0]	auto[0]	43	1			T37	1		T50	1		T208	1
all_values[9]	auto[0]	auto[0]	auto[1]	123	1			T31	3		T37	2		T68	1
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T31	2		T213	1		T140	1
all_values[9]	auto[0]	auto[1]	auto[1]	108	1			T37	5		T68	4		T13	4
all_values[9]	auto[1]	auto[0]	auto[1]	121	1			T31	2		T37	3		T68	4
all_values[9]	auto[1]	auto[1]	auto[1]	82	1			T31	1		T68	2		T13	7
all_values[10]	auto[0]	auto[0]	auto[0]	48	1			T37	1		T68	1		T140	1
all_values[10]	auto[0]	auto[0]	auto[1]	98	1			T31	3		T37	1		T13	5
all_values[10]	auto[0]	auto[1]	auto[0]	40	1			T68	2		T213	1		T140	3
all_values[10]	auto[0]	auto[1]	auto[1]	104	1			T31	2		T37	5		T68	4
all_values[10]	auto[1]	auto[0]	auto[1]	123	1			T31	1		T37	3		T68	1
all_values[10]	auto[1]	auto[1]	auto[1]	87	1			T31	2		T37	1		T68	3
all_values[11]	auto[0]	auto[0]	auto[0]	47	1			T37	2		T213	1		T208	3
all_values[11]	auto[0]	auto[0]	auto[1]	107	1			T31	1		T37	3		T68	1
all_values[11]	auto[0]	auto[1]	auto[0]	42	1			T31	1		T68	1		T213	4
all_values[11]	auto[0]	auto[1]	auto[1]	109	1			T31	4		T37	2		T68	3
all_values[11]	auto[1]	auto[0]	auto[1]	108	1			T31	1		T37	3		T68	3
all_values[11]	auto[1]	auto[1]	auto[1]	87	1			T31	1		T37	1		T68	3
all_values[12]	auto[0]	auto[0]	auto[0]	51	1			T37	3		T68	1		T50	3
all_values[12]	auto[0]	auto[0]	auto[1]	103	1			T31	2		T68	1		T13	7
all_values[12]	auto[0]	auto[1]	auto[0]	41	1			T68	4		T50	1		T206	1
all_values[12]	auto[0]	auto[1]	auto[1]	120	1			T31	1		T37	5		T68	1
all_values[12]	auto[1]	auto[0]	auto[1]	99	1			T31	1		T68	3		T13	6
all_values[12]	auto[1]	auto[1]	auto[1]	86	1			T31	4		T37	3		T68	1
all_values[13]	auto[0]	auto[0]	auto[0]	46	1			T37	1		T50	1		T140	2
all_values[13]	auto[0]	auto[0]	auto[1]	117	1			T31	2		T37	4		T68	3
all_values[13]	auto[0]	auto[1]	auto[0]	26	1			T31	2		T13	1		T206	1
all_values[13]	auto[0]	auto[1]	auto[1]	119	1			T31	3		T37	1		T68	3
all_values[13]	auto[1]	auto[0]	auto[1]	112	1			T31	1		T37	2		T68	4
all_values[13]	auto[1]	auto[1]	auto[1]	80	1			T37	3		T68	1		T13	6
all_values[14]	auto[0]	auto[0]	auto[0]	47	1			T31	1		T37	2		T213	1
all_values[14]	auto[0]	auto[0]	auto[1]	101	1			T37	2		T68	5		T13	12
all_values[14]	auto[0]	auto[1]	auto[0]	54	1			T50	1		T206	2		T213	4
all_values[14]	auto[0]	auto[1]	auto[1]	106	1			T31	6		T37	4		T68	2
all_values[14]	auto[1]	auto[0]	auto[1]	97	1			T31	1		T37	3		T68	2
all_values[14]	auto[1]	auto[1]	auto[1]	95	1			T68	2		T13	5		T50	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal