| T1061 |
/workspace/coverage/default/0.i2c_alert_test.357618362 |
|
|
Mar 19 12:56:32 PM PDT 24 |
Mar 19 12:56:33 PM PDT 24 |
14051536 ps |
| T1062 |
/workspace/coverage/default/15.i2c_host_mode_toggle.53957520 |
|
|
Mar 19 12:57:31 PM PDT 24 |
Mar 19 12:58:39 PM PDT 24 |
6555943238 ps |
| T1063 |
/workspace/coverage/default/39.i2c_host_stress_all.1137484914 |
|
|
Mar 19 12:59:40 PM PDT 24 |
Mar 19 01:50:32 PM PDT 24 |
11946778392 ps |
| T1064 |
/workspace/coverage/default/12.i2c_target_timeout.1992311108 |
|
|
Mar 19 12:57:17 PM PDT 24 |
Mar 19 12:57:25 PM PDT 24 |
3037564716 ps |
| T1065 |
/workspace/coverage/default/26.i2c_target_bad_addr.1346710548 |
|
|
Mar 19 12:58:27 PM PDT 24 |
Mar 19 12:58:33 PM PDT 24 |
1488025632 ps |
| T1066 |
/workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3215151609 |
|
|
Mar 19 12:59:42 PM PDT 24 |
Mar 19 12:59:54 PM PDT 24 |
219498095 ps |
| T1067 |
/workspace/coverage/default/34.i2c_target_hrst.1533813390 |
|
|
Mar 19 12:59:21 PM PDT 24 |
Mar 19 12:59:23 PM PDT 24 |
879890511 ps |
| T1068 |
/workspace/coverage/default/16.i2c_host_fifo_reset_rx.3373741305 |
|
|
Mar 19 12:57:27 PM PDT 24 |
Mar 19 12:57:36 PM PDT 24 |
166317913 ps |
| T1069 |
/workspace/coverage/default/35.i2c_host_fifo_reset_fmt.1530895886 |
|
|
Mar 19 12:59:17 PM PDT 24 |
Mar 19 12:59:19 PM PDT 24 |
2259371737 ps |
| T1070 |
/workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3454114191 |
|
|
Mar 19 12:59:02 PM PDT 24 |
Mar 19 12:59:11 PM PDT 24 |
510151048 ps |
| T1071 |
/workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1372345727 |
|
|
Mar 19 12:57:07 PM PDT 24 |
Mar 19 12:57:10 PM PDT 24 |
106101279 ps |
| T1072 |
/workspace/coverage/default/1.i2c_host_fifo_reset_rx.62925153 |
|
|
Mar 19 12:56:27 PM PDT 24 |
Mar 19 12:56:38 PM PDT 24 |
725183126 ps |
| T1073 |
/workspace/coverage/default/21.i2c_target_stress_wr.1388848804 |
|
|
Mar 19 12:58:08 PM PDT 24 |
Mar 19 12:58:16 PM PDT 24 |
11345970234 ps |
| T1074 |
/workspace/coverage/default/7.i2c_host_perf.3018861364 |
|
|
Mar 19 12:56:53 PM PDT 24 |
Mar 19 12:57:40 PM PDT 24 |
8437114346 ps |
| T1075 |
/workspace/coverage/default/1.i2c_host_stretch_timeout.305830228 |
|
|
Mar 19 12:56:34 PM PDT 24 |
Mar 19 12:57:23 PM PDT 24 |
1106228655 ps |
| T54 |
/workspace/coverage/default/31.i2c_target_unexp_stop.3354097015 |
|
|
Mar 19 12:58:56 PM PDT 24 |
Mar 19 12:59:02 PM PDT 24 |
1249615955 ps |
| T1076 |
/workspace/coverage/default/49.i2c_host_fifo_overflow.2132742445 |
|
|
Mar 19 01:00:37 PM PDT 24 |
Mar 19 01:02:25 PM PDT 24 |
12957017204 ps |
| T1077 |
/workspace/coverage/default/8.i2c_host_perf.2476649557 |
|
|
Mar 19 12:57:10 PM PDT 24 |
Mar 19 01:02:17 PM PDT 24 |
12455606171 ps |
| T1078 |
/workspace/coverage/default/12.i2c_host_fifo_full.462091589 |
|
|
Mar 19 12:57:09 PM PDT 24 |
Mar 19 12:58:33 PM PDT 24 |
2456293951 ps |
| T1079 |
/workspace/coverage/default/14.i2c_host_fifo_overflow.244034152 |
|
|
Mar 19 12:57:21 PM PDT 24 |
Mar 19 12:58:55 PM PDT 24 |
12198554488 ps |
| T1080 |
/workspace/coverage/default/43.i2c_host_stretch_timeout.1048788271 |
|
|
Mar 19 01:00:02 PM PDT 24 |
Mar 19 01:00:17 PM PDT 24 |
955305408 ps |
| T1081 |
/workspace/coverage/default/33.i2c_target_stress_rd.2488457865 |
|
|
Mar 19 12:59:05 PM PDT 24 |
Mar 19 12:59:11 PM PDT 24 |
1301450425 ps |
| T1082 |
/workspace/coverage/default/41.i2c_host_mode_toggle.444949469 |
|
|
Mar 19 12:59:54 PM PDT 24 |
Mar 19 01:01:55 PM PDT 24 |
2317873720 ps |
| T1083 |
/workspace/coverage/default/10.i2c_target_unexp_stop.1371572294 |
|
|
Mar 19 12:57:15 PM PDT 24 |
Mar 19 12:57:20 PM PDT 24 |
801787371 ps |
| T1084 |
/workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1347304354 |
|
|
Mar 19 12:58:24 PM PDT 24 |
Mar 19 12:58:25 PM PDT 24 |
125520803 ps |
| T1085 |
/workspace/coverage/default/2.i2c_target_stress_all.1086232737 |
|
|
Mar 19 12:56:33 PM PDT 24 |
Mar 19 12:57:30 PM PDT 24 |
10462684325 ps |
| T1086 |
/workspace/coverage/default/46.i2c_target_perf.4116546149 |
|
|
Mar 19 01:00:26 PM PDT 24 |
Mar 19 01:00:30 PM PDT 24 |
540535560 ps |
| T1087 |
/workspace/coverage/default/30.i2c_target_stretch.2754744404 |
|
|
Mar 19 12:58:47 PM PDT 24 |
Mar 19 01:07:57 PM PDT 24 |
12719650357 ps |
| T216 |
/workspace/coverage/default/42.i2c_target_fifo_reset_acq.1420972516 |
|
|
Mar 19 01:00:03 PM PDT 24 |
Mar 19 01:01:11 PM PDT 24 |
10079752827 ps |
| T1088 |
/workspace/coverage/default/21.i2c_target_intr_stress_wr.1875366256 |
|
|
Mar 19 12:58:07 PM PDT 24 |
Mar 19 12:58:13 PM PDT 24 |
2450880306 ps |
| T1089 |
/workspace/coverage/default/35.i2c_target_fifo_reset_acq.2339572524 |
|
|
Mar 19 12:59:25 PM PDT 24 |
Mar 19 12:59:55 PM PDT 24 |
10065369828 ps |
| T1090 |
/workspace/coverage/default/25.i2c_host_fifo_reset_fmt.740089753 |
|
|
Mar 19 12:58:22 PM PDT 24 |
Mar 19 12:58:23 PM PDT 24 |
226409534 ps |
| T1091 |
/workspace/coverage/default/49.i2c_host_fifo_fmt_empty.620111642 |
|
|
Mar 19 01:00:39 PM PDT 24 |
Mar 19 01:00:57 PM PDT 24 |
345883710 ps |
| T1092 |
/workspace/coverage/default/23.i2c_host_fifo_full.489652488 |
|
|
Mar 19 12:58:13 PM PDT 24 |
Mar 19 12:59:57 PM PDT 24 |
20947854578 ps |
| T1093 |
/workspace/coverage/default/30.i2c_host_mode_toggle.1694394171 |
|
|
Mar 19 12:58:49 PM PDT 24 |
Mar 19 12:59:13 PM PDT 24 |
1315701196 ps |
| T1094 |
/workspace/coverage/default/40.i2c_host_stress_all.96289684 |
|
|
Mar 19 12:59:50 PM PDT 24 |
Mar 19 01:10:22 PM PDT 24 |
18020251460 ps |
| T1095 |
/workspace/coverage/default/37.i2c_host_perf.1708994827 |
|
|
Mar 19 12:59:37 PM PDT 24 |
Mar 19 01:03:43 PM PDT 24 |
25378447422 ps |
| T1096 |
/workspace/coverage/default/20.i2c_target_timeout.4244029024 |
|
|
Mar 19 12:57:56 PM PDT 24 |
Mar 19 12:58:03 PM PDT 24 |
1481985797 ps |
| T1097 |
/workspace/coverage/default/23.i2c_host_error_intr.3907452669 |
|
|
Mar 19 12:58:15 PM PDT 24 |
Mar 19 12:58:17 PM PDT 24 |
447771364 ps |
| T1098 |
/workspace/coverage/default/22.i2c_host_fifo_reset_rx.1592109532 |
|
|
Mar 19 12:58:08 PM PDT 24 |
Mar 19 12:58:20 PM PDT 24 |
443081435 ps |
| T1099 |
/workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2463729241 |
|
|
Mar 19 01:00:22 PM PDT 24 |
Mar 19 01:00:24 PM PDT 24 |
462369347 ps |
| T1100 |
/workspace/coverage/default/37.i2c_target_fifo_reset_acq.3527916707 |
|
|
Mar 19 12:59:33 PM PDT 24 |
Mar 19 12:59:46 PM PDT 24 |
10122411935 ps |
| T203 |
/workspace/coverage/default/1.i2c_host_stress_all.3618690239 |
|
|
Mar 19 12:56:25 PM PDT 24 |
Mar 19 01:26:03 PM PDT 24 |
16337149137 ps |
| T1101 |
/workspace/coverage/default/49.i2c_host_error_intr.3565977886 |
|
|
Mar 19 01:00:39 PM PDT 24 |
Mar 19 01:00:41 PM PDT 24 |
127207257 ps |
| T1102 |
/workspace/coverage/default/25.i2c_host_fifo_overflow.2203783263 |
|
|
Mar 19 12:58:19 PM PDT 24 |
Mar 19 12:59:53 PM PDT 24 |
1442358258 ps |
| T1103 |
/workspace/coverage/default/14.i2c_target_hrst.2460385253 |
|
|
Mar 19 12:57:30 PM PDT 24 |
Mar 19 12:57:34 PM PDT 24 |
903035723 ps |
| T1104 |
/workspace/coverage/default/16.i2c_target_perf.1050556250 |
|
|
Mar 19 12:57:37 PM PDT 24 |
Mar 19 12:57:41 PM PDT 24 |
5609706817 ps |
| T1105 |
/workspace/coverage/default/38.i2c_host_mode_toggle.1633314541 |
|
|
Mar 19 12:59:40 PM PDT 24 |
Mar 19 01:02:20 PM PDT 24 |
22462625739 ps |
| T1106 |
/workspace/coverage/default/49.i2c_alert_test.180434608 |
|
|
Mar 19 01:00:44 PM PDT 24 |
Mar 19 01:00:44 PM PDT 24 |
21937845 ps |
| T1107 |
/workspace/coverage/default/40.i2c_host_fifo_full.2711186789 |
|
|
Mar 19 12:59:50 PM PDT 24 |
Mar 19 01:03:45 PM PDT 24 |
6141260990 ps |
| T1108 |
/workspace/coverage/default/2.i2c_target_hrst.663741947 |
|
|
Mar 19 12:56:39 PM PDT 24 |
Mar 19 12:56:42 PM PDT 24 |
526987718 ps |
| T1109 |
/workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1662252729 |
|
|
Mar 19 12:57:45 PM PDT 24 |
Mar 19 12:57:56 PM PDT 24 |
1000362170 ps |
| T1110 |
/workspace/coverage/default/44.i2c_host_fifo_full.3099170936 |
|
|
Mar 19 01:00:11 PM PDT 24 |
Mar 19 01:03:28 PM PDT 24 |
10544157283 ps |
| T1111 |
/workspace/coverage/default/0.i2c_host_fifo_full.2441999178 |
|
|
Mar 19 12:56:26 PM PDT 24 |
Mar 19 12:59:32 PM PDT 24 |
12101755655 ps |
| T1112 |
/workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1962434160 |
|
|
Mar 19 12:59:48 PM PDT 24 |
Mar 19 12:59:53 PM PDT 24 |
1737314162 ps |
| T1113 |
/workspace/coverage/default/45.i2c_host_fifo_watermark.273587232 |
|
|
Mar 19 01:00:15 PM PDT 24 |
Mar 19 01:01:20 PM PDT 24 |
3086070118 ps |
| T1114 |
/workspace/coverage/default/8.i2c_host_fifo_overflow.2227154869 |
|
|
Mar 19 12:57:00 PM PDT 24 |
Mar 19 12:59:11 PM PDT 24 |
7285961760 ps |
| T1115 |
/workspace/coverage/default/39.i2c_target_stress_rd.1085011894 |
|
|
Mar 19 12:59:40 PM PDT 24 |
Mar 19 12:59:58 PM PDT 24 |
1642645654 ps |
| T1116 |
/workspace/coverage/default/38.i2c_target_perf.1250032990 |
|
|
Mar 19 12:59:40 PM PDT 24 |
Mar 19 12:59:44 PM PDT 24 |
2952276222 ps |
| T1117 |
/workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3062836718 |
|
|
Mar 19 12:57:03 PM PDT 24 |
Mar 19 12:57:20 PM PDT 24 |
1458159057 ps |
| T1118 |
/workspace/coverage/default/42.i2c_host_override.1622609875 |
|
|
Mar 19 12:59:54 PM PDT 24 |
Mar 19 12:59:55 PM PDT 24 |
25733642 ps |
| T1119 |
/workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3388904447 |
|
|
Mar 19 12:58:57 PM PDT 24 |
Mar 19 12:58:59 PM PDT 24 |
2484194690 ps |
| T1120 |
/workspace/coverage/default/20.i2c_host_fifo_overflow.3087942445 |
|
|
Mar 19 12:57:56 PM PDT 24 |
Mar 19 01:01:01 PM PDT 24 |
2504242120 ps |
| T1121 |
/workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2708865369 |
|
|
Mar 19 12:57:15 PM PDT 24 |
Mar 19 12:57:29 PM PDT 24 |
3485415693 ps |
| T1122 |
/workspace/coverage/default/28.i2c_host_error_intr.22690928 |
|
|
Mar 19 12:58:37 PM PDT 24 |
Mar 19 12:58:39 PM PDT 24 |
45682357 ps |
| T1123 |
/workspace/coverage/default/5.i2c_target_fifo_reset_acq.3170053546 |
|
|
Mar 19 12:56:47 PM PDT 24 |
Mar 19 12:57:47 PM PDT 24 |
10073862218 ps |
| T1124 |
/workspace/coverage/default/6.i2c_host_stress_all.1964322838 |
|
|
Mar 19 12:56:54 PM PDT 24 |
Mar 19 01:01:19 PM PDT 24 |
39268642628 ps |
| T1125 |
/workspace/coverage/default/2.i2c_target_intr_smoke.2914454803 |
|
|
Mar 19 12:56:40 PM PDT 24 |
Mar 19 12:56:44 PM PDT 24 |
744046281 ps |
| T1126 |
/workspace/coverage/default/30.i2c_target_timeout.2052437295 |
|
|
Mar 19 12:58:47 PM PDT 24 |
Mar 19 12:58:54 PM PDT 24 |
6938070173 ps |
| T1127 |
/workspace/coverage/default/5.i2c_host_fifo_full.3303747884 |
|
|
Mar 19 12:56:40 PM PDT 24 |
Mar 19 12:58:29 PM PDT 24 |
25288503498 ps |
| T1128 |
/workspace/coverage/default/33.i2c_host_fifo_full.1497853306 |
|
|
Mar 19 12:59:04 PM PDT 24 |
Mar 19 01:00:19 PM PDT 24 |
9395038338 ps |
| T1129 |
/workspace/coverage/default/23.i2c_target_timeout.4261383451 |
|
|
Mar 19 12:58:11 PM PDT 24 |
Mar 19 12:58:18 PM PDT 24 |
9900431119 ps |
| T1130 |
/workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3705873293 |
|
|
Mar 19 12:59:25 PM PDT 24 |
Mar 19 12:59:27 PM PDT 24 |
160591756 ps |
| T1131 |
/workspace/coverage/default/26.i2c_target_stress_rd.1905050158 |
|
|
Mar 19 12:58:32 PM PDT 24 |
Mar 19 12:59:30 PM PDT 24 |
1481266400 ps |
| T1132 |
/workspace/coverage/default/49.i2c_host_smoke.953564839 |
|
|
Mar 19 01:00:36 PM PDT 24 |
Mar 19 01:01:50 PM PDT 24 |
8699958064 ps |
| T1133 |
/workspace/coverage/default/29.i2c_host_smoke.2516788218 |
|
|
Mar 19 12:58:40 PM PDT 24 |
Mar 19 12:59:15 PM PDT 24 |
2935270070 ps |
| T1134 |
/workspace/coverage/default/28.i2c_target_perf.2865649328 |
|
|
Mar 19 12:58:41 PM PDT 24 |
Mar 19 12:58:44 PM PDT 24 |
2638628592 ps |
| T202 |
/workspace/coverage/default/28.i2c_host_stretch_timeout.1044118295 |
|
|
Mar 19 12:58:37 PM PDT 24 |
Mar 19 12:59:03 PM PDT 24 |
4100899022 ps |
| T1135 |
/workspace/coverage/default/35.i2c_target_timeout.2212665662 |
|
|
Mar 19 12:59:20 PM PDT 24 |
Mar 19 12:59:29 PM PDT 24 |
42884434974 ps |
| T1136 |
/workspace/coverage/default/31.i2c_host_override.3197917417 |
|
|
Mar 19 12:58:59 PM PDT 24 |
Mar 19 12:59:00 PM PDT 24 |
19711451 ps |
| T1137 |
/workspace/coverage/default/37.i2c_target_hrst.1914355539 |
|
|
Mar 19 12:59:34 PM PDT 24 |
Mar 19 12:59:37 PM PDT 24 |
1631221823 ps |
| T1138 |
/workspace/coverage/default/15.i2c_host_fifo_full.1427231904 |
|
|
Mar 19 12:57:28 PM PDT 24 |
Mar 19 12:59:27 PM PDT 24 |
44456569003 ps |
| T1139 |
/workspace/coverage/default/5.i2c_host_fifo_overflow.1379004080 |
|
|
Mar 19 12:56:53 PM PDT 24 |
Mar 19 12:58:29 PM PDT 24 |
2556447421 ps |
| T1140 |
/workspace/coverage/default/35.i2c_host_mode_toggle.550100283 |
|
|
Mar 19 12:59:25 PM PDT 24 |
Mar 19 01:00:32 PM PDT 24 |
1188747021 ps |
| T1141 |
/workspace/coverage/default/29.i2c_host_override.2729315817 |
|
|
Mar 19 12:58:39 PM PDT 24 |
Mar 19 12:58:41 PM PDT 24 |
19728703 ps |
| T156 |
/workspace/coverage/default/37.i2c_host_stress_all.2817255593 |
|
|
Mar 19 12:59:31 PM PDT 24 |
Mar 19 01:01:26 PM PDT 24 |
4267469077 ps |
| T1142 |
/workspace/coverage/default/17.i2c_target_unexp_stop.1525001127 |
|
|
Mar 19 12:57:48 PM PDT 24 |
Mar 19 12:57:56 PM PDT 24 |
7690739094 ps |
| T1143 |
/workspace/coverage/default/7.i2c_host_mode_toggle.3368756405 |
|
|
Mar 19 12:57:02 PM PDT 24 |
Mar 19 12:57:42 PM PDT 24 |
8087575680 ps |
| T1144 |
/workspace/coverage/default/13.i2c_host_perf.457777064 |
|
|
Mar 19 12:57:15 PM PDT 24 |
Mar 19 01:05:39 PM PDT 24 |
74381968124 ps |
| T1145 |
/workspace/coverage/default/33.i2c_host_fifo_reset_fmt.225762643 |
|
|
Mar 19 12:59:02 PM PDT 24 |
Mar 19 12:59:04 PM PDT 24 |
216150110 ps |
| T1146 |
/workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3514135676 |
|
|
Mar 19 12:58:14 PM PDT 24 |
Mar 19 12:58:38 PM PDT 24 |
445952414 ps |
| T1147 |
/workspace/coverage/default/14.i2c_alert_test.2342901147 |
|
|
Mar 19 12:57:29 PM PDT 24 |
Mar 19 12:57:30 PM PDT 24 |
113675058 ps |
| T1148 |
/workspace/coverage/default/48.i2c_target_perf.2976798354 |
|
|
Mar 19 01:00:35 PM PDT 24 |
Mar 19 01:00:38 PM PDT 24 |
484195135 ps |
| T1149 |
/workspace/coverage/default/25.i2c_host_smoke.1730831430 |
|
|
Mar 19 12:58:21 PM PDT 24 |
Mar 19 12:59:15 PM PDT 24 |
2138143856 ps |
| T1150 |
/workspace/coverage/default/2.i2c_host_error_intr.4125181615 |
|
|
Mar 19 12:56:32 PM PDT 24 |
Mar 19 12:56:33 PM PDT 24 |
121798816 ps |
| T1151 |
/workspace/coverage/default/44.i2c_host_fifo_overflow.2314108329 |
|
|
Mar 19 01:00:10 PM PDT 24 |
Mar 19 01:00:50 PM PDT 24 |
2900299303 ps |
| T1152 |
/workspace/coverage/default/23.i2c_target_fifo_reset_acq.173617407 |
|
|
Mar 19 12:58:15 PM PDT 24 |
Mar 19 12:58:19 PM PDT 24 |
10494669543 ps |
| T1153 |
/workspace/coverage/default/34.i2c_host_stretch_timeout.2582193429 |
|
|
Mar 19 12:59:11 PM PDT 24 |
Mar 19 12:59:28 PM PDT 24 |
405818219 ps |
| T1154 |
/workspace/coverage/default/40.i2c_target_fifo_reset_tx.3021811881 |
|
|
Mar 19 12:59:51 PM PDT 24 |
Mar 19 01:00:07 PM PDT 24 |
10152296434 ps |
| T1155 |
/workspace/coverage/default/28.i2c_host_perf.3758164781 |
|
|
Mar 19 12:58:36 PM PDT 24 |
Mar 19 01:00:36 PM PDT 24 |
5065195249 ps |
| T1156 |
/workspace/coverage/default/36.i2c_target_timeout.3861930786 |
|
|
Mar 19 12:59:23 PM PDT 24 |
Mar 19 12:59:31 PM PDT 24 |
2844953119 ps |
| T1157 |
/workspace/coverage/default/12.i2c_host_mode_toggle.4122650219 |
|
|
Mar 19 12:57:14 PM PDT 24 |
Mar 19 12:58:07 PM PDT 24 |
8480576504 ps |
| T157 |
/workspace/coverage/default/27.i2c_host_stress_all.2198889259 |
|
|
Mar 19 12:58:34 PM PDT 24 |
Mar 19 01:08:30 PM PDT 24 |
64276703707 ps |
| T1158 |
/workspace/coverage/default/39.i2c_target_bad_addr.4039284797 |
|
|
Mar 19 12:59:50 PM PDT 24 |
Mar 19 12:59:55 PM PDT 24 |
1088655843 ps |
| T1159 |
/workspace/coverage/default/39.i2c_target_stress_wr.707898168 |
|
|
Mar 19 12:59:44 PM PDT 24 |
Mar 19 01:00:35 PM PDT 24 |
22132873570 ps |
| T1160 |
/workspace/coverage/default/39.i2c_host_fifo_reset_rx.1869570012 |
|
|
Mar 19 12:59:40 PM PDT 24 |
Mar 19 12:59:44 PM PDT 24 |
259309488 ps |
| T1161 |
/workspace/coverage/default/21.i2c_target_fifo_reset_acq.1274173610 |
|
|
Mar 19 12:58:07 PM PDT 24 |
Mar 19 12:59:18 PM PDT 24 |
10026161640 ps |
| T1162 |
/workspace/coverage/default/47.i2c_host_fifo_reset_rx.1948801013 |
|
|
Mar 19 01:00:30 PM PDT 24 |
Mar 19 01:00:37 PM PDT 24 |
424656667 ps |
| T1163 |
/workspace/coverage/default/26.i2c_host_smoke.3293526840 |
|
|
Mar 19 12:58:27 PM PDT 24 |
Mar 19 12:58:52 PM PDT 24 |
1187764861 ps |
| T1164 |
/workspace/coverage/default/37.i2c_host_mode_toggle.3510685418 |
|
|
Mar 19 12:59:34 PM PDT 24 |
Mar 19 12:59:55 PM PDT 24 |
1367853359 ps |
| T1165 |
/workspace/coverage/default/24.i2c_target_bad_addr.3978667368 |
|
|
Mar 19 12:58:19 PM PDT 24 |
Mar 19 12:58:23 PM PDT 24 |
5545119939 ps |
| T1166 |
/workspace/coverage/default/19.i2c_host_mode_toggle.1624918778 |
|
|
Mar 19 12:57:54 PM PDT 24 |
Mar 19 12:58:23 PM PDT 24 |
1460715115 ps |
| T1167 |
/workspace/coverage/default/25.i2c_host_perf.324400661 |
|
|
Mar 19 12:58:19 PM PDT 24 |
Mar 19 12:58:23 PM PDT 24 |
713804615 ps |
| T1168 |
/workspace/coverage/default/0.i2c_host_stretch_timeout.1683815987 |
|
|
Mar 19 12:56:29 PM PDT 24 |
Mar 19 12:56:53 PM PDT 24 |
3824369897 ps |
| T1169 |
/workspace/coverage/default/42.i2c_target_timeout.1926229291 |
|
|
Mar 19 12:59:54 PM PDT 24 |
Mar 19 01:00:00 PM PDT 24 |
5124406290 ps |
| T1170 |
/workspace/coverage/default/30.i2c_host_smoke.3927222742 |
|
|
Mar 19 12:58:46 PM PDT 24 |
Mar 19 12:59:34 PM PDT 24 |
2356861389 ps |
| T1171 |
/workspace/coverage/default/24.i2c_target_stress_wr.4011648717 |
|
|
Mar 19 12:58:17 PM PDT 24 |
Mar 19 12:58:26 PM PDT 24 |
14545866016 ps |
| T1172 |
/workspace/coverage/default/22.i2c_host_smoke.320084794 |
|
|
Mar 19 12:58:02 PM PDT 24 |
Mar 19 12:58:50 PM PDT 24 |
10306550154 ps |
| T1173 |
/workspace/coverage/default/33.i2c_target_perf.632515128 |
|
|
Mar 19 12:59:11 PM PDT 24 |
Mar 19 12:59:15 PM PDT 24 |
531688126 ps |
| T1174 |
/workspace/coverage/default/12.i2c_target_unexp_stop.1363811044 |
|
|
Mar 19 12:57:21 PM PDT 24 |
Mar 19 12:57:30 PM PDT 24 |
3862662265 ps |
| T1175 |
/workspace/coverage/default/8.i2c_target_stress_rd.3978530169 |
|
|
Mar 19 12:57:07 PM PDT 24 |
Mar 19 12:57:13 PM PDT 24 |
392716933 ps |
| T1176 |
/workspace/coverage/default/36.i2c_alert_test.3190555141 |
|
|
Mar 19 12:59:24 PM PDT 24 |
Mar 19 12:59:26 PM PDT 24 |
17998795 ps |
| T1177 |
/workspace/coverage/default/38.i2c_target_bad_addr.2193993631 |
|
|
Mar 19 12:59:40 PM PDT 24 |
Mar 19 12:59:44 PM PDT 24 |
3428718178 ps |
| T1178 |
/workspace/coverage/default/15.i2c_host_error_intr.3722505518 |
|
|
Mar 19 12:57:30 PM PDT 24 |
Mar 19 12:57:33 PM PDT 24 |
88692348 ps |
| T1179 |
/workspace/coverage/default/26.i2c_target_intr_smoke.2113505496 |
|
|
Mar 19 12:58:31 PM PDT 24 |
Mar 19 12:58:36 PM PDT 24 |
2995487135 ps |
| T1180 |
/workspace/coverage/default/21.i2c_host_fifo_reset_rx.979580435 |
|
|
Mar 19 12:58:08 PM PDT 24 |
Mar 19 12:58:17 PM PDT 24 |
583596816 ps |
| T1181 |
/workspace/coverage/default/14.i2c_target_timeout.574190929 |
|
|
Mar 19 12:57:31 PM PDT 24 |
Mar 19 12:57:38 PM PDT 24 |
9955173275 ps |
| T1182 |
/workspace/coverage/default/9.i2c_host_mode_toggle.220582433 |
|
|
Mar 19 12:57:02 PM PDT 24 |
Mar 19 12:57:53 PM PDT 24 |
4041201468 ps |
| T1183 |
/workspace/coverage/default/17.i2c_target_perf.3280592587 |
|
|
Mar 19 12:57:43 PM PDT 24 |
Mar 19 12:57:48 PM PDT 24 |
1452744839 ps |
| T1184 |
/workspace/coverage/default/49.i2c_target_fifo_reset_acq.3826997958 |
|
|
Mar 19 01:00:37 PM PDT 24 |
Mar 19 01:00:48 PM PDT 24 |
10753100268 ps |
| T1185 |
/workspace/coverage/default/36.i2c_host_mode_toggle.2490730812 |
|
|
Mar 19 12:59:26 PM PDT 24 |
Mar 19 01:02:20 PM PDT 24 |
2282007093 ps |
| T1186 |
/workspace/coverage/default/45.i2c_host_fifo_overflow.1966511073 |
|
|
Mar 19 01:00:17 PM PDT 24 |
Mar 19 01:01:12 PM PDT 24 |
3397006544 ps |
| T1187 |
/workspace/coverage/default/34.i2c_host_error_intr.4047363630 |
|
|
Mar 19 12:59:10 PM PDT 24 |
Mar 19 12:59:12 PM PDT 24 |
152887255 ps |
| T1188 |
/workspace/coverage/default/49.i2c_target_stretch.2205334797 |
|
|
Mar 19 01:00:38 PM PDT 24 |
Mar 19 01:10:37 PM PDT 24 |
14061247342 ps |
| T71 |
/workspace/coverage/cover_reg_top/9.i2c_tl_errors.2946332488 |
|
|
Mar 19 12:40:17 PM PDT 24 |
Mar 19 12:40:19 PM PDT 24 |
110707892 ps |
| T65 |
/workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2069961881 |
|
|
Mar 19 12:40:00 PM PDT 24 |
Mar 19 12:40:03 PM PDT 24 |
690437972 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1615061128 |
|
|
Mar 19 12:39:58 PM PDT 24 |
Mar 19 12:39:59 PM PDT 24 |
69337511 ps |
| T67 |
/workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1290250265 |
|
|
Mar 19 12:40:04 PM PDT 24 |
Mar 19 12:40:06 PM PDT 24 |
325340151 ps |
| T128 |
/workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1195523200 |
|
|
Mar 19 12:40:35 PM PDT 24 |
Mar 19 12:40:36 PM PDT 24 |
143461227 ps |
| T72 |
/workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1806687976 |
|
|
Mar 19 12:40:11 PM PDT 24 |
Mar 19 12:40:12 PM PDT 24 |
141644597 ps |
| T1189 |
/workspace/coverage/cover_reg_top/22.i2c_intr_test.40906316 |
|
|
Mar 19 12:40:43 PM PDT 24 |
Mar 19 12:40:45 PM PDT 24 |
23432708 ps |
| T73 |
/workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1875627372 |
|
|
Mar 19 12:39:58 PM PDT 24 |
Mar 19 12:39:59 PM PDT 24 |
41322100 ps |
| T114 |
/workspace/coverage/cover_reg_top/14.i2c_csr_rw.1333458916 |
|
|
Mar 19 12:40:37 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
71289130 ps |
| T129 |
/workspace/coverage/cover_reg_top/6.i2c_csr_rw.2309095341 |
|
|
Mar 19 12:40:13 PM PDT 24 |
Mar 19 12:40:13 PM PDT 24 |
36153363 ps |
| T130 |
/workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3336760823 |
|
|
Mar 19 12:40:41 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
41483468 ps |
| T131 |
/workspace/coverage/cover_reg_top/13.i2c_csr_rw.1425779174 |
|
|
Mar 19 12:40:37 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
24236820 ps |
| T74 |
/workspace/coverage/cover_reg_top/8.i2c_tl_errors.3894662711 |
|
|
Mar 19 12:40:15 PM PDT 24 |
Mar 19 12:40:18 PM PDT 24 |
160340712 ps |
| T132 |
/workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.478764946 |
|
|
Mar 19 12:40:29 PM PDT 24 |
Mar 19 12:40:29 PM PDT 24 |
62655929 ps |
| T133 |
/workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3634476503 |
|
|
Mar 19 12:40:04 PM PDT 24 |
Mar 19 12:40:06 PM PDT 24 |
42586870 ps |
| T1190 |
/workspace/coverage/cover_reg_top/41.i2c_intr_test.295380541 |
|
|
Mar 19 12:40:45 PM PDT 24 |
Mar 19 12:40:47 PM PDT 24 |
31370466 ps |
| T75 |
/workspace/coverage/cover_reg_top/15.i2c_tl_errors.3536035950 |
|
|
Mar 19 12:40:35 PM PDT 24 |
Mar 19 12:40:37 PM PDT 24 |
512515128 ps |
| T111 |
/workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.241574697 |
|
|
Mar 19 12:40:10 PM PDT 24 |
Mar 19 12:40:10 PM PDT 24 |
79384381 ps |
| T83 |
/workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4197657025 |
|
|
Mar 19 12:40:34 PM PDT 24 |
Mar 19 12:40:35 PM PDT 24 |
81900452 ps |
| T1191 |
/workspace/coverage/cover_reg_top/17.i2c_intr_test.703249833 |
|
|
Mar 19 12:40:40 PM PDT 24 |
Mar 19 12:40:40 PM PDT 24 |
74323693 ps |
| T76 |
/workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3743353559 |
|
|
Mar 19 12:40:13 PM PDT 24 |
Mar 19 12:40:14 PM PDT 24 |
245055432 ps |
| T1192 |
/workspace/coverage/cover_reg_top/28.i2c_intr_test.2467338872 |
|
|
Mar 19 12:40:44 PM PDT 24 |
Mar 19 12:40:45 PM PDT 24 |
32436783 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1562900178 |
|
|
Mar 19 12:40:00 PM PDT 24 |
Mar 19 12:40:02 PM PDT 24 |
77839250 ps |
| T112 |
/workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3143072704 |
|
|
Mar 19 12:40:19 PM PDT 24 |
Mar 19 12:40:20 PM PDT 24 |
40577841 ps |
| T86 |
/workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1319756775 |
|
|
Mar 19 12:40:42 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
129972355 ps |
| T134 |
/workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.535010579 |
|
|
Mar 19 12:40:39 PM PDT 24 |
Mar 19 12:40:40 PM PDT 24 |
33311034 ps |
| T1193 |
/workspace/coverage/cover_reg_top/11.i2c_intr_test.3509105298 |
|
|
Mar 19 12:40:30 PM PDT 24 |
Mar 19 12:40:31 PM PDT 24 |
104668619 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1440066425 |
|
|
Mar 19 12:40:03 PM PDT 24 |
Mar 19 12:40:09 PM PDT 24 |
356055602 ps |
| T1195 |
/workspace/coverage/cover_reg_top/47.i2c_intr_test.3204051288 |
|
|
Mar 19 12:40:46 PM PDT 24 |
Mar 19 12:40:48 PM PDT 24 |
19936055 ps |
| T1196 |
/workspace/coverage/cover_reg_top/16.i2c_intr_test.628051271 |
|
|
Mar 19 12:40:37 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
45526767 ps |
| T115 |
/workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2759404387 |
|
|
Mar 19 12:40:01 PM PDT 24 |
Mar 19 12:40:03 PM PDT 24 |
89759305 ps |
| T113 |
/workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.756347497 |
|
|
Mar 19 12:40:46 PM PDT 24 |
Mar 19 12:40:48 PM PDT 24 |
35418152 ps |
| T81 |
/workspace/coverage/cover_reg_top/0.i2c_tl_errors.3906036413 |
|
|
Mar 19 12:39:54 PM PDT 24 |
Mar 19 12:39:56 PM PDT 24 |
623077681 ps |
| T1197 |
/workspace/coverage/cover_reg_top/4.i2c_tl_errors.1990152295 |
|
|
Mar 19 12:40:05 PM PDT 24 |
Mar 19 12:40:07 PM PDT 24 |
73946763 ps |
| T1198 |
/workspace/coverage/cover_reg_top/29.i2c_intr_test.736596257 |
|
|
Mar 19 12:40:43 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
15131300 ps |
| T1199 |
/workspace/coverage/cover_reg_top/13.i2c_intr_test.3657407251 |
|
|
Mar 19 12:40:38 PM PDT 24 |
Mar 19 12:40:39 PM PDT 24 |
21778058 ps |
| T1200 |
/workspace/coverage/cover_reg_top/8.i2c_intr_test.550793574 |
|
|
Mar 19 12:40:15 PM PDT 24 |
Mar 19 12:40:16 PM PDT 24 |
30043960 ps |
| T1201 |
/workspace/coverage/cover_reg_top/26.i2c_intr_test.1780091465 |
|
|
Mar 19 12:40:43 PM PDT 24 |
Mar 19 12:40:45 PM PDT 24 |
18090428 ps |
| T1202 |
/workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.372734868 |
|
|
Mar 19 12:40:04 PM PDT 24 |
Mar 19 12:40:07 PM PDT 24 |
129505443 ps |
| T1203 |
/workspace/coverage/cover_reg_top/40.i2c_intr_test.2565174096 |
|
|
Mar 19 12:40:42 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
19157263 ps |
| T116 |
/workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4128139037 |
|
|
Mar 19 12:39:58 PM PDT 24 |
Mar 19 12:40:03 PM PDT 24 |
457223452 ps |
| T1204 |
/workspace/coverage/cover_reg_top/9.i2c_intr_test.2942607257 |
|
|
Mar 19 12:40:18 PM PDT 24 |
Mar 19 12:40:19 PM PDT 24 |
21509975 ps |
| T1205 |
/workspace/coverage/cover_reg_top/42.i2c_intr_test.3538901081 |
|
|
Mar 19 12:40:42 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
14824860 ps |
| T94 |
/workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.635150252 |
|
|
Mar 19 12:39:52 PM PDT 24 |
Mar 19 12:39:54 PM PDT 24 |
50637602 ps |
| T135 |
/workspace/coverage/cover_reg_top/3.i2c_csr_rw.2761815129 |
|
|
Mar 19 12:40:07 PM PDT 24 |
Mar 19 12:40:08 PM PDT 24 |
19977696 ps |
| T136 |
/workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2650800495 |
|
|
Mar 19 12:40:46 PM PDT 24 |
Mar 19 12:40:48 PM PDT 24 |
86485689 ps |
| T1206 |
/workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1856674299 |
|
|
Mar 19 12:40:23 PM PDT 24 |
Mar 19 12:40:24 PM PDT 24 |
81208763 ps |
| T93 |
/workspace/coverage/cover_reg_top/12.i2c_tl_errors.3614624126 |
|
|
Mar 19 12:40:28 PM PDT 24 |
Mar 19 12:40:29 PM PDT 24 |
240165163 ps |
| T1207 |
/workspace/coverage/cover_reg_top/36.i2c_intr_test.268962808 |
|
|
Mar 19 12:40:42 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
27302414 ps |
| T1208 |
/workspace/coverage/cover_reg_top/44.i2c_intr_test.3792577596 |
|
|
Mar 19 12:40:42 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
15203483 ps |
| T89 |
/workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1561423110 |
|
|
Mar 19 12:40:29 PM PDT 24 |
Mar 19 12:40:31 PM PDT 24 |
114531680 ps |
| T92 |
/workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.4207772865 |
|
|
Mar 19 12:40:36 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
333536783 ps |
| T82 |
/workspace/coverage/cover_reg_top/3.i2c_tl_errors.170111450 |
|
|
Mar 19 12:40:06 PM PDT 24 |
Mar 19 12:40:09 PM PDT 24 |
232097715 ps |
| T137 |
/workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2816204418 |
|
|
Mar 19 12:40:38 PM PDT 24 |
Mar 19 12:40:39 PM PDT 24 |
114885898 ps |
| T1209 |
/workspace/coverage/cover_reg_top/23.i2c_intr_test.3940790587 |
|
|
Mar 19 12:40:46 PM PDT 24 |
Mar 19 12:40:48 PM PDT 24 |
21256417 ps |
| T90 |
/workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2530507421 |
|
|
Mar 19 12:40:04 PM PDT 24 |
Mar 19 12:40:06 PM PDT 24 |
193801967 ps |
| T1210 |
/workspace/coverage/cover_reg_top/11.i2c_csr_rw.579642623 |
|
|
Mar 19 12:40:28 PM PDT 24 |
Mar 19 12:40:29 PM PDT 24 |
19176301 ps |
| T138 |
/workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.754031915 |
|
|
Mar 19 12:40:37 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
228838318 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3149432296 |
|
|
Mar 19 12:40:36 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
217435770 ps |
| T1211 |
/workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1967345381 |
|
|
Mar 19 12:40:29 PM PDT 24 |
Mar 19 12:40:30 PM PDT 24 |
234829539 ps |
| T1212 |
/workspace/coverage/cover_reg_top/2.i2c_intr_test.2349554293 |
|
|
Mar 19 12:40:00 PM PDT 24 |
Mar 19 12:40:01 PM PDT 24 |
34054551 ps |
| T1213 |
/workspace/coverage/cover_reg_top/19.i2c_tl_errors.873045313 |
|
|
Mar 19 12:40:45 PM PDT 24 |
Mar 19 12:40:48 PM PDT 24 |
58070350 ps |
| T1214 |
/workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3245025676 |
|
|
Mar 19 12:40:36 PM PDT 24 |
Mar 19 12:40:37 PM PDT 24 |
25188850 ps |
| T117 |
/workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.479820450 |
|
|
Mar 19 12:40:11 PM PDT 24 |
Mar 19 12:40:13 PM PDT 24 |
93592618 ps |
| T1215 |
/workspace/coverage/cover_reg_top/18.i2c_tl_errors.3008064956 |
|
|
Mar 19 12:40:35 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
255007277 ps |
| T1216 |
/workspace/coverage/cover_reg_top/31.i2c_intr_test.1296024634 |
|
|
Mar 19 12:40:42 PM PDT 24 |
Mar 19 12:40:43 PM PDT 24 |
18339999 ps |
| T1217 |
/workspace/coverage/cover_reg_top/7.i2c_intr_test.2078478163 |
|
|
Mar 19 12:40:20 PM PDT 24 |
Mar 19 12:40:20 PM PDT 24 |
18954222 ps |
| T1218 |
/workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.129837849 |
|
|
Mar 19 12:40:24 PM PDT 24 |
Mar 19 12:40:25 PM PDT 24 |
46436643 ps |
| T1219 |
/workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1484608113 |
|
|
Mar 19 12:40:27 PM PDT 24 |
Mar 19 12:40:28 PM PDT 24 |
74639280 ps |
| T1220 |
/workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.668332300 |
|
|
Mar 19 12:40:16 PM PDT 24 |
Mar 19 12:40:18 PM PDT 24 |
156222422 ps |
| T1221 |
/workspace/coverage/cover_reg_top/45.i2c_intr_test.400082091 |
|
|
Mar 19 12:40:43 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
20596022 ps |
| T118 |
/workspace/coverage/cover_reg_top/0.i2c_csr_rw.2321731384 |
|
|
Mar 19 12:39:53 PM PDT 24 |
Mar 19 12:39:54 PM PDT 24 |
52510944 ps |
| T1222 |
/workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2884360028 |
|
|
Mar 19 12:40:36 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
85912931 ps |
| T1223 |
/workspace/coverage/cover_reg_top/10.i2c_intr_test.1913216962 |
|
|
Mar 19 12:40:29 PM PDT 24 |
Mar 19 12:40:30 PM PDT 24 |
21414541 ps |
| T1224 |
/workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.196368878 |
|
|
Mar 19 12:40:19 PM PDT 24 |
Mar 19 12:40:20 PM PDT 24 |
51267437 ps |
| T119 |
/workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1153736276 |
|
|
Mar 19 12:40:05 PM PDT 24 |
Mar 19 12:40:06 PM PDT 24 |
89242837 ps |
| T1225 |
/workspace/coverage/cover_reg_top/37.i2c_intr_test.472474203 |
|
|
Mar 19 12:40:41 PM PDT 24 |
Mar 19 12:40:43 PM PDT 24 |
80316597 ps |
| T1226 |
/workspace/coverage/cover_reg_top/5.i2c_csr_rw.1201104293 |
|
|
Mar 19 12:40:10 PM PDT 24 |
Mar 19 12:40:10 PM PDT 24 |
111395454 ps |
| T1227 |
/workspace/coverage/cover_reg_top/33.i2c_intr_test.437798893 |
|
|
Mar 19 12:40:41 PM PDT 24 |
Mar 19 12:40:43 PM PDT 24 |
15589251 ps |
| T1228 |
/workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3750668032 |
|
|
Mar 19 12:40:14 PM PDT 24 |
Mar 19 12:40:17 PM PDT 24 |
270355543 ps |
| T1229 |
/workspace/coverage/cover_reg_top/32.i2c_intr_test.4071700353 |
|
|
Mar 19 12:40:46 PM PDT 24 |
Mar 19 12:40:48 PM PDT 24 |
23127033 ps |
| T1230 |
/workspace/coverage/cover_reg_top/5.i2c_tl_errors.2862454010 |
|
|
Mar 19 12:40:12 PM PDT 24 |
Mar 19 12:40:14 PM PDT 24 |
288074165 ps |
| T1231 |
/workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3423144129 |
|
|
Mar 19 12:40:37 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
985067333 ps |
| T1232 |
/workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.384646548 |
|
|
Mar 19 12:39:57 PM PDT 24 |
Mar 19 12:39:58 PM PDT 24 |
30537365 ps |
| T1233 |
/workspace/coverage/cover_reg_top/10.i2c_tl_errors.1928366855 |
|
|
Mar 19 12:40:16 PM PDT 24 |
Mar 19 12:40:19 PM PDT 24 |
240540504 ps |
| T120 |
/workspace/coverage/cover_reg_top/18.i2c_csr_rw.3370886654 |
|
|
Mar 19 12:40:36 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
74770785 ps |
| T1234 |
/workspace/coverage/cover_reg_top/38.i2c_intr_test.491861238 |
|
|
Mar 19 12:40:41 PM PDT 24 |
Mar 19 12:40:43 PM PDT 24 |
40915126 ps |
| T1235 |
/workspace/coverage/cover_reg_top/16.i2c_csr_rw.2842461274 |
|
|
Mar 19 12:40:40 PM PDT 24 |
Mar 19 12:40:41 PM PDT 24 |
53856856 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.i2c_intr_test.3564287552 |
|
|
Mar 19 12:39:54 PM PDT 24 |
Mar 19 12:39:55 PM PDT 24 |
24569961 ps |
| T1237 |
/workspace/coverage/cover_reg_top/1.i2c_intr_test.629140211 |
|
|
Mar 19 12:39:58 PM PDT 24 |
Mar 19 12:39:59 PM PDT 24 |
16383451 ps |
| T1238 |
/workspace/coverage/cover_reg_top/7.i2c_tl_errors.4193552620 |
|
|
Mar 19 12:40:21 PM PDT 24 |
Mar 19 12:40:23 PM PDT 24 |
135135347 ps |
| T1239 |
/workspace/coverage/cover_reg_top/7.i2c_csr_rw.3687706237 |
|
|
Mar 19 12:40:16 PM PDT 24 |
Mar 19 12:40:16 PM PDT 24 |
52874534 ps |
| T1240 |
/workspace/coverage/cover_reg_top/4.i2c_intr_test.2510571240 |
|
|
Mar 19 12:40:04 PM PDT 24 |
Mar 19 12:40:05 PM PDT 24 |
46725344 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1898085371 |
|
|
Mar 19 12:40:03 PM PDT 24 |
Mar 19 12:40:04 PM PDT 24 |
25880156 ps |
| T1241 |
/workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3202387024 |
|
|
Mar 19 12:40:10 PM PDT 24 |
Mar 19 12:40:11 PM PDT 24 |
56971143 ps |
| T1242 |
/workspace/coverage/cover_reg_top/19.i2c_csr_rw.1376483284 |
|
|
Mar 19 12:40:43 PM PDT 24 |
Mar 19 12:40:45 PM PDT 24 |
19976854 ps |
| T1243 |
/workspace/coverage/cover_reg_top/35.i2c_intr_test.3592503269 |
|
|
Mar 19 12:40:43 PM PDT 24 |
Mar 19 12:40:45 PM PDT 24 |
53781442 ps |
| T122 |
/workspace/coverage/cover_reg_top/4.i2c_csr_rw.1230789600 |
|
|
Mar 19 12:40:10 PM PDT 24 |
Mar 19 12:40:11 PM PDT 24 |
45711350 ps |
| T123 |
/workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.677824828 |
|
|
Mar 19 12:39:58 PM PDT 24 |
Mar 19 12:39:59 PM PDT 24 |
84162960 ps |
| T87 |
/workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3892933919 |
|
|
Mar 19 12:40:23 PM PDT 24 |
Mar 19 12:40:24 PM PDT 24 |
312699010 ps |
| T1244 |
/workspace/coverage/cover_reg_top/2.i2c_csr_rw.2442155781 |
|
|
Mar 19 12:39:58 PM PDT 24 |
Mar 19 12:39:59 PM PDT 24 |
63616541 ps |
| T126 |
/workspace/coverage/cover_reg_top/10.i2c_csr_rw.2318876866 |
|
|
Mar 19 12:40:22 PM PDT 24 |
Mar 19 12:40:22 PM PDT 24 |
25842619 ps |
| T1245 |
/workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4238270817 |
|
|
Mar 19 12:40:02 PM PDT 24 |
Mar 19 12:40:04 PM PDT 24 |
57403782 ps |
| T1246 |
/workspace/coverage/cover_reg_top/25.i2c_intr_test.793741165 |
|
|
Mar 19 12:40:52 PM PDT 24 |
Mar 19 12:40:53 PM PDT 24 |
17775267 ps |
| T1247 |
/workspace/coverage/cover_reg_top/14.i2c_tl_errors.3036234251 |
|
|
Mar 19 12:40:35 PM PDT 24 |
Mar 19 12:40:36 PM PDT 24 |
814348028 ps |
| T1248 |
/workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1502575964 |
|
|
Mar 19 12:40:29 PM PDT 24 |
Mar 19 12:40:30 PM PDT 24 |
31723181 ps |
| T1249 |
/workspace/coverage/cover_reg_top/9.i2c_csr_rw.1902406057 |
|
|
Mar 19 12:40:14 PM PDT 24 |
Mar 19 12:40:15 PM PDT 24 |
60423417 ps |
| T1250 |
/workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2888428104 |
|
|
Mar 19 12:40:37 PM PDT 24 |
Mar 19 12:40:38 PM PDT 24 |
276454304 ps |
| T1251 |
/workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3269200943 |
|
|
Mar 19 12:39:59 PM PDT 24 |
Mar 19 12:40:00 PM PDT 24 |
89385657 ps |
| T1252 |
/workspace/coverage/cover_reg_top/49.i2c_intr_test.142774728 |
|
|
Mar 19 12:40:47 PM PDT 24 |
Mar 19 12:40:49 PM PDT 24 |
53277864 ps |
| T1253 |
/workspace/coverage/cover_reg_top/21.i2c_intr_test.168863190 |
|
|
Mar 19 12:40:42 PM PDT 24 |
Mar 19 12:40:44 PM PDT 24 |
43421942 ps |
| T1254 |
/workspace/coverage/cover_reg_top/6.i2c_intr_test.586936684 |
|
|
Mar 19 12:40:11 PM PDT 24 |
Mar 19 12:40:12 PM PDT 24 |
39880117 ps |
| T1255 |
/workspace/coverage/cover_reg_top/39.i2c_intr_test.2757346438 |
|
|
Mar 19 12:40:45 PM PDT 24 |
Mar 19 12:40:47 PM PDT 24 |
52500256 ps |
| T1256 |
/workspace/coverage/cover_reg_top/16.i2c_tl_errors.1718160597 |
|
|
Mar 19 12:40:38 PM PDT 24 |
Mar 19 12:40:39 PM PDT 24 |
821508200 ps |
| T1257 |
/workspace/coverage/cover_reg_top/48.i2c_intr_test.491144695 |
|
|
Mar 19 12:40:49 PM PDT 24 |
Mar 19 12:40:49 PM PDT 24 |
22246407 ps |
| T88 |
/workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1022458979 |
|
|
Mar 19 12:40:14 PM PDT 24 |
Mar 19 12:40:16 PM PDT 24 |
1160123973 ps |