Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.67	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	5	55	91.67

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	5	55	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2349214	1			T1	3		T2	3		T3	3
all_values[1]	2349214	1			T1	3		T2	3		T3	3
all_values[2]	2349214	1			T1	3		T2	3		T3	3
all_values[3]	2349214	1			T1	3		T2	3		T3	3
all_values[4]	2349214	1			T1	3		T2	3		T3	3
all_values[5]	2349214	1			T1	3		T2	3		T3	3
all_values[6]	2349214	1			T1	3		T2	3		T3	3
all_values[7]	2349214	1			T1	3		T2	3		T3	3
all_values[8]	2349214	1			T1	3		T2	3		T3	3
all_values[9]	2349214	1			T1	3		T2	3		T3	3
all_values[10]	2349214	1			T1	3		T2	3		T3	3
all_values[11]	2349214	1			T1	3		T2	3		T3	3
all_values[12]	2349214	1			T1	3		T2	3		T3	3
all_values[13]	2349214	1			T1	3		T2	3		T3	3
all_values[14]	2349214	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30687150

1

T1

37

T2

38

T3

37

auto[1]

4551060

1

T1

8

T2

7

T3

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34536238

1

T1

45

T2

45

T3

45

auto[1]

701972

1

T74

354

T75

361009

T76

335566

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	5	55	91.67	5

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	587797	1			T1	1		T3	1		T6	1
all_values[0]	auto[0]	auto[1]	696	1			T75	427		T76	64		T77	36
all_values[0]	auto[1]	auto[0]	1714641	1			T1	2		T2	3		T3	2
all_values[0]	auto[1]	auto[1]	46080	1			T75	23641		T76	22307		T77	13
all_values[1]	auto[0]	auto[0]	2301914	1			T1	3		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	46677	1			T74	25		T75	24061		T76	22368
all_values[1]	auto[1]	auto[0]	466	1			T211	1		T212	6		T213	3
all_values[1]	auto[1]	auto[1]	157	1			T74	3		T75	8		T76	3
all_values[2]	auto[0]	auto[0]	2302449	1			T1	3		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	46635	1			T74	25		T75	24064		T76	22369
all_values[2]	auto[1]	auto[0]	2	1			T214	2		-	-		-	-
all_values[2]	auto[1]	auto[1]	128	1			T74	1		T75	5		T76	3
all_values[3]	auto[0]	auto[0]	2302421	1			T1	3		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	46650	1			T74	24		T75	24061		T76	22368
all_values[3]	auto[1]	auto[1]	143	1			T74	2		T75	7		T76	2
all_values[4]	auto[0]	auto[0]	2302411	1			T1	3		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	46624	1			T74	26		T75	24060		T76	22365
all_values[4]	auto[1]	auto[0]	6	1			T18	4		T31	2		-	-
all_values[4]	auto[1]	auto[1]	173	1			T74	2		T75	4		T76	5
all_values[5]	auto[0]	auto[0]	2302428	1			T1	3		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	46613	1			T75	24061		T76	22369		T77	39
all_values[5]	auto[1]	auto[1]	173	1			T76	1		T77	11		T215	1
all_values[6]	auto[0]	auto[0]	2299223	1			T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	46522	1			T74	25		T75	23983		T76	22320
all_values[6]	auto[1]	auto[0]	3200	1			T1	1		T3	1		T6	1
all_values[6]	auto[1]	auto[1]	269	1			T74	2		T75	84		T76	52
all_values[7]	auto[0]	auto[0]	1907845	1			T1	2		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	38891	1			T74	26		T75	20277		T76	18407
all_values[7]	auto[1]	auto[0]	394549	1			T1	1		T3	1		T6	1
all_values[7]	auto[1]	auto[1]	7929	1			T74	2		T75	3792		T76	3964
all_values[8]	auto[0]	auto[0]	2271882	1			T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	44645	1			T74	24		T75	23010		T76	21428
all_values[8]	auto[1]	auto[0]	30541	1			T1	1		T3	1		T6	1
all_values[8]	auto[1]	auto[1]	2146	1			T74	4		T75	1057		T76	944
all_values[9]	auto[0]	auto[0]	2300005	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	46510	1			T74	24		T75	23978		T76	22316
all_values[9]	auto[1]	auto[0]	2414	1			T1	1		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	285	1			T74	4		T75	90		T76	55
all_values[10]	auto[0]	auto[0]	2302412	1			T1	3		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	46683	1			T74	25		T75	24066		T76	22370
all_values[10]	auto[1]	auto[1]	119	1			T74	1		T75	3		T76	2
all_values[11]	auto[0]	auto[0]	1747	1			T1	1		T3	1		T6	1
all_values[11]	auto[0]	auto[1]	305	1			T74	20		T75	30		T76	37
all_values[11]	auto[1]	auto[0]	2300654	1			T1	2		T2	3		T3	2
all_values[11]	auto[1]	auto[1]	46508	1			T74	7		T75	24039		T76	22335
all_values[12]	auto[0]	auto[0]	2302400	1			T1	3		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	46668	1			T74	26		T75	24061		T76	22366
all_values[12]	auto[1]	auto[1]	146	1			T74	2		T75	3		T76	6
all_values[13]	auto[0]	auto[0]	2302406	1			T1	3		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	46644	1			T74	24		T75	24061		T76	22369
all_values[13]	auto[1]	auto[0]	7	1			T25	1		T26	1		T216	1
all_values[13]	auto[1]	auto[1]	157	1			T74	4		T75	8		T76	3
all_values[14]	auto[0]	auto[0]	2302418	1			T1	3		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	46629	1			T74	24		T75	24064		T76	22365
all_values[14]	auto[1]	auto[1]	167	1			T74	2		T75	4		T76	3