Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2349214	1			T1	3		T2	3		T3	3
all_pins[1]	2349214	1			T1	3		T2	3		T3	3
all_pins[2]	2349214	1			T1	3		T2	3		T3	3
all_pins[3]	2349214	1			T1	3		T2	3		T3	3
all_pins[4]	2349214	1			T1	3		T2	3		T3	3
all_pins[5]	2349214	1			T1	3		T2	3		T3	3
all_pins[6]	2349214	1			T1	3		T2	3		T3	3
all_pins[7]	2349214	1			T1	3		T2	3		T3	3
all_pins[8]	2349214	1			T1	3		T2	3		T3	3
all_pins[9]	2349214	1			T1	3		T2	3		T3	3
all_pins[10]	2349214	1			T1	3		T2	3		T3	3
all_pins[11]	2349214	1			T1	3		T2	3		T3	3
all_pins[12]	2349214	1			T1	3		T2	3		T3	3
all_pins[13]	2349214	1			T1	3		T2	3		T3	3
all_pins[14]	2349214	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	30665782	1			T1	37		T2	38		T3	37
values[0x1]	4572428	1			T1	8		T2	7		T3	8
transitions[0x0=>0x1]	4559121	1			T1	5		T2	7		T3	5
transitions[0x1=>0x0]	4558294	1			T1	4		T2	6		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	588624	1			T1	1		T3	1		T6	1
all_pins[0]	values[0x1]	1760590	1			T1	2		T2	3		T3	2
all_pins[0]	transitions[0x0=>0x1]	1760007	1			T1	2		T2	3		T3	2
all_pins[0]	transitions[0x1=>0x0]	57	1			T74	1		T75	1		T77	4
all_pins[1]	values[0x0]	2348574	1			T1	3		T2	3		T3	3
all_pins[1]	values[0x1]	640	1			T211	1		T212	7		T213	3
all_pins[1]	transitions[0x0=>0x1]	619	1			T211	1		T212	7		T213	3
all_pins[1]	transitions[0x1=>0x0]	52	1			T75	4		T76	2		T214	2
all_pins[2]	values[0x0]	2349141	1			T1	3		T2	3		T3	3
all_pins[2]	values[0x1]	73	1			T75	4		T76	2		T214	2
all_pins[2]	transitions[0x0=>0x1]	51	1			T75	2		T76	2		T214	2
all_pins[2]	transitions[0x1=>0x0]	59	1			T74	2		T75	2		T76	2
all_pins[3]	values[0x0]	2349133	1			T1	3		T2	3		T3	3
all_pins[3]	values[0x1]	81	1			T74	2		T75	4		T76	2
all_pins[3]	transitions[0x0=>0x1]	54	1			T74	2		T75	4		T77	6
all_pins[3]	transitions[0x1=>0x0]	68	1			T18	5		T31	2		T76	3
all_pins[4]	values[0x0]	2349119	1			T1	3		T2	3		T3	3
all_pins[4]	values[0x1]	95	1			T18	5		T31	2		T76	5
all_pins[4]	transitions[0x0=>0x1]	73	1			T18	5		T31	2		T76	4
all_pins[4]	transitions[0x1=>0x0]	59	1			T77	6		T215	1		T167	1
all_pins[5]	values[0x0]	2349133	1			T1	3		T2	3		T3	3
all_pins[5]	values[0x1]	81	1			T76	1		T77	6		T215	1
all_pins[5]	transitions[0x0=>0x1]	54	1			T76	1		T77	4		T215	1
all_pins[5]	transitions[0x1=>0x0]	3802	1			T1	1		T3	1		T6	1
all_pins[6]	values[0x0]	2345385	1			T1	2		T2	3		T3	2
all_pins[6]	values[0x1]	3829	1			T1	1		T3	1		T6	1
all_pins[6]	transitions[0x0=>0x1]	2968	1			T8	1		T15	4		T28	14
all_pins[6]	transitions[0x1=>0x0]	419069	1			T15	1017		T28	2231		T16	6646
all_pins[7]	values[0x0]	1929284	1			T1	2		T2	3		T3	2
all_pins[7]	values[0x1]	419930	1			T1	1		T3	1		T6	1
all_pins[7]	transitions[0x0=>0x1]	408578	1			T15	1008		T28	2089		T16	6439
all_pins[7]	transitions[0x1=>0x0]	25543	1			T28	239		T16	1674		T17	1
all_pins[8]	values[0x0]	2312319	1			T1	2		T2	3		T3	2
all_pins[8]	values[0x1]	36895	1			T1	1		T3	1		T6	1
all_pins[8]	transitions[0x0=>0x1]	36603	1			T15	9		T28	382		T16	1881
all_pins[8]	transitions[0x1=>0x0]	2534	1			T2	1		T4	1		T10	1
all_pins[9]	values[0x0]	2346388	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	2826	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x0=>0x1]	2814	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x1=>0x0]	40	1			T75	1		T76	2		T77	3
all_pins[10]	values[0x0]	2349162	1			T1	3		T2	3		T3	3
all_pins[10]	values[0x1]	52	1			T75	1		T76	2		T77	3
all_pins[10]	transitions[0x0=>0x1]	40	1			T75	1		T76	2		T77	3
all_pins[10]	transitions[0x1=>0x0]	2347084	1			T1	2		T2	3		T3	2
all_pins[11]	values[0x0]	2118	1			T1	1		T3	1		T6	1
all_pins[11]	values[0x1]	2347096	1			T1	2		T2	3		T3	2
all_pins[11]	transitions[0x0=>0x1]	2347082	1			T1	2		T2	3		T3	2
all_pins[11]	transitions[0x1=>0x0]	47	1			T74	1		T75	2		T76	3
all_pins[12]	values[0x0]	2349153	1			T1	3		T2	3		T3	3
all_pins[12]	values[0x1]	61	1			T74	1		T75	2		T76	3
all_pins[12]	transitions[0x0=>0x1]	47	1			T75	1		T76	2		T77	5
all_pins[12]	transitions[0x1=>0x0]	78	1			T25	1		T26	1		T74	3
all_pins[13]	values[0x0]	2349122	1			T1	3		T2	3		T3	3
all_pins[13]	values[0x1]	92	1			T25	1		T26	1		T74	4
all_pins[13]	transitions[0x0=>0x1]	72	1			T25	1		T26	1		T74	4
all_pins[13]	transitions[0x1=>0x0]	67	1			T75	1		T76	2		T77	7
all_pins[14]	values[0x0]	2349127	1			T1	3		T2	3		T3	3
all_pins[14]	values[0x1]	87	1			T75	1		T76	2		T77	8
all_pins[14]	transitions[0x0=>0x1]	59	1			T75	1		T76	2		T77	4
all_pins[14]	transitions[0x1=>0x0]	1759735	1			T1	1		T2	2		T3	1