Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	333	1			T74	4		T75	11		T76	7
all_values[1]	333	1			T74	4		T75	11		T76	7
all_values[2]	333	1			T74	4		T75	11		T76	7
all_values[3]	333	1			T74	4		T75	11		T76	7
all_values[4]	333	1			T74	4		T75	11		T76	7
all_values[5]	333	1			T74	4		T75	11		T76	7
all_values[6]	333	1			T74	4		T75	11		T76	7
all_values[7]	333	1			T74	4		T75	11		T76	7
all_values[8]	333	1			T74	4		T75	11		T76	7
all_values[9]	333	1			T74	4		T75	11		T76	7
all_values[10]	333	1			T74	4		T75	11		T76	7
all_values[11]	333	1			T74	4		T75	11		T76	7
all_values[12]	333	1			T74	4		T75	11		T76	7
all_values[13]	333	1			T74	4		T75	11		T76	7
all_values[14]	333	1			T74	4		T75	11		T76	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780

1

T74

33

T75

96

T76

63

auto[1]

2215

1

T74

27

T75

69

T76

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

837

1

T74

18

T75

23

T76

14

auto[1]

4158

1

T74

42

T75

142

T76

91

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2933

1

T74

38

T75

104

T76

59

auto[1]

2062

1

T74

22

T75

61

T76

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1			T74	3		T75	1		T76	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T75	3		T76	3		T77	1
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T74	1		T167	2		T217	1
all_values[0]	auto[0]	auto[1]	auto[1]	65	1			T75	3		T77	8		T215	1
all_values[0]	auto[1]	auto[0]	auto[1]	81	1			T75	3		T76	2		T77	5
all_values[0]	auto[1]	auto[1]	auto[1]	53	1			T75	1		T76	1		T77	3
all_values[1]	auto[0]	auto[0]	auto[0]	21	1			T76	1		T218	1		T219	1
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T74	1		T75	6		T76	2
all_values[1]	auto[0]	auto[1]	auto[0]	7	1			T218	1		T220	1		T221	2
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T75	1		T76	1		T77	3
all_values[1]	auto[1]	auto[0]	auto[1]	92	1			T74	2		T75	4		T76	1
all_values[1]	auto[1]	auto[1]	auto[1]	61	1			T74	1		T76	2		T77	7
all_values[2]	auto[0]	auto[0]	auto[0]	33	1			T77	6		T168	2		T219	1
all_values[2]	auto[0]	auto[0]	auto[1]	66	1			T74	1		T75	1		T76	2
all_values[2]	auto[0]	auto[1]	auto[0]	33	1			T74	2		T77	6		T217	1
all_values[2]	auto[0]	auto[1]	auto[1]	73	1			T75	5		T76	2		T77	1
all_values[2]	auto[1]	auto[0]	auto[1]	86	1			T74	1		T75	2		T76	3
all_values[2]	auto[1]	auto[1]	auto[1]	42	1			T75	3		T77	1		T215	2
all_values[3]	auto[0]	auto[0]	auto[0]	44	1			T75	1		T76	1		T77	1
all_values[3]	auto[0]	auto[0]	auto[1]	63	1			T75	3		T77	2		T215	1
all_values[3]	auto[0]	auto[1]	auto[0]	19	1			T74	2		T76	1		T217	1
all_values[3]	auto[0]	auto[1]	auto[1]	71	1			T74	1		T75	1		T76	3
all_values[3]	auto[1]	auto[0]	auto[1]	68	1			T75	3		T77	4		T215	2
all_values[3]	auto[1]	auto[1]	auto[1]	68	1			T74	1		T75	3		T76	2
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T75	1		T76	1		T77	1
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T74	1		T75	2		T77	5
all_values[4]	auto[0]	auto[1]	auto[0]	20	1			T75	3		T76	1		T77	1
all_values[4]	auto[0]	auto[1]	auto[1]	57	1			T75	1		T76	2		T77	2
all_values[4]	auto[1]	auto[0]	auto[1]	80	1			T74	3		T75	3		T77	5
all_values[4]	auto[1]	auto[1]	auto[1]	60	1			T75	1		T76	3		T77	4
all_values[5]	auto[0]	auto[0]	auto[0]	31	1			T74	2		T75	3		T76	2
all_values[5]	auto[0]	auto[0]	auto[1]	69	1			T76	2		T77	4		T168	1
all_values[5]	auto[0]	auto[1]	auto[0]	20	1			T74	2		T75	4		T215	1
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T75	3		T76	1		T77	4
all_values[5]	auto[1]	auto[0]	auto[1]	84	1			T76	1		T77	6		T168	1
all_values[5]	auto[1]	auto[1]	auto[1]	59	1			T75	1		T76	1		T77	4
all_values[6]	auto[0]	auto[0]	auto[0]	36	1			T75	2		T215	1		T168	1
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T74	2		T75	2		T76	2
all_values[6]	auto[0]	auto[1]	auto[0]	31	1			T74	1		T215	3		T169	1
all_values[6]	auto[0]	auto[1]	auto[1]	65	1			T75	3		T76	1		T77	6
all_values[6]	auto[1]	auto[0]	auto[1]	65	1			T74	1		T75	2		T76	2
all_values[6]	auto[1]	auto[1]	auto[1]	65	1			T75	2		T76	2		T77	2
all_values[7]	auto[0]	auto[0]	auto[0]	33	1			T76	1		T77	1		T215	1
all_values[7]	auto[0]	auto[0]	auto[1]	60	1			T75	5		T76	1		T77	4
all_values[7]	auto[0]	auto[1]	auto[0]	9	1			T167	2		T218	1		T222	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T74	3		T75	2		T76	3
all_values[7]	auto[1]	auto[0]	auto[1]	88	1			T75	2		T77	1		T215	1
all_values[7]	auto[1]	auto[1]	auto[1]	69	1			T74	1		T75	2		T76	2
all_values[8]	auto[0]	auto[0]	auto[0]	33	1			T75	1		T77	1		T168	1
all_values[8]	auto[0]	auto[0]	auto[1]	66	1			T74	2		T75	2		T76	1
all_values[8]	auto[0]	auto[1]	auto[0]	33	1			T75	1		T77	2		T168	3
all_values[8]	auto[0]	auto[1]	auto[1]	72	1			T75	3		T76	3		T77	6
all_values[8]	auto[1]	auto[0]	auto[1]	72	1			T74	1		T75	2		T76	3
all_values[8]	auto[1]	auto[1]	auto[1]	57	1			T74	1		T75	2		T77	5
all_values[9]	auto[0]	auto[0]	auto[0]	38	1			T75	1		T76	1		T77	2
all_values[9]	auto[0]	auto[0]	auto[1]	78	1			T74	2		T75	4		T76	2
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T77	1		T215	2		T170	2
all_values[9]	auto[0]	auto[1]	auto[1]	52	1			T75	2		T76	1		T77	2
all_values[9]	auto[1]	auto[0]	auto[1]	79	1			T76	3		T77	3		T168	2
all_values[9]	auto[1]	auto[1]	auto[1]	60	1			T74	2		T75	4		T77	5
all_values[10]	auto[0]	auto[0]	auto[0]	32	1			T74	1		T77	1		T215	2
all_values[10]	auto[0]	auto[0]	auto[1]	83	1			T74	1		T75	6		T76	3
all_values[10]	auto[0]	auto[1]	auto[0]	27	1			T74	1		T167	1		T168	2
all_values[10]	auto[0]	auto[1]	auto[1]	72	1			T75	2		T76	2		T77	7
all_values[10]	auto[1]	auto[0]	auto[1]	78	1			T74	1		T75	3		T76	1
all_values[10]	auto[1]	auto[1]	auto[1]	41	1			T76	1		T77	1		T168	1
all_values[11]	auto[0]	auto[0]	auto[0]	30	1			T168	1		T219	1		T220	1
all_values[11]	auto[0]	auto[0]	auto[1]	78	1			T74	1		T75	3		T76	3
all_values[11]	auto[0]	auto[1]	auto[0]	18	1			T74	1		T167	1		T217	2
all_values[11]	auto[0]	auto[1]	auto[1]	75	1			T75	3		T76	1		T77	5
all_values[11]	auto[1]	auto[0]	auto[1]	76	1			T74	1		T75	4		T76	2
all_values[11]	auto[1]	auto[1]	auto[1]	56	1			T74	1		T75	1		T76	1
all_values[12]	auto[0]	auto[0]	auto[0]	27	1			T75	3		T77	2		T167	1
all_values[12]	auto[0]	auto[0]	auto[1]	83	1			T74	2		T75	3		T76	1
all_values[12]	auto[0]	auto[1]	auto[0]	19	1			T75	1		T215	1		T170	2
all_values[12]	auto[0]	auto[1]	auto[1]	58	1			T75	1		T77	3		T215	1
all_values[12]	auto[1]	auto[0]	auto[1]	91	1			T74	1		T75	3		T76	4
all_values[12]	auto[1]	auto[1]	auto[1]	55	1			T74	1		T76	2		T77	7
all_values[13]	auto[0]	auto[0]	auto[0]	33	1			T77	1		T170	1		T218	1
all_values[13]	auto[0]	auto[0]	auto[1]	63	1			T75	1		T76	1		T77	7
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T217	1		T218	3		T223	2
all_values[13]	auto[0]	auto[1]	auto[1]	72	1			T74	2		T75	3		T76	1
all_values[13]	auto[1]	auto[0]	auto[1]	80	1			T75	4		T76	5		T77	5
all_values[13]	auto[1]	auto[1]	auto[1]	61	1			T74	2		T75	3		T77	1
all_values[14]	auto[0]	auto[0]	auto[0]	37	1			T74	1		T75	1		T76	3
all_values[14]	auto[0]	auto[0]	auto[1]	68	1			T74	1		T75	3		T77	6
all_values[14]	auto[0]	auto[1]	auto[0]	24	1			T74	1		T76	1		T167	1
all_values[14]	auto[0]	auto[1]	auto[1]	69	1			T75	4		T76	1		T77	3
all_values[14]	auto[1]	auto[0]	auto[1]	80	1			T74	1		T75	3		T76	2
all_values[14]	auto[1]	auto[1]	auto[1]	55	1			T77	3		T168	2		T170	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal