Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.53 97.38 90.88 97.65 43.87 94.77 98.44 89.71


Total test records in report: 1206
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T1070 /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3750269017 Mar 24 02:49:42 PM PDT 24 Mar 24 02:51:46 PM PDT 24 10040150591 ps
T1071 /workspace/coverage/default/41.i2c_target_intr_smoke.296071348 Mar 24 02:52:51 PM PDT 24 Mar 24 02:52:55 PM PDT 24 3314619095 ps
T1072 /workspace/coverage/default/29.i2c_target_bad_addr.1415025301 Mar 24 02:51:31 PM PDT 24 Mar 24 02:51:36 PM PDT 24 1204528675 ps
T1073 /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2245550465 Mar 24 02:50:06 PM PDT 24 Mar 24 02:50:07 PM PDT 24 130354551 ps
T1074 /workspace/coverage/default/12.i2c_target_timeout.1782066680 Mar 24 02:49:41 PM PDT 24 Mar 24 02:49:48 PM PDT 24 1367139817 ps
T1075 /workspace/coverage/default/49.i2c_target_hrst.1901846902 Mar 24 02:53:43 PM PDT 24 Mar 24 02:53:46 PM PDT 24 5491970716 ps
T1076 /workspace/coverage/default/14.i2c_host_error_intr.331190262 Mar 24 02:49:52 PM PDT 24 Mar 24 02:49:54 PM PDT 24 38509660 ps
T1077 /workspace/coverage/default/6.i2c_target_stress_rd.1359670646 Mar 24 02:49:01 PM PDT 24 Mar 24 02:49:28 PM PDT 24 2945567244 ps
T1078 /workspace/coverage/default/21.i2c_host_error_intr.201546422 Mar 24 02:50:40 PM PDT 24 Mar 24 02:50:41 PM PDT 24 153990317 ps
T1079 /workspace/coverage/default/34.i2c_target_intr_smoke.1227834361 Mar 24 02:52:04 PM PDT 24 Mar 24 02:52:09 PM PDT 24 3796979929 ps
T1080 /workspace/coverage/default/47.i2c_host_fifo_overflow.1727690773 Mar 24 02:53:28 PM PDT 24 Mar 24 02:53:59 PM PDT 24 6936289342 ps
T1081 /workspace/coverage/default/21.i2c_target_bad_addr.4185176629 Mar 24 02:50:46 PM PDT 24 Mar 24 02:50:50 PM PDT 24 772402039 ps
T1082 /workspace/coverage/default/26.i2c_host_fifo_full.1492114951 Mar 24 02:51:11 PM PDT 24 Mar 24 02:52:59 PM PDT 24 1611444823 ps
T1083 /workspace/coverage/default/22.i2c_host_fifo_overflow.393753554 Mar 24 02:50:51 PM PDT 24 Mar 24 02:52:29 PM PDT 24 5667364292 ps
T1084 /workspace/coverage/default/28.i2c_target_bad_addr.1174370143 Mar 24 02:51:31 PM PDT 24 Mar 24 02:51:37 PM PDT 24 1297318101 ps
T1085 /workspace/coverage/default/24.i2c_target_timeout.1309403870 Mar 24 02:50:59 PM PDT 24 Mar 24 02:51:07 PM PDT 24 1639559446 ps
T1086 /workspace/coverage/default/5.i2c_target_bad_addr.2710758183 Mar 24 02:48:52 PM PDT 24 Mar 24 02:48:56 PM PDT 24 1531058024 ps
T1087 /workspace/coverage/default/16.i2c_target_timeout.2971385172 Mar 24 02:50:11 PM PDT 24 Mar 24 02:50:19 PM PDT 24 11245233357 ps
T1088 /workspace/coverage/default/37.i2c_target_stress_rd.189536896 Mar 24 02:52:23 PM PDT 24 Mar 24 02:52:33 PM PDT 24 1174123470 ps
T1089 /workspace/coverage/default/35.i2c_target_hrst.375384557 Mar 24 02:52:12 PM PDT 24 Mar 24 02:52:14 PM PDT 24 1155798965 ps
T1090 /workspace/coverage/default/40.i2c_host_smoke.2154077306 Mar 24 02:52:38 PM PDT 24 Mar 24 02:54:19 PM PDT 24 1202201316 ps
T1091 /workspace/coverage/default/14.i2c_target_timeout.529585649 Mar 24 02:49:59 PM PDT 24 Mar 24 02:50:07 PM PDT 24 5061976455 ps
T1092 /workspace/coverage/default/5.i2c_host_perf.953601501 Mar 24 02:48:50 PM PDT 24 Mar 24 03:06:40 PM PDT 24 6937107674 ps
T1093 /workspace/coverage/default/4.i2c_host_fifo_watermark.286490861 Mar 24 02:48:48 PM PDT 24 Mar 24 02:50:05 PM PDT 24 2686175091 ps
T1094 /workspace/coverage/default/36.i2c_target_stretch.3291685406 Mar 24 02:52:17 PM PDT 24 Mar 24 02:56:42 PM PDT 24 9417723012 ps
T102 /workspace/coverage/default/2.i2c_sec_cm.3418464616 Mar 24 02:48:29 PM PDT 24 Mar 24 02:48:30 PM PDT 24 221696595 ps
T1095 /workspace/coverage/default/19.i2c_target_stress_wr.1759829146 Mar 24 02:50:25 PM PDT 24 Mar 24 02:50:44 PM PDT 24 16941399546 ps
T1096 /workspace/coverage/default/44.i2c_target_stress_rd.2093758505 Mar 24 02:53:13 PM PDT 24 Mar 24 02:53:24 PM PDT 24 2209264736 ps
T1097 /workspace/coverage/default/6.i2c_host_perf.2078612510 Mar 24 02:48:58 PM PDT 24 Mar 24 02:49:45 PM PDT 24 3102305950 ps
T1098 /workspace/coverage/default/31.i2c_target_stress_rd.1404424202 Mar 24 02:51:48 PM PDT 24 Mar 24 02:52:12 PM PDT 24 2408558040 ps
T1099 /workspace/coverage/default/5.i2c_target_timeout.1528026991 Mar 24 02:48:51 PM PDT 24 Mar 24 02:48:58 PM PDT 24 2798459529 ps
T1100 /workspace/coverage/default/16.i2c_host_fifo_full.520329597 Mar 24 02:50:09 PM PDT 24 Mar 24 02:50:45 PM PDT 24 5983004988 ps
T1101 /workspace/coverage/default/22.i2c_target_bad_addr.2239896996 Mar 24 02:50:51 PM PDT 24 Mar 24 02:50:54 PM PDT 24 554874281 ps
T1102 /workspace/coverage/default/13.i2c_target_fifo_reset_tx.7979016 Mar 24 02:49:49 PM PDT 24 Mar 24 02:50:32 PM PDT 24 10204995647 ps
T1103 /workspace/coverage/default/21.i2c_host_override.3466478030 Mar 24 02:50:35 PM PDT 24 Mar 24 02:50:36 PM PDT 24 17110361 ps
T1104 /workspace/coverage/default/0.i2c_target_timeout.3823092224 Mar 24 02:48:10 PM PDT 24 Mar 24 02:48:18 PM PDT 24 29640639690 ps
T1105 /workspace/coverage/default/12.i2c_host_fifo_watermark.1005953638 Mar 24 02:49:41 PM PDT 24 Mar 24 02:52:14 PM PDT 24 18631568476 ps
T1106 /workspace/coverage/default/5.i2c_host_fifo_watermark.1457558497 Mar 24 02:48:54 PM PDT 24 Mar 24 02:50:20 PM PDT 24 11983160356 ps
T77 /workspace/coverage/default/24.i2c_host_stress_all.1916048959 Mar 24 02:50:59 PM PDT 24 Mar 24 02:55:10 PM PDT 24 6468901814 ps
T1107 /workspace/coverage/default/45.i2c_host_fifo_reset_rx.543295024 Mar 24 02:53:12 PM PDT 24 Mar 24 02:53:15 PM PDT 24 419334626 ps
T1108 /workspace/coverage/default/18.i2c_target_stress_rd.699601436 Mar 24 02:50:22 PM PDT 24 Mar 24 02:50:31 PM PDT 24 619447516 ps
T1109 /workspace/coverage/default/8.i2c_host_fifo_full.2565826967 Mar 24 02:49:14 PM PDT 24 Mar 24 02:50:22 PM PDT 24 7372049186 ps
T215 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3450293228 Mar 24 12:22:14 PM PDT 24 Mar 24 12:22:15 PM PDT 24 44181083 ps
T167 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2351734571 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:14 PM PDT 24 18969166 ps
T71 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.416990612 Mar 24 12:21:09 PM PDT 24 Mar 24 12:21:10 PM PDT 24 54239370 ps
T97 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.85045315 Mar 24 12:22:14 PM PDT 24 Mar 24 12:22:16 PM PDT 24 308568227 ps
T72 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3288809530 Mar 24 12:18:30 PM PDT 24 Mar 24 12:18:32 PM PDT 24 59000914 ps
T168 /workspace/coverage/cover_reg_top/33.i2c_intr_test.227719153 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:14 PM PDT 24 28273779 ps
T73 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.717748711 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:13 PM PDT 24 20466652 ps
T169 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3914326769 Mar 24 12:19:04 PM PDT 24 Mar 24 12:19:05 PM PDT 24 21960061 ps
T217 /workspace/coverage/cover_reg_top/3.i2c_intr_test.3545268366 Mar 24 12:17:17 PM PDT 24 Mar 24 12:17:18 PM PDT 24 18103330 ps
T129 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1930139809 Mar 24 12:20:11 PM PDT 24 Mar 24 12:20:15 PM PDT 24 107398006 ps
T170 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1211824020 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 103913870 ps
T98 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3560249148 Mar 24 12:21:54 PM PDT 24 Mar 24 12:21:56 PM PDT 24 44296951 ps
T218 /workspace/coverage/cover_reg_top/29.i2c_intr_test.4276320643 Mar 24 12:19:36 PM PDT 24 Mar 24 12:19:37 PM PDT 24 16611043 ps
T171 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3427303521 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:13 PM PDT 24 39261051 ps
T144 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3391080366 Mar 24 12:18:52 PM PDT 24 Mar 24 12:18:53 PM PDT 24 275726608 ps
T105 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3599862249 Mar 24 12:20:11 PM PDT 24 Mar 24 12:20:15 PM PDT 24 36291645 ps
T130 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2565519924 Mar 24 12:20:52 PM PDT 24 Mar 24 12:20:53 PM PDT 24 16775166 ps
T145 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.437320647 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:10 PM PDT 24 46387599 ps
T146 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3295321443 Mar 24 12:22:11 PM PDT 24 Mar 24 12:22:12 PM PDT 24 18594481 ps
T107 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1768533748 Mar 24 12:21:56 PM PDT 24 Mar 24 12:21:58 PM PDT 24 417093687 ps
T106 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4015156464 Mar 24 12:19:23 PM PDT 24 Mar 24 12:19:25 PM PDT 24 267173002 ps
T117 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3375710308 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 63220537 ps
T108 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3758553534 Mar 24 12:19:09 PM PDT 24 Mar 24 12:19:10 PM PDT 24 251925118 ps
T147 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2439494519 Mar 24 12:20:18 PM PDT 24 Mar 24 12:20:19 PM PDT 24 222324855 ps
T1110 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1155886924 Mar 24 12:18:54 PM PDT 24 Mar 24 12:18:55 PM PDT 24 32882721 ps
T109 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1535393422 Mar 24 12:22:23 PM PDT 24 Mar 24 12:22:25 PM PDT 24 309694397 ps
T114 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.494345595 Mar 24 12:20:52 PM PDT 24 Mar 24 12:20:54 PM PDT 24 269754249 ps
T148 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2079377618 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:06 PM PDT 24 44785831 ps
T149 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1460607772 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:54 PM PDT 24 19459371 ps
T219 /workspace/coverage/cover_reg_top/46.i2c_intr_test.985902912 Mar 24 12:18:52 PM PDT 24 Mar 24 12:18:52 PM PDT 24 91021396 ps
T223 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2931246425 Mar 24 12:20:59 PM PDT 24 Mar 24 12:21:00 PM PDT 24 16291261 ps
T120 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3087154822 Mar 24 12:19:09 PM PDT 24 Mar 24 12:19:11 PM PDT 24 78415886 ps
T128 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1014992107 Mar 24 12:20:29 PM PDT 24 Mar 24 12:20:30 PM PDT 24 189906338 ps
T220 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1077280777 Mar 24 12:18:54 PM PDT 24 Mar 24 12:18:55 PM PDT 24 23190377 ps
T1111 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3289183272 Mar 24 12:19:56 PM PDT 24 Mar 24 12:19:58 PM PDT 24 90000877 ps
T110 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3540912059 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:07 PM PDT 24 272207262 ps
T1112 /workspace/coverage/cover_reg_top/15.i2c_intr_test.689312997 Mar 24 12:20:30 PM PDT 24 Mar 24 12:20:30 PM PDT 24 74259781 ps
T1113 /workspace/coverage/cover_reg_top/16.i2c_intr_test.841532851 Mar 24 12:20:13 PM PDT 24 Mar 24 12:20:14 PM PDT 24 50990867 ps
T150 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3225792355 Mar 24 12:20:02 PM PDT 24 Mar 24 12:20:04 PM PDT 24 36226879 ps
T152 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4164152225 Mar 24 12:20:35 PM PDT 24 Mar 24 12:20:36 PM PDT 24 55823116 ps
T121 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1520041817 Mar 24 12:21:43 PM PDT 24 Mar 24 12:21:45 PM PDT 24 548041541 ps
T221 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2298276299 Mar 24 12:18:54 PM PDT 24 Mar 24 12:18:55 PM PDT 24 22836340 ps
T151 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1330233630 Mar 24 12:22:11 PM PDT 24 Mar 24 12:22:13 PM PDT 24 88690741 ps
T1114 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1957041057 Mar 24 12:17:32 PM PDT 24 Mar 24 12:17:33 PM PDT 24 50521908 ps
T131 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.4173524259 Mar 24 12:20:02 PM PDT 24 Mar 24 12:20:04 PM PDT 24 26337430 ps
T1115 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3267758904 Mar 24 12:16:28 PM PDT 24 Mar 24 12:16:28 PM PDT 24 30113165 ps
T1116 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2298053928 Mar 24 12:17:17 PM PDT 24 Mar 24 12:17:18 PM PDT 24 62314182 ps
T1117 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1324819241 Mar 24 12:18:45 PM PDT 24 Mar 24 12:18:47 PM PDT 24 42196338 ps
T1118 /workspace/coverage/cover_reg_top/28.i2c_intr_test.516672927 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:13 PM PDT 24 82583081 ps
T1119 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3300673080 Mar 24 12:18:11 PM PDT 24 Mar 24 12:18:12 PM PDT 24 15781111 ps
T1120 /workspace/coverage/cover_reg_top/40.i2c_intr_test.812400448 Mar 24 12:19:54 PM PDT 24 Mar 24 12:19:55 PM PDT 24 26376920 ps
T1121 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3012277117 Mar 24 12:17:47 PM PDT 24 Mar 24 12:17:48 PM PDT 24 76066242 ps
T1122 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1294079161 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:14 PM PDT 24 19958137 ps
T1123 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3762324189 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 35693515 ps
T1124 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1184352331 Mar 24 12:17:34 PM PDT 24 Mar 24 12:17:34 PM PDT 24 49168598 ps
T1125 /workspace/coverage/cover_reg_top/45.i2c_intr_test.431240561 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:13 PM PDT 24 22590997 ps
T153 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3718522021 Mar 24 12:19:09 PM PDT 24 Mar 24 12:19:10 PM PDT 24 80893279 ps
T132 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1201296069 Mar 24 12:21:54 PM PDT 24 Mar 24 12:21:55 PM PDT 24 17477078 ps
T222 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3095619993 Mar 24 12:20:45 PM PDT 24 Mar 24 12:20:46 PM PDT 24 18332664 ps
T1126 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1833696957 Mar 24 12:18:34 PM PDT 24 Mar 24 12:18:35 PM PDT 24 54784773 ps
T1127 /workspace/coverage/cover_reg_top/4.i2c_intr_test.726595976 Mar 24 12:17:17 PM PDT 24 Mar 24 12:17:18 PM PDT 24 38281816 ps
T133 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3378335440 Mar 24 12:21:45 PM PDT 24 Mar 24 12:21:46 PM PDT 24 78800973 ps
T1128 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3386572910 Mar 24 12:22:32 PM PDT 24 Mar 24 12:22:33 PM PDT 24 52320589 ps
T122 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2914551069 Mar 24 12:17:17 PM PDT 24 Mar 24 12:17:19 PM PDT 24 433813286 ps
T1129 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.931690301 Mar 24 12:20:28 PM PDT 24 Mar 24 12:20:32 PM PDT 24 757765414 ps
T1130 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1688052396 Mar 24 12:18:04 PM PDT 24 Mar 24 12:18:05 PM PDT 24 76038848 ps
T134 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.10447298 Mar 24 12:17:24 PM PDT 24 Mar 24 12:17:25 PM PDT 24 36671268 ps
T135 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2332377177 Mar 24 12:17:44 PM PDT 24 Mar 24 12:17:45 PM PDT 24 62469208 ps
T124 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2649942710 Mar 24 12:22:19 PM PDT 24 Mar 24 12:22:21 PM PDT 24 100729026 ps
T136 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4077161766 Mar 24 12:17:10 PM PDT 24 Mar 24 12:17:11 PM PDT 24 19342006 ps
T125 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.204158045 Mar 24 12:21:43 PM PDT 24 Mar 24 12:21:45 PM PDT 24 487968632 ps
T137 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4254710339 Mar 24 12:19:43 PM PDT 24 Mar 24 12:19:44 PM PDT 24 63159799 ps
T1131 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.911737177 Mar 24 12:20:13 PM PDT 24 Mar 24 12:20:14 PM PDT 24 63185487 ps
T115 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1583851382 Mar 24 12:22:12 PM PDT 24 Mar 24 12:22:13 PM PDT 24 75067341 ps
T1132 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3165988479 Mar 24 12:20:35 PM PDT 24 Mar 24 12:20:37 PM PDT 24 978079314 ps
T1133 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1839816037 Mar 24 12:21:51 PM PDT 24 Mar 24 12:21:52 PM PDT 24 42114462 ps
T1134 /workspace/coverage/cover_reg_top/37.i2c_intr_test.351350897 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 55369734 ps
T138 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1518975305 Mar 24 12:22:16 PM PDT 24 Mar 24 12:22:18 PM PDT 24 76491441 ps
T1135 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2175671600 Mar 24 12:17:55 PM PDT 24 Mar 24 12:17:57 PM PDT 24 81874435 ps
T126 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2417209307 Mar 24 12:18:00 PM PDT 24 Mar 24 12:18:02 PM PDT 24 51966686 ps
T139 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1255545955 Mar 24 12:18:54 PM PDT 24 Mar 24 12:18:56 PM PDT 24 254135302 ps
T1136 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1279243028 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:03 PM PDT 24 53449715 ps
T1137 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1829520673 Mar 24 12:18:54 PM PDT 24 Mar 24 12:18:57 PM PDT 24 547091713 ps
T1138 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.668376113 Mar 24 12:22:12 PM PDT 24 Mar 24 12:22:13 PM PDT 24 24259707 ps
T1139 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1030581169 Mar 24 12:22:12 PM PDT 24 Mar 24 12:22:14 PM PDT 24 63954776 ps
T1140 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1425883350 Mar 24 12:22:28 PM PDT 24 Mar 24 12:22:30 PM PDT 24 34661756 ps
T1141 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1192475459 Mar 24 12:18:18 PM PDT 24 Mar 24 12:18:20 PM PDT 24 37041241 ps
T1142 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1068061377 Mar 24 12:20:34 PM PDT 24 Mar 24 12:20:35 PM PDT 24 41102610 ps
T1143 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1737206327 Mar 24 12:17:05 PM PDT 24 Mar 24 12:17:08 PM PDT 24 635956023 ps
T111 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1712221107 Mar 24 12:20:17 PM PDT 24 Mar 24 12:20:19 PM PDT 24 464780083 ps
T140 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1285918672 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:10 PM PDT 24 20925309 ps
T1144 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.28550351 Mar 24 12:20:30 PM PDT 24 Mar 24 12:20:31 PM PDT 24 128966725 ps
T116 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.533370604 Mar 24 12:20:02 PM PDT 24 Mar 24 12:20:04 PM PDT 24 131335227 ps
T1145 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2593969031 Mar 24 12:19:56 PM PDT 24 Mar 24 12:19:58 PM PDT 24 40879287 ps
T112 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3728250897 Mar 24 12:20:53 PM PDT 24 Mar 24 12:20:55 PM PDT 24 345222179 ps
T1146 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2135386344 Mar 24 12:22:32 PM PDT 24 Mar 24 12:22:33 PM PDT 24 249043300 ps
T1147 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2669422404 Mar 24 12:19:34 PM PDT 24 Mar 24 12:19:35 PM PDT 24 46059265 ps
T1148 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.991889452 Mar 24 12:18:31 PM PDT 24 Mar 24 12:18:32 PM PDT 24 36758440 ps
T1149 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1665619370 Mar 24 12:19:21 PM PDT 24 Mar 24 12:19:24 PM PDT 24 481177845 ps
T1150 /workspace/coverage/cover_reg_top/31.i2c_intr_test.433012555 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 131604067 ps
T1151 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1112031230 Mar 24 12:18:58 PM PDT 24 Mar 24 12:18:59 PM PDT 24 14992140 ps
T1152 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4014890237 Mar 24 12:20:38 PM PDT 24 Mar 24 12:20:39 PM PDT 24 26227329 ps
T1153 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.4222928091 Mar 24 12:17:19 PM PDT 24 Mar 24 12:17:20 PM PDT 24 20382324 ps
T1154 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4124815728 Mar 24 12:22:04 PM PDT 24 Mar 24 12:22:05 PM PDT 24 91846169 ps
T118 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2693256595 Mar 24 12:20:17 PM PDT 24 Mar 24 12:20:19 PM PDT 24 149154162 ps
T1155 /workspace/coverage/cover_reg_top/35.i2c_intr_test.269561323 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 16347409 ps
T1156 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2461738187 Mar 24 12:21:51 PM PDT 24 Mar 24 12:21:52 PM PDT 24 477840638 ps
T123 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.846688844 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:11 PM PDT 24 513838033 ps
T1157 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2943297409 Mar 24 12:18:56 PM PDT 24 Mar 24 12:18:57 PM PDT 24 21038757 ps
T1158 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2834639516 Mar 24 12:22:18 PM PDT 24 Mar 24 12:22:19 PM PDT 24 25058198 ps
T1159 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3402574648 Mar 24 12:17:05 PM PDT 24 Mar 24 12:17:07 PM PDT 24 48690685 ps
T1160 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.687615855 Mar 24 12:22:20 PM PDT 24 Mar 24 12:22:23 PM PDT 24 283400305 ps
T1161 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3034665612 Mar 24 12:18:31 PM PDT 24 Mar 24 12:18:33 PM PDT 24 153061018 ps
T1162 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.894665115 Mar 24 12:20:35 PM PDT 24 Mar 24 12:20:38 PM PDT 24 119186324 ps
T1163 /workspace/coverage/cover_reg_top/39.i2c_intr_test.4007715955 Mar 24 12:20:01 PM PDT 24 Mar 24 12:20:03 PM PDT 24 31221395 ps
T141 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1140753701 Mar 24 12:22:15 PM PDT 24 Mar 24 12:22:16 PM PDT 24 109179072 ps
T1164 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3232326975 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:13 PM PDT 24 17335434 ps
T119 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1386691367 Mar 24 12:21:44 PM PDT 24 Mar 24 12:21:45 PM PDT 24 85066167 ps
T1165 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1476126938 Mar 24 12:18:31 PM PDT 24 Mar 24 12:18:34 PM PDT 24 86423935 ps
T1166 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3085982856 Mar 24 12:18:12 PM PDT 24 Mar 24 12:18:13 PM PDT 24 48421364 ps
T142 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.490842038 Mar 24 12:21:41 PM PDT 24 Mar 24 12:21:42 PM PDT 24 18231495 ps
T1167 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3034971758 Mar 24 12:20:58 PM PDT 24 Mar 24 12:20:59 PM PDT 24 98105979 ps
T1168 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3257430641 Mar 24 12:17:18 PM PDT 24 Mar 24 12:17:19 PM PDT 24 95375636 ps
T1169 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3991820594 Mar 24 12:20:02 PM PDT 24 Mar 24 12:20:04 PM PDT 24 34925577 ps
T1170 /workspace/coverage/cover_reg_top/9.i2c_intr_test.4153689700 Mar 24 12:20:43 PM PDT 24 Mar 24 12:20:44 PM PDT 24 35324831 ps
T113 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2074517675 Mar 24 12:18:06 PM PDT 24 Mar 24 12:18:09 PM PDT 24 419088685 ps
T1171 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2800057649 Mar 24 12:21:07 PM PDT 24 Mar 24 12:21:08 PM PDT 24 17311573 ps
T1172 /workspace/coverage/cover_reg_top/25.i2c_intr_test.194725462 Mar 24 12:21:31 PM PDT 24 Mar 24 12:21:32 PM PDT 24 18272321 ps
T1173 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2194928378 Mar 24 12:17:50 PM PDT 24 Mar 24 12:17:52 PM PDT 24 151235593 ps
T1174 /workspace/coverage/cover_reg_top/0.i2c_intr_test.4215724525 Mar 24 12:19:39 PM PDT 24 Mar 24 12:19:40 PM PDT 24 15259207 ps
T1175 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3484127617 Mar 24 12:18:38 PM PDT 24 Mar 24 12:18:39 PM PDT 24 20733934 ps
T1176 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3162852270 Mar 24 12:21:08 PM PDT 24 Mar 24 12:21:09 PM PDT 24 66896415 ps
T1177 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1258138744 Mar 24 12:18:40 PM PDT 24 Mar 24 12:18:42 PM PDT 24 46900280 ps
T1178 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2277528804 Mar 24 12:16:52 PM PDT 24 Mar 24 12:16:53 PM PDT 24 128664256 ps
T1179 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3260970612 Mar 24 12:20:44 PM PDT 24 Mar 24 12:20:46 PM PDT 24 38827210 ps
T1180 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3225196786 Mar 24 12:20:03 PM PDT 24 Mar 24 12:20:05 PM PDT 24 78091718 ps
T1181 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1834483765 Mar 24 12:20:18 PM PDT 24 Mar 24 12:20:19 PM PDT 24 27016475 ps
T1182 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3015169657 Mar 24 12:20:12 PM PDT 24 Mar 24 12:20:13 PM PDT 24 26826508 ps
T1183 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3714835502 Mar 24 12:18:52 PM PDT 24 Mar 24 12:18:53 PM PDT 24 15828357 ps
T1184 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4268460046 Mar 24 12:21:56 PM PDT 24 Mar 24 12:21:58 PM PDT 24 51070984 ps
T1185 /workspace/coverage/cover_reg_top/20.i2c_intr_test.987624138 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:03 PM PDT 24 32424912 ps
T1186 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3946488227 Mar 24 12:20:28 PM PDT 24 Mar 24 12:20:29 PM PDT 24 42827670 ps
T1187 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2352587030 Mar 24 12:19:54 PM PDT 24 Mar 24 12:19:56 PM PDT 24 15337184 ps
T1188 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2594265777 Mar 24 12:20:29 PM PDT 24 Mar 24 12:20:30 PM PDT 24 224441238 ps
T1189 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2997263937 Mar 24 12:20:08 PM PDT 24 Mar 24 12:20:10 PM PDT 24 215214277 ps
T1190 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2746519462 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:04 PM PDT 24 131207416 ps
T127 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2910356253 Mar 24 12:19:24 PM PDT 24 Mar 24 12:19:25 PM PDT 24 151159259 ps
T1191 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3325466534 Mar 24 12:22:11 PM PDT 24 Mar 24 12:22:13 PM PDT 24 391599436 ps
T1192 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3696513274 Mar 24 12:20:29 PM PDT 24 Mar 24 12:20:30 PM PDT 24 107613928 ps
T1193 /workspace/coverage/cover_reg_top/7.i2c_intr_test.620941086 Mar 24 12:22:18 PM PDT 24 Mar 24 12:22:20 PM PDT 24 63389953 ps
T143 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3312328759 Mar 24 12:16:38 PM PDT 24 Mar 24 12:16:40 PM PDT 24 305603629 ps
T1194 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1012109636 Mar 24 12:18:07 PM PDT 24 Mar 24 12:18:08 PM PDT 24 16981215 ps
T1195 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2332654926 Mar 24 12:21:04 PM PDT 24 Mar 24 12:21:06 PM PDT 24 36380927 ps
T1196 /workspace/coverage/cover_reg_top/24.i2c_intr_test.328350769 Mar 24 12:21:02 PM PDT 24 Mar 24 12:21:03 PM PDT 24 16909111 ps
T1197 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.667661574 Mar 24 12:20:13 PM PDT 24 Mar 24 12:20:16 PM PDT 24 181800066 ps
T1198 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.292396218 Mar 24 12:22:04 PM PDT 24 Mar 24 12:22:06 PM PDT 24 146051581 ps
T1199 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.707874548 Mar 24 12:22:24 PM PDT 24 Mar 24 12:22:26 PM PDT 24 283033761 ps
T1200 /workspace/coverage/cover_reg_top/27.i2c_intr_test.705663406 Mar 24 12:20:44 PM PDT 24 Mar 24 12:20:46 PM PDT 24 47931449 ps
T1201 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1721546970 Mar 24 12:18:18 PM PDT 24 Mar 24 12:18:19 PM PDT 24 20312450 ps
T1202 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2472440731 Mar 24 12:22:33 PM PDT 24 Mar 24 12:22:34 PM PDT 24 16138265 ps
T1203 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1304896811 Mar 24 12:19:43 PM PDT 24 Mar 24 12:19:45 PM PDT 24 80580691 ps
T1204 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2026249687 Mar 24 12:17:11 PM PDT 24 Mar 24 12:17:13 PM PDT 24 49236365 ps
T1205 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3543258205 Mar 24 12:21:54 PM PDT 24 Mar 24 12:21:55 PM PDT 24 46579643 ps
T1206 /workspace/coverage/cover_reg_top/14.i2c_intr_test.2458839703 Mar 24 12:20:30 PM PDT 24 Mar 24 12:20:30 PM PDT 24 19560408 ps

Test location /workspace/coverage/default/6.i2c_target_smoke.2327080028
Short name T4
Test name
Test status
Simulation time 5042434390 ps
CPU time 22.04 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:49:19 PM PDT 24
Peak memory 204256 kb
Host smart-a8a13872-35fe-4001-88bd-64020d77e24b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327080028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2327080028
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1713301194
Short name T47
Test name
Test status
Simulation time 2110374686 ps
CPU time 59.21 seconds
Started Mar 24 02:48:58 PM PDT 24
Finished Mar 24 02:49:57 PM PDT 24
Peak memory 355080 kb
Host smart-6aa506ff-a0eb-46ea-b9cf-80bc2417c4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713301194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1713301194
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.1916048959
Short name T77
Test name
Test status
Simulation time 6468901814 ps
CPU time 251.17 seconds
Started Mar 24 02:50:59 PM PDT 24
Finished Mar 24 02:55:10 PM PDT 24
Peak memory 923784 kb
Host smart-b1ad7ab8-96e3-4ede-815c-8f4de2f6145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916048959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1916048959
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.777507494
Short name T51
Test name
Test status
Simulation time 10073801030 ps
CPU time 96.47 seconds
Started Mar 24 02:50:10 PM PDT 24
Finished Mar 24 02:51:46 PM PDT 24
Peak memory 601672 kb
Host smart-372c1b20-1c7f-44bb-88b0-65605c193ff5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777507494 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.777507494
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3599862249
Short name T105
Test name
Test status
Simulation time 36291645 ps
CPU time 1.02 seconds
Started Mar 24 12:20:11 PM PDT 24
Finished Mar 24 12:20:15 PM PDT 24
Peak memory 202264 kb
Host smart-e38f1cfc-d439-4be7-a974-0a48a275da9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599862249 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3599862249
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.230691904
Short name T96
Test name
Test status
Simulation time 64605690 ps
CPU time 0.9 seconds
Started Mar 24 02:48:50 PM PDT 24
Finished Mar 24 02:48:51 PM PDT 24
Peak memory 222656 kb
Host smart-1eb2a87c-cdb6-4b85-9d87-f6f4c3a192c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230691904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.230691904
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/46.i2c_host_override.1090179875
Short name T163
Test name
Test status
Simulation time 20373968 ps
CPU time 0.66 seconds
Started Mar 24 02:53:14 PM PDT 24
Finished Mar 24 02:53:15 PM PDT 24
Peak memory 203808 kb
Host smart-1d647c0a-1b9e-4e1a-8d4e-ce6be2b9021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090179875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1090179875
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.4162080912
Short name T43
Test name
Test status
Simulation time 134431616 ps
CPU time 1.36 seconds
Started Mar 24 02:50:05 PM PDT 24
Finished Mar 24 02:50:07 PM PDT 24
Peak memory 212436 kb
Host smart-4a1a0e16-f880-4cb5-84a5-5bf60f700b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162080912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.4162080912
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1442778910
Short name T39
Test name
Test status
Simulation time 7939859682 ps
CPU time 11.19 seconds
Started Mar 24 02:51:20 PM PDT 24
Finished Mar 24 02:51:31 PM PDT 24
Peak memory 257760 kb
Host smart-e00d0d96-2d35-437a-bad4-04e8d551105c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442778910 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1442778910
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.969194711
Short name T49
Test name
Test status
Simulation time 750691311 ps
CPU time 5 seconds
Started Mar 24 02:50:10 PM PDT 24
Finished Mar 24 02:50:16 PM PDT 24
Peak memory 204136 kb
Host smart-742e8832-c69b-4d73-bbe3-6601ecc38cc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969194711 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_unexp_stop.969194711
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_host_perf.171845282
Short name T15
Test name
Test status
Simulation time 1464554413 ps
CPU time 20.44 seconds
Started Mar 24 02:48:32 PM PDT 24
Finished Mar 24 02:48:53 PM PDT 24
Peak memory 271076 kb
Host smart-a1e41fa6-c351-40bd-bd79-bb56dfd92a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171845282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.171845282
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.3652854803
Short name T197
Test name
Test status
Simulation time 49774323116 ps
CPU time 2175.01 seconds
Started Mar 24 02:53:01 PM PDT 24
Finished Mar 24 03:29:17 PM PDT 24
Peak memory 2446136 kb
Host smart-a785ef1e-a88c-4a79-aa13-b84857478b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652854803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.3652854803
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2565519924
Short name T130
Test name
Test status
Simulation time 16775166 ps
CPU time 0.67 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:53 PM PDT 24
Peak memory 203072 kb
Host smart-01259639-96cc-416c-9d57-c40774d0a70b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565519924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2565519924
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3498987687
Short name T18
Test name
Test status
Simulation time 17214079705 ps
CPU time 47.48 seconds
Started Mar 24 02:52:18 PM PDT 24
Finished Mar 24 02:53:06 PM PDT 24
Peak memory 204272 kb
Host smart-028d74c2-7d83-4c9d-ae5a-40e90ff70803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498987687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3498987687
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.725646748
Short name T74
Test name
Test status
Simulation time 12009205344 ps
CPU time 253.04 seconds
Started Mar 24 02:50:39 PM PDT 24
Finished Mar 24 02:54:52 PM PDT 24
Peak memory 1706584 kb
Host smart-fdcd39e2-2d0c-4dd7-9ee7-d7d925fdb4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725646748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.725646748
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1768533748
Short name T107
Test name
Test status
Simulation time 417093687 ps
CPU time 1.9 seconds
Started Mar 24 12:21:56 PM PDT 24
Finished Mar 24 12:21:58 PM PDT 24
Peak memory 203004 kb
Host smart-a9bfb62a-a434-4ab8-94e3-457986ce5635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768533748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1768533748
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2371464897
Short name T26
Test name
Test status
Simulation time 336879053 ps
CPU time 2.31 seconds
Started Mar 24 02:50:15 PM PDT 24
Finished Mar 24 02:50:17 PM PDT 24
Peak memory 204100 kb
Host smart-35a620e7-0966-4a9a-97a0-8d8fabf5aa9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371464897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2371464897
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1556417618
Short name T11
Test name
Test status
Simulation time 1421399826 ps
CPU time 7.37 seconds
Started Mar 24 02:48:17 PM PDT 24
Finished Mar 24 02:48:25 PM PDT 24
Peak memory 212412 kb
Host smart-35822ec0-e442-4bd3-b025-6439d3b8eae8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556417618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1556417618
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3560249148
Short name T98
Test name
Test status
Simulation time 44296951 ps
CPU time 2.1 seconds
Started Mar 24 12:21:54 PM PDT 24
Finished Mar 24 12:21:56 PM PDT 24
Peak memory 203384 kb
Host smart-ac478cf5-41cc-46f1-9a3f-720f7210b776
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560249148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3560249148
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.4078588416
Short name T8
Test name
Test status
Simulation time 628234344 ps
CPU time 1.17 seconds
Started Mar 24 02:50:46 PM PDT 24
Finished Mar 24 02:50:48 PM PDT 24
Peak memory 204176 kb
Host smart-ae02de08-bf50-4138-8240-a9c5b17e5600
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078588416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.4078588416
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2430941171
Short name T40
Test name
Test status
Simulation time 611429225 ps
CPU time 1.51 seconds
Started Mar 24 02:50:29 PM PDT 24
Finished Mar 24 02:50:31 PM PDT 24
Peak memory 204048 kb
Host smart-171c576e-4680-4450-8dba-385e12f61781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430941171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2430941171
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1469834079
Short name T183
Test name
Test status
Simulation time 3609764324 ps
CPU time 195.35 seconds
Started Mar 24 02:49:25 PM PDT 24
Finished Mar 24 02:52:40 PM PDT 24
Peak memory 204260 kb
Host smart-405f331b-efc8-486e-83ae-b07d9382166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469834079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1469834079
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1077280777
Short name T220
Test name
Test status
Simulation time 23190377 ps
CPU time 0.71 seconds
Started Mar 24 12:18:54 PM PDT 24
Finished Mar 24 12:18:55 PM PDT 24
Peak memory 200592 kb
Host smart-0c4c3c76-0382-410d-8c36-90e4f9b9746e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077280777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1077280777
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1976622812
Short name T93
Test name
Test status
Simulation time 29110262 ps
CPU time 0.64 seconds
Started Mar 24 02:49:32 PM PDT 24
Finished Mar 24 02:49:33 PM PDT 24
Peak memory 203928 kb
Host smart-8141d6c7-ad63-4d28-9ce0-353445b1ce64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976622812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1976622812
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1327506965
Short name T202
Test name
Test status
Simulation time 100062576 ps
CPU time 0.88 seconds
Started Mar 24 02:51:32 PM PDT 24
Finished Mar 24 02:51:33 PM PDT 24
Peak memory 203932 kb
Host smart-eb03717b-8755-4d14-9e19-e4afeea037b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327506965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1327506965
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1656437798
Short name T211
Test name
Test status
Simulation time 1099038118 ps
CPU time 39.33 seconds
Started Mar 24 02:48:45 PM PDT 24
Finished Mar 24 02:49:24 PM PDT 24
Peak memory 281604 kb
Host smart-7e0a6e0d-9e3c-4cef-8344-04503601901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656437798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1656437798
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.927393650
Short name T322
Test name
Test status
Simulation time 865088839 ps
CPU time 6.43 seconds
Started Mar 24 02:49:31 PM PDT 24
Finished Mar 24 02:49:37 PM PDT 24
Peak memory 221376 kb
Host smart-c4a86cf2-c638-413d-87cc-9573f28f0e26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927393650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
927393650
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.571582152
Short name T22
Test name
Test status
Simulation time 3472540383 ps
CPU time 4.38 seconds
Started Mar 24 02:49:36 PM PDT 24
Finished Mar 24 02:49:40 PM PDT 24
Peak memory 204480 kb
Host smart-952c8cca-5d70-4072-a79a-c54479618f88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571582152 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.571582152
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.243422893
Short name T58
Test name
Test status
Simulation time 1996819593 ps
CPU time 73.11 seconds
Started Mar 24 02:50:25 PM PDT 24
Finished Mar 24 02:51:38 PM PDT 24
Peak memory 690556 kb
Host smart-9510056d-fc0f-49a2-b8b5-a719e09901e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243422893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.243422893
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2074517675
Short name T113
Test name
Test status
Simulation time 419088685 ps
CPU time 2.12 seconds
Started Mar 24 12:18:06 PM PDT 24
Finished Mar 24 12:18:09 PM PDT 24
Peak memory 203468 kb
Host smart-b2d66f2a-b9f0-44a6-825d-d4b9a1cae340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074517675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2074517675
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2355894433
Short name T60
Test name
Test status
Simulation time 2277044746 ps
CPU time 80.55 seconds
Started Mar 24 02:48:45 PM PDT 24
Finished Mar 24 02:50:06 PM PDT 24
Peak memory 748052 kb
Host smart-304c8769-d48c-467d-8bd1-abeee1d20fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355894433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2355894433
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3726685222
Short name T162
Test name
Test status
Simulation time 10567816345 ps
CPU time 78.41 seconds
Started Mar 24 02:50:01 PM PDT 24
Finished Mar 24 02:51:19 PM PDT 24
Peak memory 941820 kb
Host smart-c26ff6c0-81b6-4944-a5ab-3c6546033c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726685222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3726685222
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.4276320643
Short name T218
Test name
Test status
Simulation time 16611043 ps
CPU time 0.73 seconds
Started Mar 24 12:19:36 PM PDT 24
Finished Mar 24 12:19:37 PM PDT 24
Peak memory 203424 kb
Host smart-6f4d60be-098b-4837-81c9-8b44d31540da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276320643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4276320643
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.5560004
Short name T192
Test name
Test status
Simulation time 10271138711 ps
CPU time 20.1 seconds
Started Mar 24 02:51:42 PM PDT 24
Finished Mar 24 02:52:03 PM PDT 24
Peak memory 309072 kb
Host smart-ecfc0889-2705-41b1-83b5-0af4ad7e0ad9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5560004 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_fifo_reset_acq.5560004
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2311776845
Short name T188
Test name
Test status
Simulation time 157215668 ps
CPU time 1.4 seconds
Started Mar 24 02:52:30 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 212420 kb
Host smart-3cb6193b-aeb5-4a5b-aacd-e6f1e7d7b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311776845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2311776845
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.609815869
Short name T190
Test name
Test status
Simulation time 3045630961 ps
CPU time 63.78 seconds
Started Mar 24 02:53:03 PM PDT 24
Finished Mar 24 02:54:07 PM PDT 24
Peak memory 206532 kb
Host smart-36124fd6-d889-45ae-9bda-da2dc2b35ccd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609815869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.609815869
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2115874920
Short name T30
Test name
Test status
Simulation time 118587357 ps
CPU time 1.54 seconds
Started Mar 24 02:53:16 PM PDT 24
Finished Mar 24 02:53:18 PM PDT 24
Peak memory 212416 kb
Host smart-3be1242b-c299-4a8b-bc20-211627131e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115874920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2115874920
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3886488331
Short name T204
Test name
Test status
Simulation time 108487502 ps
CPU time 0.89 seconds
Started Mar 24 02:53:36 PM PDT 24
Finished Mar 24 02:53:38 PM PDT 24
Peak memory 203972 kb
Host smart-aeb960de-8f3b-45ec-b433-ab923338d335
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886488331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3886488331
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.846688844
Short name T123
Test name
Test status
Simulation time 513838033 ps
CPU time 2.17 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:11 PM PDT 24
Peak memory 203220 kb
Host smart-24c52bd9-af6e-4259-b010-3499d8c995dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846688844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.846688844
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2795493687
Short name T89
Test name
Test status
Simulation time 10085708167 ps
CPU time 15.04 seconds
Started Mar 24 02:51:21 PM PDT 24
Finished Mar 24 02:51:37 PM PDT 24
Peak memory 319376 kb
Host smart-df5e540f-c2cc-45ec-9df5-40821180a051
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795493687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2795493687
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1460720480
Short name T227
Test name
Test status
Simulation time 11172137956 ps
CPU time 7.05 seconds
Started Mar 24 02:50:11 PM PDT 24
Finished Mar 24 02:50:18 PM PDT 24
Peak memory 240552 kb
Host smart-f1c53486-da15-4a04-ac4b-136968ecf07f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460720480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.1460720480
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.730262921
Short name T206
Test name
Test status
Simulation time 1529883918 ps
CPU time 108.8 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:53:20 PM PDT 24
Peak memory 583844 kb
Host smart-86887cb5-e956-4634-bf28-a9f5f2fc09ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730262921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.730262921
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1761661088
Short name T214
Test name
Test status
Simulation time 10272694626 ps
CPU time 14.66 seconds
Started Mar 24 02:52:18 PM PDT 24
Finished Mar 24 02:52:33 PM PDT 24
Peak memory 290112 kb
Host smart-19303441-916a-4d3c-8484-0767efb2a5ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761661088 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1761661088
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2288029994
Short name T205
Test name
Test status
Simulation time 6272041324 ps
CPU time 246.13 seconds
Started Mar 24 02:53:17 PM PDT 24
Finished Mar 24 02:57:24 PM PDT 24
Peak memory 1718364 kb
Host smart-fea024a7-2d63-48fc-aacf-400965d8525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288029994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2288029994
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.4133392136
Short name T210
Test name
Test status
Simulation time 3460548085 ps
CPU time 103.86 seconds
Started Mar 24 02:49:03 PM PDT 24
Finished Mar 24 02:50:47 PM PDT 24
Peak memory 1064920 kb
Host smart-cb80b08a-9fcb-45f6-a5d2-ac8aef27d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133392136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.4133392136
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2944169792
Short name T914
Test name
Test status
Simulation time 10083249882 ps
CPU time 35.18 seconds
Started Mar 24 02:48:22 PM PDT 24
Finished Mar 24 02:48:58 PM PDT 24
Peak memory 468508 kb
Host smart-604c0141-3c2e-49f6-a752-55246fe59f01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944169792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2944169792
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.85045315
Short name T97
Test name
Test status
Simulation time 308568227 ps
CPU time 1.81 seconds
Started Mar 24 12:22:14 PM PDT 24
Finished Mar 24 12:22:16 PM PDT 24
Peak memory 202616 kb
Host smart-b45a1bce-185e-4071-a6ea-3e9ca769a5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85045315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.85045315
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3540912059
Short name T110
Test name
Test status
Simulation time 272207262 ps
CPU time 1.97 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:07 PM PDT 24
Peak memory 201552 kb
Host smart-2d37873c-1005-4468-b471-3b1789746613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540912059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3540912059
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1386691367
Short name T119
Test name
Test status
Simulation time 85066167 ps
CPU time 1.31 seconds
Started Mar 24 12:21:44 PM PDT 24
Finished Mar 24 12:21:45 PM PDT 24
Peak memory 203300 kb
Host smart-e25e3581-bcb1-4c36-9905-cf3640dc2503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386691367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1386691367
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.1667559425
Short name T83
Test name
Test status
Simulation time 10073756976 ps
CPU time 29.88 seconds
Started Mar 24 02:48:10 PM PDT 24
Finished Mar 24 02:48:40 PM PDT 24
Peak memory 372968 kb
Host smart-bcb83f81-4715-4c32-9297-756e0f47c6ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667559425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.1667559425
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1930139809
Short name T129
Test name
Test status
Simulation time 107398006 ps
CPU time 1.52 seconds
Started Mar 24 12:20:11 PM PDT 24
Finished Mar 24 12:20:15 PM PDT 24
Peak memory 202288 kb
Host smart-f4bc14bb-c8d6-45a8-b571-8a54cec4d6bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930139809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1930139809
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.931690301
Short name T1129
Test name
Test status
Simulation time 757765414 ps
CPU time 4.53 seconds
Started Mar 24 12:20:28 PM PDT 24
Finished Mar 24 12:20:32 PM PDT 24
Peak memory 203308 kb
Host smart-a36b422c-558a-4d52-abac-1cf518e86093
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931690301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.931690301
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1140753701
Short name T141
Test name
Test status
Simulation time 109179072 ps
CPU time 0.72 seconds
Started Mar 24 12:22:15 PM PDT 24
Finished Mar 24 12:22:16 PM PDT 24
Peak memory 202852 kb
Host smart-5c1f5475-4baf-4765-9d17-690ab7c930d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140753701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1140753701
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3386572910
Short name T1128
Test name
Test status
Simulation time 52320589 ps
CPU time 0.68 seconds
Started Mar 24 12:22:32 PM PDT 24
Finished Mar 24 12:22:33 PM PDT 24
Peak memory 203048 kb
Host smart-8a2f7e62-54bf-4444-9146-6266437b2906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386572910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3386572910
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.4215724525
Short name T1174
Test name
Test status
Simulation time 15259207 ps
CPU time 0.74 seconds
Started Mar 24 12:19:39 PM PDT 24
Finished Mar 24 12:19:40 PM PDT 24
Peak memory 203044 kb
Host smart-5af43e25-10bc-4628-9030-3dda944e2da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215724525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.4215724525
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3267758904
Short name T1115
Test name
Test status
Simulation time 30113165 ps
CPU time 0.9 seconds
Started Mar 24 12:16:28 PM PDT 24
Finished Mar 24 12:16:28 PM PDT 24
Peak memory 203096 kb
Host smart-43eb1db6-02a5-4dbf-a957-ecda8e424873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267758904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3267758904
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.494345595
Short name T114
Test name
Test status
Simulation time 269754249 ps
CPU time 2.14 seconds
Started Mar 24 12:20:52 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 203320 kb
Host smart-8d0883df-198e-4926-85f5-6466100da3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494345595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.494345595
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3312328759
Short name T143
Test name
Test status
Simulation time 305603629 ps
CPU time 1.58 seconds
Started Mar 24 12:16:38 PM PDT 24
Finished Mar 24 12:16:40 PM PDT 24
Peak memory 203800 kb
Host smart-34dfcf4b-db69-43ef-a8d9-b34541ce6581
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312328759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3312328759
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.687615855
Short name T1160
Test name
Test status
Simulation time 283400305 ps
CPU time 2.88 seconds
Started Mar 24 12:22:20 PM PDT 24
Finished Mar 24 12:22:23 PM PDT 24
Peak memory 203228 kb
Host smart-94e25428-d81b-4830-8405-a962ab4b124c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687615855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.687615855
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4254710339
Short name T137
Test name
Test status
Simulation time 63159799 ps
CPU time 0.68 seconds
Started Mar 24 12:19:43 PM PDT 24
Finished Mar 24 12:19:44 PM PDT 24
Peak memory 203540 kb
Host smart-cc87ce62-91c3-4aee-8ef8-6c3471cbc238
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254710339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4254710339
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2649942710
Short name T124
Test name
Test status
Simulation time 100729026 ps
CPU time 0.97 seconds
Started Mar 24 12:22:19 PM PDT 24
Finished Mar 24 12:22:21 PM PDT 24
Peak memory 203176 kb
Host smart-8d25a63c-c5c3-4b97-a588-513d63cdcd56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649942710 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2649942710
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.10447298
Short name T134
Test name
Test status
Simulation time 36671268 ps
CPU time 0.66 seconds
Started Mar 24 12:17:24 PM PDT 24
Finished Mar 24 12:17:25 PM PDT 24
Peak memory 203212 kb
Host smart-83120c73-4bd3-4080-8d64-bc6a313ac1c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10447298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.10447298
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3946488227
Short name T1186
Test name
Test status
Simulation time 42827670 ps
CPU time 0.62 seconds
Started Mar 24 12:20:28 PM PDT 24
Finished Mar 24 12:20:29 PM PDT 24
Peak memory 203020 kb
Host smart-c83eb23f-d921-45b7-98ef-f6e61040e536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946488227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3946488227
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2277528804
Short name T1178
Test name
Test status
Simulation time 128664256 ps
CPU time 0.86 seconds
Started Mar 24 12:16:52 PM PDT 24
Finished Mar 24 12:16:53 PM PDT 24
Peak memory 203576 kb
Host smart-f90aa8df-d5a8-4eb7-900f-c0376a35b2c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277528804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2277528804
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2175671600
Short name T1135
Test name
Test status
Simulation time 81874435 ps
CPU time 1.43 seconds
Started Mar 24 12:17:55 PM PDT 24
Finished Mar 24 12:17:57 PM PDT 24
Peak memory 203488 kb
Host smart-258f4aa1-3abe-4df1-8156-342b59832784
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175671600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2175671600
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4014890237
Short name T1152
Test name
Test status
Simulation time 26227329 ps
CPU time 0.79 seconds
Started Mar 24 12:20:38 PM PDT 24
Finished Mar 24 12:20:39 PM PDT 24
Peak memory 203152 kb
Host smart-745ef450-b790-46a5-bbed-970429b26dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014890237 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.4014890237
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1721546970
Short name T1201
Test name
Test status
Simulation time 20312450 ps
CPU time 0.78 seconds
Started Mar 24 12:18:18 PM PDT 24
Finished Mar 24 12:18:19 PM PDT 24
Peak memory 203216 kb
Host smart-3d91419b-1e49-4c49-bfff-8c1fa7caa925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721546970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1721546970
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3714835502
Short name T1183
Test name
Test status
Simulation time 15828357 ps
CPU time 0.69 seconds
Started Mar 24 12:18:52 PM PDT 24
Finished Mar 24 12:18:53 PM PDT 24
Peak memory 203080 kb
Host smart-73a95679-423b-4dec-bc6a-d9569847c0a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714835502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3714835502
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3034971758
Short name T1167
Test name
Test status
Simulation time 98105979 ps
CPU time 0.78 seconds
Started Mar 24 12:20:58 PM PDT 24
Finished Mar 24 12:20:59 PM PDT 24
Peak memory 203040 kb
Host smart-430db514-9472-4447-96c5-d1bd69ef33ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034971758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3034971758
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1665619370
Short name T1149
Test name
Test status
Simulation time 481177845 ps
CPU time 2.48 seconds
Started Mar 24 12:19:21 PM PDT 24
Finished Mar 24 12:19:24 PM PDT 24
Peak memory 203436 kb
Host smart-8d488afa-3cbb-42aa-b085-13b907025a28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665619370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1665619370
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2194928378
Short name T1173
Test name
Test status
Simulation time 151235593 ps
CPU time 1.33 seconds
Started Mar 24 12:17:50 PM PDT 24
Finished Mar 24 12:17:52 PM PDT 24
Peak memory 203668 kb
Host smart-1ffe764a-8f20-4c80-a2a7-0b7860f57636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194928378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2194928378
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.4268460046
Short name T1184
Test name
Test status
Simulation time 51070984 ps
CPU time 1.3 seconds
Started Mar 24 12:21:56 PM PDT 24
Finished Mar 24 12:21:58 PM PDT 24
Peak memory 202496 kb
Host smart-e8321e9f-b895-4302-8707-1169b090c352
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268460046 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.4268460046
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2834639516
Short name T1158
Test name
Test status
Simulation time 25058198 ps
CPU time 0.79 seconds
Started Mar 24 12:22:18 PM PDT 24
Finished Mar 24 12:22:19 PM PDT 24
Peak memory 203088 kb
Host smart-382064a2-527c-4235-93e1-4cf7a0eda731
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834639516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2834639516
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3300673080
Short name T1119
Test name
Test status
Simulation time 15781111 ps
CPU time 0.8 seconds
Started Mar 24 12:18:11 PM PDT 24
Finished Mar 24 12:18:12 PM PDT 24
Peak memory 203420 kb
Host smart-49de73b7-2df4-4bee-aa13-23cfca580640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300673080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3300673080
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2439494519
Short name T147
Test name
Test status
Simulation time 222324855 ps
CPU time 1.07 seconds
Started Mar 24 12:20:18 PM PDT 24
Finished Mar 24 12:20:19 PM PDT 24
Peak memory 202460 kb
Host smart-f316d259-fc18-479f-9b23-76a26c79ef2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439494519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2439494519
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2417209307
Short name T126
Test name
Test status
Simulation time 51966686 ps
CPU time 2.53 seconds
Started Mar 24 12:18:00 PM PDT 24
Finished Mar 24 12:18:02 PM PDT 24
Peak memory 203820 kb
Host smart-2c6054af-284f-479a-9eac-043a3e5f9f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417209307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2417209307
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1425883350
Short name T1140
Test name
Test status
Simulation time 34661756 ps
CPU time 0.95 seconds
Started Mar 24 12:22:28 PM PDT 24
Finished Mar 24 12:22:30 PM PDT 24
Peak memory 203196 kb
Host smart-39ab2474-5371-490c-aa0a-9592e9fca729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425883350 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1425883350
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.1834483765
Short name T1181
Test name
Test status
Simulation time 27016475 ps
CPU time 0.77 seconds
Started Mar 24 12:20:18 PM PDT 24
Finished Mar 24 12:20:19 PM PDT 24
Peak memory 202236 kb
Host smart-b6bc7577-fda8-4cf4-b405-04b24885c2de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834483765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1834483765
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1012109636
Short name T1194
Test name
Test status
Simulation time 16981215 ps
CPU time 0.67 seconds
Started Mar 24 12:18:07 PM PDT 24
Finished Mar 24 12:18:08 PM PDT 24
Peak memory 203156 kb
Host smart-b5ac9143-4375-4238-a0de-e4844e6e082f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012109636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1012109636
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1688052396
Short name T1130
Test name
Test status
Simulation time 76038848 ps
CPU time 1 seconds
Started Mar 24 12:18:04 PM PDT 24
Finished Mar 24 12:18:05 PM PDT 24
Peak memory 203720 kb
Host smart-dece36a9-4412-4022-8021-4aee94a68b8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688052396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1688052396
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1030581169
Short name T1139
Test name
Test status
Simulation time 63954776 ps
CPU time 1.4 seconds
Started Mar 24 12:22:12 PM PDT 24
Finished Mar 24 12:22:14 PM PDT 24
Peak memory 203068 kb
Host smart-563f646f-6705-48e4-b93f-6cb227baa271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030581169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1030581169
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3087154822
Short name T120
Test name
Test status
Simulation time 78415886 ps
CPU time 1.38 seconds
Started Mar 24 12:19:09 PM PDT 24
Finished Mar 24 12:19:11 PM PDT 24
Peak memory 203724 kb
Host smart-7a96977e-24fb-4546-aa3f-5376c6881a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087154822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3087154822
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2135386344
Short name T1146
Test name
Test status
Simulation time 249043300 ps
CPU time 0.88 seconds
Started Mar 24 12:22:32 PM PDT 24
Finished Mar 24 12:22:33 PM PDT 24
Peak memory 203156 kb
Host smart-9574377c-3755-4e32-a534-0402272ad4c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135386344 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2135386344
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1201296069
Short name T132
Test name
Test status
Simulation time 17477078 ps
CPU time 0.73 seconds
Started Mar 24 12:21:54 PM PDT 24
Finished Mar 24 12:21:55 PM PDT 24
Peak memory 203064 kb
Host smart-4ea163c6-7849-4078-a200-5caa5d07ddde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201296069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1201296069
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3085982856
Short name T1166
Test name
Test status
Simulation time 48421364 ps
CPU time 0.69 seconds
Started Mar 24 12:18:12 PM PDT 24
Finished Mar 24 12:18:13 PM PDT 24
Peak memory 203436 kb
Host smart-379fd214-12b8-43a7-af63-222709606bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085982856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3085982856
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3391080366
Short name T144
Test name
Test status
Simulation time 275726608 ps
CPU time 1.09 seconds
Started Mar 24 12:18:52 PM PDT 24
Finished Mar 24 12:18:53 PM PDT 24
Peak memory 203432 kb
Host smart-66747e30-96da-4847-a64d-7153516d798b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391080366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3391080366
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1192475459
Short name T1141
Test name
Test status
Simulation time 37041241 ps
CPU time 1.91 seconds
Started Mar 24 12:18:18 PM PDT 24
Finished Mar 24 12:18:20 PM PDT 24
Peak memory 203772 kb
Host smart-4a4d44be-91ce-48f3-b6ba-d5923e61a76d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192475459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1192475459
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3758553534
Short name T108
Test name
Test status
Simulation time 251925118 ps
CPU time 1.29 seconds
Started Mar 24 12:19:09 PM PDT 24
Finished Mar 24 12:19:10 PM PDT 24
Peak memory 203344 kb
Host smart-6c42e675-c42b-4b23-b47c-055a26a3c7eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758553534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3758553534
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.911737177
Short name T1131
Test name
Test status
Simulation time 63185487 ps
CPU time 0.78 seconds
Started Mar 24 12:20:13 PM PDT 24
Finished Mar 24 12:20:14 PM PDT 24
Peak memory 202564 kb
Host smart-9475b42d-6525-4d2e-9b8e-055e2e6b3a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911737177 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.911737177
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4164152225
Short name T152
Test name
Test status
Simulation time 55823116 ps
CPU time 0.68 seconds
Started Mar 24 12:20:35 PM PDT 24
Finished Mar 24 12:20:36 PM PDT 24
Peak memory 203024 kb
Host smart-f87cc0e9-5c84-4e53-af02-2b1da9b31e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164152225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4164152225
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2458839703
Short name T1206
Test name
Test status
Simulation time 19560408 ps
CPU time 0.74 seconds
Started Mar 24 12:20:30 PM PDT 24
Finished Mar 24 12:20:30 PM PDT 24
Peak memory 203060 kb
Host smart-83b979f2-2aed-4cc9-9be1-93e36cc7e078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458839703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2458839703
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2943297409
Short name T1157
Test name
Test status
Simulation time 21038757 ps
CPU time 0.84 seconds
Started Mar 24 12:18:56 PM PDT 24
Finished Mar 24 12:18:57 PM PDT 24
Peak memory 203216 kb
Host smart-11f1b27b-4c94-4dae-abd4-c85a9715176e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943297409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2943297409
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1583851382
Short name T115
Test name
Test status
Simulation time 75067341 ps
CPU time 1.33 seconds
Started Mar 24 12:22:12 PM PDT 24
Finished Mar 24 12:22:13 PM PDT 24
Peak memory 202860 kb
Host smart-2053f237-155a-46a0-8f69-f58c0a2de767
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583851382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1583851382
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3288809530
Short name T72
Test name
Test status
Simulation time 59000914 ps
CPU time 1.59 seconds
Started Mar 24 12:18:30 PM PDT 24
Finished Mar 24 12:18:32 PM PDT 24
Peak memory 203756 kb
Host smart-3a553ee7-b82b-4bdc-a633-cca548cb0d17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288809530 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3288809530
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1285918672
Short name T140
Test name
Test status
Simulation time 20925309 ps
CPU time 0.73 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:10 PM PDT 24
Peak memory 203112 kb
Host smart-f82a83f8-ce2f-4254-bc91-cc30af2c3494
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285918672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1285918672
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.689312997
Short name T1112
Test name
Test status
Simulation time 74259781 ps
CPU time 0.66 seconds
Started Mar 24 12:20:30 PM PDT 24
Finished Mar 24 12:20:30 PM PDT 24
Peak memory 203048 kb
Host smart-272de623-3d48-4895-8911-b5ab78612114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689312997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.689312997
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.437320647
Short name T145
Test name
Test status
Simulation time 46387599 ps
CPU time 1.07 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:10 PM PDT 24
Peak memory 203244 kb
Host smart-9656aa7c-1ca2-4d95-8c70-ac16e063bacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437320647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.437320647
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.667661574
Short name T1197
Test name
Test status
Simulation time 181800066 ps
CPU time 2.03 seconds
Started Mar 24 12:20:13 PM PDT 24
Finished Mar 24 12:20:16 PM PDT 24
Peak memory 202696 kb
Host smart-07adb334-bd99-4333-9a37-6d5a4e962be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667661574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.667661574
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1712221107
Short name T111
Test name
Test status
Simulation time 464780083 ps
CPU time 1.31 seconds
Started Mar 24 12:20:17 PM PDT 24
Finished Mar 24 12:20:19 PM PDT 24
Peak memory 202216 kb
Host smart-4b4af1f1-032f-4b24-ab99-bd7cd9d09696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712221107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1712221107
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3260970612
Short name T1179
Test name
Test status
Simulation time 38827210 ps
CPU time 0.99 seconds
Started Mar 24 12:20:44 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 201920 kb
Host smart-11ad8d8b-c284-4995-9b06-da28b19a8ee0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260970612 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3260970612
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.668376113
Short name T1138
Test name
Test status
Simulation time 24259707 ps
CPU time 0.71 seconds
Started Mar 24 12:22:12 PM PDT 24
Finished Mar 24 12:22:13 PM PDT 24
Peak memory 202860 kb
Host smart-b7cbed4d-5dd0-40a5-a1bd-81e561881666
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668376113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.668376113
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.841532851
Short name T1113
Test name
Test status
Simulation time 50990867 ps
CPU time 0.67 seconds
Started Mar 24 12:20:13 PM PDT 24
Finished Mar 24 12:20:14 PM PDT 24
Peak memory 202364 kb
Host smart-f5f8a4d3-caf7-4dd1-a9c1-010ddabca387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841532851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.841532851
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3034665612
Short name T1161
Test name
Test status
Simulation time 153061018 ps
CPU time 0.9 seconds
Started Mar 24 12:18:31 PM PDT 24
Finished Mar 24 12:18:33 PM PDT 24
Peak memory 203520 kb
Host smart-b185a83e-d1a1-4f25-86ee-74ed93c86c5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034665612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3034665612
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3165988479
Short name T1132
Test name
Test status
Simulation time 978079314 ps
CPU time 1.97 seconds
Started Mar 24 12:20:35 PM PDT 24
Finished Mar 24 12:20:37 PM PDT 24
Peak memory 203324 kb
Host smart-932d2aa8-2016-459a-ad07-d5aa7509c2a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165988479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3165988479
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1535393422
Short name T109
Test name
Test status
Simulation time 309694397 ps
CPU time 1.35 seconds
Started Mar 24 12:22:23 PM PDT 24
Finished Mar 24 12:22:25 PM PDT 24
Peak memory 203272 kb
Host smart-ce5bcf26-7290-4ed8-a146-d2394404f179
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535393422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1535393422
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3718522021
Short name T153
Test name
Test status
Simulation time 80893279 ps
CPU time 0.82 seconds
Started Mar 24 12:19:09 PM PDT 24
Finished Mar 24 12:19:10 PM PDT 24
Peak memory 203564 kb
Host smart-3072dc9a-cfbd-4421-b3a2-563e340d9322
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718522021 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3718522021
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3378335440
Short name T133
Test name
Test status
Simulation time 78800973 ps
CPU time 0.8 seconds
Started Mar 24 12:21:45 PM PDT 24
Finished Mar 24 12:21:46 PM PDT 24
Peak memory 203060 kb
Host smart-7221da2d-69fa-4fb2-9dfd-cda7c2a40013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378335440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3378335440
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1839816037
Short name T1133
Test name
Test status
Simulation time 42114462 ps
CPU time 0.67 seconds
Started Mar 24 12:21:51 PM PDT 24
Finished Mar 24 12:21:52 PM PDT 24
Peak memory 202108 kb
Host smart-27fc9d13-3dbc-405f-84b3-47c36ec29676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839816037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1839816037
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3484127617
Short name T1175
Test name
Test status
Simulation time 20733934 ps
CPU time 0.85 seconds
Started Mar 24 12:18:38 PM PDT 24
Finished Mar 24 12:18:39 PM PDT 24
Peak memory 203216 kb
Host smart-b53a391d-5ec0-48d0-82e3-719026669416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484127617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3484127617
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1258138744
Short name T1177
Test name
Test status
Simulation time 46900280 ps
CPU time 1.91 seconds
Started Mar 24 12:18:40 PM PDT 24
Finished Mar 24 12:18:42 PM PDT 24
Peak memory 203820 kb
Host smart-b40520ce-82c0-4467-a78f-9a85db00b4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258138744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1258138744
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1520041817
Short name T121
Test name
Test status
Simulation time 548041541 ps
CPU time 2.09 seconds
Started Mar 24 12:21:43 PM PDT 24
Finished Mar 24 12:21:45 PM PDT 24
Peak memory 203240 kb
Host smart-96b52751-2fb9-4017-8619-8ceee32f1d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520041817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1520041817
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2332654926
Short name T1195
Test name
Test status
Simulation time 36380927 ps
CPU time 1.02 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 201644 kb
Host smart-7b9604b7-5cff-4639-9c16-7a31bbe7127f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332654926 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2332654926
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.490842038
Short name T142
Test name
Test status
Simulation time 18231495 ps
CPU time 0.72 seconds
Started Mar 24 12:21:41 PM PDT 24
Finished Mar 24 12:21:42 PM PDT 24
Peak memory 202328 kb
Host smart-372c66a5-484c-4f76-a4b1-6ff57863a422
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490842038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.490842038
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2800057649
Short name T1171
Test name
Test status
Simulation time 17311573 ps
CPU time 0.69 seconds
Started Mar 24 12:21:07 PM PDT 24
Finished Mar 24 12:21:08 PM PDT 24
Peak memory 202332 kb
Host smart-6cbe26ee-d6c9-458c-b641-e7568ec6c2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800057649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2800057649
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2079377618
Short name T148
Test name
Test status
Simulation time 44785831 ps
CPU time 1.11 seconds
Started Mar 24 12:21:04 PM PDT 24
Finished Mar 24 12:21:06 PM PDT 24
Peak memory 201812 kb
Host smart-d5748769-092f-40d4-b369-abdb555fe5d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079377618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2079377618
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2461738187
Short name T1156
Test name
Test status
Simulation time 477840638 ps
CPU time 1.22 seconds
Started Mar 24 12:21:51 PM PDT 24
Finished Mar 24 12:21:52 PM PDT 24
Peak memory 202440 kb
Host smart-6479ae7f-2a7e-4618-a564-009cc493541b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461738187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2461738187
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2669422404
Short name T1147
Test name
Test status
Simulation time 46059265 ps
CPU time 0.74 seconds
Started Mar 24 12:19:34 PM PDT 24
Finished Mar 24 12:19:35 PM PDT 24
Peak memory 203072 kb
Host smart-4bd56187-3a82-492b-9d88-42f80e88b47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669422404 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2669422404
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3295321443
Short name T146
Test name
Test status
Simulation time 18594481 ps
CPU time 0.69 seconds
Started Mar 24 12:22:11 PM PDT 24
Finished Mar 24 12:22:12 PM PDT 24
Peak memory 202768 kb
Host smart-aae7e3fe-4950-4067-afb1-9d98b4ce1c14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295321443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3295321443
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1155886924
Short name T1110
Test name
Test status
Simulation time 32882721 ps
CPU time 0.75 seconds
Started Mar 24 12:18:54 PM PDT 24
Finished Mar 24 12:18:55 PM PDT 24
Peak memory 200508 kb
Host smart-48b92eca-4f22-4d79-acaf-597c080d3f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155886924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1155886924
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.416990612
Short name T71
Test name
Test status
Simulation time 54239370 ps
CPU time 1.14 seconds
Started Mar 24 12:21:09 PM PDT 24
Finished Mar 24 12:21:10 PM PDT 24
Peak memory 203300 kb
Host smart-5ce8f262-7b61-43cb-991d-0b814d8e19dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416990612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.416990612
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.204158045
Short name T125
Test name
Test status
Simulation time 487968632 ps
CPU time 2.24 seconds
Started Mar 24 12:21:43 PM PDT 24
Finished Mar 24 12:21:45 PM PDT 24
Peak memory 203328 kb
Host smart-7e3589ed-fa11-4299-b3cf-b7a8af672583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204158045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.204158045
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2746519462
Short name T1190
Test name
Test status
Simulation time 131207416 ps
CPU time 2.04 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:04 PM PDT 24
Peak memory 203332 kb
Host smart-88cdd6d5-3e50-408b-b3fc-b5a1ab13f4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746519462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2746519462
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3402574648
Short name T1159
Test name
Test status
Simulation time 48690685 ps
CPU time 1.16 seconds
Started Mar 24 12:17:05 PM PDT 24
Finished Mar 24 12:17:07 PM PDT 24
Peak memory 203700 kb
Host smart-ac57a677-796c-44cd-b696-8a2c945b530f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402574648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3402574648
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.894665115
Short name T1162
Test name
Test status
Simulation time 119186324 ps
CPU time 2.5 seconds
Started Mar 24 12:20:35 PM PDT 24
Finished Mar 24 12:20:38 PM PDT 24
Peak memory 203280 kb
Host smart-e0a987fc-3c0d-4153-83d3-e9f017dceb4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894665115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.894665115
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.4077161766
Short name T136
Test name
Test status
Simulation time 19342006 ps
CPU time 0.69 seconds
Started Mar 24 12:17:10 PM PDT 24
Finished Mar 24 12:17:11 PM PDT 24
Peak memory 203220 kb
Host smart-44f2ec0c-ee3a-4a4e-9f34-69f87b02c462
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077161766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.4077161766
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3232326975
Short name T1164
Test name
Test status
Simulation time 17335434 ps
CPU time 0.73 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 203100 kb
Host smart-419fa0fc-b5ff-40d3-92fd-e5e3778e1e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232326975 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3232326975
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1518975305
Short name T138
Test name
Test status
Simulation time 76491441 ps
CPU time 0.76 seconds
Started Mar 24 12:22:16 PM PDT 24
Finished Mar 24 12:22:18 PM PDT 24
Peak memory 202352 kb
Host smart-27c1d843-80a6-4390-975e-9dc26c68d2e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518975305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1518975305
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3257430641
Short name T1168
Test name
Test status
Simulation time 95375636 ps
CPU time 0.74 seconds
Started Mar 24 12:17:18 PM PDT 24
Finished Mar 24 12:17:19 PM PDT 24
Peak memory 203496 kb
Host smart-9e8d6c6a-cd33-4bf1-8730-e3b507fee368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257430641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3257430641
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2026249687
Short name T1204
Test name
Test status
Simulation time 49236365 ps
CPU time 0.86 seconds
Started Mar 24 12:17:11 PM PDT 24
Finished Mar 24 12:17:13 PM PDT 24
Peak memory 203488 kb
Host smart-f3a7f170-1eda-43d0-a918-f9b8a374f667
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026249687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2026249687
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2997263937
Short name T1189
Test name
Test status
Simulation time 215214277 ps
CPU time 1.25 seconds
Started Mar 24 12:20:08 PM PDT 24
Finished Mar 24 12:20:10 PM PDT 24
Peak memory 203384 kb
Host smart-8165662e-d804-4c63-a69e-7003b2b952f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997263937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2997263937
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.987624138
Short name T1185
Test name
Test status
Simulation time 32424912 ps
CPU time 0.66 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:03 PM PDT 24
Peak memory 203028 kb
Host smart-b2c9442f-9ae0-4eea-8a68-d5f5047cb9a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987624138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.987624138
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2352587030
Short name T1187
Test name
Test status
Simulation time 15337184 ps
CPU time 0.69 seconds
Started Mar 24 12:19:54 PM PDT 24
Finished Mar 24 12:19:56 PM PDT 24
Peak memory 200804 kb
Host smart-9dd52871-5eac-4b92-ab69-19b133c284e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352587030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2352587030
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2472440731
Short name T1202
Test name
Test status
Simulation time 16138265 ps
CPU time 0.63 seconds
Started Mar 24 12:22:33 PM PDT 24
Finished Mar 24 12:22:34 PM PDT 24
Peak memory 203012 kb
Host smart-64d4a0fa-b6a7-4ac7-8687-fff868dbbb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472440731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2472440731
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.328350769
Short name T1196
Test name
Test status
Simulation time 16909111 ps
CPU time 0.64 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:03 PM PDT 24
Peak memory 203024 kb
Host smart-94111641-75d6-4354-a909-71925783d48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328350769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.328350769
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.194725462
Short name T1172
Test name
Test status
Simulation time 18272321 ps
CPU time 0.67 seconds
Started Mar 24 12:21:31 PM PDT 24
Finished Mar 24 12:21:32 PM PDT 24
Peak memory 203040 kb
Host smart-2c2c0d7d-1d75-4882-815c-67af4b485396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194725462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.194725462
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1279243028
Short name T1136
Test name
Test status
Simulation time 53449715 ps
CPU time 0.67 seconds
Started Mar 24 12:21:02 PM PDT 24
Finished Mar 24 12:21:03 PM PDT 24
Peak memory 203028 kb
Host smart-223f4089-733c-41f5-a498-0c4f0039e84a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279243028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1279243028
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.705663406
Short name T1200
Test name
Test status
Simulation time 47931449 ps
CPU time 0.78 seconds
Started Mar 24 12:20:44 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 201852 kb
Host smart-9a1e6dc8-884a-485b-82f7-338f62fee1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705663406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.705663406
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.516672927
Short name T1118
Test name
Test status
Simulation time 82583081 ps
CPU time 0.62 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 203020 kb
Host smart-9e987ad2-ec5b-40f5-b07d-3c8a76d72836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516672927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.516672927
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1255545955
Short name T139
Test name
Test status
Simulation time 254135302 ps
CPU time 1.81 seconds
Started Mar 24 12:18:54 PM PDT 24
Finished Mar 24 12:18:56 PM PDT 24
Peak memory 201108 kb
Host smart-84bb1192-9fa3-4b07-a9b1-2d0cf483f40b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255545955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1255545955
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1737206327
Short name T1143
Test name
Test status
Simulation time 635956023 ps
CPU time 2.81 seconds
Started Mar 24 12:17:05 PM PDT 24
Finished Mar 24 12:17:08 PM PDT 24
Peak memory 203632 kb
Host smart-4d5b923c-4632-482d-b014-e847e256ace4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737206327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1737206327
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.717748711
Short name T73
Test name
Test status
Simulation time 20466652 ps
CPU time 0.68 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 203064 kb
Host smart-f4cab264-935a-4914-907f-ac836e71a316
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717748711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.717748711
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1014992107
Short name T128
Test name
Test status
Simulation time 189906338 ps
CPU time 0.92 seconds
Started Mar 24 12:20:29 PM PDT 24
Finished Mar 24 12:20:30 PM PDT 24
Peak memory 203188 kb
Host smart-fa5077f2-17b7-4979-b7f7-22c70fa5dcb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014992107 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1014992107
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1294079161
Short name T1122
Test name
Test status
Simulation time 19958137 ps
CPU time 0.66 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:14 PM PDT 24
Peak memory 203036 kb
Host smart-608cbb87-1d99-4634-87eb-fa99d27561e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294079161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1294079161
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3545268366
Short name T217
Test name
Test status
Simulation time 18103330 ps
CPU time 0.79 seconds
Started Mar 24 12:17:17 PM PDT 24
Finished Mar 24 12:17:18 PM PDT 24
Peak memory 203064 kb
Host smart-2b0c0faf-af1b-49c2-9def-c7a8730b6adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545268366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3545268366
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1324819241
Short name T1117
Test name
Test status
Simulation time 42196338 ps
CPU time 1 seconds
Started Mar 24 12:18:45 PM PDT 24
Finished Mar 24 12:18:47 PM PDT 24
Peak memory 203492 kb
Host smart-92a4c70e-d5de-42a3-aeed-76fbecf32c23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324819241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1324819241
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1829520673
Short name T1137
Test name
Test status
Simulation time 547091713 ps
CPU time 2.82 seconds
Started Mar 24 12:18:54 PM PDT 24
Finished Mar 24 12:18:57 PM PDT 24
Peak memory 200764 kb
Host smart-55de2591-3b58-4bc2-b36f-ff3f00eafc08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829520673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1829520673
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2693256595
Short name T118
Test name
Test status
Simulation time 149154162 ps
CPU time 1.34 seconds
Started Mar 24 12:20:17 PM PDT 24
Finished Mar 24 12:20:19 PM PDT 24
Peak memory 202296 kb
Host smart-853051ff-8baa-42bc-84e9-af2f8ea2820e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693256595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2693256595
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2931246425
Short name T223
Test name
Test status
Simulation time 16291261 ps
CPU time 0.65 seconds
Started Mar 24 12:20:59 PM PDT 24
Finished Mar 24 12:21:00 PM PDT 24
Peak memory 203008 kb
Host smart-ca67384c-6878-4937-9213-339fd64ad525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931246425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2931246425
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.433012555
Short name T1150
Test name
Test status
Simulation time 131604067 ps
CPU time 0.73 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 202520 kb
Host smart-ecd08dc5-e99f-4965-a9c0-f2c7625bee74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433012555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.433012555
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1211824020
Short name T170
Test name
Test status
Simulation time 103913870 ps
CPU time 0.69 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 202704 kb
Host smart-8702ca51-d0db-4192-b0ef-3b19127ff1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211824020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1211824020
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.227719153
Short name T168
Test name
Test status
Simulation time 28273779 ps
CPU time 0.67 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:14 PM PDT 24
Peak memory 202812 kb
Host smart-c49c79aa-3397-4fa9-9ac7-4b99f0cec6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227719153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.227719153
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2298276299
Short name T221
Test name
Test status
Simulation time 22836340 ps
CPU time 0.72 seconds
Started Mar 24 12:18:54 PM PDT 24
Finished Mar 24 12:18:55 PM PDT 24
Peak memory 200452 kb
Host smart-db559935-78fa-4306-99ee-ed92b6e65109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298276299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2298276299
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.269561323
Short name T1155
Test name
Test status
Simulation time 16347409 ps
CPU time 0.72 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 202232 kb
Host smart-0d79d6d1-3f52-45b6-a7b7-bdec0a4759ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269561323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.269561323
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3289183272
Short name T1111
Test name
Test status
Simulation time 90000877 ps
CPU time 0.71 seconds
Started Mar 24 12:19:56 PM PDT 24
Finished Mar 24 12:19:58 PM PDT 24
Peak memory 201936 kb
Host smart-e47fec61-8103-42eb-9a54-bd93c1472860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289183272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3289183272
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.351350897
Short name T1134
Test name
Test status
Simulation time 55369734 ps
CPU time 0.69 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 202668 kb
Host smart-f8002914-6f9b-44bb-9c2a-733d951224ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351350897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.351350897
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2351734571
Short name T167
Test name
Test status
Simulation time 18969166 ps
CPU time 0.66 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:14 PM PDT 24
Peak memory 202816 kb
Host smart-882203e2-d012-4d27-9897-3bb0248ca4e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351734571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2351734571
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.4007715955
Short name T1163
Test name
Test status
Simulation time 31221395 ps
CPU time 0.71 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 202296 kb
Host smart-e3b5d301-3f00-4464-9483-b2a863054439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007715955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.4007715955
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1304896811
Short name T1203
Test name
Test status
Simulation time 80580691 ps
CPU time 1.54 seconds
Started Mar 24 12:19:43 PM PDT 24
Finished Mar 24 12:19:45 PM PDT 24
Peak memory 203284 kb
Host smart-2448c3b6-936d-4b08-adec-c8337ac1fd56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304896811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1304896811
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2298053928
Short name T1116
Test name
Test status
Simulation time 62314182 ps
CPU time 0.81 seconds
Started Mar 24 12:17:17 PM PDT 24
Finished Mar 24 12:17:18 PM PDT 24
Peak memory 203124 kb
Host smart-d18c819b-580a-4f71-89b8-ba93124594bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298053928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2298053928
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3696513274
Short name T1192
Test name
Test status
Simulation time 107613928 ps
CPU time 0.87 seconds
Started Mar 24 12:20:29 PM PDT 24
Finished Mar 24 12:20:30 PM PDT 24
Peak memory 202024 kb
Host smart-c357c3fa-ebe6-48c4-8605-493882cf6d14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696513274 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3696513274
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.4222928091
Short name T1153
Test name
Test status
Simulation time 20382324 ps
CPU time 0.71 seconds
Started Mar 24 12:17:19 PM PDT 24
Finished Mar 24 12:17:20 PM PDT 24
Peak memory 203548 kb
Host smart-e753b441-3c6a-4566-8cda-86864351a5be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222928091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.4222928091
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.726595976
Short name T1127
Test name
Test status
Simulation time 38281816 ps
CPU time 0.78 seconds
Started Mar 24 12:17:17 PM PDT 24
Finished Mar 24 12:17:18 PM PDT 24
Peak memory 203068 kb
Host smart-720cd4b4-bac9-4acb-943d-6234f76728ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726595976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.726595976
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1957041057
Short name T1114
Test name
Test status
Simulation time 50521908 ps
CPU time 1.17 seconds
Started Mar 24 12:17:32 PM PDT 24
Finished Mar 24 12:17:33 PM PDT 24
Peak memory 203328 kb
Host smart-0f96591f-6d99-467e-9b49-c4e4a0f92902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957041057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1957041057
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3325466534
Short name T1191
Test name
Test status
Simulation time 391599436 ps
CPU time 1.58 seconds
Started Mar 24 12:22:11 PM PDT 24
Finished Mar 24 12:22:13 PM PDT 24
Peak memory 202244 kb
Host smart-5ce028ba-112b-4bb5-9e50-fdb636ced589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325466534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3325466534
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2914551069
Short name T122
Test name
Test status
Simulation time 433813286 ps
CPU time 2.34 seconds
Started Mar 24 12:17:17 PM PDT 24
Finished Mar 24 12:17:19 PM PDT 24
Peak memory 203392 kb
Host smart-61af1668-1652-4513-be4d-c563dec63b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914551069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2914551069
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.812400448
Short name T1120
Test name
Test status
Simulation time 26376920 ps
CPU time 0.66 seconds
Started Mar 24 12:19:54 PM PDT 24
Finished Mar 24 12:19:55 PM PDT 24
Peak memory 200788 kb
Host smart-07b5cec3-ac03-4dab-926d-2fff848202f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812400448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.812400448
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3762324189
Short name T1123
Test name
Test status
Simulation time 35693515 ps
CPU time 0.69 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 202256 kb
Host smart-067e87c5-8e36-490d-b4eb-7f47349faf1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762324189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3762324189
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3015169657
Short name T1182
Test name
Test status
Simulation time 26826508 ps
CPU time 0.66 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 203024 kb
Host smart-e67597b7-068e-4a78-b39d-e7e51a916f32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015169657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3015169657
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2593969031
Short name T1145
Test name
Test status
Simulation time 40879287 ps
CPU time 0.7 seconds
Started Mar 24 12:19:56 PM PDT 24
Finished Mar 24 12:19:58 PM PDT 24
Peak memory 201896 kb
Host smart-c142c535-7694-4b51-9b0b-6f8ddd270a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593969031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2593969031
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3427303521
Short name T171
Test name
Test status
Simulation time 39261051 ps
CPU time 0.65 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 202968 kb
Host smart-70645bdc-49be-4d73-856d-821bd7b4023e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427303521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3427303521
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.431240561
Short name T1125
Test name
Test status
Simulation time 22590997 ps
CPU time 0.73 seconds
Started Mar 24 12:20:12 PM PDT 24
Finished Mar 24 12:20:13 PM PDT 24
Peak memory 202320 kb
Host smart-29a34eee-e530-4398-b3a7-f2b3dd61cb71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431240561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.431240561
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.985902912
Short name T219
Test name
Test status
Simulation time 91021396 ps
CPU time 0.66 seconds
Started Mar 24 12:18:52 PM PDT 24
Finished Mar 24 12:18:52 PM PDT 24
Peak memory 203496 kb
Host smart-2710c752-5594-4a2b-8043-874c43c883ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985902912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.985902912
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1112031230
Short name T1151
Test name
Test status
Simulation time 14992140 ps
CPU time 0.65 seconds
Started Mar 24 12:18:58 PM PDT 24
Finished Mar 24 12:18:59 PM PDT 24
Peak memory 203436 kb
Host smart-cb987df9-b3f7-48c3-977c-8691dec3c661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112031230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1112031230
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3450293228
Short name T215
Test name
Test status
Simulation time 44181083 ps
CPU time 0.68 seconds
Started Mar 24 12:22:14 PM PDT 24
Finished Mar 24 12:22:15 PM PDT 24
Peak memory 202324 kb
Host smart-5eed8d33-8f51-457b-83c0-350cef95781d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450293228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3450293228
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3095619993
Short name T222
Test name
Test status
Simulation time 18332664 ps
CPU time 0.67 seconds
Started Mar 24 12:20:45 PM PDT 24
Finished Mar 24 12:20:46 PM PDT 24
Peak memory 203068 kb
Host smart-ca1f531b-37c3-4ad3-9396-ef8b09f1e95e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095619993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3095619993
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3012277117
Short name T1121
Test name
Test status
Simulation time 76066242 ps
CPU time 1.1 seconds
Started Mar 24 12:17:47 PM PDT 24
Finished Mar 24 12:17:48 PM PDT 24
Peak memory 203256 kb
Host smart-7c645939-1fed-4ba1-bf35-1c84ffd86809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012277117 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3012277117
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1460607772
Short name T149
Test name
Test status
Simulation time 19459371 ps
CPU time 0.65 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:54 PM PDT 24
Peak memory 201940 kb
Host smart-1a3f54d6-cfc0-4dbb-a2d8-f080cae3f4eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460607772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1460607772
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3914326769
Short name T169
Test name
Test status
Simulation time 21960061 ps
CPU time 0.72 seconds
Started Mar 24 12:19:04 PM PDT 24
Finished Mar 24 12:19:05 PM PDT 24
Peak memory 203080 kb
Host smart-6d22df0e-b2a3-4676-8a2a-7df32b56b32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914326769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3914326769
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3162852270
Short name T1176
Test name
Test status
Simulation time 66896415 ps
CPU time 0.8 seconds
Started Mar 24 12:21:08 PM PDT 24
Finished Mar 24 12:21:09 PM PDT 24
Peak memory 203024 kb
Host smart-0f863054-bde4-4b87-9d8a-1a4ec3ee33e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162852270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3162852270
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2594265777
Short name T1188
Test name
Test status
Simulation time 224441238 ps
CPU time 1.21 seconds
Started Mar 24 12:20:29 PM PDT 24
Finished Mar 24 12:20:30 PM PDT 24
Peak memory 202364 kb
Host smart-8d4fa507-0666-4452-905b-288627504c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594265777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2594265777
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3728250897
Short name T112
Test name
Test status
Simulation time 345222179 ps
CPU time 1.83 seconds
Started Mar 24 12:20:53 PM PDT 24
Finished Mar 24 12:20:55 PM PDT 24
Peak memory 202236 kb
Host smart-a37b3163-123e-430c-ac68-67465a506336
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728250897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3728250897
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1833696957
Short name T1126
Test name
Test status
Simulation time 54784773 ps
CPU time 0.93 seconds
Started Mar 24 12:18:34 PM PDT 24
Finished Mar 24 12:18:35 PM PDT 24
Peak memory 203224 kb
Host smart-e23d0bd4-28bf-41bd-85bb-6aea8f02692b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833696957 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1833696957
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1184352331
Short name T1124
Test name
Test status
Simulation time 49168598 ps
CPU time 0.69 seconds
Started Mar 24 12:17:34 PM PDT 24
Finished Mar 24 12:17:34 PM PDT 24
Peak memory 203472 kb
Host smart-8924dc1a-5789-4508-8b4e-61b16caf5df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184352331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1184352331
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1068061377
Short name T1142
Test name
Test status
Simulation time 41102610 ps
CPU time 0.66 seconds
Started Mar 24 12:20:34 PM PDT 24
Finished Mar 24 12:20:35 PM PDT 24
Peak memory 203060 kb
Host smart-0925807d-2095-4021-b6f2-5f8a34d02aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068061377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1068061377
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1330233630
Short name T151
Test name
Test status
Simulation time 88690741 ps
CPU time 1.1 seconds
Started Mar 24 12:22:11 PM PDT 24
Finished Mar 24 12:22:13 PM PDT 24
Peak memory 202616 kb
Host smart-75fe9ae2-6aa7-4198-8c63-c9b883825f22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330233630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1330233630
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.707874548
Short name T1199
Test name
Test status
Simulation time 283033761 ps
CPU time 1.44 seconds
Started Mar 24 12:22:24 PM PDT 24
Finished Mar 24 12:22:26 PM PDT 24
Peak memory 203364 kb
Host smart-6dee5818-2540-4470-b9c3-991b3c6af28b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707874548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.707874548
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.292396218
Short name T1198
Test name
Test status
Simulation time 146051581 ps
CPU time 2.08 seconds
Started Mar 24 12:22:04 PM PDT 24
Finished Mar 24 12:22:06 PM PDT 24
Peak memory 201776 kb
Host smart-f017bd61-4d5f-4ea4-9143-8bb133cf31d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292396218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.292396218
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3991820594
Short name T1169
Test name
Test status
Simulation time 34925577 ps
CPU time 0.87 seconds
Started Mar 24 12:20:02 PM PDT 24
Finished Mar 24 12:20:04 PM PDT 24
Peak memory 203596 kb
Host smart-668816a7-b1af-4eda-a6af-e219bfac7bbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991820594 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3991820594
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.4173524259
Short name T131
Test name
Test status
Simulation time 26337430 ps
CPU time 0.84 seconds
Started Mar 24 12:20:02 PM PDT 24
Finished Mar 24 12:20:04 PM PDT 24
Peak memory 203444 kb
Host smart-0dad42ef-d84b-44cb-99c8-affa18fd3546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173524259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.4173524259
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.620941086
Short name T1193
Test name
Test status
Simulation time 63389953 ps
CPU time 0.67 seconds
Started Mar 24 12:22:18 PM PDT 24
Finished Mar 24 12:22:20 PM PDT 24
Peak memory 202324 kb
Host smart-8a926cad-6609-47eb-bc8c-e9d95464b8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620941086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.620941086
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3225792355
Short name T150
Test name
Test status
Simulation time 36226879 ps
CPU time 0.91 seconds
Started Mar 24 12:20:02 PM PDT 24
Finished Mar 24 12:20:04 PM PDT 24
Peak memory 203476 kb
Host smart-de6e0ac5-d132-4d46-bdbf-489492e7d8ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225792355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3225792355
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.4015156464
Short name T106
Test name
Test status
Simulation time 267173002 ps
CPU time 1.63 seconds
Started Mar 24 12:19:23 PM PDT 24
Finished Mar 24 12:19:25 PM PDT 24
Peak memory 203820 kb
Host smart-5f2275c5-6b4c-4885-a771-fb7a6e69445b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015156464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4015156464
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2910356253
Short name T127
Test name
Test status
Simulation time 151159259 ps
CPU time 1.42 seconds
Started Mar 24 12:19:24 PM PDT 24
Finished Mar 24 12:19:25 PM PDT 24
Peak memory 203744 kb
Host smart-38bc8285-cf77-49a8-aad3-4087bedaf258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910356253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2910356253
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.28550351
Short name T1144
Test name
Test status
Simulation time 128966725 ps
CPU time 1.27 seconds
Started Mar 24 12:20:30 PM PDT 24
Finished Mar 24 12:20:31 PM PDT 24
Peak memory 203432 kb
Host smart-e185558f-e134-446a-900d-61ad568ce661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28550351 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.28550351
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2332377177
Short name T135
Test name
Test status
Simulation time 62469208 ps
CPU time 0.71 seconds
Started Mar 24 12:17:44 PM PDT 24
Finished Mar 24 12:17:45 PM PDT 24
Peak memory 203388 kb
Host smart-9415acfb-31f3-41bd-b316-fe7d607e83c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332377177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2332377177
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3543258205
Short name T1205
Test name
Test status
Simulation time 46579643 ps
CPU time 0.65 seconds
Started Mar 24 12:21:54 PM PDT 24
Finished Mar 24 12:21:55 PM PDT 24
Peak memory 203036 kb
Host smart-6b170083-2199-4f2d-8cbe-165b44da9ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543258205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3543258205
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3225196786
Short name T1180
Test name
Test status
Simulation time 78091718 ps
CPU time 0.97 seconds
Started Mar 24 12:20:03 PM PDT 24
Finished Mar 24 12:20:05 PM PDT 24
Peak memory 203140 kb
Host smart-e7042f43-450d-41a6-9fbc-93f6b601c5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225196786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3225196786
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3375710308
Short name T117
Test name
Test status
Simulation time 63220537 ps
CPU time 1.59 seconds
Started Mar 24 12:20:01 PM PDT 24
Finished Mar 24 12:20:03 PM PDT 24
Peak memory 203368 kb
Host smart-4c1bb4a2-12ca-4769-9e95-7b17931788f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375710308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3375710308
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.533370604
Short name T116
Test name
Test status
Simulation time 131335227 ps
CPU time 1.54 seconds
Started Mar 24 12:20:02 PM PDT 24
Finished Mar 24 12:20:04 PM PDT 24
Peak memory 203712 kb
Host smart-9f92be3a-134f-4542-b966-21c50add2728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533370604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.533370604
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.991889452
Short name T1148
Test name
Test status
Simulation time 36758440 ps
CPU time 0.85 seconds
Started Mar 24 12:18:31 PM PDT 24
Finished Mar 24 12:18:32 PM PDT 24
Peak memory 203584 kb
Host smart-0557672f-f513-494e-88c6-782867230204
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991889452 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.991889452
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.4153689700
Short name T1170
Test name
Test status
Simulation time 35324831 ps
CPU time 0.68 seconds
Started Mar 24 12:20:43 PM PDT 24
Finished Mar 24 12:20:44 PM PDT 24
Peak memory 202168 kb
Host smart-544f4330-8b27-4edb-b332-7aba7010199c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153689700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4153689700
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.4124815728
Short name T1154
Test name
Test status
Simulation time 91846169 ps
CPU time 0.9 seconds
Started Mar 24 12:22:04 PM PDT 24
Finished Mar 24 12:22:05 PM PDT 24
Peak memory 201556 kb
Host smart-95bd345b-8ef3-406d-ad8e-47c776cfc5cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124815728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.4124815728
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1476126938
Short name T1165
Test name
Test status
Simulation time 86423935 ps
CPU time 1.77 seconds
Started Mar 24 12:18:31 PM PDT 24
Finished Mar 24 12:18:34 PM PDT 24
Peak memory 203772 kb
Host smart-e284ebab-0798-42d9-af90-fa089b3d9f35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476126938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1476126938
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.720367759
Short name T943
Test name
Test status
Simulation time 40212329 ps
CPU time 0.59 seconds
Started Mar 24 02:48:13 PM PDT 24
Finished Mar 24 02:48:14 PM PDT 24
Peak memory 203916 kb
Host smart-e0110ec5-4904-4e54-a0f6-b11eff0ba1c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720367759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.720367759
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.4038098658
Short name T784
Test name
Test status
Simulation time 63522724 ps
CPU time 1.65 seconds
Started Mar 24 02:48:10 PM PDT 24
Finished Mar 24 02:48:11 PM PDT 24
Peak memory 212436 kb
Host smart-892ae973-9e44-4562-a14a-bc3c094c5ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038098658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.4038098658
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3819747353
Short name T69
Test name
Test status
Simulation time 411205421 ps
CPU time 6.94 seconds
Started Mar 24 02:48:05 PM PDT 24
Finished Mar 24 02:48:12 PM PDT 24
Peak memory 268812 kb
Host smart-44e96a74-084b-4aa6-9b40-cfc61c27ec62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819747353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3819747353
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.4103057443
Short name T1069
Test name
Test status
Simulation time 1798831756 ps
CPU time 109.55 seconds
Started Mar 24 02:48:04 PM PDT 24
Finished Mar 24 02:49:54 PM PDT 24
Peak memory 499140 kb
Host smart-f4225a09-ca17-464f-bf09-3b9a66e27561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103057443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.4103057443
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3181288755
Short name T33
Test name
Test status
Simulation time 1673583846 ps
CPU time 51.27 seconds
Started Mar 24 02:48:00 PM PDT 24
Finished Mar 24 02:48:51 PM PDT 24
Peak memory 619820 kb
Host smart-be77eddb-91eb-4b13-a4f8-8e4015f27bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181288755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3181288755
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.4034082065
Short name T861
Test name
Test status
Simulation time 969196923 ps
CPU time 0.91 seconds
Started Mar 24 02:48:00 PM PDT 24
Finished Mar 24 02:48:02 PM PDT 24
Peak memory 203948 kb
Host smart-257488b4-0f0a-47d1-b694-36f6523e4656
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034082065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.4034082065
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1025820225
Short name T509
Test name
Test status
Simulation time 414204315 ps
CPU time 6.48 seconds
Started Mar 24 02:48:06 PM PDT 24
Finished Mar 24 02:48:13 PM PDT 24
Peak memory 221424 kb
Host smart-2e73577b-e1bd-4483-a347-c5397dea9d8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025820225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1025820225
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3987155210
Short name T908
Test name
Test status
Simulation time 5647122074 ps
CPU time 273.21 seconds
Started Mar 24 02:47:58 PM PDT 24
Finished Mar 24 02:52:32 PM PDT 24
Peak memory 1108136 kb
Host smart-aecc62cc-e0a5-46fe-9043-c637eb197bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987155210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3987155210
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_override.3211721400
Short name T177
Test name
Test status
Simulation time 18858455 ps
CPU time 0.65 seconds
Started Mar 24 02:47:59 PM PDT 24
Finished Mar 24 02:48:01 PM PDT 24
Peak memory 203792 kb
Host smart-0639e300-d671-4136-953c-52b6501bb208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211721400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3211721400
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3707327279
Short name T891
Test name
Test status
Simulation time 12889747025 ps
CPU time 265.53 seconds
Started Mar 24 02:48:05 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 343712 kb
Host smart-1ea69ff8-0524-44c6-838a-e6dec2107b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707327279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3707327279
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2250023251
Short name T104
Test name
Test status
Simulation time 4622727268 ps
CPU time 25.14 seconds
Started Mar 24 02:48:01 PM PDT 24
Finished Mar 24 02:48:27 PM PDT 24
Peak memory 264292 kb
Host smart-920c9203-b4e3-43a2-b499-8c07f75b6906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250023251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2250023251
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.5201136
Short name T101
Test name
Test status
Simulation time 42160301 ps
CPU time 0.84 seconds
Started Mar 24 02:48:11 PM PDT 24
Finished Mar 24 02:48:12 PM PDT 24
Peak memory 221684 kb
Host smart-740e3cf4-a6ba-4bf7-9c0a-3a1a389c9405
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5201136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.5201136
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1160591706
Short name T878
Test name
Test status
Simulation time 9213867605 ps
CPU time 2.77 seconds
Started Mar 24 02:48:12 PM PDT 24
Finished Mar 24 02:48:15 PM PDT 24
Peak memory 204188 kb
Host smart-815f3ff0-57db-4cd3-ba19-fa7681be7379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160591706 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1160591706
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3290456861
Short name T711
Test name
Test status
Simulation time 10267859092 ps
CPU time 6.79 seconds
Started Mar 24 02:48:14 PM PDT 24
Finished Mar 24 02:48:21 PM PDT 24
Peak memory 259436 kb
Host smart-6406d4e4-7088-4783-8574-e862a9df9d11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290456861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3290456861
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.27573173
Short name T802
Test name
Test status
Simulation time 395119901 ps
CPU time 2.33 seconds
Started Mar 24 02:48:13 PM PDT 24
Finished Mar 24 02:48:15 PM PDT 24
Peak memory 204420 kb
Host smart-f567c391-a68f-4a26-a5be-6576e5720279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27573173 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.i2c_target_hrst.27573173
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.849941057
Short name T355
Test name
Test status
Simulation time 4027433540 ps
CPU time 5.29 seconds
Started Mar 24 02:48:10 PM PDT 24
Finished Mar 24 02:48:15 PM PDT 24
Peak memory 215372 kb
Host smart-06b52df9-45e4-40a3-a1c1-557420fc44ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849941057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.849941057
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.1608433581
Short name T872
Test name
Test status
Simulation time 5796296664 ps
CPU time 6.71 seconds
Started Mar 24 02:48:05 PM PDT 24
Finished Mar 24 02:48:12 PM PDT 24
Peak memory 204264 kb
Host smart-94f7b5d4-3dcb-44e3-b68e-51e0301fd662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608433581 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.1608433581
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3545040019
Short name T298
Test name
Test status
Simulation time 5804744923 ps
CPU time 49.25 seconds
Started Mar 24 02:48:11 PM PDT 24
Finished Mar 24 02:49:01 PM PDT 24
Peak memory 204196 kb
Host smart-7d433290-1157-4649-bba2-521f41e528e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545040019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3545040019
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.4141937672
Short name T166
Test name
Test status
Simulation time 5690020241 ps
CPU time 57.76 seconds
Started Mar 24 02:48:04 PM PDT 24
Finished Mar 24 02:49:02 PM PDT 24
Peak memory 205556 kb
Host smart-af31d1e3-7f34-4ec0-b7ce-d44fc801d9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141937672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.4141937672
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3424697736
Short name T349
Test name
Test status
Simulation time 7830077092 ps
CPU time 47.18 seconds
Started Mar 24 02:48:05 PM PDT 24
Finished Mar 24 02:48:52 PM PDT 24
Peak memory 772624 kb
Host smart-884789d9-029e-47e0-b9c7-2c16b2df5f4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424697736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3424697736
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3823092224
Short name T1104
Test name
Test status
Simulation time 29640639690 ps
CPU time 7.47 seconds
Started Mar 24 02:48:10 PM PDT 24
Finished Mar 24 02:48:18 PM PDT 24
Peak memory 218780 kb
Host smart-8aa34680-facf-4062-a384-43debcbcca9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823092224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3823092224
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3410767379
Short name T949
Test name
Test status
Simulation time 17539696 ps
CPU time 0.63 seconds
Started Mar 24 02:48:26 PM PDT 24
Finished Mar 24 02:48:27 PM PDT 24
Peak memory 203892 kb
Host smart-96fa1ba2-4326-4712-9c3d-e11d36d70f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410767379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3410767379
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.1326440112
Short name T964
Test name
Test status
Simulation time 62093456 ps
CPU time 1.26 seconds
Started Mar 24 02:48:16 PM PDT 24
Finished Mar 24 02:48:17 PM PDT 24
Peak memory 212352 kb
Host smart-6495de22-e1bc-42b2-8be1-c07dab0d772f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326440112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.1326440112
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.601565195
Short name T944
Test name
Test status
Simulation time 949196192 ps
CPU time 12.12 seconds
Started Mar 24 02:48:18 PM PDT 24
Finished Mar 24 02:48:31 PM PDT 24
Peak memory 252232 kb
Host smart-029970f6-a88c-482b-b44e-515af73c0e9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601565195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.601565195
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1711195815
Short name T1048
Test name
Test status
Simulation time 2306553044 ps
CPU time 140.47 seconds
Started Mar 24 02:48:17 PM PDT 24
Finished Mar 24 02:50:37 PM PDT 24
Peak memory 580192 kb
Host smart-4ad12330-d408-45cc-b7fe-c28aec2c3f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711195815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1711195815
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.864373222
Short name T320
Test name
Test status
Simulation time 3146678647 ps
CPU time 160.55 seconds
Started Mar 24 02:48:17 PM PDT 24
Finished Mar 24 02:50:58 PM PDT 24
Peak memory 713932 kb
Host smart-b74747e2-aa9f-40e3-b6ad-7ab678f5abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864373222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.864373222
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.4129644039
Short name T685
Test name
Test status
Simulation time 453442660 ps
CPU time 0.85 seconds
Started Mar 24 02:48:17 PM PDT 24
Finished Mar 24 02:48:18 PM PDT 24
Peak memory 203976 kb
Host smart-fecafcec-6d9a-41e5-a458-e1241dc8639e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129644039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.4129644039
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2716346351
Short name T399
Test name
Test status
Simulation time 648515218 ps
CPU time 3.02 seconds
Started Mar 24 02:48:21 PM PDT 24
Finished Mar 24 02:48:24 PM PDT 24
Peak memory 204168 kb
Host smart-dc1e36b0-7dec-4cd2-a6f1-1375b66c5622
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716346351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2716346351
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.710044412
Short name T562
Test name
Test status
Simulation time 4749452629 ps
CPU time 158.65 seconds
Started Mar 24 02:48:12 PM PDT 24
Finished Mar 24 02:50:51 PM PDT 24
Peak memory 1350760 kb
Host smart-e2cac457-4937-4b0e-a084-84df35a6eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710044412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.710044412
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_override.2383098185
Short name T989
Test name
Test status
Simulation time 17566889 ps
CPU time 0.66 seconds
Started Mar 24 02:48:13 PM PDT 24
Finished Mar 24 02:48:13 PM PDT 24
Peak memory 203824 kb
Host smart-b9f6b39a-2c2b-4e8f-a688-a907cdaa9158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383098185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2383098185
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.4190087329
Short name T592
Test name
Test status
Simulation time 851404365 ps
CPU time 7.28 seconds
Started Mar 24 02:48:17 PM PDT 24
Finished Mar 24 02:48:24 PM PDT 24
Peak memory 233068 kb
Host smart-f1e17ff1-58a9-4b6c-9b0a-aa35d8bc40a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190087329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.4190087329
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2944961728
Short name T213
Test name
Test status
Simulation time 2561284065 ps
CPU time 92.28 seconds
Started Mar 24 02:48:11 PM PDT 24
Finished Mar 24 02:49:44 PM PDT 24
Peak memory 278648 kb
Host smart-38860004-e52d-41b7-9ec6-631a67211c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944961728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2944961728
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2074135663
Short name T99
Test name
Test status
Simulation time 41972895 ps
CPU time 0.83 seconds
Started Mar 24 02:48:24 PM PDT 24
Finished Mar 24 02:48:25 PM PDT 24
Peak memory 221648 kb
Host smart-b7000011-88ee-488c-8ae7-4a3f2eea8235
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074135663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2074135663
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2046092288
Short name T605
Test name
Test status
Simulation time 928052657 ps
CPU time 2.56 seconds
Started Mar 24 02:48:26 PM PDT 24
Finished Mar 24 02:48:29 PM PDT 24
Peak memory 204136 kb
Host smart-7b7cf376-0cfe-4fb8-a01c-0bf7b5fdecf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046092288 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2046092288
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3412430236
Short name T504
Test name
Test status
Simulation time 11487154936 ps
CPU time 3.31 seconds
Started Mar 24 02:48:15 PM PDT 24
Finished Mar 24 02:48:18 PM PDT 24
Peak memory 219512 kb
Host smart-4e4b8354-bf37-4ac1-a44d-b7239e6c4425
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412430236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3412430236
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.193170449
Short name T686
Test name
Test status
Simulation time 2098860530 ps
CPU time 2.75 seconds
Started Mar 24 02:48:22 PM PDT 24
Finished Mar 24 02:48:25 PM PDT 24
Peak memory 204236 kb
Host smart-b6186d94-e8f3-4466-bf89-e0184ec56074
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193170449 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.i2c_target_hrst.193170449
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3461150606
Short name T617
Test name
Test status
Simulation time 4081023157 ps
CPU time 4.82 seconds
Started Mar 24 02:48:21 PM PDT 24
Finished Mar 24 02:48:26 PM PDT 24
Peak memory 215572 kb
Host smart-e61db017-f9ef-439a-87e3-340726f86e7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461150606 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3461150606
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.424601403
Short name T343
Test name
Test status
Simulation time 3109294241 ps
CPU time 10.56 seconds
Started Mar 24 02:48:17 PM PDT 24
Finished Mar 24 02:48:28 PM PDT 24
Peak memory 204220 kb
Host smart-f49e4f54-f75e-438b-b930-e17ec0a19652
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424601403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.424601403
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.316727636
Short name T713
Test name
Test status
Simulation time 2061060572 ps
CPU time 19.47 seconds
Started Mar 24 02:48:19 PM PDT 24
Finished Mar 24 02:48:39 PM PDT 24
Peak memory 214164 kb
Host smart-d7017237-5294-4807-b91c-f9569f990e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316727636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.316727636
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.777366432
Short name T783
Test name
Test status
Simulation time 7217441283 ps
CPU time 617.25 seconds
Started Mar 24 02:48:17 PM PDT 24
Finished Mar 24 02:58:35 PM PDT 24
Peak memory 1821132 kb
Host smart-7159925b-fac7-4e56-aeb6-77e436e3e960
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777366432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.777366432
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1533200139
Short name T283
Test name
Test status
Simulation time 133461353 ps
CPU time 2.06 seconds
Started Mar 24 02:49:24 PM PDT 24
Finished Mar 24 02:49:26 PM PDT 24
Peak memory 212400 kb
Host smart-84232fee-c069-4a60-b081-9142c2a54376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533200139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1533200139
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1557445634
Short name T348
Test name
Test status
Simulation time 1488283515 ps
CPU time 14.16 seconds
Started Mar 24 02:49:26 PM PDT 24
Finished Mar 24 02:49:41 PM PDT 24
Peak memory 262680 kb
Host smart-f644a43f-3e6c-4706-a822-c0090bcbcc32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557445634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1557445634
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.223526804
Short name T327
Test name
Test status
Simulation time 4637985885 ps
CPU time 32.09 seconds
Started Mar 24 02:49:26 PM PDT 24
Finished Mar 24 02:49:59 PM PDT 24
Peak memory 493520 kb
Host smart-21751e93-b9ad-4be3-8b87-c8bb45f35c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223526804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.223526804
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.623476351
Short name T887
Test name
Test status
Simulation time 9472363893 ps
CPU time 66.63 seconds
Started Mar 24 02:49:30 PM PDT 24
Finished Mar 24 02:50:36 PM PDT 24
Peak memory 724996 kb
Host smart-a601b445-ec5a-4507-a1b8-a268cf26becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623476351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.623476351
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2381109644
Short name T465
Test name
Test status
Simulation time 340175545 ps
CPU time 0.91 seconds
Started Mar 24 02:49:30 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 203936 kb
Host smart-5d8cf136-9c13-4aba-a559-48ce958f54c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381109644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2381109644
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.788010134
Short name T625
Test name
Test status
Simulation time 204631053 ps
CPU time 11.42 seconds
Started Mar 24 02:49:24 PM PDT 24
Finished Mar 24 02:49:36 PM PDT 24
Peak memory 242516 kb
Host smart-2ddd7924-276f-4912-846b-4b4933be6e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788010134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
788010134
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2876605292
Short name T1049
Test name
Test status
Simulation time 3588423697 ps
CPU time 89.1 seconds
Started Mar 24 02:49:25 PM PDT 24
Finished Mar 24 02:50:54 PM PDT 24
Peak memory 1061580 kb
Host smart-a285aee0-c3d8-4a4d-8d26-e7746db8daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876605292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2876605292
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_override.4167607578
Short name T729
Test name
Test status
Simulation time 36441518 ps
CPU time 0.63 seconds
Started Mar 24 02:49:25 PM PDT 24
Finished Mar 24 02:49:26 PM PDT 24
Peak memory 203840 kb
Host smart-75e6fb11-4efa-4eee-b1af-2e418684ef3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167607578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.4167607578
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1332813828
Short name T1068
Test name
Test status
Simulation time 1362088164 ps
CPU time 46.71 seconds
Started Mar 24 02:49:32 PM PDT 24
Finished Mar 24 02:50:19 PM PDT 24
Peak memory 300880 kb
Host smart-5fc3c85d-b46e-4daf-8a75-47afbc7dd12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332813828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1332813828
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2742551680
Short name T479
Test name
Test status
Simulation time 10235095492 ps
CPU time 8.24 seconds
Started Mar 24 02:49:37 PM PDT 24
Finished Mar 24 02:49:45 PM PDT 24
Peak memory 265052 kb
Host smart-8c73485e-4c3b-420f-9bc4-0c5dfee35534
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742551680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2742551680
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1238815149
Short name T819
Test name
Test status
Simulation time 10098291092 ps
CPU time 83.35 seconds
Started Mar 24 02:49:31 PM PDT 24
Finished Mar 24 02:50:54 PM PDT 24
Peak memory 724840 kb
Host smart-7efd3d55-9390-40ab-99ed-8a2e44231464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238815149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1238815149
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3356016246
Short name T703
Test name
Test status
Simulation time 428156572 ps
CPU time 2.58 seconds
Started Mar 24 02:49:32 PM PDT 24
Finished Mar 24 02:49:35 PM PDT 24
Peak memory 204148 kb
Host smart-ab10a732-92d4-472a-8088-771fa1db0ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356016246 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3356016246
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.935447695
Short name T1010
Test name
Test status
Simulation time 1034004780 ps
CPU time 5.91 seconds
Started Mar 24 02:49:23 PM PDT 24
Finished Mar 24 02:49:30 PM PDT 24
Peak memory 215200 kb
Host smart-b65a3d4c-3d3d-4172-b540-af78d4cdb89b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935447695 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.935447695
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2110676377
Short name T742
Test name
Test status
Simulation time 11585802082 ps
CPU time 12.97 seconds
Started Mar 24 02:49:25 PM PDT 24
Finished Mar 24 02:49:38 PM PDT 24
Peak memory 204204 kb
Host smart-2c72a153-e0bd-4c8a-be85-145dfa6554e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110676377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2110676377
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.603907189
Short name T1050
Test name
Test status
Simulation time 903695309 ps
CPU time 3.99 seconds
Started Mar 24 02:49:27 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 204112 kb
Host smart-423f4353-0298-4886-9913-232d83b394e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603907189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.603907189
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3244170368
Short name T379
Test name
Test status
Simulation time 41098897216 ps
CPU time 328.82 seconds
Started Mar 24 02:49:27 PM PDT 24
Finished Mar 24 02:54:56 PM PDT 24
Peak memory 2156640 kb
Host smart-f2783be8-b8f9-4642-a2fc-b38c0c52be61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244170368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3244170368
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2382353057
Short name T235
Test name
Test status
Simulation time 9387578483 ps
CPU time 6.74 seconds
Started Mar 24 02:49:25 PM PDT 24
Finished Mar 24 02:49:32 PM PDT 24
Peak memory 219608 kb
Host smart-fcd8444f-3be3-4927-8e4f-64f98aa47538
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382353057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2382353057
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1943916528
Short name T503
Test name
Test status
Simulation time 40820359 ps
CPU time 0.61 seconds
Started Mar 24 02:49:37 PM PDT 24
Finished Mar 24 02:49:38 PM PDT 24
Peak memory 203952 kb
Host smart-c2f994aa-0a42-480c-b226-e4003308b952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943916528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1943916528
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.421966956
Short name T978
Test name
Test status
Simulation time 35489998 ps
CPU time 1.19 seconds
Started Mar 24 02:49:31 PM PDT 24
Finished Mar 24 02:49:32 PM PDT 24
Peak memory 212364 kb
Host smart-44990589-b9b8-4671-8b91-254a51e88856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421966956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.421966956
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1011280910
Short name T3
Test name
Test status
Simulation time 255154044 ps
CPU time 4.59 seconds
Started Mar 24 02:49:35 PM PDT 24
Finished Mar 24 02:49:41 PM PDT 24
Peak memory 240852 kb
Host smart-c810d777-4ce1-499f-82b0-c75ae36ef73c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011280910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1011280910
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.446759556
Short name T652
Test name
Test status
Simulation time 9240134256 ps
CPU time 122.23 seconds
Started Mar 24 02:49:40 PM PDT 24
Finished Mar 24 02:51:43 PM PDT 24
Peak memory 451108 kb
Host smart-18f8689c-9b2e-4612-b087-16f9c2d39404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446759556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.446759556
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.337883638
Short name T389
Test name
Test status
Simulation time 1564532822 ps
CPU time 110.01 seconds
Started Mar 24 02:49:30 PM PDT 24
Finished Mar 24 02:51:21 PM PDT 24
Peak memory 580636 kb
Host smart-9b91bf28-eb23-4f91-9397-e11ecea1e655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337883638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.337883638
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3663552679
Short name T929
Test name
Test status
Simulation time 1121457488 ps
CPU time 1.01 seconds
Started Mar 24 02:49:31 PM PDT 24
Finished Mar 24 02:49:32 PM PDT 24
Peak memory 204184 kb
Host smart-06cc5796-c2b8-4da4-8514-7bf7ec13d711
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663552679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3663552679
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3415269247
Short name T849
Test name
Test status
Simulation time 18825239096 ps
CPU time 148.19 seconds
Started Mar 24 02:49:36 PM PDT 24
Finished Mar 24 02:52:04 PM PDT 24
Peak memory 1330336 kb
Host smart-246872c7-08af-4193-a1a2-98683c4d1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415269247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3415269247
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_override.1062654460
Short name T272
Test name
Test status
Simulation time 17692440 ps
CPU time 0.66 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:42 PM PDT 24
Peak memory 203772 kb
Host smart-a879e5f0-4899-4f33-942f-f4a02a219ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062654460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1062654460
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.533546890
Short name T560
Test name
Test status
Simulation time 783772222 ps
CPU time 15.89 seconds
Started Mar 24 02:49:30 PM PDT 24
Finished Mar 24 02:49:46 PM PDT 24
Peak memory 253184 kb
Host smart-78a32d05-00b6-4dec-9c8c-66c240784edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533546890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.533546890
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3477380876
Short name T365
Test name
Test status
Simulation time 1399097001 ps
CPU time 45.77 seconds
Started Mar 24 02:49:31 PM PDT 24
Finished Mar 24 02:50:17 PM PDT 24
Peak memory 302692 kb
Host smart-707edd26-19c2-4aad-bc22-68027310b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477380876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3477380876
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1535899803
Short name T76
Test name
Test status
Simulation time 15474210807 ps
CPU time 352.29 seconds
Started Mar 24 02:49:31 PM PDT 24
Finished Mar 24 02:55:24 PM PDT 24
Peak memory 735560 kb
Host smart-a1a7d770-5eaf-4b66-8b51-8f450330c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535899803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1535899803
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3532117280
Short name T522
Test name
Test status
Simulation time 6874875773 ps
CPU time 3.18 seconds
Started Mar 24 02:49:36 PM PDT 24
Finished Mar 24 02:49:40 PM PDT 24
Peak memory 204248 kb
Host smart-5b5de4da-3d58-4550-bf73-a9a1aba34a70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532117280 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3532117280
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2285998785
Short name T623
Test name
Test status
Simulation time 10189243628 ps
CPU time 17.55 seconds
Started Mar 24 02:49:38 PM PDT 24
Finished Mar 24 02:49:56 PM PDT 24
Peak memory 313520 kb
Host smart-ed83b30f-edba-460f-9762-ba61c1acd0f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285998785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2285998785
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3863000397
Short name T538
Test name
Test status
Simulation time 10052463934 ps
CPU time 98.41 seconds
Started Mar 24 02:49:36 PM PDT 24
Finished Mar 24 02:51:15 PM PDT 24
Peak memory 719580 kb
Host smart-cac5d3da-a254-4ba9-a122-12b6e060d4b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863000397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3863000397
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.613809569
Short name T610
Test name
Test status
Simulation time 2071323732 ps
CPU time 3.17 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:44 PM PDT 24
Peak memory 204088 kb
Host smart-dffbe212-41cd-4368-8e0d-a8d483441c62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613809569 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.613809569
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1774775817
Short name T1059
Test name
Test status
Simulation time 1094008254 ps
CPU time 4.36 seconds
Started Mar 24 02:49:31 PM PDT 24
Finished Mar 24 02:49:35 PM PDT 24
Peak memory 204808 kb
Host smart-080a6242-6332-4973-b166-ce93ddcc9ac9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774775817 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1774775817
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.2595233484
Short name T889
Test name
Test status
Simulation time 2881052699 ps
CPU time 7.24 seconds
Started Mar 24 02:49:32 PM PDT 24
Finished Mar 24 02:49:39 PM PDT 24
Peak memory 204216 kb
Host smart-7b7bc930-1f7d-42cf-af2f-2ce3cb139c22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595233484 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.2595233484
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.249563334
Short name T262
Test name
Test status
Simulation time 2122224917 ps
CPU time 40.16 seconds
Started Mar 24 02:49:30 PM PDT 24
Finished Mar 24 02:50:11 PM PDT 24
Peak memory 204084 kb
Host smart-e3b515ed-a783-4a99-a224-441c37454963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249563334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.249563334
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3310369790
Short name T535
Test name
Test status
Simulation time 5895700495 ps
CPU time 23.23 seconds
Started Mar 24 02:49:38 PM PDT 24
Finished Mar 24 02:50:01 PM PDT 24
Peak memory 228140 kb
Host smart-f5eb0135-f354-4d46-a072-c53293d7c3e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310369790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3310369790
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1542200175
Short name T656
Test name
Test status
Simulation time 18397933248 ps
CPU time 8.22 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:49 PM PDT 24
Peak memory 204108 kb
Host smart-abf2fb42-0aaf-421d-8f20-9ed1db0035e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542200175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1542200175
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2476478981
Short name T1007
Test name
Test status
Simulation time 13046304393 ps
CPU time 76.44 seconds
Started Mar 24 02:49:32 PM PDT 24
Finished Mar 24 02:50:48 PM PDT 24
Peak memory 826744 kb
Host smart-10dc48ba-8b1f-42e9-abd1-8bf06e151852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476478981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2476478981
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.2070671257
Short name T653
Test name
Test status
Simulation time 7376108962 ps
CPU time 7.76 seconds
Started Mar 24 02:49:32 PM PDT 24
Finished Mar 24 02:49:39 PM PDT 24
Peak memory 212472 kb
Host smart-497f8634-7ac2-431d-9dd5-0ba8e9889238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070671257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.2070671257
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.25484138
Short name T668
Test name
Test status
Simulation time 17371061 ps
CPU time 0.62 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:42 PM PDT 24
Peak memory 203880 kb
Host smart-9614bb64-41a7-4585-916b-e14a058249a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.25484138
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.248837248
Short name T738
Test name
Test status
Simulation time 76561657 ps
CPU time 2.25 seconds
Started Mar 24 02:49:40 PM PDT 24
Finished Mar 24 02:49:43 PM PDT 24
Peak memory 212400 kb
Host smart-861d7a23-0db8-41f6-9491-1053595a7711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248837248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.248837248
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2902410446
Short name T484
Test name
Test status
Simulation time 1969525379 ps
CPU time 5.67 seconds
Started Mar 24 02:49:37 PM PDT 24
Finished Mar 24 02:49:43 PM PDT 24
Peak memory 265336 kb
Host smart-7a70cba5-5589-47e2-b83b-7f520456209a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902410446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2902410446
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3703537277
Short name T980
Test name
Test status
Simulation time 2641777142 ps
CPU time 199.57 seconds
Started Mar 24 02:49:37 PM PDT 24
Finished Mar 24 02:52:57 PM PDT 24
Peak memory 797464 kb
Host smart-b580007b-43ee-4880-ad83-f34e71116247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703537277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3703537277
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3397520661
Short name T753
Test name
Test status
Simulation time 1216129327 ps
CPU time 31 seconds
Started Mar 24 02:49:34 PM PDT 24
Finished Mar 24 02:50:05 PM PDT 24
Peak memory 474788 kb
Host smart-36c92cf3-5ac2-4282-b9b1-20c4d70da118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397520661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3397520661
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.442814953
Short name T362
Test name
Test status
Simulation time 103632283 ps
CPU time 0.97 seconds
Started Mar 24 02:49:35 PM PDT 24
Finished Mar 24 02:49:36 PM PDT 24
Peak memory 204220 kb
Host smart-8454b1f5-f86e-45f1-b4e2-2e3c6ce240a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442814953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.442814953
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.4207167084
Short name T528
Test name
Test status
Simulation time 1341581942 ps
CPU time 6.7 seconds
Started Mar 24 02:49:34 PM PDT 24
Finished Mar 24 02:49:41 PM PDT 24
Peak memory 222076 kb
Host smart-02582983-d0b0-4778-a66b-d1c51a0c145e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207167084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.4207167084
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1005953638
Short name T1105
Test name
Test status
Simulation time 18631568476 ps
CPU time 152.26 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:52:14 PM PDT 24
Peak memory 1339068 kb
Host smart-429738fe-67f0-4283-aee7-7d35ceb59d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005953638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1005953638
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_override.1441012900
Short name T933
Test name
Test status
Simulation time 131324991 ps
CPU time 0.66 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:42 PM PDT 24
Peak memory 203776 kb
Host smart-5f85b261-cbb8-4a4e-a99a-6c5d64513c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441012900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1441012900
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3352340892
Short name T344
Test name
Test status
Simulation time 6100612946 ps
CPU time 85.77 seconds
Started Mar 24 02:49:36 PM PDT 24
Finished Mar 24 02:51:02 PM PDT 24
Peak memory 248340 kb
Host smart-c2f4f417-31c8-491c-8158-3dff90a65523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352340892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3352340892
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.276783987
Short name T212
Test name
Test status
Simulation time 5833306676 ps
CPU time 35.77 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:50:17 PM PDT 24
Peak memory 293724 kb
Host smart-3cb28185-1eb8-4df1-9888-f80eb65b96a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276783987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.276783987
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3584017328
Short name T955
Test name
Test status
Simulation time 4307993703 ps
CPU time 5.29 seconds
Started Mar 24 02:49:43 PM PDT 24
Finished Mar 24 02:49:48 PM PDT 24
Peak memory 212440 kb
Host smart-7447c5d2-8558-49c0-9d30-0191cd4b24c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584017328 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3584017328
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3703711809
Short name T707
Test name
Test status
Simulation time 10410722894 ps
CPU time 15.44 seconds
Started Mar 24 02:49:42 PM PDT 24
Finished Mar 24 02:49:57 PM PDT 24
Peak memory 294788 kb
Host smart-c9920d4f-ec87-4ffd-a3b3-6bfe40a3d873
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703711809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3703711809
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3750269017
Short name T1070
Test name
Test status
Simulation time 10040150591 ps
CPU time 124.83 seconds
Started Mar 24 02:49:42 PM PDT 24
Finished Mar 24 02:51:46 PM PDT 24
Peak memory 775136 kb
Host smart-299a3de2-2c45-48ee-a371-647e542698b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750269017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3750269017
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1248234126
Short name T655
Test name
Test status
Simulation time 385515080 ps
CPU time 2.61 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:44 PM PDT 24
Peak memory 204172 kb
Host smart-855aca2d-d869-428d-b2e6-e2aaea5413c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248234126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1248234126
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1905096054
Short name T339
Test name
Test status
Simulation time 1055145008 ps
CPU time 5.67 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:47 PM PDT 24
Peak memory 219284 kb
Host smart-34126c3b-f739-43b6-817b-f789314cfa03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905096054 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1905096054
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1676247641
Short name T664
Test name
Test status
Simulation time 21175272599 ps
CPU time 8.36 seconds
Started Mar 24 02:49:43 PM PDT 24
Finished Mar 24 02:49:52 PM PDT 24
Peak memory 204176 kb
Host smart-b8212fc9-a86b-4bc9-b684-1fb56a495193
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676247641 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1676247641
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.767818206
Short name T537
Test name
Test status
Simulation time 3245401780 ps
CPU time 19.66 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:50:01 PM PDT 24
Peak memory 204176 kb
Host smart-072cefc3-beb8-4f15-8809-1c50adfe03a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767818206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.767818206
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.93049629
Short name T251
Test name
Test status
Simulation time 6317473738 ps
CPU time 24.66 seconds
Started Mar 24 02:49:42 PM PDT 24
Finished Mar 24 02:50:07 PM PDT 24
Peak memory 226444 kb
Host smart-3cd8d347-e49b-461b-8862-d6f656a8ab78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93049629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stress_rd.93049629
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.741109856
Short name T612
Test name
Test status
Simulation time 35987765119 ps
CPU time 236.57 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:53:38 PM PDT 24
Peak memory 2110856 kb
Host smart-e0b3b851-a1df-4ec2-b264-e7a823311b7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741109856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.741109856
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.1782066680
Short name T1074
Test name
Test status
Simulation time 1367139817 ps
CPU time 7.16 seconds
Started Mar 24 02:49:41 PM PDT 24
Finished Mar 24 02:49:48 PM PDT 24
Peak memory 212424 kb
Host smart-15475b6e-9f96-468c-be0a-e8f9be665c59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782066680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.1782066680
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2856506045
Short name T953
Test name
Test status
Simulation time 29689683 ps
CPU time 0.58 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 02:49:55 PM PDT 24
Peak memory 203776 kb
Host smart-0c240962-b9ce-4b82-aa31-a031818babae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856506045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2856506045
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3756555629
Short name T758
Test name
Test status
Simulation time 38846877 ps
CPU time 1.84 seconds
Started Mar 24 02:49:50 PM PDT 24
Finished Mar 24 02:49:53 PM PDT 24
Peak memory 212332 kb
Host smart-00257a06-0715-436b-88b2-b321868da2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756555629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3756555629
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.3262598072
Short name T858
Test name
Test status
Simulation time 424738449 ps
CPU time 22.4 seconds
Started Mar 24 02:49:40 PM PDT 24
Finished Mar 24 02:50:03 PM PDT 24
Peak memory 299708 kb
Host smart-a1ba3729-f846-4fa0-88dd-368ee13d0bdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262598072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.3262598072
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.2406045775
Short name T609
Test name
Test status
Simulation time 5129374799 ps
CPU time 35.23 seconds
Started Mar 24 02:49:48 PM PDT 24
Finished Mar 24 02:50:24 PM PDT 24
Peak memory 492996 kb
Host smart-40c7ea2b-7018-4712-967c-d8a04664eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406045775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2406045775
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3123659081
Short name T812
Test name
Test status
Simulation time 13626647932 ps
CPU time 55.06 seconds
Started Mar 24 02:49:40 PM PDT 24
Finished Mar 24 02:50:35 PM PDT 24
Peak memory 612788 kb
Host smart-8ad59ca8-21bc-4e34-8243-03efe75b269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123659081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3123659081
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2905157055
Short name T1014
Test name
Test status
Simulation time 159136438 ps
CPU time 0.88 seconds
Started Mar 24 02:49:40 PM PDT 24
Finished Mar 24 02:49:41 PM PDT 24
Peak memory 203948 kb
Host smart-69753957-aca9-4c65-b262-703b090973a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905157055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2905157055
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2436592102
Short name T691
Test name
Test status
Simulation time 649312002 ps
CPU time 8.41 seconds
Started Mar 24 02:49:46 PM PDT 24
Finished Mar 24 02:49:55 PM PDT 24
Peak memory 204144 kb
Host smart-b7156bba-5fa8-4ac6-9c43-5b6749f8e823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436592102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2436592102
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3606939239
Short name T474
Test name
Test status
Simulation time 6711705624 ps
CPU time 200.5 seconds
Started Mar 24 02:49:43 PM PDT 24
Finished Mar 24 02:53:03 PM PDT 24
Peak memory 906432 kb
Host smart-a1e814c8-865a-4976-827b-f7ff83915a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606939239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3606939239
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_override.4008030760
Short name T180
Test name
Test status
Simulation time 17875060 ps
CPU time 0.64 seconds
Started Mar 24 02:49:42 PM PDT 24
Finished Mar 24 02:49:43 PM PDT 24
Peak memory 203856 kb
Host smart-99199f59-7a70-4899-b02c-a06fdae5251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008030760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.4008030760
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.453003625
Short name T634
Test name
Test status
Simulation time 7552588444 ps
CPU time 127.8 seconds
Started Mar 24 02:49:49 PM PDT 24
Finished Mar 24 02:51:58 PM PDT 24
Peak memory 295432 kb
Host smart-6fd488d9-e862-47f2-a291-ffb3dc6cb911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453003625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.453003625
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.38040604
Short name T647
Test name
Test status
Simulation time 5688348756 ps
CPU time 71.52 seconds
Started Mar 24 02:49:44 PM PDT 24
Finished Mar 24 02:50:56 PM PDT 24
Peak memory 350464 kb
Host smart-e377ae6d-e45f-4b57-9fce-a511e1575885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38040604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.38040604
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.122950712
Short name T24
Test name
Test status
Simulation time 1572260551 ps
CPU time 3.56 seconds
Started Mar 24 02:49:52 PM PDT 24
Finished Mar 24 02:49:58 PM PDT 24
Peak memory 212408 kb
Host smart-5ba69190-1a52-447f-9991-4c7444e44705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122950712 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.122950712
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1376138110
Short name T698
Test name
Test status
Simulation time 10093884140 ps
CPU time 70.51 seconds
Started Mar 24 02:49:49 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 578368 kb
Host smart-20f4c8dc-7136-4e38-bde4-07a7c344febc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376138110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1376138110
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.7979016
Short name T1102
Test name
Test status
Simulation time 10204995647 ps
CPU time 42.06 seconds
Started Mar 24 02:49:49 PM PDT 24
Finished Mar 24 02:50:32 PM PDT 24
Peak memory 469404 kb
Host smart-21e39c23-0edd-4475-b08f-0a8e16565604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7979016 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.i2c_target_fifo_reset_tx.7979016
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1232098804
Short name T278
Test name
Test status
Simulation time 402845291 ps
CPU time 2.49 seconds
Started Mar 24 02:49:52 PM PDT 24
Finished Mar 24 02:49:55 PM PDT 24
Peak memory 204184 kb
Host smart-6ec14801-52de-4b1d-a99c-cd3c8ad792a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232098804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1232098804
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1764631749
Short name T276
Test name
Test status
Simulation time 1573764901 ps
CPU time 4.06 seconds
Started Mar 24 02:49:47 PM PDT 24
Finished Mar 24 02:49:52 PM PDT 24
Peak memory 208148 kb
Host smart-4e92c538-5482-4b2e-9c62-7b140adc5f43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764631749 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1764631749
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1566216714
Short name T793
Test name
Test status
Simulation time 1562841563 ps
CPU time 22.04 seconds
Started Mar 24 02:49:49 PM PDT 24
Finished Mar 24 02:50:12 PM PDT 24
Peak memory 204172 kb
Host smart-1aaf9a88-3898-4ab1-96d7-6077909e0308
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566216714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1566216714
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1345253494
Short name T388
Test name
Test status
Simulation time 5673033608 ps
CPU time 59.53 seconds
Started Mar 24 02:49:47 PM PDT 24
Finished Mar 24 02:50:47 PM PDT 24
Peak memory 206480 kb
Host smart-a0fa33dc-f139-403b-a8a2-cc0be6077a9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345253494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1345253494
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1612755097
Short name T606
Test name
Test status
Simulation time 36273179137 ps
CPU time 64.16 seconds
Started Mar 24 02:49:50 PM PDT 24
Finished Mar 24 02:50:54 PM PDT 24
Peak memory 727912 kb
Host smart-4268be77-b282-4f36-8f49-02236c35a19e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612755097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1612755097
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3404166823
Short name T350
Test name
Test status
Simulation time 1272353816 ps
CPU time 6.91 seconds
Started Mar 24 02:49:52 PM PDT 24
Finished Mar 24 02:50:00 PM PDT 24
Peak memory 204216 kb
Host smart-bcc19cdb-60c7-46d0-900d-7bc43c2a3fe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404166823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3404166823
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.962203807
Short name T499
Test name
Test status
Simulation time 4081911865 ps
CPU time 5.24 seconds
Started Mar 24 02:49:47 PM PDT 24
Finished Mar 24 02:49:53 PM PDT 24
Peak memory 204256 kb
Host smart-806dff21-d1e5-4a90-b7e2-ac4d6d42e595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962203807 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_unexp_stop.962203807
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2412274717
Short name T997
Test name
Test status
Simulation time 18468880 ps
CPU time 0.62 seconds
Started Mar 24 02:50:02 PM PDT 24
Finished Mar 24 02:50:02 PM PDT 24
Peak memory 203932 kb
Host smart-91619242-e942-4772-a5e5-f5401e1644a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412274717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2412274717
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.331190262
Short name T1076
Test name
Test status
Simulation time 38509660 ps
CPU time 1.68 seconds
Started Mar 24 02:49:52 PM PDT 24
Finished Mar 24 02:49:54 PM PDT 24
Peak memory 220532 kb
Host smart-d36f5e4c-b2a5-4574-86a7-98e177b1e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331190262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.331190262
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3339306526
Short name T319
Test name
Test status
Simulation time 391785189 ps
CPU time 10.62 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 02:50:07 PM PDT 24
Peak memory 240608 kb
Host smart-30bfd5f7-a960-4c21-a6f7-b941f1b5324d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339306526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3339306526
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.4196488439
Short name T954
Test name
Test status
Simulation time 7176457447 ps
CPU time 55.23 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 02:50:51 PM PDT 24
Peak memory 634880 kb
Host smart-7e7848a0-8fd9-4ff7-bc87-25f4f6ad8f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196488439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.4196488439
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3398242212
Short name T626
Test name
Test status
Simulation time 3293887006 ps
CPU time 48.87 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 02:50:45 PM PDT 24
Peak memory 589304 kb
Host smart-ca63fcdf-c17a-46ba-9f80-0aff4b5adffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398242212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3398242212
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2558324300
Short name T936
Test name
Test status
Simulation time 591848406 ps
CPU time 0.79 seconds
Started Mar 24 02:49:53 PM PDT 24
Finished Mar 24 02:49:54 PM PDT 24
Peak memory 203944 kb
Host smart-dcaa6117-05e3-4504-8b01-42853336df4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558324300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2558324300
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.639180319
Short name T436
Test name
Test status
Simulation time 678545083 ps
CPU time 3.89 seconds
Started Mar 24 02:49:56 PM PDT 24
Finished Mar 24 02:50:00 PM PDT 24
Peak memory 204112 kb
Host smart-f6774747-96df-4645-abdb-2b067581294d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639180319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
639180319
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.4199911954
Short name T342
Test name
Test status
Simulation time 11654518671 ps
CPU time 178.8 seconds
Started Mar 24 02:49:53 PM PDT 24
Finished Mar 24 02:52:53 PM PDT 24
Peak memory 843480 kb
Host smart-c4811734-2db9-4f26-a39f-6eabcd21e8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199911954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.4199911954
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_override.3499454145
Short name T657
Test name
Test status
Simulation time 16850232 ps
CPU time 0.65 seconds
Started Mar 24 02:49:52 PM PDT 24
Finished Mar 24 02:49:55 PM PDT 24
Peak memory 203836 kb
Host smart-06f015fa-aeec-44f1-8dc7-5a75b7261e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499454145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3499454145
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2067805138
Short name T788
Test name
Test status
Simulation time 1630065056 ps
CPU time 119.45 seconds
Started Mar 24 02:49:52 PM PDT 24
Finished Mar 24 02:51:53 PM PDT 24
Peak memory 285464 kb
Host smart-dc28d6e6-a41e-4a7b-8019-c780c7ac394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067805138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2067805138
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.4129492891
Short name T256
Test name
Test status
Simulation time 878823712 ps
CPU time 2.51 seconds
Started Mar 24 02:49:58 PM PDT 24
Finished Mar 24 02:50:01 PM PDT 24
Peak memory 204196 kb
Host smart-3ca7dd36-d5ef-49da-b2d0-4e9ec2d2cfce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129492891 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.4129492891
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.251245282
Short name T244
Test name
Test status
Simulation time 10125157025 ps
CPU time 35.06 seconds
Started Mar 24 02:50:00 PM PDT 24
Finished Mar 24 02:50:35 PM PDT 24
Peak memory 412416 kb
Host smart-79ade276-b16e-472c-8855-96c5aeef1a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251245282 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.251245282
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.546076245
Short name T856
Test name
Test status
Simulation time 10033943090 ps
CPU time 94.73 seconds
Started Mar 24 02:49:59 PM PDT 24
Finished Mar 24 02:51:34 PM PDT 24
Peak memory 731264 kb
Host smart-80c339b6-9e0c-4a49-9cc3-33ad6e814bbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546076245 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.546076245
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.3729178761
Short name T814
Test name
Test status
Simulation time 1561069074 ps
CPU time 2.27 seconds
Started Mar 24 02:49:58 PM PDT 24
Finished Mar 24 02:50:01 PM PDT 24
Peak memory 204168 kb
Host smart-b5fa6d0b-3084-4d1a-acbb-78c39f23c641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729178761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.3729178761
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1169555565
Short name T384
Test name
Test status
Simulation time 1251256961 ps
CPU time 6.07 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 02:50:02 PM PDT 24
Peak memory 208364 kb
Host smart-24c0dd57-a20a-4fa8-9cf8-ed72a779821e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169555565 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1169555565
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.801086071
Short name T239
Test name
Test status
Simulation time 1288018960 ps
CPU time 9.79 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 02:50:06 PM PDT 24
Peak memory 204168 kb
Host smart-3bf37b47-7f97-40e1-bc04-a9d195550b46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801086071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.801086071
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.497618179
Short name T234
Test name
Test status
Simulation time 892486272 ps
CPU time 28.67 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 02:50:25 PM PDT 24
Peak memory 204220 kb
Host smart-a2883145-702e-4a24-92be-26b65ddb6cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497618179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.497618179
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3986111734
Short name T584
Test name
Test status
Simulation time 25713645460 ps
CPU time 613.26 seconds
Started Mar 24 02:49:55 PM PDT 24
Finished Mar 24 03:00:09 PM PDT 24
Peak memory 1782872 kb
Host smart-0c815203-a7c6-47cc-858a-080ce3d4d282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986111734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3986111734
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.529585649
Short name T1091
Test name
Test status
Simulation time 5061976455 ps
CPU time 7.66 seconds
Started Mar 24 02:49:59 PM PDT 24
Finished Mar 24 02:50:07 PM PDT 24
Peak memory 220412 kb
Host smart-99cc9580-c160-44fd-8dab-32d5d187f043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529585649 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_timeout.529585649
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.16794914
Short name T1042
Test name
Test status
Simulation time 54865905 ps
CPU time 0.62 seconds
Started Mar 24 02:50:05 PM PDT 24
Finished Mar 24 02:50:06 PM PDT 24
Peak memory 203920 kb
Host smart-c10cd845-ed18-4446-a055-15e25502e106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16794914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.16794914
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1657289899
Short name T1016
Test name
Test status
Simulation time 142807795 ps
CPU time 1.72 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:50:08 PM PDT 24
Peak memory 212444 kb
Host smart-442c34e8-5435-4678-a6c7-a42535c2fee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657289899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1657289899
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3370403684
Short name T825
Test name
Test status
Simulation time 355476689 ps
CPU time 17.48 seconds
Started Mar 24 02:50:02 PM PDT 24
Finished Mar 24 02:50:20 PM PDT 24
Peak memory 255780 kb
Host smart-c72e40aa-4c0c-46ec-a86e-56c94b65669e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370403684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3370403684
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3668206467
Short name T87
Test name
Test status
Simulation time 7538487390 ps
CPU time 123.62 seconds
Started Mar 24 02:49:58 PM PDT 24
Finished Mar 24 02:52:02 PM PDT 24
Peak memory 617020 kb
Host smart-9a09afef-ca7e-4755-9959-ac1ba53d337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668206467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3668206467
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.168450892
Short name T888
Test name
Test status
Simulation time 8636775348 ps
CPU time 161.85 seconds
Started Mar 24 02:50:02 PM PDT 24
Finished Mar 24 02:52:45 PM PDT 24
Peak memory 721384 kb
Host smart-f85039f7-f3bd-4edf-8807-524da9791f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168450892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.168450892
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2310835604
Short name T250
Test name
Test status
Simulation time 278525608 ps
CPU time 0.95 seconds
Started Mar 24 02:50:00 PM PDT 24
Finished Mar 24 02:50:01 PM PDT 24
Peak memory 203912 kb
Host smart-6e76bf47-8c4d-44e0-a938-e95bb8ee54ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310835604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2310835604
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2483431099
Short name T482
Test name
Test status
Simulation time 140063165 ps
CPU time 3.11 seconds
Started Mar 24 02:50:01 PM PDT 24
Finished Mar 24 02:50:04 PM PDT 24
Peak memory 220756 kb
Host smart-b003850b-4fd4-43f1-bb2e-0f64f824fde8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483431099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2483431099
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_override.3585927818
Short name T294
Test name
Test status
Simulation time 19815417 ps
CPU time 0.64 seconds
Started Mar 24 02:49:59 PM PDT 24
Finished Mar 24 02:50:00 PM PDT 24
Peak memory 203820 kb
Host smart-9fcd8aeb-4509-43fb-b28a-2750c6f5133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585927818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3585927818
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2717433862
Short name T824
Test name
Test status
Simulation time 1699957873 ps
CPU time 85.68 seconds
Started Mar 24 02:50:02 PM PDT 24
Finished Mar 24 02:51:28 PM PDT 24
Peak memory 374064 kb
Host smart-36e944bb-7150-4673-90f2-716f0258f8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717433862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2717433862
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3446394990
Short name T822
Test name
Test status
Simulation time 830658048 ps
CPU time 3.96 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:50:10 PM PDT 24
Peak memory 212340 kb
Host smart-3753ddab-e7c3-4750-845c-2bc580c1420e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446394990 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3446394990
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3529672590
Short name T838
Test name
Test status
Simulation time 10131368480 ps
CPU time 90.66 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:51:37 PM PDT 24
Peak memory 756920 kb
Host smart-f4e6fecd-26aa-48dd-8e70-04f0a184d1e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529672590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3529672590
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2807796158
Short name T835
Test name
Test status
Simulation time 316138333 ps
CPU time 2.34 seconds
Started Mar 24 02:50:08 PM PDT 24
Finished Mar 24 02:50:11 PM PDT 24
Peak memory 204156 kb
Host smart-842f3a26-3bd9-423a-ad29-bdffd4dd67df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807796158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2807796158
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.1477611238
Short name T7
Test name
Test status
Simulation time 1143927843 ps
CPU time 3.23 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:50:10 PM PDT 24
Peak memory 204172 kb
Host smart-362ef821-1402-4f08-98b1-9239df36fe4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477611238 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.1477611238
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3955990864
Short name T721
Test name
Test status
Simulation time 4394937207 ps
CPU time 17.36 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:50:24 PM PDT 24
Peak memory 204164 kb
Host smart-0fabdec0-5959-4165-88a1-9ad056be5b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955990864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3955990864
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2650606885
Short name T487
Test name
Test status
Simulation time 4635040310 ps
CPU time 20.18 seconds
Started Mar 24 02:50:05 PM PDT 24
Finished Mar 24 02:50:26 PM PDT 24
Peak memory 214564 kb
Host smart-1b9ec4ce-4c14-484e-a6ce-7ec0182d5134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650606885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2650606885
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2431710883
Short name T357
Test name
Test status
Simulation time 17911765431 ps
CPU time 334.81 seconds
Started Mar 24 02:50:07 PM PDT 24
Finished Mar 24 02:55:42 PM PDT 24
Peak memory 1132604 kb
Host smart-eda0171e-b86e-4619-879a-659d08e70b9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431710883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2431710883
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1683498240
Short name T618
Test name
Test status
Simulation time 6435092320 ps
CPU time 7.35 seconds
Started Mar 24 02:50:09 PM PDT 24
Finished Mar 24 02:50:17 PM PDT 24
Peak memory 212672 kb
Host smart-f108b218-718e-4f2d-903e-c7b927069333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683498240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1683498240
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.172609419
Short name T1025
Test name
Test status
Simulation time 43054878 ps
CPU time 0.6 seconds
Started Mar 24 02:50:11 PM PDT 24
Finished Mar 24 02:50:12 PM PDT 24
Peak memory 203912 kb
Host smart-dd2464c7-a35d-4b6c-b468-82eca16e1b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172609419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.172609419
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2859348189
Short name T293
Test name
Test status
Simulation time 290273481 ps
CPU time 14.78 seconds
Started Mar 24 02:50:05 PM PDT 24
Finished Mar 24 02:50:20 PM PDT 24
Peak memory 266352 kb
Host smart-953f1446-1916-4af4-9a4a-b54240fa5915
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859348189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2859348189
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.520329597
Short name T1100
Test name
Test status
Simulation time 5983004988 ps
CPU time 35.73 seconds
Started Mar 24 02:50:09 PM PDT 24
Finished Mar 24 02:50:45 PM PDT 24
Peak memory 409584 kb
Host smart-5f9eb401-d474-4301-8c27-421843870cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520329597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.520329597
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.410721836
Short name T236
Test name
Test status
Simulation time 9970974686 ps
CPU time 59.57 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:51:06 PM PDT 24
Peak memory 627488 kb
Host smart-3c6b3eab-328b-4a14-a8c4-47f2f28e8734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410721836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.410721836
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2245550465
Short name T1073
Test name
Test status
Simulation time 130354551 ps
CPU time 0.81 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:50:07 PM PDT 24
Peak memory 203868 kb
Host smart-141c3594-ad08-47d0-a252-daac4bfd613f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245550465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2245550465
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3798950455
Short name T689
Test name
Test status
Simulation time 761463239 ps
CPU time 3 seconds
Started Mar 24 02:50:10 PM PDT 24
Finished Mar 24 02:50:13 PM PDT 24
Peak memory 204100 kb
Host smart-313bf63f-1ce1-42b4-b74c-0a8d500651c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798950455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3798950455
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3227134060
Short name T880
Test name
Test status
Simulation time 24481052799 ps
CPU time 224.25 seconds
Started Mar 24 02:50:07 PM PDT 24
Finished Mar 24 02:53:52 PM PDT 24
Peak memory 997560 kb
Host smart-a291bcf0-4d2c-4aa7-997d-42c0d2fb17b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227134060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3227134060
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_override.1369673403
Short name T178
Test name
Test status
Simulation time 227466023 ps
CPU time 0.65 seconds
Started Mar 24 02:50:08 PM PDT 24
Finished Mar 24 02:50:08 PM PDT 24
Peak memory 203852 kb
Host smart-9ea50738-e8e1-4c1b-9cde-c9187bcfe4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369673403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1369673403
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2417285920
Short name T381
Test name
Test status
Simulation time 490844959 ps
CPU time 4.1 seconds
Started Mar 24 02:50:08 PM PDT 24
Finished Mar 24 02:50:12 PM PDT 24
Peak memory 228696 kb
Host smart-b41d61f6-afea-48d0-877c-d7f460f08612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417285920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2417285920
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2284608433
Short name T514
Test name
Test status
Simulation time 11491203055 ps
CPU time 47.04 seconds
Started Mar 24 02:50:10 PM PDT 24
Finished Mar 24 02:50:57 PM PDT 24
Peak memory 299616 kb
Host smart-be7739d7-6150-4674-83fa-21d0b23ee9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284608433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2284608433
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.245043162
Short name T160
Test name
Test status
Simulation time 11938903995 ps
CPU time 2360 seconds
Started Mar 24 02:50:07 PM PDT 24
Finished Mar 24 03:29:28 PM PDT 24
Peak memory 1949116 kb
Host smart-2d14ce24-8eb5-4d30-8568-cdf9653727ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245043162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.245043162
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2866991973
Short name T257
Test name
Test status
Simulation time 2530757348 ps
CPU time 3.18 seconds
Started Mar 24 02:50:13 PM PDT 24
Finished Mar 24 02:50:17 PM PDT 24
Peak memory 204192 kb
Host smart-e0fdaf5f-20a1-490f-865d-4408fff2ec75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866991973 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2866991973
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1763827810
Short name T258
Test name
Test status
Simulation time 10480142621 ps
CPU time 15.97 seconds
Started Mar 24 02:50:11 PM PDT 24
Finished Mar 24 02:50:27 PM PDT 24
Peak memory 324552 kb
Host smart-9d7ba3cc-9a3c-44b5-92e0-4f87d1321603
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763827810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1763827810
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.867252063
Short name T789
Test name
Test status
Simulation time 958728652 ps
CPU time 4.64 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:50:11 PM PDT 24
Peak memory 204232 kb
Host smart-310a71f8-64cf-453f-9ee8-06deee1ec85e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867252063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.867252063
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3213265818
Short name T948
Test name
Test status
Simulation time 792711883 ps
CPU time 24.44 seconds
Started Mar 24 02:50:06 PM PDT 24
Finished Mar 24 02:50:31 PM PDT 24
Peak memory 204128 kb
Host smart-c1d85bb7-8755-4728-8a95-944fe69f049f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213265818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3213265818
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2692944662
Short name T695
Test name
Test status
Simulation time 956683061 ps
CPU time 39.45 seconds
Started Mar 24 02:50:08 PM PDT 24
Finished Mar 24 02:50:47 PM PDT 24
Peak memory 204140 kb
Host smart-9774b658-6b4b-4bcf-a893-1d855c5ed878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692944662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2692944662
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2087877528
Short name T397
Test name
Test status
Simulation time 15260391726 ps
CPU time 6.71 seconds
Started Mar 24 02:50:07 PM PDT 24
Finished Mar 24 02:50:14 PM PDT 24
Peak memory 204188 kb
Host smart-c26709d5-20b9-4d5a-b8bf-422cf1093f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087877528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2087877528
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.150143742
Short name T1046
Test name
Test status
Simulation time 16072326920 ps
CPU time 933.17 seconds
Started Mar 24 02:50:07 PM PDT 24
Finished Mar 24 03:05:40 PM PDT 24
Peak memory 3602792 kb
Host smart-ee012a4f-8287-43a2-aea0-8a119425379d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150143742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.150143742
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2971385172
Short name T1087
Test name
Test status
Simulation time 11245233357 ps
CPU time 8.41 seconds
Started Mar 24 02:50:11 PM PDT 24
Finished Mar 24 02:50:19 PM PDT 24
Peak memory 220420 kb
Host smart-e0a905ba-331c-460a-82e2-5887973f5ae8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971385172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2971385172
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.258213682
Short name T95
Test name
Test status
Simulation time 19653940 ps
CPU time 0.62 seconds
Started Mar 24 02:50:16 PM PDT 24
Finished Mar 24 02:50:16 PM PDT 24
Peak memory 203908 kb
Host smart-55380605-3dd5-4f29-abfb-09cefd8e5628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258213682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.258213682
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.4093821415
Short name T353
Test name
Test status
Simulation time 131922741 ps
CPU time 1.3 seconds
Started Mar 24 02:50:13 PM PDT 24
Finished Mar 24 02:50:15 PM PDT 24
Peak memory 212392 kb
Host smart-3b8222e3-61db-4a8d-accb-eefbf52381a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093821415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.4093821415
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2722923373
Short name T883
Test name
Test status
Simulation time 336368449 ps
CPU time 4.59 seconds
Started Mar 24 02:50:14 PM PDT 24
Finished Mar 24 02:50:19 PM PDT 24
Peak memory 216668 kb
Host smart-5353095d-be6e-4e7f-a8bc-1f48d24d6e72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722923373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2722923373
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1965359946
Short name T550
Test name
Test status
Simulation time 6245013756 ps
CPU time 48.57 seconds
Started Mar 24 02:50:11 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 504900 kb
Host smart-e29da94d-2394-4c71-9db5-7edbbd125040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965359946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1965359946
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2310274277
Short name T641
Test name
Test status
Simulation time 1999994567 ps
CPU time 63.34 seconds
Started Mar 24 02:50:12 PM PDT 24
Finished Mar 24 02:51:15 PM PDT 24
Peak memory 691472 kb
Host smart-e46be9a9-1170-45d5-bad2-969d2a1e9842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310274277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2310274277
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3106896021
Short name T568
Test name
Test status
Simulation time 312032053 ps
CPU time 1.02 seconds
Started Mar 24 02:50:11 PM PDT 24
Finished Mar 24 02:50:12 PM PDT 24
Peak memory 204144 kb
Host smart-84fa0569-a6c4-4c61-8eca-ba8d76d1453f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106896021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3106896021
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.63289447
Short name T286
Test name
Test status
Simulation time 236934193 ps
CPU time 3.41 seconds
Started Mar 24 02:50:11 PM PDT 24
Finished Mar 24 02:50:14 PM PDT 24
Peak memory 225376 kb
Host smart-81fe3eb8-4239-426e-a657-4e6bcaaf4553
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63289447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.63289447
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.3249744832
Short name T794
Test name
Test status
Simulation time 16434366040 ps
CPU time 103.14 seconds
Started Mar 24 02:50:10 PM PDT 24
Finished Mar 24 02:51:53 PM PDT 24
Peak memory 1012204 kb
Host smart-31cacc56-7e04-483d-98a7-d5baf82fcdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249744832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.3249744832
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_override.1321609612
Short name T518
Test name
Test status
Simulation time 29839488 ps
CPU time 0.64 seconds
Started Mar 24 02:50:12 PM PDT 24
Finished Mar 24 02:50:13 PM PDT 24
Peak memory 203836 kb
Host smart-6645c291-940e-4fbc-a74e-0fa99e00daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321609612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1321609612
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1215647322
Short name T16
Test name
Test status
Simulation time 19104526993 ps
CPU time 388.41 seconds
Started Mar 24 02:50:09 PM PDT 24
Finished Mar 24 02:56:37 PM PDT 24
Peak memory 342500 kb
Host smart-35812b87-c1a6-4c7e-8755-a46be8e18b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215647322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1215647322
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3630326651
Short name T1052
Test name
Test status
Simulation time 4467551684 ps
CPU time 46.56 seconds
Started Mar 24 02:50:15 PM PDT 24
Finished Mar 24 02:51:02 PM PDT 24
Peak memory 310084 kb
Host smart-5379557f-d20e-4e6f-bebe-c9952e4eb637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630326651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3630326651
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3014226830
Short name T863
Test name
Test status
Simulation time 2653591144 ps
CPU time 3.88 seconds
Started Mar 24 02:50:15 PM PDT 24
Finished Mar 24 02:50:19 PM PDT 24
Peak memory 212448 kb
Host smart-d90b090e-aa79-409d-a500-98241201adcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014226830 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3014226830
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1719827573
Short name T473
Test name
Test status
Simulation time 10119826097 ps
CPU time 6.14 seconds
Started Mar 24 02:50:17 PM PDT 24
Finished Mar 24 02:50:23 PM PDT 24
Peak memory 227932 kb
Host smart-30b88795-79e3-4e30-ab73-e3cdf95a1255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719827573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1719827573
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2179661172
Short name T287
Test name
Test status
Simulation time 10051744104 ps
CPU time 92.91 seconds
Started Mar 24 02:50:16 PM PDT 24
Finished Mar 24 02:51:49 PM PDT 24
Peak memory 742376 kb
Host smart-c4916d37-6856-484c-8dc3-d78a857cbeaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179661172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2179661172
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1095935797
Short name T419
Test name
Test status
Simulation time 3119893283 ps
CPU time 2.54 seconds
Started Mar 24 02:50:17 PM PDT 24
Finished Mar 24 02:50:19 PM PDT 24
Peak memory 204232 kb
Host smart-e4d7fb36-a8bb-412a-8541-04e4db672144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095935797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1095935797
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1228789437
Short name T358
Test name
Test status
Simulation time 1427530435 ps
CPU time 6.91 seconds
Started Mar 24 02:50:17 PM PDT 24
Finished Mar 24 02:50:24 PM PDT 24
Peak memory 204148 kb
Host smart-95b091a8-f9fe-45dd-91da-a07b79c28456
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228789437 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1228789437
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1493873941
Short name T862
Test name
Test status
Simulation time 601703454 ps
CPU time 22.11 seconds
Started Mar 24 02:50:15 PM PDT 24
Finished Mar 24 02:50:37 PM PDT 24
Peak memory 204116 kb
Host smart-4d256e9f-9a5e-4f39-b4e0-b2ea220aa641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493873941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1493873941
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1228845326
Short name T961
Test name
Test status
Simulation time 924098695 ps
CPU time 16.91 seconds
Started Mar 24 02:50:15 PM PDT 24
Finished Mar 24 02:50:32 PM PDT 24
Peak memory 213764 kb
Host smart-20355be9-447c-41af-8f40-3ccc1bbb06ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228845326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1228845326
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3690510000
Short name T620
Test name
Test status
Simulation time 11878837227 ps
CPU time 13.55 seconds
Started Mar 24 02:50:16 PM PDT 24
Finished Mar 24 02:50:30 PM PDT 24
Peak memory 204168 kb
Host smart-c5f73952-41dd-4c2a-b91c-dcfd9a561931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690510000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3690510000
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.4218410802
Short name T935
Test name
Test status
Simulation time 9037951479 ps
CPU time 336.17 seconds
Started Mar 24 02:50:16 PM PDT 24
Finished Mar 24 02:55:52 PM PDT 24
Peak memory 2293928 kb
Host smart-e9242790-f977-4d18-bc37-311f11e283af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218410802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.4218410802
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3269024780
Short name T599
Test name
Test status
Simulation time 11808949026 ps
CPU time 6.14 seconds
Started Mar 24 02:50:17 PM PDT 24
Finished Mar 24 02:50:23 PM PDT 24
Peak memory 209908 kb
Host smart-2fe6a04d-3434-466d-8d47-a4fc42d19a5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269024780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3269024780
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2451414860
Short name T803
Test name
Test status
Simulation time 27256336 ps
CPU time 0.61 seconds
Started Mar 24 02:50:27 PM PDT 24
Finished Mar 24 02:50:28 PM PDT 24
Peak memory 203964 kb
Host smart-db047f4b-2495-40b8-8c0a-43671cb9ce42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451414860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2451414860
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3264956781
Short name T650
Test name
Test status
Simulation time 57717314 ps
CPU time 1.17 seconds
Started Mar 24 02:50:22 PM PDT 24
Finished Mar 24 02:50:23 PM PDT 24
Peak memory 212432 kb
Host smart-6a3e151c-62f4-4f04-9cf3-9553dd834863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264956781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3264956781
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.929636085
Short name T733
Test name
Test status
Simulation time 348382547 ps
CPU time 6.51 seconds
Started Mar 24 02:50:23 PM PDT 24
Finished Mar 24 02:50:30 PM PDT 24
Peak memory 276996 kb
Host smart-dab3b9dd-9d65-4d93-a744-31e64ad375d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929636085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.929636085
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.4193811999
Short name T785
Test name
Test status
Simulation time 6712812480 ps
CPU time 100.53 seconds
Started Mar 24 02:50:22 PM PDT 24
Finished Mar 24 02:52:03 PM PDT 24
Peak memory 555956 kb
Host smart-ce91a078-f150-481b-92d8-f21ce2699a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193811999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4193811999
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2494990751
Short name T14
Test name
Test status
Simulation time 5347258296 ps
CPU time 52.91 seconds
Started Mar 24 02:50:16 PM PDT 24
Finished Mar 24 02:51:09 PM PDT 24
Peak memory 540348 kb
Host smart-c93b5390-e7fa-41af-9ccb-ff61c0628cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494990751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2494990751
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.4186201263
Short name T376
Test name
Test status
Simulation time 123257400 ps
CPU time 1.07 seconds
Started Mar 24 02:50:21 PM PDT 24
Finished Mar 24 02:50:23 PM PDT 24
Peak memory 204160 kb
Host smart-58a9842f-368d-418d-a647-40f2b6bba000
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186201263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.4186201263
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3354107448
Short name T196
Test name
Test status
Simulation time 402404322 ps
CPU time 3.07 seconds
Started Mar 24 02:50:22 PM PDT 24
Finished Mar 24 02:50:26 PM PDT 24
Peak memory 217472 kb
Host smart-2592dd72-717c-4c11-96dc-6c138c1d9805
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354107448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3354107448
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1825212422
Short name T159
Test name
Test status
Simulation time 4564896964 ps
CPU time 117.76 seconds
Started Mar 24 02:50:15 PM PDT 24
Finished Mar 24 02:52:12 PM PDT 24
Peak memory 1299760 kb
Host smart-9e80e2d1-4c59-40dc-a439-e9cd72e605c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825212422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1825212422
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_override.4076587282
Short name T988
Test name
Test status
Simulation time 40312693 ps
CPU time 0.61 seconds
Started Mar 24 02:50:16 PM PDT 24
Finished Mar 24 02:50:16 PM PDT 24
Peak memory 203820 kb
Host smart-0f07f38d-f965-477e-b6e0-4c382fb74a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076587282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.4076587282
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1456548817
Short name T851
Test name
Test status
Simulation time 7280431364 ps
CPU time 101.69 seconds
Started Mar 24 02:50:23 PM PDT 24
Finished Mar 24 02:52:05 PM PDT 24
Peak memory 220636 kb
Host smart-34bcb7de-de72-4c19-97c3-eb45a4ea942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456548817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1456548817
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3354486664
Short name T1057
Test name
Test status
Simulation time 1106176376 ps
CPU time 61.33 seconds
Started Mar 24 02:50:15 PM PDT 24
Finished Mar 24 02:51:16 PM PDT 24
Peak memory 267092 kb
Host smart-d95cb175-8229-49f9-91bf-15bfd7538631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354486664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3354486664
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.1217418164
Short name T23
Test name
Test status
Simulation time 721491547 ps
CPU time 3.45 seconds
Started Mar 24 02:50:22 PM PDT 24
Finished Mar 24 02:50:26 PM PDT 24
Peak memory 204212 kb
Host smart-c42c8ee5-0ab4-4be3-81f9-b7ea539c9101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217418164 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1217418164
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.30513118
Short name T697
Test name
Test status
Simulation time 10084070359 ps
CPU time 82.52 seconds
Started Mar 24 02:50:21 PM PDT 24
Finished Mar 24 02:51:43 PM PDT 24
Peak memory 628744 kb
Host smart-483718d3-07cb-425e-a071-f999c762af79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30513118 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_acq.30513118
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.276414315
Short name T873
Test name
Test status
Simulation time 10321774658 ps
CPU time 39.83 seconds
Started Mar 24 02:50:21 PM PDT 24
Finished Mar 24 02:51:01 PM PDT 24
Peak memory 472992 kb
Host smart-f10f1b6d-6f05-461d-a05b-f8e881b05a39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276414315 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_tx.276414315
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1556298971
Short name T370
Test name
Test status
Simulation time 398016259 ps
CPU time 2.36 seconds
Started Mar 24 02:50:25 PM PDT 24
Finished Mar 24 02:50:28 PM PDT 24
Peak memory 204132 kb
Host smart-5d565919-5b82-4de6-aa8b-4bc8a01b6ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556298971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1556298971
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1017108901
Short name T312
Test name
Test status
Simulation time 1727492066 ps
CPU time 3.73 seconds
Started Mar 24 02:50:21 PM PDT 24
Finished Mar 24 02:50:25 PM PDT 24
Peak memory 204140 kb
Host smart-ed6147ab-38ee-4a6b-9ed8-c6d0fe024c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017108901 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1017108901
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3405795085
Short name T470
Test name
Test status
Simulation time 6093004628 ps
CPU time 5.39 seconds
Started Mar 24 02:50:20 PM PDT 24
Finished Mar 24 02:50:25 PM PDT 24
Peak memory 204204 kb
Host smart-55cd2d03-0069-46ff-a94b-b275860d77e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405795085 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3405795085
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3978392440
Short name T635
Test name
Test status
Simulation time 598751078 ps
CPU time 23.01 seconds
Started Mar 24 02:50:19 PM PDT 24
Finished Mar 24 02:50:42 PM PDT 24
Peak memory 204044 kb
Host smart-88be5798-7bc3-4615-a2e8-ef917627e2a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978392440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3978392440
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.699601436
Short name T1108
Test name
Test status
Simulation time 619447516 ps
CPU time 9.19 seconds
Started Mar 24 02:50:22 PM PDT 24
Finished Mar 24 02:50:31 PM PDT 24
Peak memory 208460 kb
Host smart-967cc79a-933a-44f2-9717-0bcaa9165c07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699601436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.699601436
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.826971734
Short name T291
Test name
Test status
Simulation time 7851976413 ps
CPU time 87.68 seconds
Started Mar 24 02:50:20 PM PDT 24
Finished Mar 24 02:51:48 PM PDT 24
Peak memory 565092 kb
Host smart-2dfae7df-3a64-4d24-9b6a-5dc4521cc0d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826971734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_t
arget_stretch.826971734
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.411856505
Short name T12
Test name
Test status
Simulation time 5953600943 ps
CPU time 7.4 seconds
Started Mar 24 02:50:19 PM PDT 24
Finished Mar 24 02:50:26 PM PDT 24
Peak memory 212420 kb
Host smart-41c2609b-417e-48ad-8274-b2fd2f09d9fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411856505 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.411856505
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3804037608
Short name T884
Test name
Test status
Simulation time 35319360 ps
CPU time 0.63 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:50:36 PM PDT 24
Peak memory 203952 kb
Host smart-e4cae1bc-9f92-4ab6-8e2d-cf699959301b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804037608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3804037608
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3665114543
Short name T881
Test name
Test status
Simulation time 912176868 ps
CPU time 1.49 seconds
Started Mar 24 02:50:23 PM PDT 24
Finished Mar 24 02:50:24 PM PDT 24
Peak memory 212400 kb
Host smart-fe5e9d22-0ad0-4e38-b9c5-188cfcd8065c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665114543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3665114543
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1610689316
Short name T532
Test name
Test status
Simulation time 1969476627 ps
CPU time 11.16 seconds
Started Mar 24 02:50:25 PM PDT 24
Finished Mar 24 02:50:36 PM PDT 24
Peak memory 318224 kb
Host smart-c7dd2875-2121-42fb-8e40-2754395f7931
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610689316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1610689316
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3880321564
Short name T573
Test name
Test status
Simulation time 6855883500 ps
CPU time 60.23 seconds
Started Mar 24 02:50:25 PM PDT 24
Finished Mar 24 02:51:26 PM PDT 24
Peak memory 614668 kb
Host smart-8d65e20f-0973-43c4-9013-5679762f085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880321564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3880321564
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1070404912
Short name T658
Test name
Test status
Simulation time 315654899 ps
CPU time 1.13 seconds
Started Mar 24 02:50:25 PM PDT 24
Finished Mar 24 02:50:26 PM PDT 24
Peak memory 204168 kb
Host smart-47ebace9-54d8-4fa1-b0e8-9d35cd482f89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070404912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1070404912
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1047281523
Short name T1043
Test name
Test status
Simulation time 271572457 ps
CPU time 3.51 seconds
Started Mar 24 02:50:27 PM PDT 24
Finished Mar 24 02:50:30 PM PDT 24
Peak memory 204164 kb
Host smart-209d130a-fa6b-448e-bc7f-4e47710c2078
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047281523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1047281523
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.956236541
Short name T924
Test name
Test status
Simulation time 15854724906 ps
CPU time 324.33 seconds
Started Mar 24 02:50:23 PM PDT 24
Finished Mar 24 02:55:47 PM PDT 24
Peak memory 1152548 kb
Host smart-c417f47f-5e4b-4db0-afbd-17ebfcdac89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956236541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.956236541
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_override.4225356026
Short name T748
Test name
Test status
Simulation time 19849627 ps
CPU time 0.66 seconds
Started Mar 24 02:50:24 PM PDT 24
Finished Mar 24 02:50:25 PM PDT 24
Peak memory 203824 kb
Host smart-4cb2ed1f-3402-4241-b002-494c4300e99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225356026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.4225356026
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1923674901
Short name T629
Test name
Test status
Simulation time 2818624374 ps
CPU time 58.37 seconds
Started Mar 24 02:50:27 PM PDT 24
Finished Mar 24 02:51:25 PM PDT 24
Peak memory 212476 kb
Host smart-8eafb38b-39ac-466d-b655-31f675b70410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923674901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1923674901
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3529875645
Short name T805
Test name
Test status
Simulation time 1324030844 ps
CPU time 126.12 seconds
Started Mar 24 02:50:26 PM PDT 24
Finished Mar 24 02:52:32 PM PDT 24
Peak memory 307752 kb
Host smart-146ed27c-5e3d-4fe8-80be-7db97335fc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529875645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3529875645
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1028365236
Short name T578
Test name
Test status
Simulation time 1066134358 ps
CPU time 4.56 seconds
Started Mar 24 02:50:28 PM PDT 24
Finished Mar 24 02:50:32 PM PDT 24
Peak memory 204148 kb
Host smart-83bf1065-af25-4232-aba2-9f4e55ac29d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028365236 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1028365236
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.439403162
Short name T68
Test name
Test status
Simulation time 10041277595 ps
CPU time 82.64 seconds
Started Mar 24 02:50:30 PM PDT 24
Finished Mar 24 02:51:53 PM PDT 24
Peak memory 571168 kb
Host smart-7c57afef-98a3-4423-b695-43828649d861
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439403162 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.439403162
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3175654546
Short name T63
Test name
Test status
Simulation time 10443309705 ps
CPU time 19.05 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:50:54 PM PDT 24
Peak memory 345840 kb
Host smart-8822d13c-cb80-4d30-b1b2-9940591314e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175654546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3175654546
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.389514719
Short name T860
Test name
Test status
Simulation time 1833523736 ps
CPU time 6.2 seconds
Started Mar 24 02:50:23 PM PDT 24
Finished Mar 24 02:50:29 PM PDT 24
Peak memory 214900 kb
Host smart-7120d46f-c89d-4615-aef6-223a7b89519f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389514719 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.389514719
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3417016135
Short name T483
Test name
Test status
Simulation time 4352865529 ps
CPU time 6.05 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:50:41 PM PDT 24
Peak memory 204208 kb
Host smart-acfdbc0b-ba3e-48c1-a080-1f551cae944f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417016135 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3417016135
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3122720458
Short name T530
Test name
Test status
Simulation time 3836371224 ps
CPU time 17.35 seconds
Started Mar 24 02:50:24 PM PDT 24
Finished Mar 24 02:50:42 PM PDT 24
Peak memory 204264 kb
Host smart-a96b593c-c890-4640-a73c-36ece0687308
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122720458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3122720458
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3900137665
Short name T672
Test name
Test status
Simulation time 9031187193 ps
CPU time 26.59 seconds
Started Mar 24 02:50:27 PM PDT 24
Finished Mar 24 02:50:53 PM PDT 24
Peak memory 224152 kb
Host smart-eb311855-1443-4ba7-bdc6-5ea4346f2134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900137665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3900137665
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1759829146
Short name T1095
Test name
Test status
Simulation time 16941399546 ps
CPU time 19 seconds
Started Mar 24 02:50:25 PM PDT 24
Finished Mar 24 02:50:44 PM PDT 24
Peak memory 204136 kb
Host smart-6eecfbff-708e-455e-b0e2-864766a44934
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759829146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1759829146
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1983665302
Short name T747
Test name
Test status
Simulation time 9663503794 ps
CPU time 6.49 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:50:41 PM PDT 24
Peak memory 212424 kb
Host smart-901c54e2-3ab4-46c6-853e-9668752bd1d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983665302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1983665302
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.2825866210
Short name T821
Test name
Test status
Simulation time 1498531540 ps
CPU time 4.4 seconds
Started Mar 24 02:50:34 PM PDT 24
Finished Mar 24 02:50:39 PM PDT 24
Peak memory 204156 kb
Host smart-d26b713b-c8dd-49c4-b3bb-8ef879d7336c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825866210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.2825866210
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2803515187
Short name T301
Test name
Test status
Simulation time 17439404 ps
CPU time 0.62 seconds
Started Mar 24 02:48:35 PM PDT 24
Finished Mar 24 02:48:36 PM PDT 24
Peak memory 203816 kb
Host smart-3d9a137d-a279-4b1c-940f-1b194e63be25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803515187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2803515187
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3379547828
Short name T336
Test name
Test status
Simulation time 53836596 ps
CPU time 1.52 seconds
Started Mar 24 02:48:23 PM PDT 24
Finished Mar 24 02:48:25 PM PDT 24
Peak memory 216068 kb
Host smart-65e12d13-a019-4746-8c50-d1a4b6f5904c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379547828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3379547828
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2928284541
Short name T427
Test name
Test status
Simulation time 154413922 ps
CPU time 3.29 seconds
Started Mar 24 02:48:22 PM PDT 24
Finished Mar 24 02:48:26 PM PDT 24
Peak memory 225720 kb
Host smart-21ad7f4b-58b3-44f9-9dcf-179a881a9257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928284541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2928284541
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2180692209
Short name T461
Test name
Test status
Simulation time 31594133776 ps
CPU time 97.02 seconds
Started Mar 24 02:48:21 PM PDT 24
Finished Mar 24 02:49:58 PM PDT 24
Peak memory 836688 kb
Host smart-430837ed-36a3-4373-8892-3183bbf443d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180692209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2180692209
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2573336558
Short name T511
Test name
Test status
Simulation time 15126351123 ps
CPU time 81.14 seconds
Started Mar 24 02:48:29 PM PDT 24
Finished Mar 24 02:49:50 PM PDT 24
Peak memory 771180 kb
Host smart-41d03083-2384-4fc5-9e74-3441eeb8e5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573336558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2573336558
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3399252166
Short name T663
Test name
Test status
Simulation time 308625626 ps
CPU time 0.8 seconds
Started Mar 24 02:48:26 PM PDT 24
Finished Mar 24 02:48:27 PM PDT 24
Peak memory 203896 kb
Host smart-7f48090f-f1d4-4bd1-907e-e85c338534c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399252166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3399252166
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3995982275
Short name T1027
Test name
Test status
Simulation time 130538381 ps
CPU time 3.6 seconds
Started Mar 24 02:48:23 PM PDT 24
Finished Mar 24 02:48:27 PM PDT 24
Peak memory 224068 kb
Host smart-4c846d3d-a424-4166-9c82-4956d79e4894
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995982275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3995982275
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2823838211
Short name T593
Test name
Test status
Simulation time 16434243070 ps
CPU time 284.07 seconds
Started Mar 24 02:48:31 PM PDT 24
Finished Mar 24 02:53:15 PM PDT 24
Peak memory 1121724 kb
Host smart-95729fca-5682-4b69-b616-ab25b42ae049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823838211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2823838211
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_override.1458337765
Short name T478
Test name
Test status
Simulation time 27386736 ps
CPU time 0.7 seconds
Started Mar 24 02:48:27 PM PDT 24
Finished Mar 24 02:48:29 PM PDT 24
Peak memory 203824 kb
Host smart-afc47472-83f1-4c65-b689-5d08ace96e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458337765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1458337765
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3054118459
Short name T622
Test name
Test status
Simulation time 47627414597 ps
CPU time 192.43 seconds
Started Mar 24 02:48:22 PM PDT 24
Finished Mar 24 02:51:35 PM PDT 24
Peak memory 204448 kb
Host smart-44351360-55d3-4a61-b84e-97172ec9793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054118459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3054118459
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3370963360
Short name T750
Test name
Test status
Simulation time 5256890118 ps
CPU time 85.99 seconds
Started Mar 24 02:48:25 PM PDT 24
Finished Mar 24 02:49:52 PM PDT 24
Peak memory 366024 kb
Host smart-f70f22ce-0fc7-4255-b962-3fe30ea420f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370963360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3370963360
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3418464616
Short name T102
Test name
Test status
Simulation time 221696595 ps
CPU time 0.95 seconds
Started Mar 24 02:48:29 PM PDT 24
Finished Mar 24 02:48:30 PM PDT 24
Peak memory 222644 kb
Host smart-c3feeb93-2565-4993-bf22-cb938d56e70d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418464616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3418464616
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.359949105
Short name T512
Test name
Test status
Simulation time 2159431375 ps
CPU time 4.97 seconds
Started Mar 24 02:48:30 PM PDT 24
Finished Mar 24 02:48:35 PM PDT 24
Peak memory 204260 kb
Host smart-13a9876a-6e09-46c6-9a5f-d16993d01d36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359949105 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.359949105
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2968166122
Short name T659
Test name
Test status
Simulation time 10076235518 ps
CPU time 72.06 seconds
Started Mar 24 02:48:31 PM PDT 24
Finished Mar 24 02:49:43 PM PDT 24
Peak memory 525160 kb
Host smart-53a27158-8309-49cb-8e88-a7407a97a946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968166122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2968166122
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3906682162
Short name T165
Test name
Test status
Simulation time 10252398758 ps
CPU time 33.74 seconds
Started Mar 24 02:48:31 PM PDT 24
Finished Mar 24 02:49:05 PM PDT 24
Peak memory 437068 kb
Host smart-a8b99718-61e7-4a1a-a4ed-eed8286f9384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906682162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3906682162
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2348829891
Short name T797
Test name
Test status
Simulation time 1226192593 ps
CPU time 1.87 seconds
Started Mar 24 02:48:27 PM PDT 24
Finished Mar 24 02:48:29 PM PDT 24
Peak memory 204204 kb
Host smart-36a24ab5-603b-40b4-885c-7ac8c6d3e637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348829891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2348829891
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.684974254
Short name T267
Test name
Test status
Simulation time 1678490792 ps
CPU time 4.76 seconds
Started Mar 24 02:48:28 PM PDT 24
Finished Mar 24 02:48:34 PM PDT 24
Peak memory 204136 kb
Host smart-6a98b46d-e721-4cb1-b7b5-fd646fcd9d57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684974254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_intr_smoke.684974254
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.164242767
Short name T325
Test name
Test status
Simulation time 12640808286 ps
CPU time 4.97 seconds
Started Mar 24 02:48:28 PM PDT 24
Finished Mar 24 02:48:34 PM PDT 24
Peak memory 204248 kb
Host smart-a7984ba8-f6d1-4c96-a1b0-50cd9255bf5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164242767 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.164242767
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3658570462
Short name T415
Test name
Test status
Simulation time 968715496 ps
CPU time 35.25 seconds
Started Mar 24 02:48:29 PM PDT 24
Finished Mar 24 02:49:04 PM PDT 24
Peak memory 204088 kb
Host smart-d4e38a3e-5da1-4d70-a2b2-9ff804cdd6f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658570462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3658570462
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.3277887841
Short name T868
Test name
Test status
Simulation time 13350006691 ps
CPU time 79.73 seconds
Started Mar 24 02:48:28 PM PDT 24
Finished Mar 24 02:49:49 PM PDT 24
Peak memory 209932 kb
Host smart-097e3aa7-b17b-4790-a96b-1b7436f449b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277887841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.3277887841
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.832940047
Short name T770
Test name
Test status
Simulation time 32717160116 ps
CPU time 289.91 seconds
Started Mar 24 02:48:29 PM PDT 24
Finished Mar 24 02:53:19 PM PDT 24
Peak memory 2011132 kb
Host smart-d7fb88bd-d309-47e0-a8c1-30c96e4970a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832940047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.832940047
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1242393795
Short name T901
Test name
Test status
Simulation time 4891592189 ps
CPU time 6.96 seconds
Started Mar 24 02:48:28 PM PDT 24
Finished Mar 24 02:48:36 PM PDT 24
Peak memory 211476 kb
Host smart-547d09fe-7e8d-4c87-bd4b-bb52f741edd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242393795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1242393795
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1520370842
Short name T382
Test name
Test status
Simulation time 46469850 ps
CPU time 0.63 seconds
Started Mar 24 02:50:37 PM PDT 24
Finished Mar 24 02:50:38 PM PDT 24
Peak memory 203948 kb
Host smart-8571a51a-dd4f-469c-9f32-9cc055b4112d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520370842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1520370842
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3728078676
Short name T44
Test name
Test status
Simulation time 61632331 ps
CPU time 1.04 seconds
Started Mar 24 02:50:36 PM PDT 24
Finished Mar 24 02:50:37 PM PDT 24
Peak memory 204228 kb
Host smart-a8e37681-a5d7-4a34-afcb-1a0ac6e77fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728078676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3728078676
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3856723469
Short name T491
Test name
Test status
Simulation time 1683565961 ps
CPU time 15.89 seconds
Started Mar 24 02:50:34 PM PDT 24
Finished Mar 24 02:50:50 PM PDT 24
Peak memory 256240 kb
Host smart-0226aa77-2053-45cc-951a-e5abc8b2e8ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856723469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3856723469
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.729013319
Short name T588
Test name
Test status
Simulation time 1237251521 ps
CPU time 35.97 seconds
Started Mar 24 02:50:32 PM PDT 24
Finished Mar 24 02:51:08 PM PDT 24
Peak memory 511076 kb
Host smart-f7d8078a-2ab2-4a19-b72f-d72ccae54dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729013319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.729013319
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2786837190
Short name T683
Test name
Test status
Simulation time 7046254120 ps
CPU time 128.15 seconds
Started Mar 24 02:50:32 PM PDT 24
Finished Mar 24 02:52:41 PM PDT 24
Peak memory 620620 kb
Host smart-c4fcb445-67a8-4784-ade6-fd3af0ac5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786837190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2786837190
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1424305553
Short name T1001
Test name
Test status
Simulation time 237216962 ps
CPU time 0.81 seconds
Started Mar 24 02:50:37 PM PDT 24
Finished Mar 24 02:50:39 PM PDT 24
Peak memory 203908 kb
Host smart-403f836e-7f07-46ef-a070-94ee6ff933ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424305553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1424305553
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3381318471
Short name T195
Test name
Test status
Simulation time 154519818 ps
CPU time 3.63 seconds
Started Mar 24 02:50:32 PM PDT 24
Finished Mar 24 02:50:36 PM PDT 24
Peak memory 230252 kb
Host smart-5cb30771-de6f-4007-ab7d-66654499ae6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381318471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3381318471
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1700300256
Short name T952
Test name
Test status
Simulation time 4206202307 ps
CPU time 105.46 seconds
Started Mar 24 02:50:32 PM PDT 24
Finished Mar 24 02:52:17 PM PDT 24
Peak memory 1208740 kb
Host smart-6bcf6f8e-c2da-445e-93b5-c3ab9bcfac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700300256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1700300256
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_override.1787765824
Short name T179
Test name
Test status
Simulation time 19807918 ps
CPU time 0.66 seconds
Started Mar 24 02:50:37 PM PDT 24
Finished Mar 24 02:50:39 PM PDT 24
Peak memory 203836 kb
Host smart-13f400d5-bd0f-4bd5-a521-cfd5d6f77ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787765824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1787765824
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.6849805
Short name T185
Test name
Test status
Simulation time 4166212065 ps
CPU time 88.25 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:52:04 PM PDT 24
Peak memory 365660 kb
Host smart-1b78a55b-261a-46e4-97cb-5c72d67a8fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6849805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.6849805
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1316797290
Short name T682
Test name
Test status
Simulation time 6565211910 ps
CPU time 79.47 seconds
Started Mar 24 02:50:34 PM PDT 24
Finished Mar 24 02:51:54 PM PDT 24
Peak memory 366140 kb
Host smart-0ad6598a-08ed-469a-8270-16f9f388eeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316797290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1316797290
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.935471683
Short name T946
Test name
Test status
Simulation time 2268697920 ps
CPU time 2.84 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:50:38 PM PDT 24
Peak memory 204188 kb
Host smart-1c63d91d-5eaa-4690-82d3-854d592ea61e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935471683 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.935471683
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3402174143
Short name T82
Test name
Test status
Simulation time 10457591256 ps
CPU time 4.52 seconds
Started Mar 24 02:50:41 PM PDT 24
Finished Mar 24 02:50:45 PM PDT 24
Peak memory 233020 kb
Host smart-136c627b-a279-4739-b348-6bbb8aba9dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402174143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3402174143
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3188365990
Short name T636
Test name
Test status
Simulation time 10107191632 ps
CPU time 16.57 seconds
Started Mar 24 02:50:34 PM PDT 24
Finished Mar 24 02:50:51 PM PDT 24
Peak memory 314876 kb
Host smart-4bbae496-b5f3-40a6-8b5c-5f402ecae0da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188365990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3188365990
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2226627356
Short name T837
Test name
Test status
Simulation time 500856346 ps
CPU time 2.88 seconds
Started Mar 24 02:50:37 PM PDT 24
Finished Mar 24 02:50:40 PM PDT 24
Peak memory 204160 kb
Host smart-63f74d28-f2ac-4a5e-8773-9eaa03e7e8bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226627356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2226627356
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3080623433
Short name T290
Test name
Test status
Simulation time 1428139464 ps
CPU time 3.93 seconds
Started Mar 24 02:50:33 PM PDT 24
Finished Mar 24 02:50:37 PM PDT 24
Peak memory 204168 kb
Host smart-095a17c2-3b6f-425b-ac25-520f65344797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080623433 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3080623433
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2077568559
Short name T598
Test name
Test status
Simulation time 2576293803 ps
CPU time 24.63 seconds
Started Mar 24 02:50:34 PM PDT 24
Finished Mar 24 02:50:58 PM PDT 24
Peak memory 204156 kb
Host smart-8e109be4-536b-497b-95ce-09ea96266fa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077568559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2077568559
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3855440629
Short name T386
Test name
Test status
Simulation time 3250613832 ps
CPU time 13.03 seconds
Started Mar 24 02:50:36 PM PDT 24
Finished Mar 24 02:50:49 PM PDT 24
Peak memory 216748 kb
Host smart-855dbe03-2df7-4f91-9b44-ee1dbcc25d34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855440629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3855440629
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2990111354
Short name T869
Test name
Test status
Simulation time 34654911137 ps
CPU time 739.41 seconds
Started Mar 24 02:50:34 PM PDT 24
Finished Mar 24 03:02:54 PM PDT 24
Peak memory 4195244 kb
Host smart-03630557-8ebe-4266-83d2-baa68e308e21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990111354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2990111354
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2926510013
Short name T651
Test name
Test status
Simulation time 2286083476 ps
CPU time 6.93 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:50:42 PM PDT 24
Peak memory 213848 kb
Host smart-db3ea03a-22b9-4e69-a893-837862ad638a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926510013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2926510013
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.1326898068
Short name T437
Test name
Test status
Simulation time 1879011916 ps
CPU time 5.46 seconds
Started Mar 24 02:50:41 PM PDT 24
Finished Mar 24 02:50:47 PM PDT 24
Peak memory 212064 kb
Host smart-17346d04-6790-4374-a16c-fe4ee96c22fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326898068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.1326898068
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2361771951
Short name T462
Test name
Test status
Simulation time 18364235 ps
CPU time 0.67 seconds
Started Mar 24 02:50:51 PM PDT 24
Finished Mar 24 02:50:52 PM PDT 24
Peak memory 203988 kb
Host smart-ecec5f45-84d6-4a35-b2c9-0d53c05e536a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361771951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2361771951
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.201546422
Short name T1078
Test name
Test status
Simulation time 153990317 ps
CPU time 1.33 seconds
Started Mar 24 02:50:40 PM PDT 24
Finished Mar 24 02:50:41 PM PDT 24
Peak memory 212320 kb
Host smart-3343258a-ef2f-4b14-87ca-c43ebfe5c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201546422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.201546422
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2631971948
Short name T585
Test name
Test status
Simulation time 2474789639 ps
CPU time 18.74 seconds
Started Mar 24 02:50:39 PM PDT 24
Finished Mar 24 02:50:58 PM PDT 24
Peak memory 276136 kb
Host smart-9dc0bb9e-3c7a-4dcf-9727-1d7863f4c5bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631971948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2631971948
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1659166651
Short name T20
Test name
Test status
Simulation time 5681136563 ps
CPU time 42.2 seconds
Started Mar 24 02:50:41 PM PDT 24
Finished Mar 24 02:51:23 PM PDT 24
Peak memory 530948 kb
Host smart-c14240c4-b925-4de9-a4a9-d1eb2bad2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659166651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1659166651
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2512920050
Short name T1040
Test name
Test status
Simulation time 4045538172 ps
CPU time 106.15 seconds
Started Mar 24 02:50:47 PM PDT 24
Finished Mar 24 02:52:33 PM PDT 24
Peak memory 577392 kb
Host smart-c58917ff-508a-4dea-ac20-637a73a74627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512920050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2512920050
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1516331969
Short name T35
Test name
Test status
Simulation time 166560958 ps
CPU time 0.95 seconds
Started Mar 24 02:50:37 PM PDT 24
Finished Mar 24 02:50:38 PM PDT 24
Peak memory 203952 kb
Host smart-efa3ad69-e2b4-4f4c-b716-bff8abc0fe5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516331969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1516331969
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.821319184
Short name T877
Test name
Test status
Simulation time 1060673072 ps
CPU time 3.94 seconds
Started Mar 24 02:50:39 PM PDT 24
Finished Mar 24 02:50:43 PM PDT 24
Peak memory 204144 kb
Host smart-8f4bffcc-dfc7-4c7f-bd68-7e008f3725a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821319184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
821319184
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2283155469
Short name T762
Test name
Test status
Simulation time 4081650378 ps
CPU time 124.48 seconds
Started Mar 24 02:50:39 PM PDT 24
Finished Mar 24 02:52:44 PM PDT 24
Peak memory 1179228 kb
Host smart-324e34e1-42b6-4775-865d-ae19d35c1588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283155469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2283155469
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_override.3466478030
Short name T1103
Test name
Test status
Simulation time 17110361 ps
CPU time 0.63 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:50:36 PM PDT 24
Peak memory 203816 kb
Host smart-b058caee-c6f0-4931-aa68-539b85e36eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466478030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3466478030
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1301558287
Short name T778
Test name
Test status
Simulation time 2474726280 ps
CPU time 40.19 seconds
Started Mar 24 02:50:35 PM PDT 24
Finished Mar 24 02:51:16 PM PDT 24
Peak memory 318120 kb
Host smart-d0c35d10-34b1-499c-90a6-6e7efbe8ea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301558287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1301558287
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.4185176629
Short name T1081
Test name
Test status
Simulation time 772402039 ps
CPU time 3.98 seconds
Started Mar 24 02:50:46 PM PDT 24
Finished Mar 24 02:50:50 PM PDT 24
Peak memory 204220 kb
Host smart-955c4b9d-854f-49a9-852b-60a15ffee13d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185176629 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.4185176629
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1005855422
Short name T443
Test name
Test status
Simulation time 10095815890 ps
CPU time 14.51 seconds
Started Mar 24 02:50:44 PM PDT 24
Finished Mar 24 02:50:58 PM PDT 24
Peak memory 267224 kb
Host smart-f47d89e4-b5ad-4fa2-9284-f8c331d1783b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005855422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1005855422
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3278019986
Short name T678
Test name
Test status
Simulation time 10208299283 ps
CPU time 22.37 seconds
Started Mar 24 02:50:44 PM PDT 24
Finished Mar 24 02:51:06 PM PDT 24
Peak memory 363072 kb
Host smart-7dd07e18-7b79-46f4-9787-d02acf9b9292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278019986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3278019986
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2433818178
Short name T216
Test name
Test status
Simulation time 788053109 ps
CPU time 2.35 seconds
Started Mar 24 02:50:43 PM PDT 24
Finished Mar 24 02:50:46 PM PDT 24
Peak memory 204156 kb
Host smart-9a321446-8dee-448a-bf35-31c563424050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433818178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2433818178
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1454459685
Short name T523
Test name
Test status
Simulation time 2171174307 ps
CPU time 5.1 seconds
Started Mar 24 02:50:38 PM PDT 24
Finished Mar 24 02:50:43 PM PDT 24
Peak memory 204980 kb
Host smart-2fed4271-be87-40c4-b851-8f235b974ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454459685 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1454459685
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.378905956
Short name T864
Test name
Test status
Simulation time 16427045449 ps
CPU time 39.08 seconds
Started Mar 24 02:50:41 PM PDT 24
Finished Mar 24 02:51:21 PM PDT 24
Peak memory 204248 kb
Host smart-d3e4a782-868a-4374-bc41-93020d2270c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378905956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.378905956
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1834112404
Short name T966
Test name
Test status
Simulation time 303381343 ps
CPU time 12.78 seconds
Started Mar 24 02:50:47 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 204172 kb
Host smart-a0875699-6055-45ce-9fd3-ac0ffaf1d05f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834112404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1834112404
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.498944761
Short name T871
Test name
Test status
Simulation time 9617697730 ps
CPU time 5.23 seconds
Started Mar 24 02:50:45 PM PDT 24
Finished Mar 24 02:50:51 PM PDT 24
Peak memory 204160 kb
Host smart-fda74edf-9229-4e3b-b76a-f2a645185362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498944761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.498944761
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2522781828
Short name T882
Test name
Test status
Simulation time 4882882275 ps
CPU time 6.49 seconds
Started Mar 24 02:50:38 PM PDT 24
Finished Mar 24 02:50:45 PM PDT 24
Peak memory 212472 kb
Host smart-5ec22bc8-4721-40ec-bf2e-396502d9baa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522781828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2522781828
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1893675153
Short name T808
Test name
Test status
Simulation time 18451323 ps
CPU time 0.62 seconds
Started Mar 24 02:50:48 PM PDT 24
Finished Mar 24 02:50:49 PM PDT 24
Peak memory 203916 kb
Host smart-549229d7-74c7-40d7-891f-f280c50f9ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893675153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1893675153
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.640209897
Short name T818
Test name
Test status
Simulation time 39611580 ps
CPU time 1.89 seconds
Started Mar 24 02:50:51 PM PDT 24
Finished Mar 24 02:50:53 PM PDT 24
Peak memory 212464 kb
Host smart-83939128-a315-42f3-8de7-825038680390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640209897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.640209897
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.4200844465
Short name T630
Test name
Test status
Simulation time 516311139 ps
CPU time 4.54 seconds
Started Mar 24 02:50:43 PM PDT 24
Finished Mar 24 02:50:48 PM PDT 24
Peak memory 236224 kb
Host smart-3fd75619-ccff-4d4c-92b0-ba0c45ca65f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200844465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.4200844465
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.46224070
Short name T92
Test name
Test status
Simulation time 12104385770 ps
CPU time 112.79 seconds
Started Mar 24 02:50:44 PM PDT 24
Finished Mar 24 02:52:37 PM PDT 24
Peak memory 558420 kb
Host smart-53c00784-1434-4e86-9cae-b8a95175e5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46224070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.46224070
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.393753554
Short name T1083
Test name
Test status
Simulation time 5667364292 ps
CPU time 97.58 seconds
Started Mar 24 02:50:51 PM PDT 24
Finished Mar 24 02:52:29 PM PDT 24
Peak memory 518996 kb
Host smart-087ec56f-ecca-44d5-bf71-0a708be5aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393753554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.393753554
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1177844699
Short name T475
Test name
Test status
Simulation time 1652103069 ps
CPU time 3.79 seconds
Started Mar 24 02:50:50 PM PDT 24
Finished Mar 24 02:50:55 PM PDT 24
Peak memory 223972 kb
Host smart-7190bd41-f8e3-4390-9326-a95c9d3e1b95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177844699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1177844699
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1174088459
Short name T155
Test name
Test status
Simulation time 21613849496 ps
CPU time 65.34 seconds
Started Mar 24 02:50:43 PM PDT 24
Finished Mar 24 02:51:48 PM PDT 24
Peak memory 843384 kb
Host smart-6e407a78-e646-4b82-b222-fafe21e8be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174088459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1174088459
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_override.2530274521
Short name T921
Test name
Test status
Simulation time 168414797 ps
CPU time 0.62 seconds
Started Mar 24 02:50:46 PM PDT 24
Finished Mar 24 02:50:47 PM PDT 24
Peak memory 203824 kb
Host smart-5994032e-8729-4841-a67d-507452795da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530274521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2530274521
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1855569935
Short name T456
Test name
Test status
Simulation time 3273367836 ps
CPU time 87.96 seconds
Started Mar 24 02:50:43 PM PDT 24
Finished Mar 24 02:52:11 PM PDT 24
Peak memory 287192 kb
Host smart-7d9c971a-b5bb-4fd5-8534-c7e09f80f18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855569935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1855569935
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.145585352
Short name T543
Test name
Test status
Simulation time 3293958545 ps
CPU time 35.65 seconds
Started Mar 24 02:50:44 PM PDT 24
Finished Mar 24 02:51:20 PM PDT 24
Peak memory 293756 kb
Host smart-8fcdd45e-e743-4f6b-9517-9cbc34bb464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145585352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.145585352
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2239896996
Short name T1101
Test name
Test status
Simulation time 554874281 ps
CPU time 2.55 seconds
Started Mar 24 02:50:51 PM PDT 24
Finished Mar 24 02:50:54 PM PDT 24
Peak memory 204144 kb
Host smart-944a172a-6964-4725-ba1e-5e5b17fabd25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239896996 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2239896996
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3328687904
Short name T260
Test name
Test status
Simulation time 10053735663 ps
CPU time 83.18 seconds
Started Mar 24 02:50:50 PM PDT 24
Finished Mar 24 02:52:13 PM PDT 24
Peak memory 600412 kb
Host smart-9673a781-fabf-4bc8-ac50-fb4dd134570e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328687904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3328687904
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.4257564348
Short name T409
Test name
Test status
Simulation time 10038411761 ps
CPU time 65.22 seconds
Started Mar 24 02:50:49 PM PDT 24
Finished Mar 24 02:51:55 PM PDT 24
Peak memory 612176 kb
Host smart-cfdbdb55-5031-488a-a052-00b5ec02d27b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257564348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.4257564348
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.4235355275
Short name T233
Test name
Test status
Simulation time 1487654515 ps
CPU time 2.4 seconds
Started Mar 24 02:50:51 PM PDT 24
Finished Mar 24 02:50:54 PM PDT 24
Peak memory 204160 kb
Host smart-53b1eb78-76b2-475d-933f-cbedb746316b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235355275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.4235355275
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3857065670
Short name T796
Test name
Test status
Simulation time 4642235755 ps
CPU time 6.73 seconds
Started Mar 24 02:50:50 PM PDT 24
Finished Mar 24 02:50:57 PM PDT 24
Peak memory 220480 kb
Host smart-b1f89263-24a8-4fd0-8b81-87a4f6f70e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857065670 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3857065670
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.12267364
Short name T391
Test name
Test status
Simulation time 2334346782 ps
CPU time 20.84 seconds
Started Mar 24 02:50:45 PM PDT 24
Finished Mar 24 02:51:07 PM PDT 24
Peak memory 204244 kb
Host smart-5798543e-6304-4584-adfc-8be3da1592d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12267364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_targ
et_smoke.12267364
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3815788585
Short name T424
Test name
Test status
Simulation time 1734559468 ps
CPU time 19 seconds
Started Mar 24 02:50:48 PM PDT 24
Finished Mar 24 02:51:07 PM PDT 24
Peak memory 204140 kb
Host smart-96d845c4-d7a2-4733-911a-4e83414a8126
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815788585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3815788585
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3987743119
Short name T486
Test name
Test status
Simulation time 29891021651 ps
CPU time 2773.93 seconds
Started Mar 24 02:50:49 PM PDT 24
Finished Mar 24 03:37:04 PM PDT 24
Peak memory 6861000 kb
Host smart-a126b942-50f9-49d5-84dd-0b91e1ebcf2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987743119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3987743119
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3702136526
Short name T360
Test name
Test status
Simulation time 10730255087 ps
CPU time 7.51 seconds
Started Mar 24 02:50:51 PM PDT 24
Finished Mar 24 02:50:59 PM PDT 24
Peak memory 211356 kb
Host smart-76000776-21aa-4c15-93e1-275b033690e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702136526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3702136526
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2602876208
Short name T790
Test name
Test status
Simulation time 56207903 ps
CPU time 0.62 seconds
Started Mar 24 02:51:00 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 203968 kb
Host smart-1593b0d6-891f-4486-afec-8a8a358b95d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602876208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2602876208
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.937642130
Short name T714
Test name
Test status
Simulation time 235375505 ps
CPU time 1.43 seconds
Started Mar 24 02:50:55 PM PDT 24
Finished Mar 24 02:50:56 PM PDT 24
Peak memory 212360 kb
Host smart-2cdd099f-3d46-4661-b72e-132bf32ee412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937642130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.937642130
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3676569927
Short name T88
Test name
Test status
Simulation time 303120498 ps
CPU time 10.51 seconds
Started Mar 24 02:50:50 PM PDT 24
Finished Mar 24 02:51:01 PM PDT 24
Peak memory 242680 kb
Host smart-e58d5d8c-c335-4875-968c-d83b18ec626d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676569927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3676569927
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.374815548
Short name T81
Test name
Test status
Simulation time 4032267992 ps
CPU time 76.88 seconds
Started Mar 24 02:51:03 PM PDT 24
Finished Mar 24 02:52:20 PM PDT 24
Peak memory 660888 kb
Host smart-22e9c8b5-d1e5-4a91-aa3e-c9d499c11eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374815548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.374815548
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.632461738
Short name T1000
Test name
Test status
Simulation time 5199081571 ps
CPU time 34.4 seconds
Started Mar 24 02:50:53 PM PDT 24
Finished Mar 24 02:51:28 PM PDT 24
Peak memory 515512 kb
Host smart-24d8de03-4549-4c67-9384-5f68d3ba0178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632461738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.632461738
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.113224391
Short name T526
Test name
Test status
Simulation time 126739053 ps
CPU time 1.11 seconds
Started Mar 24 02:50:50 PM PDT 24
Finished Mar 24 02:50:51 PM PDT 24
Peak memory 204124 kb
Host smart-e04b703c-ea2f-4f3c-81eb-ed5a02623284
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113224391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fm
t.113224391
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2647075918
Short name T746
Test name
Test status
Simulation time 140617503 ps
CPU time 7.88 seconds
Started Mar 24 02:50:53 PM PDT 24
Finished Mar 24 02:51:02 PM PDT 24
Peak memory 227908 kb
Host smart-df7efcd0-8473-480c-8b65-5b67986107f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647075918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2647075918
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.4291405219
Short name T1044
Test name
Test status
Simulation time 8808119074 ps
CPU time 53.55 seconds
Started Mar 24 02:50:49 PM PDT 24
Finished Mar 24 02:51:43 PM PDT 24
Peak memory 700664 kb
Host smart-1a42f56d-511b-49dc-8cf2-cc5f9d879646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291405219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.4291405219
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_override.1498460069
Short name T289
Test name
Test status
Simulation time 17826056 ps
CPU time 0.67 seconds
Started Mar 24 02:50:51 PM PDT 24
Finished Mar 24 02:50:52 PM PDT 24
Peak memory 203876 kb
Host smart-ad74163b-a62b-42b6-b9c4-e2dc639f9273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498460069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1498460069
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3378966974
Short name T756
Test name
Test status
Simulation time 27296874097 ps
CPU time 1231 seconds
Started Mar 24 02:50:58 PM PDT 24
Finished Mar 24 03:11:29 PM PDT 24
Peak memory 1004552 kb
Host smart-526d4264-9d62-4f10-b43c-d2a5c1f5a515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378966974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3378966974
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3635211246
Short name T313
Test name
Test status
Simulation time 13319174698 ps
CPU time 86.24 seconds
Started Mar 24 02:50:50 PM PDT 24
Finished Mar 24 02:52:17 PM PDT 24
Peak memory 295344 kb
Host smart-096a21ec-f6ac-4fd6-a719-43bafc74a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635211246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3635211246
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1353047208
Short name T645
Test name
Test status
Simulation time 1697708698 ps
CPU time 3.93 seconds
Started Mar 24 02:50:55 PM PDT 24
Finished Mar 24 02:50:59 PM PDT 24
Peak memory 204172 kb
Host smart-51c234e5-4aa1-42da-a861-09bb19550f00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353047208 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1353047208
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2585635155
Short name T54
Test name
Test status
Simulation time 10090338941 ps
CPU time 83.74 seconds
Started Mar 24 02:50:55 PM PDT 24
Finished Mar 24 02:52:19 PM PDT 24
Peak memory 652816 kb
Host smart-25c90a07-3c72-44f4-8ce1-6a1903cfdfc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585635155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2585635155
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1315690990
Short name T710
Test name
Test status
Simulation time 10284416962 ps
CPU time 15.66 seconds
Started Mar 24 02:51:01 PM PDT 24
Finished Mar 24 02:51:16 PM PDT 24
Peak memory 326008 kb
Host smart-db14afd4-1535-44f6-996b-4a1b08d0a056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315690990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1315690990
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1343415668
Short name T380
Test name
Test status
Simulation time 756744871 ps
CPU time 2.53 seconds
Started Mar 24 02:50:57 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 204220 kb
Host smart-74b774ae-cc6e-4a87-bb69-e30ed0b8c56a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343415668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1343415668
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1251353245
Short name T541
Test name
Test status
Simulation time 3554748829 ps
CPU time 4.69 seconds
Started Mar 24 02:50:56 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 216684 kb
Host smart-6de5f9f5-46d2-4ee2-90ec-5de147bf9b9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251353245 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1251353245
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2765242712
Short name T395
Test name
Test status
Simulation time 1265190156 ps
CPU time 47.67 seconds
Started Mar 24 02:50:57 PM PDT 24
Finished Mar 24 02:51:45 PM PDT 24
Peak memory 204040 kb
Host smart-3c772d2e-96c8-4b0b-a0e7-0aa48be1fba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765242712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2765242712
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2348778250
Short name T1065
Test name
Test status
Simulation time 4738875897 ps
CPU time 49.69 seconds
Started Mar 24 02:50:57 PM PDT 24
Finished Mar 24 02:51:47 PM PDT 24
Peak memory 204216 kb
Host smart-c46522a8-2bc1-474f-8880-8dac752341e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348778250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2348778250
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3196043673
Short name T551
Test name
Test status
Simulation time 22311273863 ps
CPU time 1416.91 seconds
Started Mar 24 02:51:01 PM PDT 24
Finished Mar 24 03:14:39 PM PDT 24
Peak memory 5388496 kb
Host smart-9a1dfc3a-1c78-4123-9807-3d98fc344723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196043673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3196043673
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1509359765
Short name T693
Test name
Test status
Simulation time 2410928631 ps
CPU time 6.53 seconds
Started Mar 24 02:50:54 PM PDT 24
Finished Mar 24 02:51:01 PM PDT 24
Peak memory 204248 kb
Host smart-e7e10e89-a82c-46d3-beb7-69e1cc3035ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509359765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1509359765
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1680921153
Short name T94
Test name
Test status
Simulation time 19180127 ps
CPU time 0.6 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:51:06 PM PDT 24
Peak memory 203940 kb
Host smart-9ee8befc-b6cd-4187-ae83-20e8a7256271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680921153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1680921153
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3021993889
Short name T1024
Test name
Test status
Simulation time 118875048 ps
CPU time 1.8 seconds
Started Mar 24 02:50:59 PM PDT 24
Finished Mar 24 02:51:01 PM PDT 24
Peak memory 212608 kb
Host smart-332cb141-8cfa-4419-a830-bf80ef95af08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021993889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3021993889
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.66635629
Short name T263
Test name
Test status
Simulation time 908343991 ps
CPU time 12.09 seconds
Started Mar 24 02:51:00 PM PDT 24
Finished Mar 24 02:51:12 PM PDT 24
Peak memory 246288 kb
Host smart-b08e7ff2-13d6-4af0-828c-af39d51eeca4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66635629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty
.66635629
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1542223539
Short name T80
Test name
Test status
Simulation time 10940870901 ps
CPU time 150.35 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:53:36 PM PDT 24
Peak memory 601588 kb
Host smart-8cfeacca-d963-4c30-9cc1-c5513ab8f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542223539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1542223539
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.550964164
Short name T405
Test name
Test status
Simulation time 11025543316 ps
CPU time 122.76 seconds
Started Mar 24 02:51:03 PM PDT 24
Finished Mar 24 02:53:06 PM PDT 24
Peak memory 617324 kb
Host smart-bb8e26a8-9a8a-4283-85c7-a53857fb5186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550964164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.550964164
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3862054837
Short name T859
Test name
Test status
Simulation time 159090309 ps
CPU time 0.75 seconds
Started Mar 24 02:50:58 PM PDT 24
Finished Mar 24 02:50:59 PM PDT 24
Peak memory 203968 kb
Host smart-8d4409a7-6b74-4ea6-97b3-870caf50f644
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862054837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3862054837
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.4064181858
Short name T181
Test name
Test status
Simulation time 464740300 ps
CPU time 2.67 seconds
Started Mar 24 02:50:59 PM PDT 24
Finished Mar 24 02:51:02 PM PDT 24
Peak memory 204192 kb
Host smart-ddf6c5b5-2977-487e-b309-cd669c15e9c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064181858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.4064181858
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2137720945
Short name T460
Test name
Test status
Simulation time 4148473220 ps
CPU time 134.63 seconds
Started Mar 24 02:51:03 PM PDT 24
Finished Mar 24 02:53:17 PM PDT 24
Peak memory 1236584 kb
Host smart-82d30c96-315e-478b-bac4-d5e521787962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137720945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2137720945
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_override.303856309
Short name T1035
Test name
Test status
Simulation time 22016744 ps
CPU time 0.63 seconds
Started Mar 24 02:50:57 PM PDT 24
Finished Mar 24 02:50:58 PM PDT 24
Peak memory 203832 kb
Host smart-931466e7-f179-4ea3-9577-5790820ef2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303856309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.303856309
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2150117779
Short name T311
Test name
Test status
Simulation time 6168597436 ps
CPU time 144.49 seconds
Started Mar 24 02:51:02 PM PDT 24
Finished Mar 24 02:53:27 PM PDT 24
Peak memory 212452 kb
Host smart-6cdc1e91-482a-4d01-a5a4-eab3a77e8c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150117779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2150117779
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1490303278
Short name T757
Test name
Test status
Simulation time 19414659510 ps
CPU time 47.01 seconds
Started Mar 24 02:51:02 PM PDT 24
Finished Mar 24 02:51:50 PM PDT 24
Peak memory 301516 kb
Host smart-47f0f6e6-537c-4c47-9e66-5e7d2ce66a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490303278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1490303278
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.2347938385
Short name T576
Test name
Test status
Simulation time 466971482 ps
CPU time 2.46 seconds
Started Mar 24 02:51:03 PM PDT 24
Finished Mar 24 02:51:05 PM PDT 24
Peak memory 204168 kb
Host smart-db9e1f0f-f007-4471-8d78-a101909cfd5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347938385 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.2347938385
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.2425759730
Short name T1037
Test name
Test status
Simulation time 11108645115 ps
CPU time 8.4 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:51:14 PM PDT 24
Peak memory 255472 kb
Host smart-bd708ef0-a013-4b1c-9e60-80d70dae30fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425759730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.2425759730
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1307154707
Short name T285
Test name
Test status
Simulation time 10227933368 ps
CPU time 17.43 seconds
Started Mar 24 02:50:59 PM PDT 24
Finished Mar 24 02:51:16 PM PDT 24
Peak memory 342332 kb
Host smart-51ed0fed-949c-486a-99f1-bfabbff053bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307154707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1307154707
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.3773310842
Short name T411
Test name
Test status
Simulation time 1678927439 ps
CPU time 2.71 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:51:09 PM PDT 24
Peak memory 204160 kb
Host smart-85c715a1-60b5-4293-8da5-05042e11a3cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773310842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.3773310842
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2076637722
Short name T990
Test name
Test status
Simulation time 3878445427 ps
CPU time 4.3 seconds
Started Mar 24 02:50:59 PM PDT 24
Finished Mar 24 02:51:03 PM PDT 24
Peak memory 204240 kb
Host smart-fd016fad-d30e-4849-8534-0487a26f3e5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076637722 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2076637722
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.4189444317
Short name T911
Test name
Test status
Simulation time 3192475837 ps
CPU time 2.89 seconds
Started Mar 24 02:50:59 PM PDT 24
Finished Mar 24 02:51:02 PM PDT 24
Peak memory 204204 kb
Host smart-e000ed74-324f-4f20-8fbe-803f3dd51ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189444317 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.4189444317
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3215001295
Short name T310
Test name
Test status
Simulation time 4002086427 ps
CPU time 13.65 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:51:19 PM PDT 24
Peak memory 204180 kb
Host smart-b4523eab-08bb-4f02-a868-d14d31f7520a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215001295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3215001295
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2168109665
Short name T232
Test name
Test status
Simulation time 420883449 ps
CPU time 8.55 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:51:15 PM PDT 24
Peak memory 204164 kb
Host smart-fd8661e7-7615-4b4f-af35-726191c7eae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168109665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2168109665
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3637658054
Short name T1058
Test name
Test status
Simulation time 23221761373 ps
CPU time 1842.64 seconds
Started Mar 24 02:51:03 PM PDT 24
Finished Mar 24 03:21:46 PM PDT 24
Peak memory 5450084 kb
Host smart-88d8301f-71b8-400e-a74b-737fb5c05de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637658054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3637658054
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1309403870
Short name T1085
Test name
Test status
Simulation time 1639559446 ps
CPU time 7.97 seconds
Started Mar 24 02:50:59 PM PDT 24
Finished Mar 24 02:51:07 PM PDT 24
Peak memory 212392 kb
Host smart-24bb397a-da4e-4d7d-842c-006949c6f83e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309403870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1309403870
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3082009692
Short name T498
Test name
Test status
Simulation time 16225019 ps
CPU time 0.64 seconds
Started Mar 24 02:51:09 PM PDT 24
Finished Mar 24 02:51:10 PM PDT 24
Peak memory 203948 kb
Host smart-4dcbc65d-621e-4330-915a-50d5cc2d120d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082009692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3082009692
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.723889211
Short name T346
Test name
Test status
Simulation time 29334207 ps
CPU time 1.36 seconds
Started Mar 24 02:51:08 PM PDT 24
Finished Mar 24 02:51:09 PM PDT 24
Peak memory 212380 kb
Host smart-7a6c41c9-fac1-4c3c-a1f6-38ac2da0ad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723889211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.723889211
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.1990136936
Short name T587
Test name
Test status
Simulation time 301080257 ps
CPU time 6.42 seconds
Started Mar 24 02:51:03 PM PDT 24
Finished Mar 24 02:51:10 PM PDT 24
Peak memory 253160 kb
Host smart-b3d69df8-a542-4717-ac8c-9dc52e1a65b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990136936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.1990136936
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.694004348
Short name T19
Test name
Test status
Simulation time 1514713790 ps
CPU time 82.59 seconds
Started Mar 24 02:51:04 PM PDT 24
Finished Mar 24 02:52:27 PM PDT 24
Peak memory 387888 kb
Host smart-3bdce2a3-5137-4d26-8a8c-ddb249d2b31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694004348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.694004348
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.636149967
Short name T628
Test name
Test status
Simulation time 10657199909 ps
CPU time 34.24 seconds
Started Mar 24 02:51:02 PM PDT 24
Finished Mar 24 02:51:37 PM PDT 24
Peak memory 497040 kb
Host smart-4060d058-ba8b-4dbb-91e8-9ef3ba5d703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636149967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.636149967
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1030879633
Short name T769
Test name
Test status
Simulation time 84368939 ps
CPU time 0.94 seconds
Started Mar 24 02:51:05 PM PDT 24
Finished Mar 24 02:51:06 PM PDT 24
Peak memory 203908 kb
Host smart-27d546ea-2bea-4094-98cd-e2ff09fcbdd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030879633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1030879633
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3715896520
Short name T581
Test name
Test status
Simulation time 262849299 ps
CPU time 2.88 seconds
Started Mar 24 02:51:03 PM PDT 24
Finished Mar 24 02:51:06 PM PDT 24
Peak memory 204100 kb
Host smart-1a7be8ee-fddf-4588-9517-4d2e0ad1d7f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715896520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3715896520
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2183941258
Short name T696
Test name
Test status
Simulation time 3904658691 ps
CPU time 114.74 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:53:01 PM PDT 24
Peak memory 1063236 kb
Host smart-5695c076-2a87-44d8-ac29-0249e3efd8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183941258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2183941258
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_override.2745121400
Short name T458
Test name
Test status
Simulation time 20264175 ps
CPU time 0.66 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:51:07 PM PDT 24
Peak memory 203816 kb
Host smart-29e29502-28ac-470e-9143-082780d90ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745121400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2745121400
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2991370620
Short name T705
Test name
Test status
Simulation time 584516542 ps
CPU time 13.86 seconds
Started Mar 24 02:51:06 PM PDT 24
Finished Mar 24 02:51:20 PM PDT 24
Peak memory 247372 kb
Host smart-56380a78-c377-4d22-951e-804a28579632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991370620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2991370620
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.1117391504
Short name T752
Test name
Test status
Simulation time 1246084645 ps
CPU time 56.19 seconds
Started Mar 24 02:51:04 PM PDT 24
Finished Mar 24 02:52:01 PM PDT 24
Peak memory 326276 kb
Host smart-08678408-46d8-423a-85be-764cd30dec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117391504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.1117391504
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.3535439623
Short name T91
Test name
Test status
Simulation time 6192162586 ps
CPU time 547.73 seconds
Started Mar 24 02:51:04 PM PDT 24
Finished Mar 24 03:00:12 PM PDT 24
Peak memory 1088808 kb
Host smart-a7254f7e-e8f9-4c0e-8c08-db7c157b5a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535439623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.3535439623
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3952937835
Short name T1055
Test name
Test status
Simulation time 808682630 ps
CPU time 3.79 seconds
Started Mar 24 02:51:08 PM PDT 24
Finished Mar 24 02:51:12 PM PDT 24
Peak memory 204160 kb
Host smart-291d26f7-e9b6-4dbe-aee0-63a1485daba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952937835 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3952937835
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1649589039
Short name T806
Test name
Test status
Simulation time 10142482880 ps
CPU time 64.39 seconds
Started Mar 24 02:51:08 PM PDT 24
Finished Mar 24 02:52:13 PM PDT 24
Peak memory 540388 kb
Host smart-60b3f6f5-77c9-41ea-a945-c33be1606207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649589039 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1649589039
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1460948730
Short name T247
Test name
Test status
Simulation time 10030409250 ps
CPU time 93.3 seconds
Started Mar 24 02:51:11 PM PDT 24
Finished Mar 24 02:52:44 PM PDT 24
Peak memory 708444 kb
Host smart-e51690b4-fda6-4dd7-aebb-2b95bd57502f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460948730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1460948730
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.868904473
Short name T741
Test name
Test status
Simulation time 392808820 ps
CPU time 2.62 seconds
Started Mar 24 02:51:10 PM PDT 24
Finished Mar 24 02:51:13 PM PDT 24
Peak memory 204176 kb
Host smart-74addafe-c4c8-40a6-8345-481d4641fc44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868904473 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.868904473
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1643707805
Short name T897
Test name
Test status
Simulation time 1495862135 ps
CPU time 6.85 seconds
Started Mar 24 02:51:09 PM PDT 24
Finished Mar 24 02:51:17 PM PDT 24
Peak memory 220320 kb
Host smart-e279cd4f-fdc4-4ecc-824e-b735445e8416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643707805 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1643707805
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.771398304
Short name T970
Test name
Test status
Simulation time 10047670731 ps
CPU time 25.26 seconds
Started Mar 24 02:51:05 PM PDT 24
Finished Mar 24 02:51:30 PM PDT 24
Peak memory 204128 kb
Host smart-91299e09-5f93-4488-a60f-c78a1a6bf657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771398304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.771398304
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1217050531
Short name T998
Test name
Test status
Simulation time 2883681431 ps
CPU time 30.09 seconds
Started Mar 24 02:51:11 PM PDT 24
Finished Mar 24 02:51:42 PM PDT 24
Peak memory 204200 kb
Host smart-a266e9e9-1608-403e-ab9f-a25b5c74f1ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217050531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1217050531
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.4273396068
Short name T681
Test name
Test status
Simulation time 31512875674 ps
CPU time 3444.16 seconds
Started Mar 24 02:51:09 PM PDT 24
Finished Mar 24 03:48:34 PM PDT 24
Peak memory 7390468 kb
Host smart-aa0b90b8-158c-4564-a356-27f175ed6eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273396068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.4273396068
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2652225600
Short name T13
Test name
Test status
Simulation time 1231721101 ps
CPU time 6.84 seconds
Started Mar 24 02:51:08 PM PDT 24
Finished Mar 24 02:51:15 PM PDT 24
Peak memory 220300 kb
Host smart-3c26fe58-b45d-4e27-924d-75049272a684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652225600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2652225600
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.414829219
Short name T799
Test name
Test status
Simulation time 17804408 ps
CPU time 0.67 seconds
Started Mar 24 02:51:16 PM PDT 24
Finished Mar 24 02:51:16 PM PDT 24
Peak memory 203924 kb
Host smart-62825c1c-66dd-4cf2-bb35-bcabe3ae18b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414829219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.414829219
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.4294456654
Short name T337
Test name
Test status
Simulation time 30151390 ps
CPU time 1.25 seconds
Started Mar 24 02:51:11 PM PDT 24
Finished Mar 24 02:51:12 PM PDT 24
Peak memory 212360 kb
Host smart-5ae19875-2977-4c1b-a738-2c07447becc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294456654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4294456654
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3527606920
Short name T932
Test name
Test status
Simulation time 234162824 ps
CPU time 5.52 seconds
Started Mar 24 02:51:10 PM PDT 24
Finished Mar 24 02:51:16 PM PDT 24
Peak memory 250444 kb
Host smart-d6543d2c-b2db-4de9-a94d-1edac1ca68c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527606920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3527606920
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1492114951
Short name T1082
Test name
Test status
Simulation time 1611444823 ps
CPU time 107.72 seconds
Started Mar 24 02:51:11 PM PDT 24
Finished Mar 24 02:52:59 PM PDT 24
Peak memory 588128 kb
Host smart-29ae833d-230f-441b-a004-4aea3acf5eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492114951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1492114951
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2228999608
Short name T684
Test name
Test status
Simulation time 1451839281 ps
CPU time 40.53 seconds
Started Mar 24 02:51:13 PM PDT 24
Finished Mar 24 02:51:54 PM PDT 24
Peak memory 549436 kb
Host smart-99bb50b5-e5da-4a6c-be61-e5432e069597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228999608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2228999608
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1076064000
Short name T631
Test name
Test status
Simulation time 298986614 ps
CPU time 0.84 seconds
Started Mar 24 02:51:08 PM PDT 24
Finished Mar 24 02:51:09 PM PDT 24
Peak memory 203900 kb
Host smart-0d6f4c3e-064f-452b-b920-2f85da2c75ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076064000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1076064000
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2741402093
Short name T329
Test name
Test status
Simulation time 119707259 ps
CPU time 2.51 seconds
Started Mar 24 02:51:11 PM PDT 24
Finished Mar 24 02:51:14 PM PDT 24
Peak memory 204192 kb
Host smart-8c1c9510-51c7-463b-a1f7-6947a617226f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741402093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2741402093
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3406309792
Short name T904
Test name
Test status
Simulation time 5948970921 ps
CPU time 216.13 seconds
Started Mar 24 02:51:09 PM PDT 24
Finished Mar 24 02:54:45 PM PDT 24
Peak memory 944996 kb
Host smart-8bf83aa9-6827-4ea7-932d-4468acd27acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406309792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3406309792
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_override.331587219
Short name T589
Test name
Test status
Simulation time 33363251 ps
CPU time 0.64 seconds
Started Mar 24 02:51:08 PM PDT 24
Finished Mar 24 02:51:09 PM PDT 24
Peak memory 203832 kb
Host smart-80bc292e-a0af-4b68-9b15-42f37786a14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331587219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.331587219
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2254748363
Short name T1017
Test name
Test status
Simulation time 12748925412 ps
CPU time 195.39 seconds
Started Mar 24 02:51:13 PM PDT 24
Finished Mar 24 02:54:29 PM PDT 24
Peak memory 471796 kb
Host smart-f169a9a9-06e6-4021-bff3-a60283dd77f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254748363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2254748363
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.2640068580
Short name T224
Test name
Test status
Simulation time 6542793542 ps
CPU time 156.53 seconds
Started Mar 24 02:51:14 PM PDT 24
Finished Mar 24 02:53:51 PM PDT 24
Peak memory 319904 kb
Host smart-b6eecd93-4f1c-46e9-8dfa-2e66d758e5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640068580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2640068580
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4057101639
Short name T1039
Test name
Test status
Simulation time 1211061554 ps
CPU time 5.36 seconds
Started Mar 24 02:51:15 PM PDT 24
Finished Mar 24 02:51:21 PM PDT 24
Peak memory 205908 kb
Host smart-6c6b6260-e972-490a-a454-1459d72d4855
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057101639 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4057101639
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.4255144604
Short name T455
Test name
Test status
Simulation time 10025136262 ps
CPU time 76.82 seconds
Started Mar 24 02:51:21 PM PDT 24
Finished Mar 24 02:52:38 PM PDT 24
Peak memory 614708 kb
Host smart-c8450e2d-b2da-4ca7-afd6-a5f02d5db9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255144604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.4255144604
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3891071886
Short name T56
Test name
Test status
Simulation time 10155270414 ps
CPU time 38.53 seconds
Started Mar 24 02:51:15 PM PDT 24
Finished Mar 24 02:51:54 PM PDT 24
Peak memory 455828 kb
Host smart-d853ce3f-bb7f-4a0a-8318-4c7e59d2efe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891071886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3891071886
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.89365326
Short name T237
Test name
Test status
Simulation time 1467266116 ps
CPU time 2.55 seconds
Started Mar 24 02:51:15 PM PDT 24
Finished Mar 24 02:51:18 PM PDT 24
Peak memory 204192 kb
Host smart-8f5c62a6-9527-47b4-ba86-32b4552cc5b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89365326 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.i2c_target_hrst.89365326
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2394188075
Short name T675
Test name
Test status
Simulation time 4005050683 ps
CPU time 7.66 seconds
Started Mar 24 02:51:16 PM PDT 24
Finished Mar 24 02:51:24 PM PDT 24
Peak memory 218580 kb
Host smart-c5230f9b-d5b4-4a83-8f53-02637ef1cd86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394188075 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2394188075
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2760877569
Short name T893
Test name
Test status
Simulation time 848307634 ps
CPU time 11.28 seconds
Started Mar 24 02:51:11 PM PDT 24
Finished Mar 24 02:51:22 PM PDT 24
Peak memory 204176 kb
Host smart-50877e5c-e416-4901-9a1f-21038fa810d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760877569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2760877569
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.4124561565
Short name T726
Test name
Test status
Simulation time 3165830839 ps
CPU time 31.64 seconds
Started Mar 24 02:51:14 PM PDT 24
Finished Mar 24 02:51:46 PM PDT 24
Peak memory 231024 kb
Host smart-4e368199-4386-4b50-83b3-d76133d45cda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124561565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.4124561565
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3506249927
Short name T572
Test name
Test status
Simulation time 21377911232 ps
CPU time 112.7 seconds
Started Mar 24 02:51:17 PM PDT 24
Finished Mar 24 02:53:10 PM PDT 24
Peak memory 569496 kb
Host smart-e34f73d7-7fc8-45ee-842a-7debabbf9ad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506249927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3506249927
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1202485450
Short name T300
Test name
Test status
Simulation time 1582878568 ps
CPU time 7.77 seconds
Started Mar 24 02:51:14 PM PDT 24
Finished Mar 24 02:51:22 PM PDT 24
Peak memory 212432 kb
Host smart-4d6c7644-6089-49f4-8dfd-402fb572ac15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202485450 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1202485450
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3377468812
Short name T417
Test name
Test status
Simulation time 21056024 ps
CPU time 0.59 seconds
Started Mar 24 02:51:22 PM PDT 24
Finished Mar 24 02:51:23 PM PDT 24
Peak memory 203912 kb
Host smart-e4f787ca-c1c7-41bd-9573-a28dc34c9ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377468812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3377468812
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3910292268
Short name T804
Test name
Test status
Simulation time 59053018 ps
CPU time 1.16 seconds
Started Mar 24 02:51:23 PM PDT 24
Finished Mar 24 02:51:24 PM PDT 24
Peak memory 220616 kb
Host smart-903c1733-45f7-4e93-be16-7b7fc7ef3840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910292268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3910292268
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1232418313
Short name T396
Test name
Test status
Simulation time 1129214691 ps
CPU time 5.34 seconds
Started Mar 24 02:51:20 PM PDT 24
Finished Mar 24 02:51:26 PM PDT 24
Peak memory 261296 kb
Host smart-007ceac2-0e9a-4ada-803d-babde2d5c3e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232418313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1232418313
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.2028995380
Short name T735
Test name
Test status
Simulation time 8323782112 ps
CPU time 122.89 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:53:27 PM PDT 24
Peak memory 604260 kb
Host smart-6a790819-d4df-4d13-96e7-70edd62aebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028995380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2028995380
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.4087602258
Short name T481
Test name
Test status
Simulation time 1225446069 ps
CPU time 72.79 seconds
Started Mar 24 02:51:16 PM PDT 24
Finished Mar 24 02:52:29 PM PDT 24
Peak memory 383192 kb
Host smart-f6f95040-f844-4a05-b6ab-c35971299f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087602258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4087602258
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2668186236
Short name T323
Test name
Test status
Simulation time 115641964 ps
CPU time 1.21 seconds
Started Mar 24 02:51:17 PM PDT 24
Finished Mar 24 02:51:19 PM PDT 24
Peak memory 204184 kb
Host smart-9412ce83-1e0e-42a1-aa84-8f2207d476a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668186236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2668186236
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1674331579
Short name T1036
Test name
Test status
Simulation time 97107134 ps
CPU time 2.57 seconds
Started Mar 24 02:51:14 PM PDT 24
Finished Mar 24 02:51:17 PM PDT 24
Peak memory 216228 kb
Host smart-55be171c-84c3-4232-b96a-7872e001db63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674331579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1674331579
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1985349102
Short name T157
Test name
Test status
Simulation time 8972372137 ps
CPU time 126.86 seconds
Started Mar 24 02:51:14 PM PDT 24
Finished Mar 24 02:53:21 PM PDT 24
Peak memory 1294464 kb
Host smart-6ccc9686-0474-49e2-b027-cc0f53dd326e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985349102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1985349102
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_override.249196174
Short name T736
Test name
Test status
Simulation time 16955342 ps
CPU time 0.66 seconds
Started Mar 24 02:51:13 PM PDT 24
Finished Mar 24 02:51:14 PM PDT 24
Peak memory 203836 kb
Host smart-8c741094-4bcd-4cfb-8379-24a373d0e076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249196174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.249196174
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1239040863
Short name T492
Test name
Test status
Simulation time 5183248611 ps
CPU time 179.84 seconds
Started Mar 24 02:51:19 PM PDT 24
Finished Mar 24 02:54:19 PM PDT 24
Peak memory 308192 kb
Host smart-31a43994-be41-4eda-8066-e3d7bb7df069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239040863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1239040863
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1212089214
Short name T1063
Test name
Test status
Simulation time 1384768866 ps
CPU time 50.88 seconds
Started Mar 24 02:51:14 PM PDT 24
Finished Mar 24 02:52:05 PM PDT 24
Peak memory 300488 kb
Host smart-dc76ebdd-781a-47f9-a363-99465570b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212089214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1212089214
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1066271458
Short name T412
Test name
Test status
Simulation time 3545601655 ps
CPU time 4.29 seconds
Started Mar 24 02:51:25 PM PDT 24
Finished Mar 24 02:51:29 PM PDT 24
Peak memory 212368 kb
Host smart-e0ba5976-7a59-4596-b353-30fd7b893cfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066271458 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1066271458
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1260307524
Short name T61
Test name
Test status
Simulation time 10123758136 ps
CPU time 72.94 seconds
Started Mar 24 02:51:19 PM PDT 24
Finished Mar 24 02:52:32 PM PDT 24
Peak memory 580164 kb
Host smart-05482a9e-69d1-4882-b55a-3536ee0f77a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260307524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1260307524
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2583476572
Short name T755
Test name
Test status
Simulation time 374633995 ps
CPU time 2.27 seconds
Started Mar 24 02:51:21 PM PDT 24
Finished Mar 24 02:51:23 PM PDT 24
Peak memory 204196 kb
Host smart-ce0e9489-5f65-4039-8211-5440fe0a37b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583476572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2583476572
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2190108272
Short name T942
Test name
Test status
Simulation time 1064350192 ps
CPU time 5.88 seconds
Started Mar 24 02:51:20 PM PDT 24
Finished Mar 24 02:51:26 PM PDT 24
Peak memory 211848 kb
Host smart-4e54611b-194d-40e2-a9c1-8988996d1d85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190108272 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2190108272
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.718519649
Short name T463
Test name
Test status
Simulation time 3521507586 ps
CPU time 14.5 seconds
Started Mar 24 02:51:25 PM PDT 24
Finished Mar 24 02:51:40 PM PDT 24
Peak memory 204140 kb
Host smart-b354f70c-4725-4845-b4fb-d96260b314bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718519649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.718519649
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1156421762
Short name T1056
Test name
Test status
Simulation time 5833296474 ps
CPU time 22.92 seconds
Started Mar 24 02:51:19 PM PDT 24
Finished Mar 24 02:51:42 PM PDT 24
Peak memory 224668 kb
Host smart-5b510d4c-87eb-4203-a6e7-fcf5225a84ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156421762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1156421762
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.4040745264
Short name T1030
Test name
Test status
Simulation time 28541637972 ps
CPU time 234.58 seconds
Started Mar 24 02:51:19 PM PDT 24
Finished Mar 24 02:55:14 PM PDT 24
Peak memory 1926448 kb
Host smart-f00b67aa-0dcf-4070-a7cb-bb386053a35b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040745264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.4040745264
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.1765108162
Short name T958
Test name
Test status
Simulation time 1531875517 ps
CPU time 7.46 seconds
Started Mar 24 02:51:21 PM PDT 24
Finished Mar 24 02:51:28 PM PDT 24
Peak memory 210216 kb
Host smart-4088866f-329d-4ab4-ba90-b99612ec71c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765108162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.1765108162
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.2956796903
Short name T909
Test name
Test status
Simulation time 6842522253 ps
CPU time 6.72 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:51:31 PM PDT 24
Peak memory 204248 kb
Host smart-fe82bf4d-bcc3-4cd0-9c51-7797cbe28518
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956796903 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.i2c_target_unexp_stop.2956796903
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1017424381
Short name T442
Test name
Test status
Simulation time 39125648 ps
CPU time 0.59 seconds
Started Mar 24 02:51:29 PM PDT 24
Finished Mar 24 02:51:30 PM PDT 24
Peak memory 203940 kb
Host smart-09cb8829-22e7-496f-8f04-06c7bd481f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017424381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1017424381
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2065015840
Short name T640
Test name
Test status
Simulation time 138016131 ps
CPU time 1.05 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:51:25 PM PDT 24
Peak memory 212392 kb
Host smart-04f9ab44-6d4b-43dd-a74f-ad11123e2647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065015840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2065015840
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.410313516
Short name T986
Test name
Test status
Simulation time 1194582280 ps
CPU time 6.66 seconds
Started Mar 24 02:51:27 PM PDT 24
Finished Mar 24 02:51:34 PM PDT 24
Peak memory 255816 kb
Host smart-d22ff1e7-9708-472f-8995-5ece93eee391
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410313516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.410313516
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3896897260
Short name T57
Test name
Test status
Simulation time 9236940113 ps
CPU time 46.28 seconds
Started Mar 24 02:51:23 PM PDT 24
Finished Mar 24 02:52:09 PM PDT 24
Peak memory 495180 kb
Host smart-721e18d5-3dd1-409d-8ff4-e0d70543cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896897260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3896897260
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.4073256083
Short name T731
Test name
Test status
Simulation time 6630269762 ps
CPU time 83.39 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:52:48 PM PDT 24
Peak memory 502380 kb
Host smart-1c49768d-9a93-4023-8313-cb71d519c99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073256083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.4073256083
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2595172455
Short name T597
Test name
Test status
Simulation time 182480943 ps
CPU time 1 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:51:25 PM PDT 24
Peak memory 203964 kb
Host smart-26e21b69-e503-4416-a518-e865a2010c18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595172455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2595172455
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2915463278
Short name T603
Test name
Test status
Simulation time 704119581 ps
CPU time 6.75 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:51:31 PM PDT 24
Peak memory 204192 kb
Host smart-b9ab93a4-a578-4e13-929a-af83a9e58b0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915463278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2915463278
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3355811942
Short name T161
Test name
Test status
Simulation time 22139813894 ps
CPU time 95.3 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:52:59 PM PDT 24
Peak memory 1087544 kb
Host smart-149b54fc-e96e-4f7f-b3e4-4a1d2cfc7bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355811942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3355811942
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_override.3772459541
Short name T173
Test name
Test status
Simulation time 23707081 ps
CPU time 0.66 seconds
Started Mar 24 02:51:26 PM PDT 24
Finished Mar 24 02:51:27 PM PDT 24
Peak memory 203884 kb
Host smart-a7779f95-f5af-4c83-9f09-20c13974fd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772459541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3772459541
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.564034746
Short name T371
Test name
Test status
Simulation time 3271814646 ps
CPU time 87.68 seconds
Started Mar 24 02:51:26 PM PDT 24
Finished Mar 24 02:52:54 PM PDT 24
Peak memory 295864 kb
Host smart-8eb71941-f19a-4ba6-9f0a-2f3e5ba60034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564034746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.564034746
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.4157082931
Short name T464
Test name
Test status
Simulation time 3528926356 ps
CPU time 77.04 seconds
Started Mar 24 02:51:24 PM PDT 24
Finished Mar 24 02:52:41 PM PDT 24
Peak memory 355400 kb
Host smart-5251bf23-6cf2-4b6e-9460-6377528171a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157082931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.4157082931
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1174370143
Short name T1084
Test name
Test status
Simulation time 1297318101 ps
CPU time 5.88 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:51:37 PM PDT 24
Peak memory 212360 kb
Host smart-3f583750-063d-4484-a0da-f59ff4096e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174370143 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1174370143
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.769317180
Short name T246
Test name
Test status
Simulation time 10271152991 ps
CPU time 31.47 seconds
Started Mar 24 02:51:29 PM PDT 24
Finished Mar 24 02:52:00 PM PDT 24
Peak memory 382504 kb
Host smart-75d32802-d7fa-4345-9e2a-5bcd9614a26f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769317180 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.769317180
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1052248411
Short name T616
Test name
Test status
Simulation time 10034401776 ps
CPU time 121.22 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:53:33 PM PDT 24
Peak memory 704288 kb
Host smart-1b9997ed-1450-41bc-9a04-7e4ebeddd0bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052248411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1052248411
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.4141347807
Short name T317
Test name
Test status
Simulation time 469158239 ps
CPU time 2.69 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:51:34 PM PDT 24
Peak memory 204196 kb
Host smart-a5d15be5-46de-4f98-a308-ec4d6e2d7b12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141347807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.4141347807
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.362675810
Short name T318
Test name
Test status
Simulation time 1467246550 ps
CPU time 7.82 seconds
Started Mar 24 02:51:29 PM PDT 24
Finished Mar 24 02:51:37 PM PDT 24
Peak memory 219952 kb
Host smart-71bc9726-396c-4fe5-81d5-168cc8eaca16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362675810 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.362675810
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2268830477
Short name T400
Test name
Test status
Simulation time 1449053175 ps
CPU time 57.41 seconds
Started Mar 24 02:51:25 PM PDT 24
Finished Mar 24 02:52:23 PM PDT 24
Peak memory 204132 kb
Host smart-bbc117b8-aed1-4aa4-9c03-abf92d0c4314
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268830477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2268830477
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3066919829
Short name T830
Test name
Test status
Simulation time 1045134262 ps
CPU time 20.08 seconds
Started Mar 24 02:51:26 PM PDT 24
Finished Mar 24 02:51:46 PM PDT 24
Peak memory 217944 kb
Host smart-210ce033-3ea6-4bf4-b468-f5cbf9cb1000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066919829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3066919829
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3402697492
Short name T586
Test name
Test status
Simulation time 34040381352 ps
CPU time 2736.78 seconds
Started Mar 24 02:51:29 PM PDT 24
Finished Mar 24 03:37:06 PM PDT 24
Peak memory 7723320 kb
Host smart-122a7dd0-0303-428e-9a2d-447937b536c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402697492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3402697492
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2025620074
Short name T1011
Test name
Test status
Simulation time 1398722898 ps
CPU time 6.98 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:51:38 PM PDT 24
Peak memory 212444 kb
Host smart-e8a7ee89-09c3-4c53-ba85-b68162b68d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025620074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2025620074
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3390407126
Short name T649
Test name
Test status
Simulation time 21980428 ps
CPU time 0.61 seconds
Started Mar 24 02:51:35 PM PDT 24
Finished Mar 24 02:51:36 PM PDT 24
Peak memory 203916 kb
Host smart-1f8863f3-915e-4fe0-ad00-db54ecd77b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390407126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3390407126
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.4280932493
Short name T777
Test name
Test status
Simulation time 62153344 ps
CPU time 1.06 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:51:33 PM PDT 24
Peak memory 212368 kb
Host smart-80ab2ce3-8b09-4643-b855-59b2d2dd131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280932493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.4280932493
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.850855690
Short name T669
Test name
Test status
Simulation time 310089602 ps
CPU time 5.82 seconds
Started Mar 24 02:51:35 PM PDT 24
Finished Mar 24 02:51:41 PM PDT 24
Peak memory 268064 kb
Host smart-4a9b1759-ef44-471c-b8a1-de65e54f9439
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850855690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.850855690
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.465381862
Short name T648
Test name
Test status
Simulation time 1558580451 ps
CPU time 97.08 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:53:09 PM PDT 24
Peak memory 467372 kb
Host smart-7f10d534-629a-4f59-bec9-9171baf3f4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465381862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.465381862
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.52777805
Short name T1031
Test name
Test status
Simulation time 149276159 ps
CPU time 1.18 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:51:32 PM PDT 24
Peak memory 204208 kb
Host smart-3b5e9b57-3459-4308-819f-9255d9e7bdd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52777805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt
.52777805
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2002734755
Short name T341
Test name
Test status
Simulation time 122440200 ps
CPU time 2.97 seconds
Started Mar 24 02:51:34 PM PDT 24
Finished Mar 24 02:51:37 PM PDT 24
Peak memory 204156 kb
Host smart-513a959a-1057-4ca9-99f6-2a3e8cb73cbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002734755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2002734755
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.835365915
Short name T855
Test name
Test status
Simulation time 2431875130 ps
CPU time 54.38 seconds
Started Mar 24 02:51:29 PM PDT 24
Finished Mar 24 02:52:23 PM PDT 24
Peak memory 591116 kb
Host smart-592a8940-074c-4226-9a8e-40def228a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835365915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.835365915
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_override.3868185804
Short name T516
Test name
Test status
Simulation time 40673205 ps
CPU time 0.65 seconds
Started Mar 24 02:51:30 PM PDT 24
Finished Mar 24 02:51:31 PM PDT 24
Peak memory 203832 kb
Host smart-824286ae-d05b-4243-b80c-964f7e3a6726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868185804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3868185804
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3742934297
Short name T832
Test name
Test status
Simulation time 6264210122 ps
CPU time 842.83 seconds
Started Mar 24 02:51:30 PM PDT 24
Finished Mar 24 03:05:33 PM PDT 24
Peak memory 873644 kb
Host smart-27daa2c2-7d72-4201-abcc-0ee29b5a4832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742934297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3742934297
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3409783962
Short name T248
Test name
Test status
Simulation time 1272435483 ps
CPU time 62.77 seconds
Started Mar 24 02:51:30 PM PDT 24
Finished Mar 24 02:52:33 PM PDT 24
Peak memory 354016 kb
Host smart-e200bdc5-5a62-4004-a603-bbaaf867ca45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409783962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3409783962
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1415025301
Short name T1072
Test name
Test status
Simulation time 1204528675 ps
CPU time 4.1 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:51:36 PM PDT 24
Peak memory 212372 kb
Host smart-cecafe18-a666-4394-8212-61da67939d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415025301 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1415025301
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3717686384
Short name T996
Test name
Test status
Simulation time 10065541729 ps
CPU time 34.88 seconds
Started Mar 24 02:51:32 PM PDT 24
Finished Mar 24 02:52:08 PM PDT 24
Peak memory 400196 kb
Host smart-9dad9110-1dd2-49a5-9734-4b6b2b350a07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717686384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3717686384
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1417048955
Short name T555
Test name
Test status
Simulation time 10490599856 ps
CPU time 3.95 seconds
Started Mar 24 02:51:35 PM PDT 24
Finished Mar 24 02:51:39 PM PDT 24
Peak memory 238832 kb
Host smart-f5f711a9-11fb-4a9d-baa6-424c14116638
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417048955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1417048955
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.482874420
Short name T433
Test name
Test status
Simulation time 372162998 ps
CPU time 2.45 seconds
Started Mar 24 02:51:34 PM PDT 24
Finished Mar 24 02:51:37 PM PDT 24
Peak memory 204164 kb
Host smart-53af00f5-47e1-44fd-9f7a-db691197da17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482874420 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.482874420
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2141858327
Short name T414
Test name
Test status
Simulation time 4663654380 ps
CPU time 4.09 seconds
Started Mar 24 02:51:32 PM PDT 24
Finished Mar 24 02:51:36 PM PDT 24
Peak memory 204256 kb
Host smart-8b9efdeb-0014-4429-b0d1-b5c9c67cf142
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141858327 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2141858327
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2850597011
Short name T842
Test name
Test status
Simulation time 632758955 ps
CPU time 9.22 seconds
Started Mar 24 02:51:29 PM PDT 24
Finished Mar 24 02:51:38 PM PDT 24
Peak memory 204160 kb
Host smart-7710da4e-2489-49cf-af40-2c3bb31c8284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850597011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2850597011
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.4284260867
Short name T351
Test name
Test status
Simulation time 1653870591 ps
CPU time 24.86 seconds
Started Mar 24 02:51:35 PM PDT 24
Finished Mar 24 02:52:00 PM PDT 24
Peak memory 234008 kb
Host smart-34daf59d-bfae-40f2-a8de-225fb147de20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284260867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.4284260867
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1851140462
Short name T957
Test name
Test status
Simulation time 18196238082 ps
CPU time 51.22 seconds
Started Mar 24 02:51:34 PM PDT 24
Finished Mar 24 02:52:25 PM PDT 24
Peak memory 326140 kb
Host smart-931ccf22-0615-4159-8853-ced8f863fc99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851140462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1851140462
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3957749812
Short name T435
Test name
Test status
Simulation time 5044189133 ps
CPU time 7.1 seconds
Started Mar 24 02:51:33 PM PDT 24
Finished Mar 24 02:51:40 PM PDT 24
Peak memory 211860 kb
Host smart-086e0c64-0512-40c3-93b8-103b885cf81b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957749812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3957749812
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.267848517
Short name T699
Test name
Test status
Simulation time 18054406 ps
CPU time 0.62 seconds
Started Mar 24 02:48:46 PM PDT 24
Finished Mar 24 02:48:46 PM PDT 24
Peak memory 203896 kb
Host smart-460a3382-07e0-4056-bc38-901fbb983302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267848517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.267848517
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1188133147
Short name T1066
Test name
Test status
Simulation time 163655299 ps
CPU time 1.18 seconds
Started Mar 24 02:48:32 PM PDT 24
Finished Mar 24 02:48:34 PM PDT 24
Peak memory 220604 kb
Host smart-f388fa87-a7a1-411a-bfad-d09c0788fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188133147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1188133147
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.4023838408
Short name T330
Test name
Test status
Simulation time 393777089 ps
CPU time 10.17 seconds
Started Mar 24 02:48:34 PM PDT 24
Finished Mar 24 02:48:45 PM PDT 24
Peak memory 233124 kb
Host smart-6d66eca5-96f1-4156-a1a0-99439a61610e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023838408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.4023838408
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1204966013
Short name T910
Test name
Test status
Simulation time 6119974897 ps
CPU time 58.59 seconds
Started Mar 24 02:48:34 PM PDT 24
Finished Mar 24 02:49:34 PM PDT 24
Peak memory 662948 kb
Host smart-eaf231bd-0b27-41eb-bb46-c2a7546dbfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204966013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1204966013
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.952170516
Short name T917
Test name
Test status
Simulation time 1925421597 ps
CPU time 57.73 seconds
Started Mar 24 02:48:34 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 655440 kb
Host smart-500d8b4c-314f-4a0b-9486-c73fc2fbc547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952170516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.952170516
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1548151103
Short name T529
Test name
Test status
Simulation time 302592443 ps
CPU time 0.79 seconds
Started Mar 24 02:48:36 PM PDT 24
Finished Mar 24 02:48:37 PM PDT 24
Peak memory 203900 kb
Host smart-a9c85030-6417-408c-93b2-74f5250aa562
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548151103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1548151103
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.4089890864
Short name T937
Test name
Test status
Simulation time 1255714632 ps
CPU time 10.62 seconds
Started Mar 24 02:48:34 PM PDT 24
Finished Mar 24 02:48:46 PM PDT 24
Peak memory 239780 kb
Host smart-93a96733-194c-49e8-a6bc-cac6b91588e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089890864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
4089890864
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2318097658
Short name T368
Test name
Test status
Simulation time 2386900918 ps
CPU time 142.14 seconds
Started Mar 24 02:48:33 PM PDT 24
Finished Mar 24 02:50:55 PM PDT 24
Peak memory 680708 kb
Host smart-a0a834bb-2f65-40dc-a207-f79ac86d6c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318097658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2318097658
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_override.301142765
Short name T915
Test name
Test status
Simulation time 51619721 ps
CPU time 0.62 seconds
Started Mar 24 02:48:36 PM PDT 24
Finished Mar 24 02:48:37 PM PDT 24
Peak memory 203864 kb
Host smart-f8d2cedb-9286-41c5-8450-947f8e6579ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301142765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.301142765
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.354981811
Short name T428
Test name
Test status
Simulation time 4441575715 ps
CPU time 62.53 seconds
Started Mar 24 02:48:33 PM PDT 24
Finished Mar 24 02:49:35 PM PDT 24
Peak memory 247732 kb
Host smart-9cd1645d-b6a6-4575-8571-415ff92e6a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354981811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.354981811
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2125678885
Short name T100
Test name
Test status
Simulation time 145332073 ps
CPU time 0.8 seconds
Started Mar 24 02:48:41 PM PDT 24
Finished Mar 24 02:48:42 PM PDT 24
Peak memory 221584 kb
Host smart-6c7d4fd5-7633-4730-b3e3-2e7253082498
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125678885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2125678885
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3664681662
Short name T524
Test name
Test status
Simulation time 1929366049 ps
CPU time 4.88 seconds
Started Mar 24 02:48:38 PM PDT 24
Finished Mar 24 02:48:43 PM PDT 24
Peak memory 204140 kb
Host smart-b3e38689-1587-442f-a4e8-374d9d1a8687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664681662 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3664681662
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.949021010
Short name T590
Test name
Test status
Simulation time 10097696054 ps
CPU time 80.82 seconds
Started Mar 24 02:48:40 PM PDT 24
Finished Mar 24 02:50:01 PM PDT 24
Peak memory 603112 kb
Host smart-9f4be581-307c-42ff-b7e2-2a84faf94147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949021010 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.949021010
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2764271659
Short name T661
Test name
Test status
Simulation time 10084872501 ps
CPU time 69.32 seconds
Started Mar 24 02:48:39 PM PDT 24
Finished Mar 24 02:49:48 PM PDT 24
Peak memory 631628 kb
Host smart-972baddc-e048-43df-8bf3-4a44b966b97e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764271659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2764271659
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3237981916
Short name T496
Test name
Test status
Simulation time 1738203689 ps
CPU time 2.72 seconds
Started Mar 24 02:48:41 PM PDT 24
Finished Mar 24 02:48:44 PM PDT 24
Peak memory 204168 kb
Host smart-913dd174-ee14-499b-883c-6d45102d5290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237981916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3237981916
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2769952944
Short name T896
Test name
Test status
Simulation time 15014475121 ps
CPU time 6.07 seconds
Started Mar 24 02:48:41 PM PDT 24
Finished Mar 24 02:48:48 PM PDT 24
Peak memory 215932 kb
Host smart-48ab7e6e-543f-4ad1-8f13-5b426e49f9ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769952944 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2769952944
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2881408815
Short name T624
Test name
Test status
Simulation time 4353271069 ps
CPU time 13.94 seconds
Started Mar 24 02:48:40 PM PDT 24
Finished Mar 24 02:48:54 PM PDT 24
Peak memory 204168 kb
Host smart-8e87bd4a-161d-4a36-aadf-dc6bd1150a89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881408815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2881408815
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3177813498
Short name T416
Test name
Test status
Simulation time 1148179154 ps
CPU time 4.75 seconds
Started Mar 24 02:48:38 PM PDT 24
Finished Mar 24 02:48:43 PM PDT 24
Peak memory 204164 kb
Host smart-fb4b9558-73da-4287-aecc-f5a4d8028abf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177813498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3177813498
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1714471711
Short name T191
Test name
Test status
Simulation time 3153195962 ps
CPU time 13.9 seconds
Started Mar 24 02:48:39 PM PDT 24
Finished Mar 24 02:48:53 PM PDT 24
Peak memory 311256 kb
Host smart-258c7d59-5940-47ad-9162-f35ec213ee73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714471711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1714471711
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.150746088
Short name T751
Test name
Test status
Simulation time 1059346816 ps
CPU time 6.12 seconds
Started Mar 24 02:48:38 PM PDT 24
Finished Mar 24 02:48:45 PM PDT 24
Peak memory 220304 kb
Host smart-772ae407-9de2-44e6-ba31-6afc2915e335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150746088 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.150746088
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2924359029
Short name T913
Test name
Test status
Simulation time 19402862 ps
CPU time 0.62 seconds
Started Mar 24 02:51:38 PM PDT 24
Finished Mar 24 02:51:39 PM PDT 24
Peak memory 203904 kb
Host smart-9e9b5ee6-1e0b-4bcf-bc47-0ae8508c4045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924359029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2924359029
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3591598368
Short name T270
Test name
Test status
Simulation time 82554058 ps
CPU time 1.25 seconds
Started Mar 24 02:51:43 PM PDT 24
Finished Mar 24 02:51:44 PM PDT 24
Peak memory 212372 kb
Host smart-5fe728d1-9851-4c54-a4c4-3c43dc12e5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591598368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3591598368
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3240704204
Short name T766
Test name
Test status
Simulation time 2944305748 ps
CPU time 19.36 seconds
Started Mar 24 02:51:34 PM PDT 24
Finished Mar 24 02:51:53 PM PDT 24
Peak memory 283908 kb
Host smart-ec3050d2-83e2-45b4-85cc-e9b9f025b61a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240704204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3240704204
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.959078192
Short name T975
Test name
Test status
Simulation time 17306285379 ps
CPU time 176.45 seconds
Started Mar 24 02:51:34 PM PDT 24
Finished Mar 24 02:54:30 PM PDT 24
Peak memory 735560 kb
Host smart-973d7767-a51d-4efb-829c-0a122edd0645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959078192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.959078192
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.358480777
Short name T457
Test name
Test status
Simulation time 2271669986 ps
CPU time 159.1 seconds
Started Mar 24 02:51:33 PM PDT 24
Finished Mar 24 02:54:13 PM PDT 24
Peak memory 670708 kb
Host smart-19aa1517-cd41-491c-b1eb-4ebd4f5e5168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358480777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.358480777
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2564758977
Short name T918
Test name
Test status
Simulation time 705104185 ps
CPU time 4.63 seconds
Started Mar 24 02:51:33 PM PDT 24
Finished Mar 24 02:51:38 PM PDT 24
Peak memory 237156 kb
Host smart-4e7ac2fd-99ee-4d31-84dd-0825b086c77e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564758977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2564758977
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3143280240
Short name T600
Test name
Test status
Simulation time 17523901930 ps
CPU time 111.43 seconds
Started Mar 24 02:51:34 PM PDT 24
Finished Mar 24 02:53:25 PM PDT 24
Peak memory 1087128 kb
Host smart-68ac51a1-7386-41aa-9899-7e475ba05fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143280240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3143280240
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_override.2374602995
Short name T402
Test name
Test status
Simulation time 15937775 ps
CPU time 0.64 seconds
Started Mar 24 02:51:31 PM PDT 24
Finished Mar 24 02:51:32 PM PDT 24
Peak memory 203764 kb
Host smart-c1cc6711-9a57-417e-ad7c-4468fc12a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374602995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2374602995
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3857351905
Short name T295
Test name
Test status
Simulation time 7329093849 ps
CPU time 31.29 seconds
Started Mar 24 02:51:35 PM PDT 24
Finished Mar 24 02:52:06 PM PDT 24
Peak memory 220604 kb
Host smart-05f766f5-b327-41e0-bb17-10a0eed0f144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857351905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3857351905
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1178234351
Short name T719
Test name
Test status
Simulation time 3503710429 ps
CPU time 90.77 seconds
Started Mar 24 02:51:34 PM PDT 24
Finished Mar 24 02:53:05 PM PDT 24
Peak memory 357276 kb
Host smart-55ee03bc-3313-438d-a87c-c29e50629854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178234351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1178234351
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3082942590
Short name T931
Test name
Test status
Simulation time 42571681492 ps
CPU time 3310.43 seconds
Started Mar 24 02:51:42 PM PDT 24
Finished Mar 24 03:46:54 PM PDT 24
Peak memory 2001196 kb
Host smart-bf7620bf-271b-4d84-9b3e-b49504c04d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082942590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3082942590
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3152368277
Short name T916
Test name
Test status
Simulation time 2250659529 ps
CPU time 5.32 seconds
Started Mar 24 02:51:38 PM PDT 24
Finished Mar 24 02:51:43 PM PDT 24
Peak memory 205492 kb
Host smart-03da93a5-be8b-4dfd-bdfd-13e52359be62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152368277 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3152368277
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.280337844
Short name T66
Test name
Test status
Simulation time 10045639672 ps
CPU time 65.69 seconds
Started Mar 24 02:51:36 PM PDT 24
Finished Mar 24 02:52:42 PM PDT 24
Peak memory 593104 kb
Host smart-6ac16cc2-e14d-42b1-a3f4-be65f2a49a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280337844 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.280337844
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.786542922
Short name T510
Test name
Test status
Simulation time 11020993289 ps
CPU time 8.41 seconds
Started Mar 24 02:51:39 PM PDT 24
Finished Mar 24 02:51:48 PM PDT 24
Peak memory 271096 kb
Host smart-80910885-5ef8-4341-ac07-22339446a467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786542922 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.786542922
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2546098153
Short name T801
Test name
Test status
Simulation time 1708808599 ps
CPU time 2.47 seconds
Started Mar 24 02:51:39 PM PDT 24
Finished Mar 24 02:51:41 PM PDT 24
Peak memory 204132 kb
Host smart-7515616a-6700-4aaf-af9f-4ffc034398e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546098153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2546098153
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2827818564
Short name T280
Test name
Test status
Simulation time 1835237323 ps
CPU time 4.85 seconds
Started Mar 24 02:51:37 PM PDT 24
Finished Mar 24 02:51:42 PM PDT 24
Peak memory 204176 kb
Host smart-6fa46b9a-1fb9-42a0-91fb-5d1a6ec3e329
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827818564 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2827818564
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3142011024
Short name T245
Test name
Test status
Simulation time 3276249564 ps
CPU time 2.48 seconds
Started Mar 24 02:51:33 PM PDT 24
Finished Mar 24 02:51:36 PM PDT 24
Peak memory 203828 kb
Host smart-c5395043-309f-4ac7-85b5-128a68d4d28b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142011024 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3142011024
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2372081565
Short name T900
Test name
Test status
Simulation time 6513377609 ps
CPU time 31.46 seconds
Started Mar 24 02:51:33 PM PDT 24
Finished Mar 24 02:52:05 PM PDT 24
Peak memory 204252 kb
Host smart-28765277-0495-403d-808d-40e5a180f470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372081565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2372081565
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2949336809
Short name T677
Test name
Test status
Simulation time 2438299791 ps
CPU time 26.23 seconds
Started Mar 24 02:51:42 PM PDT 24
Finished Mar 24 02:52:09 PM PDT 24
Peak memory 220216 kb
Host smart-c4d7c765-d35e-4970-ab11-99f16f144467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949336809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2949336809
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1656704128
Short name T720
Test name
Test status
Simulation time 43091066773 ps
CPU time 39.17 seconds
Started Mar 24 02:51:42 PM PDT 24
Finished Mar 24 02:52:21 PM PDT 24
Peak memory 428708 kb
Host smart-4a5cd715-4879-4ed5-9399-cd0af9ed63cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656704128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1656704128
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3065797755
Short name T701
Test name
Test status
Simulation time 1379156280 ps
CPU time 7.37 seconds
Started Mar 24 02:51:36 PM PDT 24
Finished Mar 24 02:51:44 PM PDT 24
Peak memory 215532 kb
Host smart-222313d3-f807-45b2-809f-490723afcf55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065797755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3065797755
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2121367447
Short name T309
Test name
Test status
Simulation time 17135768 ps
CPU time 0.62 seconds
Started Mar 24 02:51:54 PM PDT 24
Finished Mar 24 02:51:55 PM PDT 24
Peak memory 204168 kb
Host smart-e807b752-3680-437f-a085-2a108d8aea2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121367447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2121367447
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3653357598
Short name T32
Test name
Test status
Simulation time 153916001 ps
CPU time 1.49 seconds
Started Mar 24 02:51:43 PM PDT 24
Finished Mar 24 02:51:45 PM PDT 24
Peak memory 212316 kb
Host smart-1ffc2376-6ae8-4160-8585-38d586eaf5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653357598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3653357598
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.622868184
Short name T702
Test name
Test status
Simulation time 420685374 ps
CPU time 10.38 seconds
Started Mar 24 02:51:45 PM PDT 24
Finished Mar 24 02:51:56 PM PDT 24
Peak memory 242316 kb
Host smart-85fc4790-aa00-46ba-9c76-f9418e856a87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622868184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.622868184
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2120880587
Short name T899
Test name
Test status
Simulation time 10295279147 ps
CPU time 51.67 seconds
Started Mar 24 02:51:43 PM PDT 24
Finished Mar 24 02:52:35 PM PDT 24
Peak memory 590248 kb
Host smart-175140fd-3476-4486-9ecc-a5fc3f84b34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120880587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2120880587
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2673543595
Short name T688
Test name
Test status
Simulation time 22998512278 ps
CPU time 159.9 seconds
Started Mar 24 02:51:40 PM PDT 24
Finished Mar 24 02:54:20 PM PDT 24
Peak memory 720724 kb
Host smart-14149b40-4359-4593-9e86-a1fe9f4c2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673543595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2673543595
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3037621350
Short name T432
Test name
Test status
Simulation time 169962675 ps
CPU time 0.85 seconds
Started Mar 24 02:51:38 PM PDT 24
Finished Mar 24 02:51:39 PM PDT 24
Peak memory 203956 kb
Host smart-8da5e263-2b23-4ed6-abf8-f4ef92697cc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037621350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3037621350
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.3775608760
Short name T488
Test name
Test status
Simulation time 124608160 ps
CPU time 6.93 seconds
Started Mar 24 02:51:45 PM PDT 24
Finished Mar 24 02:51:52 PM PDT 24
Peak memory 224108 kb
Host smart-eac34de8-de9c-407d-a904-e2c88806173c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775608760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.3775608760
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.4293504169
Short name T207
Test name
Test status
Simulation time 3898561517 ps
CPU time 121.21 seconds
Started Mar 24 02:51:40 PM PDT 24
Finished Mar 24 02:53:41 PM PDT 24
Peak memory 1174072 kb
Host smart-ab959634-09e8-4126-ac91-fd5a31bd74d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293504169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4293504169
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_override.3055128406
Short name T815
Test name
Test status
Simulation time 16234341 ps
CPU time 0.65 seconds
Started Mar 24 02:51:37 PM PDT 24
Finished Mar 24 02:51:38 PM PDT 24
Peak memory 203824 kb
Host smart-c872e808-4d7f-4254-948f-72e653abbeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055128406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3055128406
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2440578673
Short name T874
Test name
Test status
Simulation time 2887908270 ps
CPU time 23.66 seconds
Started Mar 24 02:51:48 PM PDT 24
Finished Mar 24 02:52:11 PM PDT 24
Peak memory 204264 kb
Host smart-0ef9bbb4-a9a2-43eb-837a-f6d645af44b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440578673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2440578673
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1221632119
Short name T670
Test name
Test status
Simulation time 1561250726 ps
CPU time 129.8 seconds
Started Mar 24 02:51:38 PM PDT 24
Finished Mar 24 02:53:48 PM PDT 24
Peak memory 280604 kb
Host smart-de91ff73-938e-4b04-9a86-4fcaff1c5eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221632119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1221632119
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.56910727
Short name T816
Test name
Test status
Simulation time 2658505134 ps
CPU time 3.31 seconds
Started Mar 24 02:51:54 PM PDT 24
Finished Mar 24 02:51:57 PM PDT 24
Peak memory 212592 kb
Host smart-eee4e8a2-18a6-4394-97b2-20d8f0a04d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56910727 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_bad_addr.56910727
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1064643651
Short name T643
Test name
Test status
Simulation time 10562674917 ps
CPU time 10.01 seconds
Started Mar 24 02:51:41 PM PDT 24
Finished Mar 24 02:51:51 PM PDT 24
Peak memory 275180 kb
Host smart-41087115-1ecc-424e-8368-4141c58dcc27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064643651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1064643651
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1562641801
Short name T595
Test name
Test status
Simulation time 708065853 ps
CPU time 3.17 seconds
Started Mar 24 02:51:48 PM PDT 24
Finished Mar 24 02:51:51 PM PDT 24
Peak memory 204124 kb
Host smart-5e93f5d5-45d4-4774-a3b2-098fb2de69b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562641801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1562641801
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.452124030
Short name T284
Test name
Test status
Simulation time 4177264962 ps
CPU time 5.61 seconds
Started Mar 24 02:51:45 PM PDT 24
Finished Mar 24 02:51:50 PM PDT 24
Peak memory 209772 kb
Host smart-4a6e9ac5-26d9-484e-a28d-194ecf0cd321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452124030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.452124030
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.412270461
Short name T418
Test name
Test status
Simulation time 8871906524 ps
CPU time 3.38 seconds
Started Mar 24 02:51:44 PM PDT 24
Finished Mar 24 02:51:47 PM PDT 24
Peak memory 204188 kb
Host smart-dcdba19b-7966-4e8c-ad51-a55804b19c7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412270461 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.412270461
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1618048093
Short name T730
Test name
Test status
Simulation time 2943149060 ps
CPU time 27.58 seconds
Started Mar 24 02:51:42 PM PDT 24
Finished Mar 24 02:52:10 PM PDT 24
Peak memory 204196 kb
Host smart-46609eae-31c0-4afc-96d9-4de65dd0c3f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618048093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1618048093
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1404424202
Short name T1098
Test name
Test status
Simulation time 2408558040 ps
CPU time 24.13 seconds
Started Mar 24 02:51:48 PM PDT 24
Finished Mar 24 02:52:12 PM PDT 24
Peak memory 204244 kb
Host smart-7523b51f-1acd-4bbe-821e-69788c5d1bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404424202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1404424202
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.4282048099
Short name T489
Test name
Test status
Simulation time 17280607209 ps
CPU time 323.72 seconds
Started Mar 24 02:51:43 PM PDT 24
Finished Mar 24 02:57:07 PM PDT 24
Peak memory 2211260 kb
Host smart-5946aeb6-b220-4e88-bf92-5d8c3d5743a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282048099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.4282048099
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1542530460
Short name T480
Test name
Test status
Simulation time 2790561109 ps
CPU time 6.7 seconds
Started Mar 24 02:51:44 PM PDT 24
Finished Mar 24 02:51:50 PM PDT 24
Peak memory 209892 kb
Host smart-ec8a1b14-b9a7-4d8e-8a29-2942686336ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542530460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1542530460
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3742415240
Short name T734
Test name
Test status
Simulation time 42079894 ps
CPU time 0.58 seconds
Started Mar 24 02:51:52 PM PDT 24
Finished Mar 24 02:51:53 PM PDT 24
Peak memory 203916 kb
Host smart-b7955681-cd8e-4a8d-89a7-c11bda73c06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742415240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3742415240
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.722428076
Short name T366
Test name
Test status
Simulation time 155796821 ps
CPU time 1.34 seconds
Started Mar 24 02:51:47 PM PDT 24
Finished Mar 24 02:51:49 PM PDT 24
Peak memory 212360 kb
Host smart-d4316851-362b-4cb3-a52c-3d75576b04c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722428076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.722428076
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2121325535
Short name T1060
Test name
Test status
Simulation time 239532768 ps
CPU time 5.11 seconds
Started Mar 24 02:51:48 PM PDT 24
Finished Mar 24 02:51:53 PM PDT 24
Peak memory 253280 kb
Host smart-877c2b52-dbd1-4794-8cc8-88135ccf21f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121325535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2121325535
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.1112235191
Short name T579
Test name
Test status
Simulation time 7629581889 ps
CPU time 112.13 seconds
Started Mar 24 02:51:46 PM PDT 24
Finished Mar 24 02:53:38 PM PDT 24
Peak memory 511336 kb
Host smart-bbd8d028-0a4f-4b4a-988f-504cba60bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112235191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1112235191
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2405916774
Short name T823
Test name
Test status
Simulation time 1291560838 ps
CPU time 31.4 seconds
Started Mar 24 02:51:54 PM PDT 24
Finished Mar 24 02:52:26 PM PDT 24
Peak memory 478304 kb
Host smart-991837a3-51a8-4f4d-8580-e745e2047bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405916774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2405916774
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1103333352
Short name T1045
Test name
Test status
Simulation time 219268131 ps
CPU time 1.03 seconds
Started Mar 24 02:51:46 PM PDT 24
Finished Mar 24 02:51:48 PM PDT 24
Peak memory 203940 kb
Host smart-ca64dbf2-bf2c-4c35-a624-c0ce87417529
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103333352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1103333352
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.971827843
Short name T692
Test name
Test status
Simulation time 101046451 ps
CPU time 5.42 seconds
Started Mar 24 02:51:44 PM PDT 24
Finished Mar 24 02:51:50 PM PDT 24
Peak memory 204224 kb
Host smart-3afed475-1aea-495b-8ca0-d172c5d3b2a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971827843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
971827843
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2714602514
Short name T673
Test name
Test status
Simulation time 5535431879 ps
CPU time 262.82 seconds
Started Mar 24 02:51:47 PM PDT 24
Finished Mar 24 02:56:10 PM PDT 24
Peak memory 1037544 kb
Host smart-c9541a6f-902d-4117-a986-a3414a18df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714602514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2714602514
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_override.714580910
Short name T175
Test name
Test status
Simulation time 20346595 ps
CPU time 0.67 seconds
Started Mar 24 02:51:47 PM PDT 24
Finished Mar 24 02:51:47 PM PDT 24
Peak memory 203860 kb
Host smart-72f43391-fca7-48a2-81cf-d65b70f7d070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714580910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.714580910
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2093538247
Short name T186
Test name
Test status
Simulation time 27287810434 ps
CPU time 389.52 seconds
Started Mar 24 02:51:50 PM PDT 24
Finished Mar 24 02:58:19 PM PDT 24
Peak memory 219556 kb
Host smart-222c2645-eba6-4dbe-a3dd-6963c5404a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093538247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2093538247
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4271815247
Short name T773
Test name
Test status
Simulation time 1694279239 ps
CPU time 58.21 seconds
Started Mar 24 02:51:48 PM PDT 24
Finished Mar 24 02:52:46 PM PDT 24
Peak memory 251632 kb
Host smart-3f33ae45-2af5-4ba4-a828-b7f07965b939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271815247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4271815247
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3991751633
Short name T1032
Test name
Test status
Simulation time 2868907469 ps
CPU time 3.93 seconds
Started Mar 24 02:51:53 PM PDT 24
Finished Mar 24 02:51:57 PM PDT 24
Peak memory 204324 kb
Host smart-9af53f4a-6921-40fd-aca2-f01b9cff62d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991751633 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3991751633
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3110738665
Short name T582
Test name
Test status
Simulation time 11436748425 ps
CPU time 3.76 seconds
Started Mar 24 02:51:52 PM PDT 24
Finished Mar 24 02:51:56 PM PDT 24
Peak memory 223976 kb
Host smart-7d1bb928-8d50-43e7-ba18-08aa31e745e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110738665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3110738665
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1350590794
Short name T67
Test name
Test status
Simulation time 10112140211 ps
CPU time 84.83 seconds
Started Mar 24 02:51:55 PM PDT 24
Finished Mar 24 02:53:20 PM PDT 24
Peak memory 708828 kb
Host smart-a1990a9b-3695-4a97-8fe5-f92bee56baf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350590794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1350590794
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3097915215
Short name T679
Test name
Test status
Simulation time 523932773 ps
CPU time 2.8 seconds
Started Mar 24 02:51:55 PM PDT 24
Finished Mar 24 02:51:58 PM PDT 24
Peak memory 204076 kb
Host smart-e6190ee3-54af-4474-abcf-b544342c841a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097915215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3097915215
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.4185672709
Short name T926
Test name
Test status
Simulation time 1168510428 ps
CPU time 5.97 seconds
Started Mar 24 02:51:45 PM PDT 24
Finished Mar 24 02:51:51 PM PDT 24
Peak memory 204180 kb
Host smart-a6f4ccdb-6af3-405e-87f2-9361ab75d45f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185672709 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.4185672709
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.795693344
Short name T875
Test name
Test status
Simulation time 2206037737 ps
CPU time 13.02 seconds
Started Mar 24 02:51:47 PM PDT 24
Finished Mar 24 02:52:00 PM PDT 24
Peak memory 204200 kb
Host smart-f4386271-7068-4924-8260-00e4d83ed04a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795693344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.795693344
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2594185706
Short name T993
Test name
Test status
Simulation time 2017895731 ps
CPU time 22.08 seconds
Started Mar 24 02:51:49 PM PDT 24
Finished Mar 24 02:52:11 PM PDT 24
Peak memory 204132 kb
Host smart-2cbbe6d8-bb3e-4e71-a298-fb7e2be1d9e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594185706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2594185706
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.959883045
Short name T853
Test name
Test status
Simulation time 39070827171 ps
CPU time 1114.55 seconds
Started Mar 24 02:51:48 PM PDT 24
Finished Mar 24 03:10:23 PM PDT 24
Peak memory 4406876 kb
Host smart-250405d4-2c20-4e29-b4af-73b33b5f9d0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959883045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.959883045
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1523609483
Short name T390
Test name
Test status
Simulation time 2768367042 ps
CPU time 7.15 seconds
Started Mar 24 02:51:54 PM PDT 24
Finished Mar 24 02:52:02 PM PDT 24
Peak memory 211492 kb
Host smart-3836d8b2-e286-4516-a73f-8d92dd536fce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523609483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1523609483
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3748038288
Short name T448
Test name
Test status
Simulation time 19550170 ps
CPU time 0.64 seconds
Started Mar 24 02:51:58 PM PDT 24
Finished Mar 24 02:51:59 PM PDT 24
Peak memory 203960 kb
Host smart-ba93e923-e817-42eb-9fbf-a5d99caf8e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748038288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3748038288
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1610548697
Short name T903
Test name
Test status
Simulation time 66628359 ps
CPU time 1.11 seconds
Started Mar 24 02:51:59 PM PDT 24
Finished Mar 24 02:52:00 PM PDT 24
Peak memory 212376 kb
Host smart-8c0029d5-33be-491a-8642-6977623c2452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610548697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1610548697
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1282478991
Short name T732
Test name
Test status
Simulation time 391022766 ps
CPU time 6.98 seconds
Started Mar 24 02:51:54 PM PDT 24
Finished Mar 24 02:52:02 PM PDT 24
Peak memory 278220 kb
Host smart-740ffaff-ade7-4fbb-8c40-481c0d0c2934
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282478991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1282478991
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.4224165895
Short name T394
Test name
Test status
Simulation time 1577335344 ps
CPU time 110.7 seconds
Started Mar 24 02:51:56 PM PDT 24
Finished Mar 24 02:53:47 PM PDT 24
Peak memory 591928 kb
Host smart-3739ef69-f5d2-4453-b94d-dcb32191c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224165895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.4224165895
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2352400074
Short name T266
Test name
Test status
Simulation time 1940463748 ps
CPU time 57.81 seconds
Started Mar 24 02:51:55 PM PDT 24
Finished Mar 24 02:52:53 PM PDT 24
Peak memory 672412 kb
Host smart-cec24eaa-7a37-444c-ab4e-de66988cc689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352400074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2352400074
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3842382081
Short name T200
Test name
Test status
Simulation time 376630443 ps
CPU time 0.93 seconds
Started Mar 24 02:51:53 PM PDT 24
Finished Mar 24 02:51:54 PM PDT 24
Peak memory 203960 kb
Host smart-e310ad92-7687-4921-8672-a12fc37112c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842382081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3842382081
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.698341479
Short name T469
Test name
Test status
Simulation time 391509256 ps
CPU time 2.7 seconds
Started Mar 24 02:51:52 PM PDT 24
Finished Mar 24 02:51:55 PM PDT 24
Peak memory 204180 kb
Host smart-d7e82249-a040-4d09-8b4b-528fba383618
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698341479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
698341479
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.4061794586
Short name T831
Test name
Test status
Simulation time 2878571777 ps
CPU time 82.44 seconds
Started Mar 24 02:51:54 PM PDT 24
Finished Mar 24 02:53:17 PM PDT 24
Peak memory 889836 kb
Host smart-1cc588b3-eb7d-4782-854b-d290443cc273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061794586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.4061794586
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_override.3401225721
Short name T172
Test name
Test status
Simulation time 49673441 ps
CPU time 0.66 seconds
Started Mar 24 02:51:56 PM PDT 24
Finished Mar 24 02:51:57 PM PDT 24
Peak memory 203740 kb
Host smart-f97cdc6f-a163-4918-983b-d8dc5d680e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401225721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3401225721
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.4291631747
Short name T38
Test name
Test status
Simulation time 47797819470 ps
CPU time 939.58 seconds
Started Mar 24 02:52:00 PM PDT 24
Finished Mar 24 03:07:40 PM PDT 24
Peak memory 862572 kb
Host smart-126013d0-7531-49e1-be9b-72a3568367fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291631747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.4291631747
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.835466452
Short name T723
Test name
Test status
Simulation time 4938448399 ps
CPU time 43.16 seconds
Started Mar 24 02:51:58 PM PDT 24
Finished Mar 24 02:52:41 PM PDT 24
Peak memory 313012 kb
Host smart-83ae3a84-c12e-47a7-8e7e-eec16adf8e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835466452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.835466452
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3874629860
Short name T539
Test name
Test status
Simulation time 1990437262 ps
CPU time 2.68 seconds
Started Mar 24 02:51:59 PM PDT 24
Finished Mar 24 02:52:02 PM PDT 24
Peak memory 204176 kb
Host smart-e3e02d13-7670-4698-97ef-0ab505868fb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874629860 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3874629860
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.614023690
Short name T507
Test name
Test status
Simulation time 10400132679 ps
CPU time 14.69 seconds
Started Mar 24 02:52:00 PM PDT 24
Finished Mar 24 02:52:15 PM PDT 24
Peak memory 302384 kb
Host smart-e265ec2d-fa83-4b5b-9737-90a6b64cd7f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614023690 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.614023690
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2025450169
Short name T829
Test name
Test status
Simulation time 10632454566 ps
CPU time 9.21 seconds
Started Mar 24 02:52:00 PM PDT 24
Finished Mar 24 02:52:10 PM PDT 24
Peak memory 287880 kb
Host smart-1ac93853-896f-4eca-8f8f-da576d5c4309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025450169 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2025450169
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3077960601
Short name T700
Test name
Test status
Simulation time 2675813076 ps
CPU time 1.97 seconds
Started Mar 24 02:52:00 PM PDT 24
Finished Mar 24 02:52:02 PM PDT 24
Peak memory 204204 kb
Host smart-2d9254e3-9d7c-457b-b09f-397612d29e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077960601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3077960601
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3415001716
Short name T962
Test name
Test status
Simulation time 1265327198 ps
CPU time 3.52 seconds
Started Mar 24 02:52:01 PM PDT 24
Finished Mar 24 02:52:05 PM PDT 24
Peak memory 204168 kb
Host smart-7b0327fa-3060-42e9-a83f-f3c1f3d69dd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415001716 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3415001716
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1272996372
Short name T848
Test name
Test status
Simulation time 4615343714 ps
CPU time 15.84 seconds
Started Mar 24 02:51:57 PM PDT 24
Finished Mar 24 02:52:13 PM PDT 24
Peak memory 204172 kb
Host smart-42c86408-c414-476d-a8de-72b0d68307d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272996372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1272996372
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.603639485
Short name T792
Test name
Test status
Simulation time 1149643854 ps
CPU time 19.14 seconds
Started Mar 24 02:52:00 PM PDT 24
Finished Mar 24 02:52:20 PM PDT 24
Peak memory 222924 kb
Host smart-8a193199-cdf9-4631-aeb1-77b11220c7b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603639485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.603639485
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1577445041
Short name T565
Test name
Test status
Simulation time 43208020050 ps
CPU time 2990.12 seconds
Started Mar 24 02:52:02 PM PDT 24
Finished Mar 24 03:41:52 PM PDT 24
Peak memory 4483820 kb
Host smart-f936a0fe-b46a-46db-8930-c2ab492d8fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577445041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1577445041
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3241159347
Short name T608
Test name
Test status
Simulation time 6153412706 ps
CPU time 7.82 seconds
Started Mar 24 02:52:01 PM PDT 24
Finished Mar 24 02:52:08 PM PDT 24
Peak memory 212460 kb
Host smart-66182b60-05fa-4b20-8117-89c1dca606e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241159347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3241159347
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.926672625
Short name T971
Test name
Test status
Simulation time 41134355 ps
CPU time 0.64 seconds
Started Mar 24 02:52:07 PM PDT 24
Finished Mar 24 02:52:08 PM PDT 24
Peak memory 203928 kb
Host smart-c5cd3fff-6825-4b51-ac74-252694961d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926672625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.926672625
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.366439660
Short name T840
Test name
Test status
Simulation time 45515118 ps
CPU time 1.25 seconds
Started Mar 24 02:52:02 PM PDT 24
Finished Mar 24 02:52:04 PM PDT 24
Peak memory 212396 kb
Host smart-cc54a191-d483-4337-942e-eddb258bcd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366439660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.366439660
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.4017292252
Short name T334
Test name
Test status
Simulation time 504384446 ps
CPU time 12.9 seconds
Started Mar 24 02:52:02 PM PDT 24
Finished Mar 24 02:52:15 PM PDT 24
Peak memory 253780 kb
Host smart-2801000f-f8a2-4c9a-aa07-178ad310da4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017292252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.4017292252
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.4268290910
Short name T1021
Test name
Test status
Simulation time 2068588048 ps
CPU time 90.86 seconds
Started Mar 24 02:52:04 PM PDT 24
Finished Mar 24 02:53:35 PM PDT 24
Peak memory 533020 kb
Host smart-4fddc82f-16c6-4d06-a0c6-3e01a4def00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268290910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.4268290910
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2041555342
Short name T646
Test name
Test status
Simulation time 3858003528 ps
CPU time 143.16 seconds
Started Mar 24 02:52:01 PM PDT 24
Finished Mar 24 02:54:24 PM PDT 24
Peak memory 675836 kb
Host smart-a7fb029d-106c-477e-bdcf-95c24855e9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041555342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2041555342
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.880818224
Short name T201
Test name
Test status
Simulation time 185075741 ps
CPU time 0.91 seconds
Started Mar 24 02:52:00 PM PDT 24
Finished Mar 24 02:52:01 PM PDT 24
Peak memory 203900 kb
Host smart-ef59fa9f-ab8c-48ce-8940-c5e6e21ef454
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880818224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.880818224
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2499658993
Short name T497
Test name
Test status
Simulation time 259604006 ps
CPU time 3.42 seconds
Started Mar 24 02:52:02 PM PDT 24
Finished Mar 24 02:52:05 PM PDT 24
Peak memory 225340 kb
Host smart-cff87e43-76ce-4425-85a1-8101c684d119
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499658993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2499658993
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.771934951
Short name T995
Test name
Test status
Simulation time 4288926566 ps
CPU time 334.31 seconds
Started Mar 24 02:52:03 PM PDT 24
Finished Mar 24 02:57:38 PM PDT 24
Peak memory 1228592 kb
Host smart-a0229b4e-c97c-4acd-aca6-8a55db4284bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771934951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.771934951
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_override.1358985822
Short name T459
Test name
Test status
Simulation time 17505940 ps
CPU time 0.67 seconds
Started Mar 24 02:52:03 PM PDT 24
Finished Mar 24 02:52:04 PM PDT 24
Peak memory 203864 kb
Host smart-9c561142-e0f5-4307-8c56-fe6c851e4a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358985822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1358985822
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.401137010
Short name T826
Test name
Test status
Simulation time 54312068550 ps
CPU time 849.21 seconds
Started Mar 24 02:52:03 PM PDT 24
Finished Mar 24 03:06:13 PM PDT 24
Peak memory 809020 kb
Host smart-ca3cc799-6a97-46c3-b7b2-6ff4c03703fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401137010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.401137010
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3591559241
Short name T375
Test name
Test status
Simulation time 957170017 ps
CPU time 54.09 seconds
Started Mar 24 02:52:02 PM PDT 24
Finished Mar 24 02:52:56 PM PDT 24
Peak memory 230712 kb
Host smart-f6a8d87e-f742-488f-a4a7-0fa96612e3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591559241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3591559241
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1045586286
Short name T771
Test name
Test status
Simulation time 1327041383 ps
CPU time 3.49 seconds
Started Mar 24 02:52:08 PM PDT 24
Finished Mar 24 02:52:11 PM PDT 24
Peak memory 204132 kb
Host smart-33be321c-5120-4141-b1ff-d5f68c8a626b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045586286 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1045586286
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.735634099
Short name T963
Test name
Test status
Simulation time 10026626022 ps
CPU time 94.42 seconds
Started Mar 24 02:52:07 PM PDT 24
Finished Mar 24 02:53:42 PM PDT 24
Peak memory 625056 kb
Host smart-d853aee2-59c1-43f2-b49c-16f94425aefa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735634099 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.735634099
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1835571124
Short name T967
Test name
Test status
Simulation time 10418951575 ps
CPU time 16.45 seconds
Started Mar 24 02:52:06 PM PDT 24
Finished Mar 24 02:52:23 PM PDT 24
Peak memory 319272 kb
Host smart-477eb963-eb91-4546-9349-99aa9323d10d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835571124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1835571124
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.272489271
Short name T985
Test name
Test status
Simulation time 918685610 ps
CPU time 2.58 seconds
Started Mar 24 02:52:10 PM PDT 24
Finished Mar 24 02:52:13 PM PDT 24
Peak memory 204212 kb
Host smart-05b570db-1c68-49c2-84ac-dc7a4f1842eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272489271 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 34.i2c_target_hrst.272489271
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1227834361
Short name T1079
Test name
Test status
Simulation time 3796979929 ps
CPU time 4.6 seconds
Started Mar 24 02:52:04 PM PDT 24
Finished Mar 24 02:52:09 PM PDT 24
Peak memory 204228 kb
Host smart-77e57862-f995-4eb4-87a2-c7b285d3a621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227834361 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1227834361
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3204958626
Short name T240
Test name
Test status
Simulation time 2318152404 ps
CPU time 14.31 seconds
Started Mar 24 02:52:00 PM PDT 24
Finished Mar 24 02:52:15 PM PDT 24
Peak memory 204180 kb
Host smart-a357c8f2-c8cb-4438-9b69-87d8721bc55f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204958626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3204958626
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.553618464
Short name T1047
Test name
Test status
Simulation time 954597907 ps
CPU time 3.89 seconds
Started Mar 24 02:52:01 PM PDT 24
Finished Mar 24 02:52:05 PM PDT 24
Peak memory 204176 kb
Host smart-7fdba116-78dd-4d29-97e8-d067c2d9d3aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553618464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.553618464
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.834191237
Short name T264
Test name
Test status
Simulation time 17340978088 ps
CPU time 36.76 seconds
Started Mar 24 02:51:59 PM PDT 24
Finished Mar 24 02:52:36 PM PDT 24
Peak memory 204212 kb
Host smart-6bd1d4ec-9e14-4b6e-9f84-921fa18ed5d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834191237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.834191237
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.674555816
Short name T1062
Test name
Test status
Simulation time 9989662608 ps
CPU time 101.07 seconds
Started Mar 24 02:51:59 PM PDT 24
Finished Mar 24 02:53:40 PM PDT 24
Peak memory 1271012 kb
Host smart-16a51c09-b8c9-4746-b8e9-8c3934353d50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674555816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.674555816
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1970511156
Short name T364
Test name
Test status
Simulation time 1181631786 ps
CPU time 6.88 seconds
Started Mar 24 02:52:02 PM PDT 24
Finished Mar 24 02:52:09 PM PDT 24
Peak memory 218944 kb
Host smart-d95e195f-5abc-4e63-ad95-be5f955166e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970511156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1970511156
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3843865644
Short name T521
Test name
Test status
Simulation time 37047453 ps
CPU time 0.63 seconds
Started Mar 24 02:52:13 PM PDT 24
Finished Mar 24 02:52:14 PM PDT 24
Peak memory 203948 kb
Host smart-031a78fa-9027-405a-8888-56d6f551a485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843865644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3843865644
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1282314583
Short name T627
Test name
Test status
Simulation time 121432713 ps
CPU time 1.74 seconds
Started Mar 24 02:52:09 PM PDT 24
Finished Mar 24 02:52:11 PM PDT 24
Peak memory 212456 kb
Host smart-5fbd368f-da5e-4ddf-bf30-2d3e261e3644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282314583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1282314583
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1604531807
Short name T667
Test name
Test status
Simulation time 1017712720 ps
CPU time 6.44 seconds
Started Mar 24 02:52:06 PM PDT 24
Finished Mar 24 02:52:12 PM PDT 24
Peak memory 262360 kb
Host smart-f7ad9b49-8ed6-4834-a6cc-4239e40e27cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604531807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1604531807
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.421530124
Short name T544
Test name
Test status
Simulation time 8663023743 ps
CPU time 156.87 seconds
Started Mar 24 02:52:08 PM PDT 24
Finished Mar 24 02:54:45 PM PDT 24
Peak memory 719936 kb
Host smart-1918ce88-45c8-462c-a4c5-5eca31460b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421530124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.421530124
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2427742262
Short name T865
Test name
Test status
Simulation time 8038440274 ps
CPU time 72.55 seconds
Started Mar 24 02:52:07 PM PDT 24
Finished Mar 24 02:53:20 PM PDT 24
Peak memory 706612 kb
Host smart-079e1a0a-4ebd-4fd4-8b23-5364ca2dad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427742262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2427742262
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.111840491
Short name T34
Test name
Test status
Simulation time 100432141 ps
CPU time 0.99 seconds
Started Mar 24 02:52:08 PM PDT 24
Finished Mar 24 02:52:09 PM PDT 24
Peak memory 203920 kb
Host smart-ea811e33-a27d-4fec-bec7-31f0011f1eb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111840491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.111840491
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2592656125
Short name T847
Test name
Test status
Simulation time 435120570 ps
CPU time 3.47 seconds
Started Mar 24 02:52:10 PM PDT 24
Finished Mar 24 02:52:14 PM PDT 24
Peak memory 221960 kb
Host smart-a217140a-9f19-4f48-a06d-55ff15498834
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592656125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2592656125
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2031980929
Short name T468
Test name
Test status
Simulation time 49734183895 ps
CPU time 98.16 seconds
Started Mar 24 02:52:08 PM PDT 24
Finished Mar 24 02:53:47 PM PDT 24
Peak memory 1015408 kb
Host smart-b04e8070-ead5-4115-973d-3f58d6135121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031980929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2031980929
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_override.3644690513
Short name T243
Test name
Test status
Simulation time 32144189 ps
CPU time 0.63 seconds
Started Mar 24 02:52:10 PM PDT 24
Finished Mar 24 02:52:11 PM PDT 24
Peak memory 203824 kb
Host smart-bbd595c9-7dbf-43a0-903b-6abe37200be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644690513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3644690513
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1546461355
Short name T984
Test name
Test status
Simulation time 94145627496 ps
CPU time 1175.11 seconds
Started Mar 24 02:52:07 PM PDT 24
Finished Mar 24 03:11:43 PM PDT 24
Peak memory 204248 kb
Host smart-76e989a5-8aac-4e7e-8f7d-6c22fe11488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546461355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1546461355
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1824513293
Short name T879
Test name
Test status
Simulation time 5002187564 ps
CPU time 77.57 seconds
Started Mar 24 02:52:09 PM PDT 24
Finished Mar 24 02:53:26 PM PDT 24
Peak memory 252948 kb
Host smart-c21a67aa-263d-4262-8667-27e333b5634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824513293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1824513293
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2600202009
Short name T607
Test name
Test status
Simulation time 2473559725 ps
CPU time 3.39 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:52:16 PM PDT 24
Peak memory 204140 kb
Host smart-b7ef4aa3-9081-4fbc-a9a8-6632c125c619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600202009 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2600202009
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3789711793
Short name T920
Test name
Test status
Simulation time 10027274241 ps
CPU time 59.66 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:53:14 PM PDT 24
Peak memory 491760 kb
Host smart-178ac7fc-2756-4238-9eac-32ee0b582b0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789711793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3789711793
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3796545024
Short name T906
Test name
Test status
Simulation time 10065456490 ps
CPU time 81.92 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:53:34 PM PDT 24
Peak memory 629700 kb
Host smart-887197ce-950c-4354-a329-9716891c6d55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796545024 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3796545024
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.375384557
Short name T1089
Test name
Test status
Simulation time 1155798965 ps
CPU time 1.9 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:52:14 PM PDT 24
Peak memory 204220 kb
Host smart-914fe5ec-7349-48ec-8275-ba2f48a2cfb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375384557 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.375384557
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.932897283
Short name T297
Test name
Test status
Simulation time 4568184852 ps
CPU time 5.18 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:52:18 PM PDT 24
Peak memory 212448 kb
Host smart-36323845-909e-4767-8342-69cd82c6732a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932897283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.932897283
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3413093726
Short name T308
Test name
Test status
Simulation time 7040149208 ps
CPU time 15.02 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:52:28 PM PDT 24
Peak memory 204216 kb
Host smart-71c04689-70e2-4597-9e05-a68ca8deda96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413093726 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3413093726
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1549611251
Short name T306
Test name
Test status
Simulation time 2248889699 ps
CPU time 33.69 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:52:46 PM PDT 24
Peak memory 204236 kb
Host smart-0fdbffe6-d02d-490f-a3be-54000b3c0306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549611251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1549611251
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1747411769
Short name T979
Test name
Test status
Simulation time 1087069630 ps
CPU time 17.99 seconds
Started Mar 24 02:52:13 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 210164 kb
Host smart-d96042ea-67cb-49bb-84d0-b86e6a9f1fd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747411769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1747411769
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2670413807
Short name T429
Test name
Test status
Simulation time 35820070949 ps
CPU time 243.2 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:56:15 PM PDT 24
Peak memory 1757172 kb
Host smart-4ca595fe-84d5-493e-b2d1-6123b2f2a64f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670413807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2670413807
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2990454594
Short name T728
Test name
Test status
Simulation time 1491215356 ps
CPU time 6.66 seconds
Started Mar 24 02:52:13 PM PDT 24
Finished Mar 24 02:52:20 PM PDT 24
Peak memory 204164 kb
Host smart-1b58bbd7-a6b9-4bae-8548-2ba80583321d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990454594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2990454594
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.2357676377
Short name T27
Test name
Test status
Simulation time 1477546626 ps
CPU time 5.02 seconds
Started Mar 24 02:52:11 PM PDT 24
Finished Mar 24 02:52:17 PM PDT 24
Peak memory 204204 kb
Host smart-96101b09-f2ad-402e-8ee3-d8ad12cd0336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357676377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.2357676377
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2266522357
Short name T976
Test name
Test status
Simulation time 15262215 ps
CPU time 0.6 seconds
Started Mar 24 02:52:17 PM PDT 24
Finished Mar 24 02:52:18 PM PDT 24
Peak memory 203924 kb
Host smart-c1f98c24-49c3-468d-b675-859db739b2f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266522357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2266522357
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.431560334
Short name T619
Test name
Test status
Simulation time 88180504 ps
CPU time 1.36 seconds
Started Mar 24 02:52:11 PM PDT 24
Finished Mar 24 02:52:12 PM PDT 24
Peak memory 212352 kb
Host smart-0e22d15c-2c46-4dd0-a171-56d4d7689da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431560334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.431560334
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3344650825
Short name T299
Test name
Test status
Simulation time 636506073 ps
CPU time 3.58 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:52:18 PM PDT 24
Peak memory 235204 kb
Host smart-d503f167-05d4-413a-af34-d020af48881d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344650825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3344650825
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2030704458
Short name T716
Test name
Test status
Simulation time 1760675805 ps
CPU time 60.75 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:53:15 PM PDT 24
Peak memory 637068 kb
Host smart-a9e8515f-628e-4326-a022-b3b1d11f6509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030704458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2030704458
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.235273577
Short name T506
Test name
Test status
Simulation time 5110141526 ps
CPU time 78.68 seconds
Started Mar 24 02:52:13 PM PDT 24
Finished Mar 24 02:53:32 PM PDT 24
Peak memory 461068 kb
Host smart-4732b7a0-0400-4296-9f61-910b920d4409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235273577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.235273577
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1104110302
Short name T845
Test name
Test status
Simulation time 192598003 ps
CPU time 0.92 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:52:15 PM PDT 24
Peak memory 203740 kb
Host smart-4167033d-2641-411d-bb4c-7021ad9cd571
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104110302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1104110302
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.496245912
Short name T1051
Test name
Test status
Simulation time 198857053 ps
CPU time 5.7 seconds
Started Mar 24 02:52:12 PM PDT 24
Finished Mar 24 02:52:17 PM PDT 24
Peak memory 204204 kb
Host smart-be682b36-d2fc-4f84-9078-2480f90060c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496245912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
496245912
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.290462879
Short name T452
Test name
Test status
Simulation time 6694671426 ps
CPU time 218.18 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:55:53 PM PDT 24
Peak memory 971264 kb
Host smart-28bdb44f-b067-4832-b738-a6c2d14ba1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290462879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.290462879
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_override.2744051347
Short name T798
Test name
Test status
Simulation time 55058781 ps
CPU time 0.68 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:52:15 PM PDT 24
Peak memory 203536 kb
Host smart-edf2efd5-d55b-4b5b-b8b5-bfe875901ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744051347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2744051347
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3132876832
Short name T36
Test name
Test status
Simulation time 30070038360 ps
CPU time 2151.69 seconds
Started Mar 24 02:52:11 PM PDT 24
Finished Mar 24 03:28:03 PM PDT 24
Peak memory 811956 kb
Host smart-676d8964-87d9-47f7-a2c7-cc5ab48d4e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132876832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3132876832
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.654660409
Short name T265
Test name
Test status
Simulation time 1625943707 ps
CPU time 58.62 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:53:13 PM PDT 24
Peak memory 307652 kb
Host smart-13fca51c-676e-4edd-b0b4-f7d82a37e45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654660409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.654660409
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2404860833
Short name T1061
Test name
Test status
Simulation time 1204883547 ps
CPU time 3.38 seconds
Started Mar 24 02:52:18 PM PDT 24
Finished Mar 24 02:52:22 PM PDT 24
Peak memory 204132 kb
Host smart-19223c64-44bd-426e-8e53-c9eabad34504
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404860833 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2404860833
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2307111850
Short name T490
Test name
Test status
Simulation time 10093144032 ps
CPU time 88.21 seconds
Started Mar 24 02:52:19 PM PDT 24
Finished Mar 24 02:53:47 PM PDT 24
Peak memory 689080 kb
Host smart-abc7dd51-5231-4c20-9dba-3a3f0fc42e8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307111850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2307111850
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.706595332
Short name T471
Test name
Test status
Simulation time 928440755 ps
CPU time 2.51 seconds
Started Mar 24 02:52:16 PM PDT 24
Finished Mar 24 02:52:18 PM PDT 24
Peak memory 204152 kb
Host smart-021f1962-1d7e-4655-87d6-beb37349c45d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706595332 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.706595332
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.764683906
Short name T252
Test name
Test status
Simulation time 668074269 ps
CPU time 4.04 seconds
Started Mar 24 02:52:17 PM PDT 24
Finished Mar 24 02:52:21 PM PDT 24
Peak memory 204172 kb
Host smart-b1ed2c70-82c1-4f59-97a2-e1907e553df5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764683906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.764683906
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2477793039
Short name T827
Test name
Test status
Simulation time 4133697756 ps
CPU time 17.47 seconds
Started Mar 24 02:52:14 PM PDT 24
Finished Mar 24 02:52:32 PM PDT 24
Peak memory 204172 kb
Host smart-2ab617f4-ce58-4371-9a38-f8bb6cf76587
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477793039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2477793039
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2206016211
Short name T1053
Test name
Test status
Simulation time 2232999128 ps
CPU time 19.25 seconds
Started Mar 24 02:52:15 PM PDT 24
Finished Mar 24 02:52:34 PM PDT 24
Peak memory 218988 kb
Host smart-e9572c3a-6562-4ca6-b8ef-0fbc5e9a36db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206016211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2206016211
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3291685406
Short name T1094
Test name
Test status
Simulation time 9417723012 ps
CPU time 265.6 seconds
Started Mar 24 02:52:17 PM PDT 24
Finished Mar 24 02:56:42 PM PDT 24
Peak memory 2176300 kb
Host smart-82c1599b-752c-4fec-84e1-34bbedddda97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291685406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3291685406
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1630385297
Short name T531
Test name
Test status
Simulation time 1253427393 ps
CPU time 6.55 seconds
Started Mar 24 02:52:19 PM PDT 24
Finished Mar 24 02:52:26 PM PDT 24
Peak memory 212404 kb
Host smart-47bb28e1-a89e-43fa-88fb-c40af9a12a44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630385297 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1630385297
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.598001514
Short name T615
Test name
Test status
Simulation time 45751907 ps
CPU time 0.6 seconds
Started Mar 24 02:52:25 PM PDT 24
Finished Mar 24 02:52:26 PM PDT 24
Peak memory 204256 kb
Host smart-733a36c5-c3d1-4cbd-8cac-96f9f6c40d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598001514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.598001514
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3775269054
Short name T1041
Test name
Test status
Simulation time 402265056 ps
CPU time 21.68 seconds
Started Mar 24 02:52:18 PM PDT 24
Finished Mar 24 02:52:40 PM PDT 24
Peak memory 294248 kb
Host smart-2623ab13-3373-4448-9bf6-34433756869f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775269054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3775269054
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2512601144
Short name T1003
Test name
Test status
Simulation time 1841999265 ps
CPU time 88.3 seconds
Started Mar 24 02:52:18 PM PDT 24
Finished Mar 24 02:53:46 PM PDT 24
Peak memory 319900 kb
Host smart-03c987b8-ab9c-46cc-aa1e-c8f824bfea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512601144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2512601144
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2657836987
Short name T708
Test name
Test status
Simulation time 13033763926 ps
CPU time 82.77 seconds
Started Mar 24 02:52:20 PM PDT 24
Finished Mar 24 02:53:42 PM PDT 24
Peak memory 758132 kb
Host smart-7963ea63-49a4-445e-a0bd-3ed882bc4c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657836987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2657836987
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1318195496
Short name T542
Test name
Test status
Simulation time 97983116 ps
CPU time 0.92 seconds
Started Mar 24 02:52:17 PM PDT 24
Finished Mar 24 02:52:18 PM PDT 24
Peak memory 204140 kb
Host smart-204bbb72-d512-45b5-8865-12b7b0a3862a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318195496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1318195496
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2808425809
Short name T6
Test name
Test status
Simulation time 803948259 ps
CPU time 4.59 seconds
Started Mar 24 02:52:17 PM PDT 24
Finished Mar 24 02:52:22 PM PDT 24
Peak memory 232656 kb
Host smart-a29394e9-56ab-4cd4-8fb0-44c3e61779d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808425809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2808425809
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3667655813
Short name T559
Test name
Test status
Simulation time 20750090638 ps
CPU time 154.39 seconds
Started Mar 24 02:52:19 PM PDT 24
Finished Mar 24 02:54:54 PM PDT 24
Peak memory 1316164 kb
Host smart-1b9e86ad-a34a-4953-8677-edf2e02513dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667655813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3667655813
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_override.4276574500
Short name T21
Test name
Test status
Simulation time 69631825 ps
CPU time 0.71 seconds
Started Mar 24 02:52:18 PM PDT 24
Finished Mar 24 02:52:19 PM PDT 24
Peak memory 203788 kb
Host smart-e6a3f0d3-e50c-4188-ac51-a7d79bea3346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276574500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.4276574500
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2882191657
Short name T895
Test name
Test status
Simulation time 5932387588 ps
CPU time 125.46 seconds
Started Mar 24 02:52:19 PM PDT 24
Finished Mar 24 02:54:25 PM PDT 24
Peak memory 295452 kb
Host smart-a0c47935-d08e-4ba0-9399-4e17909a7ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882191657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2882191657
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2073716142
Short name T867
Test name
Test status
Simulation time 556220893 ps
CPU time 2.98 seconds
Started Mar 24 02:52:24 PM PDT 24
Finished Mar 24 02:52:27 PM PDT 24
Peak memory 204220 kb
Host smart-0cba0aa4-25e6-40f9-a37c-01bbe9cf4eea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073716142 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2073716142
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.2146553501
Short name T566
Test name
Test status
Simulation time 10477667202 ps
CPU time 13.03 seconds
Started Mar 24 02:52:24 PM PDT 24
Finished Mar 24 02:52:38 PM PDT 24
Peak memory 266304 kb
Host smart-5b18e8b5-123c-4b7e-a440-d3f3e72a1ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146553501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.2146553501
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3940247335
Short name T241
Test name
Test status
Simulation time 10079220233 ps
CPU time 96.61 seconds
Started Mar 24 02:52:22 PM PDT 24
Finished Mar 24 02:53:59 PM PDT 24
Peak memory 726784 kb
Host smart-203e3111-f535-46ac-a1e1-2ad24a1b2067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940247335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3940247335
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.2407928103
Short name T759
Test name
Test status
Simulation time 1203149914 ps
CPU time 3.03 seconds
Started Mar 24 02:52:21 PM PDT 24
Finished Mar 24 02:52:24 PM PDT 24
Peak memory 204420 kb
Host smart-25e2a66e-f8ec-403e-9ffa-1fa88269f199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407928103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.2407928103
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3892096276
Short name T271
Test name
Test status
Simulation time 3227190422 ps
CPU time 4.41 seconds
Started Mar 24 02:52:22 PM PDT 24
Finished Mar 24 02:52:26 PM PDT 24
Peak memory 204176 kb
Host smart-1a3072df-2fbc-4105-af54-78674c6c29ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892096276 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3892096276
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.4288726947
Short name T377
Test name
Test status
Simulation time 3021284326 ps
CPU time 37.5 seconds
Started Mar 24 02:52:21 PM PDT 24
Finished Mar 24 02:52:59 PM PDT 24
Peak memory 204096 kb
Host smart-fe151c94-8907-46fd-88f7-ea942ef95dc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288726947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.4288726947
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.189536896
Short name T1088
Test name
Test status
Simulation time 1174123470 ps
CPU time 9.57 seconds
Started Mar 24 02:52:23 PM PDT 24
Finished Mar 24 02:52:33 PM PDT 24
Peak memory 208240 kb
Host smart-06cfb2f4-9f7b-40f2-9ba0-b4e5a27c7dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189536896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.189536896
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3507361415
Short name T502
Test name
Test status
Simulation time 39197757327 ps
CPU time 293.3 seconds
Started Mar 24 02:52:21 PM PDT 24
Finished Mar 24 02:57:14 PM PDT 24
Peak memory 2271512 kb
Host smart-78df3771-95fb-4857-a1a0-b27ba3189edf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507361415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3507361415
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.2690875173
Short name T571
Test name
Test status
Simulation time 6530357919 ps
CPU time 7.7 seconds
Started Mar 24 02:52:21 PM PDT 24
Finished Mar 24 02:52:28 PM PDT 24
Peak memory 220356 kb
Host smart-2d535a92-5402-49b3-9955-df588944e9e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690875173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.2690875173
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.2303342871
Short name T836
Test name
Test status
Simulation time 2669953962 ps
CPU time 7.57 seconds
Started Mar 24 02:52:31 PM PDT 24
Finished Mar 24 02:52:40 PM PDT 24
Peak memory 211240 kb
Host smart-ed22694d-a8b4-4ef1-bdfa-44596c2ca3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303342871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.2303342871
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1062618983
Short name T927
Test name
Test status
Simulation time 42564497 ps
CPU time 0.63 seconds
Started Mar 24 02:52:29 PM PDT 24
Finished Mar 24 02:52:30 PM PDT 24
Peak memory 203944 kb
Host smart-6122e932-6d98-4d62-bd32-eae7b3bda049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062618983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1062618983
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3801262309
Short name T811
Test name
Test status
Simulation time 299239160 ps
CPU time 1.19 seconds
Started Mar 24 02:52:31 PM PDT 24
Finished Mar 24 02:52:34 PM PDT 24
Peak memory 212368 kb
Host smart-9dd3dea0-e633-4625-ae7a-10d806cd17ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801262309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3801262309
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2744456987
Short name T817
Test name
Test status
Simulation time 1211067224 ps
CPU time 7.46 seconds
Started Mar 24 02:52:28 PM PDT 24
Finished Mar 24 02:52:36 PM PDT 24
Peak memory 271052 kb
Host smart-26c93fd5-2ef8-4a08-baf2-1a5253dbc44f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744456987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2744456987
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.4282679819
Short name T445
Test name
Test status
Simulation time 1345278553 ps
CPU time 33.79 seconds
Started Mar 24 02:52:26 PM PDT 24
Finished Mar 24 02:53:00 PM PDT 24
Peak memory 469948 kb
Host smart-ab9fa35a-d904-48af-abd8-c3988e03ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282679819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4282679819
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.3679123626
Short name T638
Test name
Test status
Simulation time 3242213260 ps
CPU time 97.75 seconds
Started Mar 24 02:52:25 PM PDT 24
Finished Mar 24 02:54:03 PM PDT 24
Peak memory 551496 kb
Host smart-50a7f64b-54e2-40ee-a85a-8dca49a39778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679123626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3679123626
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3683778296
Short name T857
Test name
Test status
Simulation time 400232899 ps
CPU time 0.98 seconds
Started Mar 24 02:52:25 PM PDT 24
Finished Mar 24 02:52:26 PM PDT 24
Peak memory 203976 kb
Host smart-ad3076f3-2863-46cc-8d1c-5c1e9416bb9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683778296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3683778296
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1976240340
Short name T567
Test name
Test status
Simulation time 608074228 ps
CPU time 9.42 seconds
Started Mar 24 02:52:25 PM PDT 24
Finished Mar 24 02:52:35 PM PDT 24
Peak memory 232192 kb
Host smart-227d3d77-429d-4868-b694-31b31eb5e556
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976240340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1976240340
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.25176470
Short name T951
Test name
Test status
Simulation time 11187226367 ps
CPU time 203.75 seconds
Started Mar 24 02:52:31 PM PDT 24
Finished Mar 24 02:55:56 PM PDT 24
Peak memory 929000 kb
Host smart-98f16429-60a2-4e8d-abca-ad45df73ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25176470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.25176470
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_override.1631924265
Short name T843
Test name
Test status
Simulation time 25867653 ps
CPU time 0.64 seconds
Started Mar 24 02:52:26 PM PDT 24
Finished Mar 24 02:52:26 PM PDT 24
Peak memory 203852 kb
Host smart-ef3032cc-e36f-4861-b6d0-485ed241305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631924265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1631924265
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.385646661
Short name T275
Test name
Test status
Simulation time 449162921 ps
CPU time 3.29 seconds
Started Mar 24 02:52:28 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 223808 kb
Host smart-9b9a5dab-686a-44ca-b2a7-2b846de61be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385646661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.385646661
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1564172830
Short name T1034
Test name
Test status
Simulation time 4737143908 ps
CPU time 40.88 seconds
Started Mar 24 02:52:35 PM PDT 24
Finished Mar 24 02:53:17 PM PDT 24
Peak memory 295784 kb
Host smart-b7e7f99b-83e3-406a-81f0-91108ca5e527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564172830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1564172830
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1439911550
Short name T533
Test name
Test status
Simulation time 2496864978 ps
CPU time 3.47 seconds
Started Mar 24 02:52:31 PM PDT 24
Finished Mar 24 02:52:36 PM PDT 24
Peak memory 204236 kb
Host smart-bbd1cdb5-3b85-4570-8c5e-f8d1bd6efdef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439911550 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1439911550
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3473612079
Short name T513
Test name
Test status
Simulation time 10244463020 ps
CPU time 13.71 seconds
Started Mar 24 02:52:32 PM PDT 24
Finished Mar 24 02:52:46 PM PDT 24
Peak memory 297044 kb
Host smart-b7faf42f-bd8e-4807-863a-43863430b246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473612079 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3473612079
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3635843348
Short name T781
Test name
Test status
Simulation time 10054552783 ps
CPU time 80.7 seconds
Started Mar 24 02:52:30 PM PDT 24
Finished Mar 24 02:53:51 PM PDT 24
Peak memory 722952 kb
Host smart-9ad48b78-4d3c-4973-929e-eb1fdcf84225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635843348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3635843348
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1079799051
Short name T268
Test name
Test status
Simulation time 1020016342 ps
CPU time 2.49 seconds
Started Mar 24 02:52:32 PM PDT 24
Finished Mar 24 02:52:35 PM PDT 24
Peak memory 203904 kb
Host smart-18adf428-3ee6-4d0e-b108-2d4d7473df28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079799051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1079799051
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.495230884
Short name T767
Test name
Test status
Simulation time 865048261 ps
CPU time 4.59 seconds
Started Mar 24 02:52:26 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 208000 kb
Host smart-0b1989aa-9c21-443a-8d93-5260571daa21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495230884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.495230884
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3756661367
Short name T557
Test name
Test status
Simulation time 575405250 ps
CPU time 7.8 seconds
Started Mar 24 02:52:25 PM PDT 24
Finished Mar 24 02:52:33 PM PDT 24
Peak memory 204128 kb
Host smart-92182960-5163-44ae-acf1-12d48e1d6d2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756661367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3756661367
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.2685286092
Short name T965
Test name
Test status
Simulation time 6594118240 ps
CPU time 31.24 seconds
Started Mar 24 02:52:36 PM PDT 24
Finished Mar 24 02:53:08 PM PDT 24
Peak memory 222180 kb
Host smart-c874a7c8-ab5a-4f04-b1a6-b47fc9ee312e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685286092 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.2685286092
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2188197841
Short name T787
Test name
Test status
Simulation time 2396077355 ps
CPU time 18.02 seconds
Started Mar 24 02:52:28 PM PDT 24
Finished Mar 24 02:52:47 PM PDT 24
Peak memory 218996 kb
Host smart-88cb4197-1f99-4ff8-8cad-c429e77fee3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188197841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2188197841
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1207220180
Short name T662
Test name
Test status
Simulation time 7701032122 ps
CPU time 687.92 seconds
Started Mar 24 02:52:27 PM PDT 24
Finished Mar 24 03:03:55 PM PDT 24
Peak memory 1961368 kb
Host smart-4037a898-53d9-4f4e-bf6a-f582aff37fa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207220180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1207220180
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.458302541
Short name T401
Test name
Test status
Simulation time 2713050462 ps
CPU time 6.5 seconds
Started Mar 24 02:52:24 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 219484 kb
Host smart-a9af93a5-bb54-49c3-b3d7-3926c59d6ffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458302541 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.458302541
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3348863332
Short name T324
Test name
Test status
Simulation time 16068824 ps
CPU time 0.61 seconds
Started Mar 24 02:52:36 PM PDT 24
Finished Mar 24 02:52:38 PM PDT 24
Peak memory 203820 kb
Host smart-b9fcdb74-2d88-4b76-b116-6ec0894848e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348863332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3348863332
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3978373983
Short name T591
Test name
Test status
Simulation time 34563150 ps
CPU time 1.06 seconds
Started Mar 24 02:52:31 PM PDT 24
Finished Mar 24 02:52:33 PM PDT 24
Peak memory 212420 kb
Host smart-40a93340-a00d-49d7-9517-37adbb4db02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978373983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3978373983
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.300089202
Short name T253
Test name
Test status
Simulation time 798655524 ps
CPU time 4.16 seconds
Started Mar 24 02:52:33 PM PDT 24
Finished Mar 24 02:52:38 PM PDT 24
Peak memory 213280 kb
Host smart-2dea1445-d328-419c-bc0e-1ad533b27037
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300089202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.300089202
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3315439003
Short name T780
Test name
Test status
Simulation time 9745053712 ps
CPU time 180.83 seconds
Started Mar 24 02:52:32 PM PDT 24
Finished Mar 24 02:55:33 PM PDT 24
Peak memory 788048 kb
Host smart-a01e5b72-c9de-4d26-b7e1-cadf0359b4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315439003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3315439003
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2103647254
Short name T725
Test name
Test status
Simulation time 1108715250 ps
CPU time 74.63 seconds
Started Mar 24 02:52:31 PM PDT 24
Finished Mar 24 02:53:45 PM PDT 24
Peak memory 475748 kb
Host smart-9777a929-fe4b-4d70-a900-762612eb9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103647254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2103647254
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3190396038
Short name T199
Test name
Test status
Simulation time 133114804 ps
CPU time 0.94 seconds
Started Mar 24 02:52:29 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 203968 kb
Host smart-a361f929-78fc-49fc-82c1-bd56d6ef62de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190396038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3190396038
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3858960196
Short name T296
Test name
Test status
Simulation time 168455984 ps
CPU time 4.52 seconds
Started Mar 24 02:52:32 PM PDT 24
Finished Mar 24 02:52:37 PM PDT 24
Peak memory 204176 kb
Host smart-a301bf57-8799-4fed-906d-2e72faebb62e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858960196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3858960196
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1028853644
Short name T209
Test name
Test status
Simulation time 6455722888 ps
CPU time 234.14 seconds
Started Mar 24 02:52:33 PM PDT 24
Finished Mar 24 02:56:29 PM PDT 24
Peak memory 992052 kb
Host smart-e003865b-a0b4-4125-a3f7-d2102c9da0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028853644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1028853644
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_override.2946546283
Short name T956
Test name
Test status
Simulation time 23819953 ps
CPU time 0.66 seconds
Started Mar 24 02:52:30 PM PDT 24
Finished Mar 24 02:52:31 PM PDT 24
Peak memory 203816 kb
Host smart-46dfeb52-7831-43a6-b05a-f6756c4ead45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946546283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2946546283
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2369984881
Short name T973
Test name
Test status
Simulation time 6962893967 ps
CPU time 138.22 seconds
Started Mar 24 02:52:33 PM PDT 24
Finished Mar 24 02:54:53 PM PDT 24
Peak memory 284720 kb
Host smart-1fe343ec-866b-4470-9fd9-f0cd502cd27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369984881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2369984881
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2456659837
Short name T982
Test name
Test status
Simulation time 809951524 ps
CPU time 54.88 seconds
Started Mar 24 02:52:29 PM PDT 24
Finished Mar 24 02:53:24 PM PDT 24
Peak memory 249104 kb
Host smart-49956078-001d-439d-ade4-e40b9e67d515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456659837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2456659837
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1565808070
Short name T1054
Test name
Test status
Simulation time 4290113720 ps
CPU time 5.16 seconds
Started Mar 24 02:52:36 PM PDT 24
Finished Mar 24 02:52:42 PM PDT 24
Peak memory 204228 kb
Host smart-51cc5480-419d-4688-be15-30d63b68f0e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565808070 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1565808070
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.4062097371
Short name T934
Test name
Test status
Simulation time 10145546079 ps
CPU time 38.49 seconds
Started Mar 24 02:52:35 PM PDT 24
Finished Mar 24 02:53:14 PM PDT 24
Peak memory 410900 kb
Host smart-db3a4a14-4182-4607-b61e-824fba74ca7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062097371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.4062097371
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3011614094
Short name T517
Test name
Test status
Simulation time 10190090175 ps
CPU time 38.66 seconds
Started Mar 24 02:52:37 PM PDT 24
Finished Mar 24 02:53:16 PM PDT 24
Peak memory 478740 kb
Host smart-129367fa-6875-479b-94ee-626809984190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011614094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3011614094
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1678426808
Short name T467
Test name
Test status
Simulation time 540828952 ps
CPU time 3.09 seconds
Started Mar 24 02:52:35 PM PDT 24
Finished Mar 24 02:52:39 PM PDT 24
Peak memory 204116 kb
Host smart-ed447904-a853-4d5d-a4dd-a290ba443729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678426808 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1678426808
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.237074631
Short name T981
Test name
Test status
Simulation time 1132494745 ps
CPU time 5.26 seconds
Started Mar 24 02:52:33 PM PDT 24
Finished Mar 24 02:52:40 PM PDT 24
Peak memory 212324 kb
Host smart-3eaf7fe3-53a1-4272-b5d4-88aff657ed31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237074631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.237074631
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.4204423958
Short name T90
Test name
Test status
Simulation time 739328190 ps
CPU time 12.56 seconds
Started Mar 24 02:52:29 PM PDT 24
Finished Mar 24 02:52:42 PM PDT 24
Peak memory 204180 kb
Host smart-8955c5dd-2f88-4cd1-9bcb-c78b6edc0ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204423958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.4204423958
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.26679586
Short name T765
Test name
Test status
Simulation time 863263921 ps
CPU time 5.68 seconds
Started Mar 24 02:52:34 PM PDT 24
Finished Mar 24 02:52:41 PM PDT 24
Peak memory 204164 kb
Host smart-7cf198f0-4483-49c7-8d5e-eb564652cfc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26679586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stress_rd.26679586
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.184417308
Short name T945
Test name
Test status
Simulation time 1486769787 ps
CPU time 7.11 seconds
Started Mar 24 02:52:34 PM PDT 24
Finished Mar 24 02:52:43 PM PDT 24
Peak memory 218112 kb
Host smart-5bce7104-7459-42b3-af72-76f3a4b0f804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184417308 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.184417308
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3623068624
Short name T820
Test name
Test status
Simulation time 27021486 ps
CPU time 0.61 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:48:58 PM PDT 24
Peak memory 203936 kb
Host smart-65a008eb-a5c8-4f87-a09a-93a5e23420d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623068624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3623068624
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.136383318
Short name T666
Test name
Test status
Simulation time 251206000 ps
CPU time 1.41 seconds
Started Mar 24 02:48:45 PM PDT 24
Finished Mar 24 02:48:46 PM PDT 24
Peak memory 212352 kb
Host smart-687e15d4-6089-4309-be17-8d2667985418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136383318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.136383318
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3561516134
Short name T520
Test name
Test status
Simulation time 4661172862 ps
CPU time 7.16 seconds
Started Mar 24 02:48:46 PM PDT 24
Finished Mar 24 02:48:54 PM PDT 24
Peak memory 263208 kb
Host smart-b7962280-6f7b-419b-bec4-116dd3f01ffe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561516134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3561516134
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3939569899
Short name T392
Test name
Test status
Simulation time 2302724359 ps
CPU time 80.85 seconds
Started Mar 24 02:48:47 PM PDT 24
Finished Mar 24 02:50:08 PM PDT 24
Peak memory 705008 kb
Host smart-d8ba6ac2-7694-4c41-b130-577cacf13e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939569899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3939569899
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.480281675
Short name T972
Test name
Test status
Simulation time 120981018 ps
CPU time 1 seconds
Started Mar 24 02:48:48 PM PDT 24
Finished Mar 24 02:48:50 PM PDT 24
Peak memory 203952 kb
Host smart-601d4b3c-7b38-4c91-87aa-7eea25300570
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480281675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.480281675
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1472337600
Short name T680
Test name
Test status
Simulation time 344170544 ps
CPU time 4.14 seconds
Started Mar 24 02:48:46 PM PDT 24
Finished Mar 24 02:48:51 PM PDT 24
Peak memory 204152 kb
Host smart-6fa20339-2bc2-4543-91cf-43848e6c93da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472337600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1472337600
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.286490861
Short name T1093
Test name
Test status
Simulation time 2686175091 ps
CPU time 76.99 seconds
Started Mar 24 02:48:48 PM PDT 24
Finished Mar 24 02:50:05 PM PDT 24
Peak memory 871704 kb
Host smart-9ce2eb8f-042f-410c-bf94-a7d1775cffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286490861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.286490861
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_override.3746475336
Short name T103
Test name
Test status
Simulation time 41216494 ps
CPU time 0.64 seconds
Started Mar 24 02:48:47 PM PDT 24
Finished Mar 24 02:48:48 PM PDT 24
Peak memory 203816 kb
Host smart-2f674bb9-681d-410c-89f1-cc01b01c8d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746475336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3746475336
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1492023556
Short name T261
Test name
Test status
Simulation time 1371916681 ps
CPU time 8.34 seconds
Started Mar 24 02:48:49 PM PDT 24
Finished Mar 24 02:48:58 PM PDT 24
Peak memory 212364 kb
Host smart-c294cc17-f265-42c9-8091-ad1d6859f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492023556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1492023556
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1615135282
Short name T800
Test name
Test status
Simulation time 1116708291 ps
CPU time 2.73 seconds
Started Mar 24 02:48:51 PM PDT 24
Finished Mar 24 02:48:54 PM PDT 24
Peak memory 204144 kb
Host smart-57ac844a-0694-4966-a6e8-8bb6ae101cc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615135282 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1615135282
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2276511229
Short name T225
Test name
Test status
Simulation time 10112908305 ps
CPU time 29.77 seconds
Started Mar 24 02:48:44 PM PDT 24
Finished Mar 24 02:49:14 PM PDT 24
Peak memory 380044 kb
Host smart-ebaaf563-f572-43c3-a7a2-14e3faff5609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276511229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2276511229
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1882755455
Short name T441
Test name
Test status
Simulation time 10191270580 ps
CPU time 15.79 seconds
Started Mar 24 02:48:47 PM PDT 24
Finished Mar 24 02:49:03 PM PDT 24
Peak memory 325172 kb
Host smart-0327b521-0240-4482-b1cf-770368e8fc60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882755455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1882755455
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.960378012
Short name T727
Test name
Test status
Simulation time 3610308507 ps
CPU time 2.4 seconds
Started Mar 24 02:48:49 PM PDT 24
Finished Mar 24 02:48:52 PM PDT 24
Peak memory 204256 kb
Host smart-a6648bae-2bb4-4be0-8670-5191a7cb6ce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960378012 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.960378012
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1702255811
Short name T1029
Test name
Test status
Simulation time 2091140704 ps
CPU time 2.96 seconds
Started Mar 24 02:48:49 PM PDT 24
Finished Mar 24 02:48:52 PM PDT 24
Peak memory 204184 kb
Host smart-272fc436-c0c6-42d2-a0fc-81fd78b96b9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702255811 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1702255811
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2494334242
Short name T359
Test name
Test status
Simulation time 804312616 ps
CPU time 13.84 seconds
Started Mar 24 02:48:46 PM PDT 24
Finished Mar 24 02:49:00 PM PDT 24
Peak memory 204188 kb
Host smart-6c793649-3226-4437-9f40-c22219324dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494334242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2494334242
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1722774104
Short name T563
Test name
Test status
Simulation time 3250055289 ps
CPU time 13.82 seconds
Started Mar 24 02:48:46 PM PDT 24
Finished Mar 24 02:49:00 PM PDT 24
Peak memory 215644 kb
Host smart-a830d878-7af6-4f0d-a4a6-9aa0db50197e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722774104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1722774104
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2040371862
Short name T10
Test name
Test status
Simulation time 8188315102 ps
CPU time 567.81 seconds
Started Mar 24 02:48:48 PM PDT 24
Finished Mar 24 02:58:16 PM PDT 24
Peak memory 1690484 kb
Host smart-a39145a6-7244-4d89-a91a-6bde2ec9331c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040371862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2040371862
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3988181563
Short name T925
Test name
Test status
Simulation time 1633635794 ps
CPU time 8.21 seconds
Started Mar 24 02:48:45 PM PDT 24
Finished Mar 24 02:48:53 PM PDT 24
Peak memory 220084 kb
Host smart-fe464b56-5dce-45bc-ba4b-d7e9c8a2c692
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988181563 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3988181563
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1688365643
Short name T254
Test name
Test status
Simulation time 18458489 ps
CPU time 0.63 seconds
Started Mar 24 02:52:49 PM PDT 24
Finished Mar 24 02:52:50 PM PDT 24
Peak memory 203936 kb
Host smart-6927af63-4148-499d-952d-86957e9504de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688365643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1688365643
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.783145097
Short name T660
Test name
Test status
Simulation time 51926570 ps
CPU time 1.56 seconds
Started Mar 24 02:52:42 PM PDT 24
Finished Mar 24 02:52:44 PM PDT 24
Peak memory 212336 kb
Host smart-e56ca7cb-c1f0-4abe-8322-2de3f9950c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783145097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.783145097
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.414859473
Short name T70
Test name
Test status
Simulation time 322418885 ps
CPU time 6.65 seconds
Started Mar 24 02:52:35 PM PDT 24
Finished Mar 24 02:52:42 PM PDT 24
Peak memory 256540 kb
Host smart-d7b88b21-e040-4757-9dae-b6f457b3bc87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414859473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.414859473
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2988004648
Short name T86
Test name
Test status
Simulation time 2001391216 ps
CPU time 51.41 seconds
Started Mar 24 02:52:41 PM PDT 24
Finished Mar 24 02:53:32 PM PDT 24
Peak memory 324192 kb
Host smart-905fc472-aca8-4ef8-a529-3840f13d04a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988004648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2988004648
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1272649686
Short name T164
Test name
Test status
Simulation time 2140671794 ps
CPU time 65.03 seconds
Started Mar 24 02:52:35 PM PDT 24
Finished Mar 24 02:53:41 PM PDT 24
Peak memory 715616 kb
Host smart-cf4580b3-da00-4715-98d8-45f1dd8d162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272649686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1272649686
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.4014809204
Short name T378
Test name
Test status
Simulation time 1913010679 ps
CPU time 0.93 seconds
Started Mar 24 02:52:36 PM PDT 24
Finished Mar 24 02:52:38 PM PDT 24
Peak memory 203892 kb
Host smart-d6fc4207-f295-42b5-ac3a-7925fb02aae5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014809204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.4014809204
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.563061057
Short name T556
Test name
Test status
Simulation time 553062212 ps
CPU time 3.27 seconds
Started Mar 24 02:52:36 PM PDT 24
Finished Mar 24 02:52:40 PM PDT 24
Peak memory 204104 kb
Host smart-d9ccf739-0101-4181-be0d-9fa80bfa0ca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563061057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
563061057
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1986525956
Short name T316
Test name
Test status
Simulation time 10369188317 ps
CPU time 174.7 seconds
Started Mar 24 02:52:35 PM PDT 24
Finished Mar 24 02:55:30 PM PDT 24
Peak memory 850268 kb
Host smart-10980786-e04a-4ac8-a5c5-29ae2e8dd990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986525956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1986525956
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_override.1935117297
Short name T9
Test name
Test status
Simulation time 16548487 ps
CPU time 0.65 seconds
Started Mar 24 02:52:34 PM PDT 24
Finished Mar 24 02:52:35 PM PDT 24
Peak memory 203816 kb
Host smart-fa910c11-ae78-4424-b991-62f31a356fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935117297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1935117297
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2154077306
Short name T1090
Test name
Test status
Simulation time 1202201316 ps
CPU time 100.68 seconds
Started Mar 24 02:52:38 PM PDT 24
Finished Mar 24 02:54:19 PM PDT 24
Peak memory 293620 kb
Host smart-926c9855-f5a7-4685-a7e9-8c9c63ffc951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154077306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2154077306
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.153121610
Short name T549
Test name
Test status
Simulation time 1760414581 ps
CPU time 4.48 seconds
Started Mar 24 02:52:45 PM PDT 24
Finished Mar 24 02:52:49 PM PDT 24
Peak memory 212400 kb
Host smart-0d2bfd2b-9789-4d31-8100-56a4b9b9cb2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153121610 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.153121610
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2315876264
Short name T226
Test name
Test status
Simulation time 10069841634 ps
CPU time 74.94 seconds
Started Mar 24 02:52:41 PM PDT 24
Finished Mar 24 02:53:56 PM PDT 24
Peak memory 607328 kb
Host smart-cb66029b-0d62-4829-99ed-557cf2548c6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315876264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2315876264
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1591067973
Short name T1008
Test name
Test status
Simulation time 10171471731 ps
CPU time 9.48 seconds
Started Mar 24 02:52:41 PM PDT 24
Finished Mar 24 02:52:50 PM PDT 24
Peak memory 280972 kb
Host smart-e89dca99-58d6-4508-9130-5ec02cfc97fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591067973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1591067973
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1831556737
Short name T644
Test name
Test status
Simulation time 517307862 ps
CPU time 2.93 seconds
Started Mar 24 02:52:46 PM PDT 24
Finished Mar 24 02:52:49 PM PDT 24
Peak memory 204132 kb
Host smart-46307e4a-5e8d-41d3-92a5-b4ca53359198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831556737 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1831556737
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1916575155
Short name T229
Test name
Test status
Simulation time 903115756 ps
CPU time 5.06 seconds
Started Mar 24 02:52:40 PM PDT 24
Finished Mar 24 02:52:46 PM PDT 24
Peak memory 212360 kb
Host smart-5f50fc66-c8a0-4f1f-a163-dea74d46ab0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916575155 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1916575155
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3036583896
Short name T454
Test name
Test status
Simulation time 4290941087 ps
CPU time 44.31 seconds
Started Mar 24 02:52:40 PM PDT 24
Finished Mar 24 02:53:25 PM PDT 24
Peak memory 204220 kb
Host smart-5498cc8c-f99d-4d07-94a1-608620af6aa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036583896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3036583896
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.640370166
Short name T52
Test name
Test status
Simulation time 234493256 ps
CPU time 4.51 seconds
Started Mar 24 02:52:43 PM PDT 24
Finished Mar 24 02:52:48 PM PDT 24
Peak memory 204196 kb
Host smart-c28e04ef-cfa1-40a9-991a-83216111dc26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640370166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_rd.640370166
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.4122947771
Short name T637
Test name
Test status
Simulation time 12906043339 ps
CPU time 28.2 seconds
Started Mar 24 02:52:40 PM PDT 24
Finished Mar 24 02:53:09 PM PDT 24
Peak memory 204220 kb
Host smart-a748c17d-ab8c-4921-abfe-18981f7d656c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122947771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.4122947771
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1767668986
Short name T745
Test name
Test status
Simulation time 29457782345 ps
CPU time 1631.31 seconds
Started Mar 24 02:52:42 PM PDT 24
Finished Mar 24 03:19:54 PM PDT 24
Peak memory 3279532 kb
Host smart-02773dea-59b0-4908-b22c-4e543dd6a6a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767668986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1767668986
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.3948885615
Short name T447
Test name
Test status
Simulation time 1400629864 ps
CPU time 6.87 seconds
Started Mar 24 02:52:43 PM PDT 24
Finished Mar 24 02:52:50 PM PDT 24
Peak memory 204200 kb
Host smart-a107450a-794e-42b3-a362-4a0e15a5bfca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948885615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.3948885615
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.742636016
Short name T259
Test name
Test status
Simulation time 91540716 ps
CPU time 0.62 seconds
Started Mar 24 02:52:48 PM PDT 24
Finished Mar 24 02:52:49 PM PDT 24
Peak memory 203920 kb
Host smart-7512aa8a-290c-4bea-99ac-360c9ca2ef80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742636016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.742636016
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2866438021
Short name T690
Test name
Test status
Simulation time 84156390 ps
CPU time 1.43 seconds
Started Mar 24 02:52:50 PM PDT 24
Finished Mar 24 02:52:52 PM PDT 24
Peak memory 212324 kb
Host smart-f96f3429-f3d4-4deb-9f26-13cd5d3b7a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866438021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2866438021
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.4029554155
Short name T928
Test name
Test status
Simulation time 293090638 ps
CPU time 13.97 seconds
Started Mar 24 02:52:51 PM PDT 24
Finished Mar 24 02:53:05 PM PDT 24
Peak memory 262712 kb
Host smart-e7793067-2d5a-40ec-b708-2469ffaf72c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029554155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.4029554155
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3758102918
Short name T79
Test name
Test status
Simulation time 11378145315 ps
CPU time 70.07 seconds
Started Mar 24 02:52:47 PM PDT 24
Finished Mar 24 02:53:57 PM PDT 24
Peak memory 731176 kb
Host smart-7e309505-8eba-417d-b03c-40e3016b8695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758102918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3758102918
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1922973335
Short name T328
Test name
Test status
Simulation time 1966712485 ps
CPU time 149.82 seconds
Started Mar 24 02:52:52 PM PDT 24
Finished Mar 24 02:55:22 PM PDT 24
Peak memory 692420 kb
Host smart-fce336cc-bbb3-495c-b57e-1d179b58ad45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922973335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1922973335
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.82521769
Short name T407
Test name
Test status
Simulation time 432521205 ps
CPU time 0.97 seconds
Started Mar 24 02:52:52 PM PDT 24
Finished Mar 24 02:52:53 PM PDT 24
Peak memory 203932 kb
Host smart-02094a84-62e3-4c7a-83ad-c1d8cb3ec49a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82521769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt
.82521769
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.4120075442
Short name T340
Test name
Test status
Simulation time 137649450 ps
CPU time 7.17 seconds
Started Mar 24 02:52:50 PM PDT 24
Finished Mar 24 02:52:57 PM PDT 24
Peak memory 204208 kb
Host smart-adcbde2d-1be2-4407-9331-1cbd4e3908f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120075442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.4120075442
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1028557542
Short name T158
Test name
Test status
Simulation time 2804857555 ps
CPU time 58.17 seconds
Started Mar 24 02:52:43 PM PDT 24
Finished Mar 24 02:53:42 PM PDT 24
Peak memory 832616 kb
Host smart-63c916f1-a8cf-451a-91cb-a66962cbb79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028557542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1028557542
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_override.4193772617
Short name T994
Test name
Test status
Simulation time 124057437 ps
CPU time 0.63 seconds
Started Mar 24 02:52:44 PM PDT 24
Finished Mar 24 02:52:45 PM PDT 24
Peak memory 203836 kb
Host smart-098c5115-87ea-4b98-8119-46cf4cc8bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193772617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.4193772617
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.109972940
Short name T717
Test name
Test status
Simulation time 5025119123 ps
CPU time 71.57 seconds
Started Mar 24 02:52:46 PM PDT 24
Finished Mar 24 02:53:58 PM PDT 24
Peak memory 222516 kb
Host smart-325fb118-7055-4bd4-8596-e39ab284dd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109972940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.109972940
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2222302864
Short name T999
Test name
Test status
Simulation time 4014208374 ps
CPU time 74.03 seconds
Started Mar 24 02:52:47 PM PDT 24
Finished Mar 24 02:54:01 PM PDT 24
Peak memory 268632 kb
Host smart-7367150d-07c1-4106-9b77-4f3a1c3f6694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222302864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2222302864
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2529646813
Short name T345
Test name
Test status
Simulation time 2889380166 ps
CPU time 3.73 seconds
Started Mar 24 02:52:44 PM PDT 24
Finished Mar 24 02:52:47 PM PDT 24
Peak memory 204252 kb
Host smart-5f1777b2-3867-46a0-aa2b-ff4c3a018585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529646813 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2529646813
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.2654889703
Short name T193
Test name
Test status
Simulation time 10277852799 ps
CPU time 15.78 seconds
Started Mar 24 02:52:48 PM PDT 24
Finished Mar 24 02:53:03 PM PDT 24
Peak memory 291568 kb
Host smart-62fead25-76e4-4b51-811f-debcf65ad23e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654889703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.2654889703
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3823150297
Short name T515
Test name
Test status
Simulation time 10147918180 ps
CPU time 91.07 seconds
Started Mar 24 02:52:47 PM PDT 24
Finished Mar 24 02:54:18 PM PDT 24
Peak memory 699608 kb
Host smart-f324a3c1-caac-4265-8564-3e5d8f8d953e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823150297 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3823150297
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2128888304
Short name T505
Test name
Test status
Simulation time 2755760422 ps
CPU time 2.57 seconds
Started Mar 24 02:52:50 PM PDT 24
Finished Mar 24 02:52:52 PM PDT 24
Peak memory 204244 kb
Host smart-b7537bad-db75-4d80-93d7-d9e1c2de0d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128888304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2128888304
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.296071348
Short name T1071
Test name
Test status
Simulation time 3314619095 ps
CPU time 4.09 seconds
Started Mar 24 02:52:51 PM PDT 24
Finished Mar 24 02:52:55 PM PDT 24
Peak memory 204172 kb
Host smart-a4bc5567-2bae-4130-8c38-dc8d44a1d95d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296071348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.296071348
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.625286850
Short name T941
Test name
Test status
Simulation time 5128562165 ps
CPU time 44.01 seconds
Started Mar 24 02:52:45 PM PDT 24
Finished Mar 24 02:53:29 PM PDT 24
Peak memory 204224 kb
Host smart-3499a7c5-6bcf-4bea-bb50-6b2a7d3c7d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625286850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.625286850
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.4124038446
Short name T302
Test name
Test status
Simulation time 3148675166 ps
CPU time 34.17 seconds
Started Mar 24 02:52:44 PM PDT 24
Finished Mar 24 02:53:19 PM PDT 24
Peak memory 204208 kb
Host smart-0ef22369-822c-475e-8984-5e173bd34295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124038446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.4124038446
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3012654597
Short name T902
Test name
Test status
Simulation time 15952025448 ps
CPU time 294.47 seconds
Started Mar 24 02:52:48 PM PDT 24
Finished Mar 24 02:57:42 PM PDT 24
Peak memory 2011840 kb
Host smart-e6a6cc00-cf95-499f-bd8c-4814d288bfc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012654597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3012654597
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1083572134
Short name T477
Test name
Test status
Simulation time 4676412850 ps
CPU time 7.43 seconds
Started Mar 24 02:52:52 PM PDT 24
Finished Mar 24 02:52:59 PM PDT 24
Peak memory 212652 kb
Host smart-bdfa0fdb-1bd6-4540-b50b-6d45691bd9db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083572134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1083572134
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.557710275
Short name T333
Test name
Test status
Simulation time 16743671 ps
CPU time 0.6 seconds
Started Mar 24 02:52:54 PM PDT 24
Finished Mar 24 02:52:55 PM PDT 24
Peak memory 203936 kb
Host smart-711e4623-4104-4511-a57d-6152d69ed081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557710275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.557710275
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1684546644
Short name T534
Test name
Test status
Simulation time 92555439 ps
CPU time 1.54 seconds
Started Mar 24 02:52:52 PM PDT 24
Finished Mar 24 02:52:53 PM PDT 24
Peak memory 212380 kb
Host smart-0269f3e9-0778-4fcb-af49-a533ea137aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684546644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1684546644
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.866283665
Short name T356
Test name
Test status
Simulation time 867964292 ps
CPU time 4.73 seconds
Started Mar 24 02:52:51 PM PDT 24
Finished Mar 24 02:52:56 PM PDT 24
Peak memory 243116 kb
Host smart-24882075-356f-4d78-b143-f184c06dd2b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866283665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.866283665
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.404390240
Short name T807
Test name
Test status
Simulation time 4392692173 ps
CPU time 157.48 seconds
Started Mar 24 02:52:51 PM PDT 24
Finished Mar 24 02:55:29 PM PDT 24
Peak memory 729844 kb
Host smart-8036b451-47aa-459d-b4f2-1c2c88b4c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404390240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.404390240
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2459642400
Short name T763
Test name
Test status
Simulation time 1763449147 ps
CPU time 135.03 seconds
Started Mar 24 02:52:48 PM PDT 24
Finished Mar 24 02:55:04 PM PDT 24
Peak memory 641792 kb
Host smart-1bd3ec85-e62f-40e3-989f-0cc708532f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459642400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2459642400
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.527349326
Short name T476
Test name
Test status
Simulation time 88962752 ps
CPU time 0.9 seconds
Started Mar 24 02:52:51 PM PDT 24
Finished Mar 24 02:52:52 PM PDT 24
Peak memory 203896 kb
Host smart-a2ccfdc6-9273-421c-a909-670576a13b1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527349326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.527349326
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.185366004
Short name T1004
Test name
Test status
Simulation time 380383551 ps
CPU time 5.85 seconds
Started Mar 24 02:52:52 PM PDT 24
Finished Mar 24 02:52:58 PM PDT 24
Peak memory 217828 kb
Host smart-ee9db032-01c9-4c4b-977d-58514002a65e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185366004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
185366004
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3226141806
Short name T791
Test name
Test status
Simulation time 2817328508 ps
CPU time 157.1 seconds
Started Mar 24 02:52:49 PM PDT 24
Finished Mar 24 02:55:26 PM PDT 24
Peak memory 720572 kb
Host smart-c9b65421-b548-4279-b941-37c88758a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226141806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3226141806
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_override.567746527
Short name T991
Test name
Test status
Simulation time 17440657 ps
CPU time 0.65 seconds
Started Mar 24 02:52:50 PM PDT 24
Finished Mar 24 02:52:51 PM PDT 24
Peak memory 203832 kb
Host smart-276dc62f-f25e-4796-94f8-7fc2d77554f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567746527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.567746527
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.4224774111
Short name T184
Test name
Test status
Simulation time 24867540244 ps
CPU time 332.54 seconds
Started Mar 24 02:52:48 PM PDT 24
Finished Mar 24 02:58:21 PM PDT 24
Peak memory 230420 kb
Host smart-75b7f225-4664-43ca-a081-32d8d2f7e864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224774111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.4224774111
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3374236645
Short name T665
Test name
Test status
Simulation time 6614230145 ps
CPU time 67.19 seconds
Started Mar 24 02:52:51 PM PDT 24
Finished Mar 24 02:53:59 PM PDT 24
Peak memory 333660 kb
Host smart-d96adbb4-9080-4f52-9fab-3f3d893a8d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374236645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3374236645
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2930942613
Short name T314
Test name
Test status
Simulation time 964061727 ps
CPU time 4.14 seconds
Started Mar 24 02:52:54 PM PDT 24
Finished Mar 24 02:52:58 PM PDT 24
Peak memory 204148 kb
Host smart-68ec39e2-e061-4397-bc14-d9672fed416e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930942613 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2930942613
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1507332471
Short name T923
Test name
Test status
Simulation time 10033107794 ps
CPU time 83.5 seconds
Started Mar 24 02:52:55 PM PDT 24
Finished Mar 24 02:54:18 PM PDT 24
Peak memory 570040 kb
Host smart-ad83c6ef-2d4c-4321-af67-ad916714d668
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507332471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1507332471
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3207415633
Short name T194
Test name
Test status
Simulation time 10068239786 ps
CPU time 81.94 seconds
Started Mar 24 02:52:53 PM PDT 24
Finished Mar 24 02:54:15 PM PDT 24
Peak memory 673100 kb
Host smart-5de91082-8c56-4a23-93f8-c4719f304a73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207415633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3207415633
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2399775833
Short name T712
Test name
Test status
Simulation time 325739931 ps
CPU time 2.06 seconds
Started Mar 24 02:52:56 PM PDT 24
Finished Mar 24 02:52:58 PM PDT 24
Peak memory 204140 kb
Host smart-47703766-a226-4740-83dc-0bfde9216fad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399775833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2399775833
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.634091300
Short name T1005
Test name
Test status
Simulation time 592248331 ps
CPU time 3.52 seconds
Started Mar 24 02:52:54 PM PDT 24
Finished Mar 24 02:52:58 PM PDT 24
Peak memory 204132 kb
Host smart-5e170037-9c15-4a95-be87-fac246dcc5d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634091300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.634091300
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1912499652
Short name T403
Test name
Test status
Simulation time 2726033725 ps
CPU time 6.1 seconds
Started Mar 24 02:52:55 PM PDT 24
Finished Mar 24 02:53:02 PM PDT 24
Peak memory 204200 kb
Host smart-eb7d1a0b-221b-4f28-930f-4b54b6b56c87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912499652 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1912499652
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1855233016
Short name T273
Test name
Test status
Simulation time 1147076264 ps
CPU time 15.51 seconds
Started Mar 24 02:52:51 PM PDT 24
Finished Mar 24 02:53:07 PM PDT 24
Peak memory 204120 kb
Host smart-5a454aca-d7fe-476a-8c20-470767a53ea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855233016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1855233016
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2619165347
Short name T947
Test name
Test status
Simulation time 1015230280 ps
CPU time 30.16 seconds
Started Mar 24 02:52:54 PM PDT 24
Finished Mar 24 02:53:24 PM PDT 24
Peak memory 204144 kb
Host smart-4c731842-84b5-4098-be2b-9e5eaf7aa620
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619165347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2619165347
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3278618505
Short name T744
Test name
Test status
Simulation time 24821164625 ps
CPU time 139.49 seconds
Started Mar 24 02:52:55 PM PDT 24
Finished Mar 24 02:55:15 PM PDT 24
Peak memory 1325240 kb
Host smart-69504704-6fda-4495-9ae4-18fb535170c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278618505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3278618505
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1388409761
Short name T775
Test name
Test status
Simulation time 1875458517 ps
CPU time 6.74 seconds
Started Mar 24 02:52:53 PM PDT 24
Finished Mar 24 02:53:00 PM PDT 24
Peak memory 212396 kb
Host smart-25f52525-ddab-4c49-a292-5aa49406ae0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388409761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1388409761
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2130769961
Short name T279
Test name
Test status
Simulation time 18995619 ps
CPU time 0.58 seconds
Started Mar 24 02:53:06 PM PDT 24
Finished Mar 24 02:53:07 PM PDT 24
Peak memory 203908 kb
Host smart-b050781a-1e0a-4aff-a522-e5b214683e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130769961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2130769961
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2820742882
Short name T282
Test name
Test status
Simulation time 85680179 ps
CPU time 1.25 seconds
Started Mar 24 02:53:01 PM PDT 24
Finished Mar 24 02:53:02 PM PDT 24
Peak memory 212256 kb
Host smart-05a848f2-c165-4b3a-ac9c-c01cf45e2c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820742882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2820742882
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3570786200
Short name T939
Test name
Test status
Simulation time 986113630 ps
CPU time 5.37 seconds
Started Mar 24 02:52:58 PM PDT 24
Finished Mar 24 02:53:03 PM PDT 24
Peak memory 256928 kb
Host smart-ac63f653-dabf-4514-b039-740c57f3c873
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570786200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3570786200
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1464282736
Short name T59
Test name
Test status
Simulation time 6401055741 ps
CPU time 97.05 seconds
Started Mar 24 02:53:01 PM PDT 24
Finished Mar 24 02:54:38 PM PDT 24
Peak memory 539964 kb
Host smart-eee0ab8f-6a24-4922-824a-62e51465dabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464282736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1464282736
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1204871367
Short name T332
Test name
Test status
Simulation time 4046377364 ps
CPU time 34.69 seconds
Started Mar 24 02:52:52 PM PDT 24
Finished Mar 24 02:53:27 PM PDT 24
Peak memory 438536 kb
Host smart-1935f0e6-462a-4cd5-8bda-5d3d2dc71893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204871367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1204871367
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3697676136
Short name T269
Test name
Test status
Simulation time 176027502 ps
CPU time 1.1 seconds
Started Mar 24 02:52:56 PM PDT 24
Finished Mar 24 02:52:58 PM PDT 24
Peak memory 204160 kb
Host smart-89daff9a-8382-49c4-8b40-fdebc0d6f7fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697676136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3697676136
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3160121288
Short name T372
Test name
Test status
Simulation time 273030410 ps
CPU time 3.35 seconds
Started Mar 24 02:52:57 PM PDT 24
Finished Mar 24 02:53:00 PM PDT 24
Peak memory 204176 kb
Host smart-0a19267a-05fe-405d-98d8-3870a4a8b045
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160121288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3160121288
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3047170926
Short name T78
Test name
Test status
Simulation time 10449333834 ps
CPU time 61.95 seconds
Started Mar 24 02:52:55 PM PDT 24
Finished Mar 24 02:53:57 PM PDT 24
Peak memory 829312 kb
Host smart-af271387-8a77-4de9-a77f-fa44ddbf730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047170926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3047170926
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_override.1010101385
Short name T451
Test name
Test status
Simulation time 16388081 ps
CPU time 0.64 seconds
Started Mar 24 02:52:55 PM PDT 24
Finished Mar 24 02:52:56 PM PDT 24
Peak memory 203852 kb
Host smart-a1ef0a10-57a8-4baf-aeea-9caab2ae0446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010101385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1010101385
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.529820152
Short name T17
Test name
Test status
Simulation time 5014399935 ps
CPU time 2346.2 seconds
Started Mar 24 02:53:01 PM PDT 24
Finished Mar 24 03:32:08 PM PDT 24
Peak memory 774360 kb
Host smart-a4721bff-a915-45a3-b7b3-98337132c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529820152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.529820152
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1017390993
Short name T493
Test name
Test status
Simulation time 3177621491 ps
CPU time 74.29 seconds
Started Mar 24 02:52:57 PM PDT 24
Finished Mar 24 02:54:12 PM PDT 24
Peak memory 261584 kb
Host smart-237f5db7-8a4a-4df9-87d6-e10af2e601bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017390993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1017390993
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.704921038
Short name T558
Test name
Test status
Simulation time 1846953997 ps
CPU time 3.8 seconds
Started Mar 24 02:53:07 PM PDT 24
Finished Mar 24 02:53:11 PM PDT 24
Peak memory 204232 kb
Host smart-137d3baf-4fda-440a-be56-06b8bf160290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704921038 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.704921038
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3842478385
Short name T62
Test name
Test status
Simulation time 10066207955 ps
CPU time 93.1 seconds
Started Mar 24 02:53:01 PM PDT 24
Finished Mar 24 02:54:35 PM PDT 24
Peak memory 615296 kb
Host smart-bc4b14f4-e861-44b4-9d17-6920bdd64e45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842478385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3842478385
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2140422682
Short name T548
Test name
Test status
Simulation time 10169443119 ps
CPU time 17.16 seconds
Started Mar 24 02:53:01 PM PDT 24
Finished Mar 24 02:53:18 PM PDT 24
Peak memory 353468 kb
Host smart-0b4fcffc-aeae-44db-9c70-ee3739889945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140422682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2140422682
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3585894164
Short name T25
Test name
Test status
Simulation time 779811865 ps
CPU time 2.25 seconds
Started Mar 24 02:53:06 PM PDT 24
Finished Mar 24 02:53:09 PM PDT 24
Peak memory 204128 kb
Host smart-10b5d7e2-aa04-42d5-8f2a-425ac40a98c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585894164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3585894164
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3511060368
Short name T231
Test name
Test status
Simulation time 1191954069 ps
CPU time 6.37 seconds
Started Mar 24 02:53:04 PM PDT 24
Finished Mar 24 02:53:10 PM PDT 24
Peak memory 204204 kb
Host smart-0323bbb0-ab36-4dfc-9088-c1420ea1da38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511060368 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3511060368
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2919700452
Short name T540
Test name
Test status
Simulation time 2657395746 ps
CPU time 10.54 seconds
Started Mar 24 02:53:03 PM PDT 24
Finished Mar 24 02:53:14 PM PDT 24
Peak memory 204192 kb
Host smart-89892fc9-5c9c-4282-b7c3-4b80cc8eddbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919700452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2919700452
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.3969331601
Short name T574
Test name
Test status
Simulation time 34556408587 ps
CPU time 2779.14 seconds
Started Mar 24 02:52:59 PM PDT 24
Finished Mar 24 03:39:19 PM PDT 24
Peak memory 7648896 kb
Host smart-ddc60ba6-a505-4d7f-834b-27dbdfb85ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969331601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.3969331601
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2020894935
Short name T694
Test name
Test status
Simulation time 4814946922 ps
CPU time 6.69 seconds
Started Mar 24 02:53:00 PM PDT 24
Finished Mar 24 02:53:08 PM PDT 24
Peak memory 204196 kb
Host smart-bf1c2979-0691-47f7-9632-5f1023713d06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020894935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2020894935
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1290618705
Short name T525
Test name
Test status
Simulation time 18121267 ps
CPU time 0.62 seconds
Started Mar 24 02:53:09 PM PDT 24
Finished Mar 24 02:53:09 PM PDT 24
Peak memory 203940 kb
Host smart-c60f0cbb-b773-4b4b-bc19-53cfc2605e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290618705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1290618705
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.499391468
Short name T45
Test name
Test status
Simulation time 77512393 ps
CPU time 1.41 seconds
Started Mar 24 02:53:05 PM PDT 24
Finished Mar 24 02:53:07 PM PDT 24
Peak memory 204164 kb
Host smart-a36dad7e-ce2f-428c-9449-5707a44e06f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499391468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.499391468
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3841489812
Short name T596
Test name
Test status
Simulation time 701701925 ps
CPU time 4.94 seconds
Started Mar 24 02:53:12 PM PDT 24
Finished Mar 24 02:53:17 PM PDT 24
Peak memory 237680 kb
Host smart-19ec9f9e-ddc7-47a1-b529-8a31d0f207ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841489812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3841489812
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1116176287
Short name T776
Test name
Test status
Simulation time 1966416498 ps
CPU time 59.13 seconds
Started Mar 24 02:53:04 PM PDT 24
Finished Mar 24 02:54:03 PM PDT 24
Peak memory 693160 kb
Host smart-ab7ccd22-5eff-4e9c-829d-a4189ebc0f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116176287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1116176287
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3484201834
Short name T1033
Test name
Test status
Simulation time 6916983023 ps
CPU time 119.71 seconds
Started Mar 24 02:53:06 PM PDT 24
Finished Mar 24 02:55:06 PM PDT 24
Peak memory 618580 kb
Host smart-603538a2-0744-4b3e-aadd-4d114f94ab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484201834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3484201834
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3384744754
Short name T203
Test name
Test status
Simulation time 521339261 ps
CPU time 0.96 seconds
Started Mar 24 02:53:13 PM PDT 24
Finished Mar 24 02:53:14 PM PDT 24
Peak memory 204124 kb
Host smart-6df263dd-e456-4ae8-bb83-d51530e55621
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384744754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.3384744754
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1066623918
Short name T1028
Test name
Test status
Simulation time 382033078 ps
CPU time 4.49 seconds
Started Mar 24 02:53:06 PM PDT 24
Finished Mar 24 02:53:10 PM PDT 24
Peak memory 234200 kb
Host smart-e9cdb567-69e5-4544-bc5a-c286596bcdb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066623918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1066623918
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1263258100
Short name T426
Test name
Test status
Simulation time 11762570563 ps
CPU time 212.03 seconds
Started Mar 24 02:53:04 PM PDT 24
Finished Mar 24 02:56:36 PM PDT 24
Peak memory 876892 kb
Host smart-ab06fdfc-f6c6-499c-8734-0e313a176f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263258100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1263258100
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_override.2994709055
Short name T570
Test name
Test status
Simulation time 16607684 ps
CPU time 0.63 seconds
Started Mar 24 02:53:05 PM PDT 24
Finished Mar 24 02:53:06 PM PDT 24
Peak memory 203796 kb
Host smart-a2217382-c948-4037-9d65-e02ec05c30f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994709055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2994709055
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2824386968
Short name T31
Test name
Test status
Simulation time 815330903 ps
CPU time 2.76 seconds
Started Mar 24 02:53:04 PM PDT 24
Finished Mar 24 02:53:08 PM PDT 24
Peak memory 220108 kb
Host smart-784ecea1-ddce-45d9-baba-36c0e725b701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824386968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2824386968
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.158398798
Short name T408
Test name
Test status
Simulation time 6662368014 ps
CPU time 75.2 seconds
Started Mar 24 02:53:13 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 334444 kb
Host smart-64b21883-abc8-4f17-9f24-717d2bdd25c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158398798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.158398798
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2538717151
Short name T737
Test name
Test status
Simulation time 1055767964 ps
CPU time 2.13 seconds
Started Mar 24 02:53:11 PM PDT 24
Finished Mar 24 02:53:13 PM PDT 24
Peak memory 204140 kb
Host smart-f374a755-ed78-458d-bc37-b504c75634bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538717151 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2538717151
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2560819089
Short name T374
Test name
Test status
Simulation time 10442440733 ps
CPU time 3.29 seconds
Started Mar 24 02:53:07 PM PDT 24
Finished Mar 24 02:53:10 PM PDT 24
Peak memory 221172 kb
Host smart-c05af76f-911f-4510-a3c6-acccbfc03674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560819089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2560819089
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3140350137
Short name T249
Test name
Test status
Simulation time 10530549678 ps
CPU time 7.61 seconds
Started Mar 24 02:53:10 PM PDT 24
Finished Mar 24 02:53:18 PM PDT 24
Peak memory 261328 kb
Host smart-349d35d2-ee0c-4daf-903c-fcd11e388bf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140350137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3140350137
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.966922469
Short name T885
Test name
Test status
Simulation time 635480862 ps
CPU time 3.42 seconds
Started Mar 24 02:53:08 PM PDT 24
Finished Mar 24 02:53:11 PM PDT 24
Peak memory 204332 kb
Host smart-e22b5bbd-0d64-4507-b23e-d67103a14190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966922469 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.966922469
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.4188540329
Short name T841
Test name
Test status
Simulation time 5140021628 ps
CPU time 5.7 seconds
Started Mar 24 02:53:06 PM PDT 24
Finished Mar 24 02:53:12 PM PDT 24
Peak memory 220352 kb
Host smart-497fbdd9-c032-433c-bf4c-b446e000592f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188540329 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.4188540329
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3394490640
Short name T676
Test name
Test status
Simulation time 2327587524 ps
CPU time 20.19 seconds
Started Mar 24 02:53:07 PM PDT 24
Finished Mar 24 02:53:27 PM PDT 24
Peak memory 204168 kb
Host smart-274d9ed3-6c8d-407e-9a63-c0461b481067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394490640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3394490640
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2093758505
Short name T1096
Test name
Test status
Simulation time 2209264736 ps
CPU time 10.41 seconds
Started Mar 24 02:53:13 PM PDT 24
Finished Mar 24 02:53:24 PM PDT 24
Peak memory 206708 kb
Host smart-62f7ae65-16e5-4659-87a7-f1b796207432
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093758505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2093758505
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1682636063
Short name T292
Test name
Test status
Simulation time 16289068745 ps
CPU time 810.9 seconds
Started Mar 24 02:53:06 PM PDT 24
Finished Mar 24 03:06:37 PM PDT 24
Peak memory 2130364 kb
Host smart-9858f993-d86f-41b5-be2d-b247cd39b106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682636063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1682636063
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.436073575
Short name T383
Test name
Test status
Simulation time 1175649756 ps
CPU time 6.38 seconds
Started Mar 24 02:53:08 PM PDT 24
Finished Mar 24 02:53:14 PM PDT 24
Peak memory 212396 kb
Host smart-6e9dc15d-4086-4ed6-a8d9-810b0a0228b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436073575 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.436073575
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.204832945
Short name T866
Test name
Test status
Simulation time 20385651 ps
CPU time 0.64 seconds
Started Mar 24 02:53:13 PM PDT 24
Finished Mar 24 02:53:13 PM PDT 24
Peak memory 203896 kb
Host smart-aeac130e-2b6d-4afb-a0a5-1af3779bffdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204832945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.204832945
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.4214134694
Short name T420
Test name
Test status
Simulation time 257501802 ps
CPU time 5.77 seconds
Started Mar 24 02:53:07 PM PDT 24
Finished Mar 24 02:53:13 PM PDT 24
Peak memory 254964 kb
Host smart-d5714220-18e0-4427-8c75-7e64d1d4760e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214134694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.4214134694
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.56466068
Short name T633
Test name
Test status
Simulation time 5283139801 ps
CPU time 43.1 seconds
Started Mar 24 02:53:10 PM PDT 24
Finished Mar 24 02:53:53 PM PDT 24
Peak memory 498168 kb
Host smart-ffba27db-d12d-4f2b-9389-5fe567453124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56466068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.56466068
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2176561059
Short name T894
Test name
Test status
Simulation time 8784112879 ps
CPU time 69.72 seconds
Started Mar 24 02:53:08 PM PDT 24
Finished Mar 24 02:54:18 PM PDT 24
Peak memory 640500 kb
Host smart-8fcd8b0c-b2e5-4592-adfa-dce31fce48a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176561059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2176561059
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.968173729
Short name T494
Test name
Test status
Simulation time 243321728 ps
CPU time 0.94 seconds
Started Mar 24 02:53:09 PM PDT 24
Finished Mar 24 02:53:10 PM PDT 24
Peak memory 204144 kb
Host smart-c26305a5-0d7a-4888-9310-44abeefe7ab7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968173729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.968173729
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.543295024
Short name T1107
Test name
Test status
Simulation time 419334626 ps
CPU time 3.33 seconds
Started Mar 24 02:53:12 PM PDT 24
Finished Mar 24 02:53:15 PM PDT 24
Peak memory 218208 kb
Host smart-19a85e32-967e-4f2c-8520-97ddf012473d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543295024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
543295024
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.439718861
Short name T754
Test name
Test status
Simulation time 3883667966 ps
CPU time 111.52 seconds
Started Mar 24 02:53:08 PM PDT 24
Finished Mar 24 02:55:00 PM PDT 24
Peak memory 1070540 kb
Host smart-6797fb73-f8b3-4041-960e-59d27d805f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439718861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.439718861
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_override.2830130097
Short name T604
Test name
Test status
Simulation time 46685047 ps
CPU time 0.63 seconds
Started Mar 24 02:53:08 PM PDT 24
Finished Mar 24 02:53:09 PM PDT 24
Peak memory 203836 kb
Host smart-ad78f200-5afd-4612-b552-302a0232bfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830130097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2830130097
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1463707678
Short name T238
Test name
Test status
Simulation time 12982296966 ps
CPU time 307.51 seconds
Started Mar 24 02:53:11 PM PDT 24
Finished Mar 24 02:58:18 PM PDT 24
Peak memory 603072 kb
Host smart-5e537d42-3947-496e-8257-1022ca2bd0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463707678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1463707678
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2457759862
Short name T892
Test name
Test status
Simulation time 6704788558 ps
CPU time 46.64 seconds
Started Mar 24 02:53:11 PM PDT 24
Finished Mar 24 02:53:58 PM PDT 24
Peak memory 299180 kb
Host smart-8d390583-ecf7-4790-b824-767a398b6d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457759862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2457759862
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.4160442917
Short name T198
Test name
Test status
Simulation time 61827729776 ps
CPU time 870.07 seconds
Started Mar 24 02:53:14 PM PDT 24
Finished Mar 24 03:07:44 PM PDT 24
Peak memory 1207060 kb
Host smart-b30fb0ad-1069-4b20-9a88-6a799dab0621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160442917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.4160442917
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2725062693
Short name T919
Test name
Test status
Simulation time 2586491595 ps
CPU time 5.81 seconds
Started Mar 24 02:53:15 PM PDT 24
Finished Mar 24 02:53:21 PM PDT 24
Peak memory 204224 kb
Host smart-ad2445b4-633a-4185-ae0b-63a42cb50d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725062693 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2725062693
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1406290943
Short name T64
Test name
Test status
Simulation time 10109608843 ps
CPU time 78.95 seconds
Started Mar 24 02:53:15 PM PDT 24
Finished Mar 24 02:54:34 PM PDT 24
Peak memory 606780 kb
Host smart-93093d58-08c8-4cc5-9674-bd0dcb28969a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406290943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1406290943
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1243999576
Short name T393
Test name
Test status
Simulation time 10206516450 ps
CPU time 41.95 seconds
Started Mar 24 02:53:14 PM PDT 24
Finished Mar 24 02:53:56 PM PDT 24
Peak memory 477960 kb
Host smart-dac91c48-9a3c-40dd-a41a-98e651dd407c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243999576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1243999576
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2236972614
Short name T41
Test name
Test status
Simulation time 470238565 ps
CPU time 2.77 seconds
Started Mar 24 02:53:11 PM PDT 24
Finished Mar 24 02:53:14 PM PDT 24
Peak memory 204168 kb
Host smart-8b230049-d0f6-4a11-9df3-9608f264d68e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236972614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2236972614
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2382657720
Short name T1026
Test name
Test status
Simulation time 902243593 ps
CPU time 4.42 seconds
Started Mar 24 02:53:15 PM PDT 24
Finished Mar 24 02:53:19 PM PDT 24
Peak memory 204132 kb
Host smart-71cf5b9e-90f9-4739-bff9-6f14d02fb730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382657720 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2382657720
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1798521877
Short name T53
Test name
Test status
Simulation time 5073529821 ps
CPU time 16.14 seconds
Started Mar 24 02:53:16 PM PDT 24
Finished Mar 24 02:53:32 PM PDT 24
Peak memory 204144 kb
Host smart-6b8fab08-bfce-4abd-be9b-109d491ede25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798521877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1798521877
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2528377068
Short name T613
Test name
Test status
Simulation time 1404700443 ps
CPU time 4.92 seconds
Started Mar 24 02:53:17 PM PDT 24
Finished Mar 24 02:53:22 PM PDT 24
Peak memory 204192 kb
Host smart-e5371f15-548c-4c22-82cd-5d92403eb035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528377068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2528377068
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1800870336
Short name T274
Test name
Test status
Simulation time 45366932895 ps
CPU time 314.93 seconds
Started Mar 24 02:53:16 PM PDT 24
Finished Mar 24 02:58:32 PM PDT 24
Peak memory 1028592 kb
Host smart-fcfb5104-6bff-4cc9-9b53-d01478fb9a0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800870336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1800870336
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2140032866
Short name T968
Test name
Test status
Simulation time 1557179799 ps
CPU time 8.11 seconds
Started Mar 24 02:53:16 PM PDT 24
Finished Mar 24 02:53:25 PM PDT 24
Peak memory 220292 kb
Host smart-bd62d396-38b8-4084-a2d7-edea264bd1bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140032866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2140032866
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2677057307
Short name T431
Test name
Test status
Simulation time 41069474 ps
CPU time 0.63 seconds
Started Mar 24 02:53:25 PM PDT 24
Finished Mar 24 02:53:26 PM PDT 24
Peak memory 203920 kb
Host smart-093b20c7-8f16-4965-9cf5-1ff5c3270382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677057307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2677057307
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2923188384
Short name T410
Test name
Test status
Simulation time 45547459 ps
CPU time 1.28 seconds
Started Mar 24 02:53:20 PM PDT 24
Finished Mar 24 02:53:22 PM PDT 24
Peak memory 212380 kb
Host smart-fac04ff5-f968-458f-aa38-795a768acb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923188384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2923188384
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.940500346
Short name T642
Test name
Test status
Simulation time 1751725224 ps
CPU time 7.64 seconds
Started Mar 24 02:53:18 PM PDT 24
Finished Mar 24 02:53:26 PM PDT 24
Peak memory 274260 kb
Host smart-53d220df-8b8d-460e-9df8-c28dbfbb78b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940500346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.940500346
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1675634240
Short name T886
Test name
Test status
Simulation time 2113921461 ps
CPU time 86.42 seconds
Started Mar 24 02:53:16 PM PDT 24
Finished Mar 24 02:54:43 PM PDT 24
Peak memory 498696 kb
Host smart-fc983906-bc77-4e42-b61b-377bb59f097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675634240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1675634240
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2206688160
Short name T303
Test name
Test status
Simulation time 7677510643 ps
CPU time 49.45 seconds
Started Mar 24 02:53:16 PM PDT 24
Finished Mar 24 02:54:06 PM PDT 24
Peak memory 636704 kb
Host smart-440c1426-c815-4e35-945e-aa6218f4e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206688160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2206688160
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3799871061
Short name T444
Test name
Test status
Simulation time 156989987 ps
CPU time 1.06 seconds
Started Mar 24 02:53:19 PM PDT 24
Finished Mar 24 02:53:20 PM PDT 24
Peak memory 204144 kb
Host smart-4720f55b-3464-473a-9ac9-0969695f6a6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799871061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3799871061
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3622328217
Short name T854
Test name
Test status
Simulation time 108584957 ps
CPU time 2.49 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:53:31 PM PDT 24
Peak memory 204196 kb
Host smart-d61196de-bb00-41cf-ad09-d76cf20d1eb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622328217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3622328217
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2968226419
Short name T930
Test name
Test status
Simulation time 7831640942 ps
CPU time 306.08 seconds
Started Mar 24 02:53:13 PM PDT 24
Finished Mar 24 02:58:19 PM PDT 24
Peak memory 1179740 kb
Host smart-38bedf90-4e37-41e9-ba0a-df0ba9960a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968226419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2968226419
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3002470771
Short name T187
Test name
Test status
Simulation time 6566548727 ps
CPU time 3028.52 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 03:43:58 PM PDT 24
Peak memory 853576 kb
Host smart-9129f609-d196-48cf-9b18-dc9269a4904c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002470771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3002470771
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3861633567
Short name T406
Test name
Test status
Simulation time 4991659344 ps
CPU time 41.38 seconds
Started Mar 24 02:53:16 PM PDT 24
Finished Mar 24 02:53:58 PM PDT 24
Peak memory 301216 kb
Host smart-d0fc512b-bc03-406a-ba21-db5e2b60a307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861633567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3861633567
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1393294433
Short name T453
Test name
Test status
Simulation time 983446054 ps
CPU time 4.17 seconds
Started Mar 24 02:53:17 PM PDT 24
Finished Mar 24 02:53:22 PM PDT 24
Peak memory 204112 kb
Host smart-c864ccc5-1b33-4efe-befe-5911a353ce1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393294433 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1393294433
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1617802945
Short name T580
Test name
Test status
Simulation time 10170093183 ps
CPU time 34.4 seconds
Started Mar 24 02:53:18 PM PDT 24
Finished Mar 24 02:53:53 PM PDT 24
Peak memory 406328 kb
Host smart-f8794c3c-ea5b-45ca-8066-2c92a6049394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617802945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1617802945
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.4238506840
Short name T65
Test name
Test status
Simulation time 10176196461 ps
CPU time 36.28 seconds
Started Mar 24 02:53:27 PM PDT 24
Finished Mar 24 02:54:03 PM PDT 24
Peak memory 450124 kb
Host smart-0344377c-7b59-4b91-8a88-fc7ecb594288
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238506840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.4238506840
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.4215068938
Short name T42
Test name
Test status
Simulation time 773540280 ps
CPU time 2.29 seconds
Started Mar 24 02:53:18 PM PDT 24
Finished Mar 24 02:53:21 PM PDT 24
Peak memory 204164 kb
Host smart-4f4a938b-d532-470b-a205-e0234651b7a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215068938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.4215068938
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.194399183
Short name T687
Test name
Test status
Simulation time 3677342415 ps
CPU time 4.97 seconds
Started Mar 24 02:53:17 PM PDT 24
Finished Mar 24 02:53:22 PM PDT 24
Peak memory 204248 kb
Host smart-2c5d5695-7c08-4a9d-afa6-9fc75143a46a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194399183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.194399183
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.4054248842
Short name T974
Test name
Test status
Simulation time 1726131292 ps
CPU time 22.63 seconds
Started Mar 24 02:53:18 PM PDT 24
Finished Mar 24 02:53:41 PM PDT 24
Peak memory 204168 kb
Host smart-a13f2225-ec5f-4e45-bd8c-62b17eab5c34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054248842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.4054248842
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1669109114
Short name T398
Test name
Test status
Simulation time 10403494403 ps
CPU time 55.89 seconds
Started Mar 24 02:53:19 PM PDT 24
Finished Mar 24 02:54:15 PM PDT 24
Peak memory 206676 kb
Host smart-05182481-78f9-4b07-a7fc-d1ce004fdde7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669109114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1669109114
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.463286058
Short name T1067
Test name
Test status
Simulation time 16416656920 ps
CPU time 34.82 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:54:04 PM PDT 24
Peak memory 204200 kb
Host smart-a132a9e9-dfe3-416d-bc5b-0a095c04982b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463286058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.463286058
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2171216773
Short name T601
Test name
Test status
Simulation time 22725887094 ps
CPU time 94.92 seconds
Started Mar 24 02:53:19 PM PDT 24
Finished Mar 24 02:54:54 PM PDT 24
Peak memory 1013912 kb
Host smart-0fa0e9a2-3222-4a69-a45b-cacb60209967
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171216773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2171216773
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.4105987439
Short name T242
Test name
Test status
Simulation time 1283007423 ps
CPU time 7.33 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:53:36 PM PDT 24
Peak memory 209928 kb
Host smart-4d55748e-2b56-41d9-ad7a-18fe082790f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105987439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.4105987439
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.294578369
Short name T326
Test name
Test status
Simulation time 18386116 ps
CPU time 0.63 seconds
Started Mar 24 02:53:31 PM PDT 24
Finished Mar 24 02:53:32 PM PDT 24
Peak memory 203940 kb
Host smart-4f708559-1319-4783-b30a-df10f8f551b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294578369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.294578369
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3000027732
Short name T519
Test name
Test status
Simulation time 67153461 ps
CPU time 1.46 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:53:31 PM PDT 24
Peak memory 212392 kb
Host smart-34b69fad-b9c1-4f2a-80ee-e0a50c665e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000027732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3000027732
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.507777703
Short name T545
Test name
Test status
Simulation time 398095582 ps
CPU time 8.01 seconds
Started Mar 24 02:53:25 PM PDT 24
Finished Mar 24 02:53:34 PM PDT 24
Peak memory 292008 kb
Host smart-7105b3e3-1709-418a-a447-c0092ce128ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507777703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.507777703
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.905187547
Short name T614
Test name
Test status
Simulation time 2197275339 ps
CPU time 61.93 seconds
Started Mar 24 02:53:25 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 476568 kb
Host smart-66d94cb3-a183-4745-8208-20b296f62103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905187547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.905187547
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1727690773
Short name T1080
Test name
Test status
Simulation time 6936289342 ps
CPU time 30.34 seconds
Started Mar 24 02:53:28 PM PDT 24
Finished Mar 24 02:53:59 PM PDT 24
Peak memory 481372 kb
Host smart-d1c4546c-8108-4498-b19e-4269efadcad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727690773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1727690773
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.813783325
Short name T938
Test name
Test status
Simulation time 131156024 ps
CPU time 1.12 seconds
Started Mar 24 02:53:25 PM PDT 24
Finished Mar 24 02:53:27 PM PDT 24
Peak memory 204176 kb
Host smart-e83c0fc0-a57d-44cf-9765-46728def34a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813783325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fm
t.813783325
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3831271238
Short name T575
Test name
Test status
Simulation time 174815686 ps
CPU time 4.55 seconds
Started Mar 24 02:53:25 PM PDT 24
Finished Mar 24 02:53:30 PM PDT 24
Peak memory 234904 kb
Host smart-0e80c6f7-2315-4552-8e9c-7b52be3fb0d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831271238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3831271238
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.629089805
Short name T208
Test name
Test status
Simulation time 14883508725 ps
CPU time 261.21 seconds
Started Mar 24 02:53:22 PM PDT 24
Finished Mar 24 02:57:44 PM PDT 24
Peak memory 1094404 kb
Host smart-3be41716-dbd1-452e-9e09-a95c17a25b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629089805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.629089805
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_override.2161147563
Short name T844
Test name
Test status
Simulation time 105510426 ps
CPU time 0.65 seconds
Started Mar 24 02:53:23 PM PDT 24
Finished Mar 24 02:53:24 PM PDT 24
Peak memory 203884 kb
Host smart-6e990b82-7fb3-4030-a8ea-b28fd40f122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161147563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2161147563
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.652214669
Short name T85
Test name
Test status
Simulation time 13053960988 ps
CPU time 624.8 seconds
Started Mar 24 02:53:25 PM PDT 24
Finished Mar 24 03:03:51 PM PDT 24
Peak memory 787056 kb
Host smart-cab3211a-1c5a-441b-9ff9-58b85fd6db6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652214669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.652214669
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2733522159
Short name T564
Test name
Test status
Simulation time 1061920499 ps
CPU time 42.12 seconds
Started Mar 24 02:53:22 PM PDT 24
Finished Mar 24 02:54:05 PM PDT 24
Peak memory 313092 kb
Host smart-6a1fda55-0109-4d50-be8d-0cbb32cfd03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733522159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2733522159
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.2258061446
Short name T75
Test name
Test status
Simulation time 9909335171 ps
CPU time 677.55 seconds
Started Mar 24 02:53:26 PM PDT 24
Finished Mar 24 03:04:43 PM PDT 24
Peak memory 1315896 kb
Host smart-ccd42c83-7d44-41ff-a585-bc7713bced94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258061446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.2258061446
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3886368523
Short name T305
Test name
Test status
Simulation time 19370180308 ps
CPU time 4.22 seconds
Started Mar 24 02:53:30 PM PDT 24
Finished Mar 24 02:53:34 PM PDT 24
Peak memory 204164 kb
Host smart-8adcdbf8-9570-45ba-8e86-bdb21735cbe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886368523 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3886368523
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2585502041
Short name T577
Test name
Test status
Simulation time 10060567886 ps
CPU time 73.97 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:54:43 PM PDT 24
Peak memory 543456 kb
Host smart-e3b571b4-304e-4f23-9121-3bdb3197a874
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585502041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2585502041
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2086737153
Short name T749
Test name
Test status
Simulation time 10116423963 ps
CPU time 99.46 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:55:08 PM PDT 24
Peak memory 751768 kb
Host smart-7a2b6850-abd1-4de1-b71e-b2bf4c17dc2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086737153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2086737153
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.4242643099
Short name T501
Test name
Test status
Simulation time 441750390 ps
CPU time 2.71 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:53:31 PM PDT 24
Peak memory 204156 kb
Host smart-151916b6-bf0c-4bcd-998b-a0ebc11e2089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242643099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.4242643099
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1516519147
Short name T706
Test name
Test status
Simulation time 12545816644 ps
CPU time 5.68 seconds
Started Mar 24 02:53:29 PM PDT 24
Finished Mar 24 02:53:35 PM PDT 24
Peak memory 217504 kb
Host smart-e27c421f-c0e8-4988-adad-d7823f2381ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516519147 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1516519147
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.3390014989
Short name T722
Test name
Test status
Simulation time 7516494606 ps
CPU time 6.19 seconds
Started Mar 24 02:53:28 PM PDT 24
Finished Mar 24 02:53:34 PM PDT 24
Peak memory 204240 kb
Host smart-6b28c6ba-5741-402a-bd11-8490c5550540
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390014989 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3390014989
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.4135195392
Short name T536
Test name
Test status
Simulation time 1033504124 ps
CPU time 14.63 seconds
Started Mar 24 02:53:28 PM PDT 24
Finished Mar 24 02:53:43 PM PDT 24
Peak memory 204112 kb
Host smart-e44f9164-abfb-414f-8672-159fac70c3cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135195392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.4135195392
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.3786331860
Short name T912
Test name
Test status
Simulation time 722225577 ps
CPU time 11.47 seconds
Started Mar 24 02:53:21 PM PDT 24
Finished Mar 24 02:53:34 PM PDT 24
Peak memory 208620 kb
Host smart-2cefd2b8-0b88-4fe5-ac61-238c1ee3c9f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786331860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.3786331860
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.1560751547
Short name T761
Test name
Test status
Simulation time 36520716874 ps
CPU time 327.81 seconds
Started Mar 24 02:53:22 PM PDT 24
Finished Mar 24 02:58:51 PM PDT 24
Peak memory 2107696 kb
Host smart-0ae9c28f-3851-47a6-8a9f-3a1a74d17f71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560751547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.1560751547
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3762268744
Short name T1023
Test name
Test status
Simulation time 1539963591 ps
CPU time 8 seconds
Started Mar 24 02:53:27 PM PDT 24
Finished Mar 24 02:53:35 PM PDT 24
Peak memory 220392 kb
Host smart-52827438-fa31-4fce-9e2b-603a0af875bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762268744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3762268744
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1142253683
Short name T331
Test name
Test status
Simulation time 47453295 ps
CPU time 0.62 seconds
Started Mar 24 02:53:38 PM PDT 24
Finished Mar 24 02:53:39 PM PDT 24
Peak memory 203864 kb
Host smart-dc7af385-2dde-4613-b8f2-ad32a8250f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142253683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1142253683
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.231977540
Short name T46
Test name
Test status
Simulation time 40187677 ps
CPU time 1.93 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:53:35 PM PDT 24
Peak memory 212392 kb
Host smart-a1434773-6735-4e25-b1f1-788ae4b5c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231977540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.231977540
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2037594110
Short name T1019
Test name
Test status
Simulation time 584094486 ps
CPU time 6.63 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:53:40 PM PDT 24
Peak memory 263952 kb
Host smart-469a5f37-ffe5-4834-8ca9-1f437d9da432
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037594110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2037594110
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3225848206
Short name T959
Test name
Test status
Simulation time 10128030808 ps
CPU time 173.59 seconds
Started Mar 24 02:53:33 PM PDT 24
Finished Mar 24 02:56:27 PM PDT 24
Peak memory 760280 kb
Host smart-084e7e66-3305-4557-be30-63a9403f91cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225848206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3225848206
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3153737347
Short name T1
Test name
Test status
Simulation time 1317072197 ps
CPU time 34.38 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:54:06 PM PDT 24
Peak memory 373016 kb
Host smart-76e7bf06-28de-4a41-b58f-b0c8e1da49bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153737347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3153737347
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3731641518
Short name T1020
Test name
Test status
Simulation time 120903636 ps
CPU time 1.08 seconds
Started Mar 24 02:53:31 PM PDT 24
Finished Mar 24 02:53:33 PM PDT 24
Peak memory 204204 kb
Host smart-49d85e76-c2be-47d3-9753-ccc2ecc38a54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731641518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3731641518
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.708815592
Short name T740
Test name
Test status
Simulation time 134241171 ps
CPU time 7.1 seconds
Started Mar 24 02:53:33 PM PDT 24
Finished Mar 24 02:53:41 PM PDT 24
Peak memory 204436 kb
Host smart-b46ac3d2-9842-4384-8f5e-4a7f49c521cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708815592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
708815592
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.504106968
Short name T813
Test name
Test status
Simulation time 3215031539 ps
CPU time 216.94 seconds
Started Mar 24 02:53:30 PM PDT 24
Finished Mar 24 02:57:08 PM PDT 24
Peak memory 971844 kb
Host smart-0e4d5824-654e-48b0-bfda-10d4ff18e4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504106968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.504106968
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_override.748152470
Short name T174
Test name
Test status
Simulation time 46233984 ps
CPU time 0.65 seconds
Started Mar 24 02:53:30 PM PDT 24
Finished Mar 24 02:53:31 PM PDT 24
Peak memory 203844 kb
Host smart-71d37ec6-1c22-42fb-9019-fff1b63c57a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748152470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.748152470
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1094429876
Short name T338
Test name
Test status
Simulation time 6123076232 ps
CPU time 118.16 seconds
Started Mar 24 02:53:33 PM PDT 24
Finished Mar 24 02:55:32 PM PDT 24
Peak memory 222568 kb
Host smart-de97ffb4-45ef-44f7-b27b-2f70563a17fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094429876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1094429876
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2497613680
Short name T28
Test name
Test status
Simulation time 1495297105 ps
CPU time 55.83 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:54:28 PM PDT 24
Peak memory 268716 kb
Host smart-1a5502e1-12eb-47f5-865a-e45f737c0422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497613680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2497613680
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2951767889
Short name T1038
Test name
Test status
Simulation time 1884829859 ps
CPU time 4.52 seconds
Started Mar 24 02:53:36 PM PDT 24
Finished Mar 24 02:53:41 PM PDT 24
Peak memory 212432 kb
Host smart-e62d599a-59c7-4859-86cc-88071df1d0e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951767889 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2951767889
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1501959655
Short name T950
Test name
Test status
Simulation time 10059726782 ps
CPU time 33.49 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:54:06 PM PDT 24
Peak memory 426948 kb
Host smart-de49a1d4-aa16-466c-a268-32122a5d4ca5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501959655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1501959655
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3256425772
Short name T422
Test name
Test status
Simulation time 10173234544 ps
CPU time 14.89 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:53:47 PM PDT 24
Peak memory 322400 kb
Host smart-4f598c98-16c4-44d0-b00b-2b2980095ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256425772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3256425772
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.495545561
Short name T5
Test name
Test status
Simulation time 321016198 ps
CPU time 2.3 seconds
Started Mar 24 02:53:40 PM PDT 24
Finished Mar 24 02:53:42 PM PDT 24
Peak memory 204172 kb
Host smart-90cc5b87-8166-4e0b-a578-76a38c2925d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495545561 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.495545561
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.112136233
Short name T404
Test name
Test status
Simulation time 760176471 ps
CPU time 4.07 seconds
Started Mar 24 02:53:31 PM PDT 24
Finished Mar 24 02:53:35 PM PDT 24
Peak memory 206032 kb
Host smart-07ed3d86-2b22-4036-b1ee-e4fca7d1499e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112136233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.112136233
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1686783269
Short name T434
Test name
Test status
Simulation time 3717239635 ps
CPU time 14.31 seconds
Started Mar 24 02:53:34 PM PDT 24
Finished Mar 24 02:53:49 PM PDT 24
Peak memory 204148 kb
Host smart-92ff66c1-57a5-48a7-985c-bcfed9cc58da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686783269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1686783269
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3538994745
Short name T50
Test name
Test status
Simulation time 2243809095 ps
CPU time 6.01 seconds
Started Mar 24 02:53:37 PM PDT 24
Finished Mar 24 02:53:43 PM PDT 24
Peak memory 204252 kb
Host smart-0ea290c5-0a88-4045-90ab-b1bde937059c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538994745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3538994745
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2153820068
Short name T782
Test name
Test status
Simulation time 22175638663 ps
CPU time 8.21 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:53:40 PM PDT 24
Peak memory 204244 kb
Host smart-24a9464a-66a0-4dab-9aec-e3b1b5299ef6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153820068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2153820068
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3965835585
Short name T430
Test name
Test status
Simulation time 39857152153 ps
CPU time 355.77 seconds
Started Mar 24 02:53:31 PM PDT 24
Finished Mar 24 02:59:27 PM PDT 24
Peak memory 2310888 kb
Host smart-17f647d6-7bd3-4779-9ae2-f30d9320c9a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965835585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3965835585
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1777691618
Short name T440
Test name
Test status
Simulation time 1639279200 ps
CPU time 7.67 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:53:41 PM PDT 24
Peak memory 212384 kb
Host smart-81f72b1b-1e9f-4c66-867e-1d4fe2636e36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777691618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1777691618
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.2332919111
Short name T423
Test name
Test status
Simulation time 2905726670 ps
CPU time 5.5 seconds
Started Mar 24 02:53:32 PM PDT 24
Finished Mar 24 02:53:38 PM PDT 24
Peak memory 204236 kb
Host smart-7b256bbd-0755-47ac-a81a-3de83730fcff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332919111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.2332919111
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3808581931
Short name T1006
Test name
Test status
Simulation time 41805711 ps
CPU time 0.61 seconds
Started Mar 24 02:53:42 PM PDT 24
Finished Mar 24 02:53:42 PM PDT 24
Peak memory 203948 kb
Host smart-bf62720d-4c8e-4a0d-a11b-a22b8e9ef107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808581931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3808581931
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.355230509
Short name T602
Test name
Test status
Simulation time 54213698 ps
CPU time 1.59 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 02:53:45 PM PDT 24
Peak memory 212396 kb
Host smart-4f0fac6d-41bd-4f49-beb6-098a8912d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355230509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.355230509
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3583459738
Short name T779
Test name
Test status
Simulation time 1155012691 ps
CPU time 14.7 seconds
Started Mar 24 02:53:35 PM PDT 24
Finished Mar 24 02:53:50 PM PDT 24
Peak memory 252404 kb
Host smart-51ace832-28aa-4dbb-8dca-453894d37a12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583459738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3583459738
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2586960492
Short name T387
Test name
Test status
Simulation time 7492066091 ps
CPU time 55.73 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 02:54:39 PM PDT 24
Peak memory 653388 kb
Host smart-a6e81d7c-3d82-419f-b52c-d1337a6fdb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586960492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2586960492
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1952100827
Short name T583
Test name
Test status
Simulation time 3969966700 ps
CPU time 70.09 seconds
Started Mar 24 02:53:35 PM PDT 24
Finished Mar 24 02:54:46 PM PDT 24
Peak memory 699496 kb
Host smart-3dbf3403-98df-4cb8-b23a-349ddd33172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952100827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1952100827
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3776160640
Short name T449
Test name
Test status
Simulation time 116314211 ps
CPU time 6.63 seconds
Started Mar 24 02:53:42 PM PDT 24
Finished Mar 24 02:53:49 PM PDT 24
Peak memory 222732 kb
Host smart-bc736417-aea1-4427-9792-2deef77f833d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776160640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3776160640
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.4026298963
Short name T154
Test name
Test status
Simulation time 11091542372 ps
CPU time 67.43 seconds
Started Mar 24 02:53:37 PM PDT 24
Finished Mar 24 02:54:45 PM PDT 24
Peak memory 868092 kb
Host smart-46a74ccc-7c62-40db-aea4-2f5e0ae84324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026298963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.4026298963
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_override.3896983234
Short name T768
Test name
Test status
Simulation time 31440805 ps
CPU time 0.65 seconds
Started Mar 24 02:53:38 PM PDT 24
Finished Mar 24 02:53:39 PM PDT 24
Peak memory 203820 kb
Host smart-cda6dff0-32ed-4f2b-9d92-69c209790a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896983234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3896983234
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.4245501180
Short name T472
Test name
Test status
Simulation time 18042479757 ps
CPU time 2403.61 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 03:33:47 PM PDT 24
Peak memory 693540 kb
Host smart-18cd420c-a652-459f-94b1-b2a49354f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245501180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.4245501180
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1526935226
Short name T385
Test name
Test status
Simulation time 1646150735 ps
CPU time 136.68 seconds
Started Mar 24 02:53:36 PM PDT 24
Finished Mar 24 02:55:53 PM PDT 24
Peak memory 313580 kb
Host smart-a5e125f1-6646-4879-9781-7a388ad45986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526935226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1526935226
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1059456101
Short name T833
Test name
Test status
Simulation time 1274568808 ps
CPU time 3.39 seconds
Started Mar 24 02:53:42 PM PDT 24
Finished Mar 24 02:53:46 PM PDT 24
Peak memory 204176 kb
Host smart-633e6044-6c63-4df7-bd01-d9119af64861
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059456101 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1059456101
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.926141693
Short name T230
Test name
Test status
Simulation time 10221181990 ps
CPU time 8.35 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 02:53:52 PM PDT 24
Peak memory 236628 kb
Host smart-cfe6dbc6-8bbe-4248-be0d-54fbc0c09618
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926141693 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_acq.926141693
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3736013117
Short name T466
Test name
Test status
Simulation time 10154684078 ps
CPU time 15.19 seconds
Started Mar 24 02:53:48 PM PDT 24
Finished Mar 24 02:54:04 PM PDT 24
Peak memory 325980 kb
Host smart-9bdc3da1-6305-462d-90be-390091161eb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736013117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3736013117
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1901846902
Short name T1075
Test name
Test status
Simulation time 5491970716 ps
CPU time 2.66 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 02:53:46 PM PDT 24
Peak memory 204156 kb
Host smart-01fc6385-42f4-40ce-8248-d71e6f8f999b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901846902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1901846902
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1837637415
Short name T1064
Test name
Test status
Simulation time 1144517170 ps
CPU time 5.61 seconds
Started Mar 24 02:53:42 PM PDT 24
Finished Mar 24 02:53:48 PM PDT 24
Peak memory 207240 kb
Host smart-8128af19-10d1-44a3-998c-3cb2ec4a69be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837637415 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1837637415
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2492298683
Short name T446
Test name
Test status
Simulation time 1091375328 ps
CPU time 43.64 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 02:54:27 PM PDT 24
Peak memory 204180 kb
Host smart-490dc914-2020-48bd-8e25-ebc0ab49ca32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492298683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2492298683
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3203961097
Short name T992
Test name
Test status
Simulation time 3750341956 ps
CPU time 19.03 seconds
Started Mar 24 02:53:42 PM PDT 24
Finished Mar 24 02:54:01 PM PDT 24
Peak memory 214344 kb
Host smart-91c60bfa-595a-42c5-83ed-b6765aad87af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203961097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3203961097
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1165603434
Short name T307
Test name
Test status
Simulation time 20660576589 ps
CPU time 972.68 seconds
Started Mar 24 02:53:48 PM PDT 24
Finished Mar 24 03:10:02 PM PDT 24
Peak memory 4022016 kb
Host smart-a5ba2886-8500-4440-aa93-92582de9a773
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165603434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1165603434
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2581739943
Short name T304
Test name
Test status
Simulation time 1521671209 ps
CPU time 7.5 seconds
Started Mar 24 02:53:43 PM PDT 24
Finished Mar 24 02:53:50 PM PDT 24
Peak memory 217560 kb
Host smart-190f087e-3e96-419c-8ca6-b07f1fc0f720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581739943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2581739943
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.447123385
Short name T960
Test name
Test status
Simulation time 14982375 ps
CPU time 0.63 seconds
Started Mar 24 02:48:55 PM PDT 24
Finished Mar 24 02:48:56 PM PDT 24
Peak memory 203944 kb
Host smart-aba08f14-35c9-4b83-90aa-3c40bb7b9b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447123385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.447123385
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3687940944
Short name T277
Test name
Test status
Simulation time 24391821 ps
CPU time 1.07 seconds
Started Mar 24 02:48:50 PM PDT 24
Finished Mar 24 02:48:51 PM PDT 24
Peak memory 212412 kb
Host smart-8b12ae7e-28f6-47ad-9dff-627b1fd07613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687940944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3687940944
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2088237195
Short name T352
Test name
Test status
Simulation time 862584537 ps
CPU time 24.6 seconds
Started Mar 24 02:48:49 PM PDT 24
Finished Mar 24 02:49:14 PM PDT 24
Peak memory 306776 kb
Host smart-0f3282c7-7083-420a-83b2-d1ef577f5413
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088237195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2088237195
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3014637693
Short name T508
Test name
Test status
Simulation time 8678944366 ps
CPU time 54.67 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:49:52 PM PDT 24
Peak memory 594556 kb
Host smart-0cf8409a-1840-49ec-937e-2ab1ee897290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014637693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3014637693
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.658452301
Short name T764
Test name
Test status
Simulation time 2213131407 ps
CPU time 72.89 seconds
Started Mar 24 02:48:56 PM PDT 24
Finished Mar 24 02:50:09 PM PDT 24
Peak memory 479176 kb
Host smart-a4969723-03f9-410c-aa34-c53dafa9530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658452301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.658452301
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1261116734
Short name T739
Test name
Test status
Simulation time 1619449689 ps
CPU time 1.08 seconds
Started Mar 24 02:48:52 PM PDT 24
Finished Mar 24 02:48:53 PM PDT 24
Peak memory 204152 kb
Host smart-82b6d0d0-481c-4ad2-939c-b8e63067ed39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261116734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1261116734
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3815997285
Short name T870
Test name
Test status
Simulation time 526924181 ps
CPU time 4 seconds
Started Mar 24 02:48:56 PM PDT 24
Finished Mar 24 02:49:00 PM PDT 24
Peak memory 226492 kb
Host smart-8aa46878-0027-4b29-9aec-47f080171a10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815997285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3815997285
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1457558497
Short name T1106
Test name
Test status
Simulation time 11983160356 ps
CPU time 85.85 seconds
Started Mar 24 02:48:54 PM PDT 24
Finished Mar 24 02:50:20 PM PDT 24
Peak memory 920676 kb
Host smart-1cc9f573-6eef-4f69-bc14-4b549ee33e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457558497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1457558497
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_override.4267620036
Short name T55
Test name
Test status
Simulation time 15662615 ps
CPU time 0.65 seconds
Started Mar 24 02:48:50 PM PDT 24
Finished Mar 24 02:48:51 PM PDT 24
Peak memory 203828 kb
Host smart-5ec1126a-2720-4565-8cbb-40da356406e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267620036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.4267620036
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.953601501
Short name T1092
Test name
Test status
Simulation time 6937107674 ps
CPU time 1069.99 seconds
Started Mar 24 02:48:50 PM PDT 24
Finished Mar 24 03:06:40 PM PDT 24
Peak memory 633128 kb
Host smart-a760611c-f7de-4a6e-b443-927616331648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953601501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.953601501
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3077939900
Short name T828
Test name
Test status
Simulation time 3653581433 ps
CPU time 98.46 seconds
Started Mar 24 02:48:51 PM PDT 24
Finished Mar 24 02:50:30 PM PDT 24
Peak memory 402080 kb
Host smart-a0357898-57ab-49d7-b132-93bf3901c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077939900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3077939900
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2710758183
Short name T1086
Test name
Test status
Simulation time 1531058024 ps
CPU time 3.81 seconds
Started Mar 24 02:48:52 PM PDT 24
Finished Mar 24 02:48:56 PM PDT 24
Peak memory 213740 kb
Host smart-87ba2ca2-261f-4225-bfcb-1b30021612e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710758183 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2710758183
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.822600313
Short name T228
Test name
Test status
Simulation time 10110580502 ps
CPU time 35.32 seconds
Started Mar 24 02:48:51 PM PDT 24
Finished Mar 24 02:49:27 PM PDT 24
Peak memory 400360 kb
Host smart-2e05d55a-7f40-4f43-a12c-de302210dae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822600313 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.822600313
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.456692504
Short name T639
Test name
Test status
Simulation time 10157407134 ps
CPU time 32.2 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:49:29 PM PDT 24
Peak memory 418532 kb
Host smart-f058fffb-a075-4ac1-a00b-98b0420d36b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456692504 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.456692504
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.282430832
Short name T922
Test name
Test status
Simulation time 1002273868 ps
CPU time 2.79 seconds
Started Mar 24 02:48:50 PM PDT 24
Finished Mar 24 02:48:52 PM PDT 24
Peak memory 204088 kb
Host smart-b9cdad5d-bf27-49d0-991f-7f6d06b96c1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282430832 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.282430832
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.3217888080
Short name T786
Test name
Test status
Simulation time 1199596071 ps
CPU time 6 seconds
Started Mar 24 02:48:52 PM PDT 24
Finished Mar 24 02:48:58 PM PDT 24
Peak memory 204216 kb
Host smart-e407c79d-0542-4c4b-ad2a-bb7505c374c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217888080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.3217888080
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3462938023
Short name T547
Test name
Test status
Simulation time 3487710216 ps
CPU time 12.26 seconds
Started Mar 24 02:48:55 PM PDT 24
Finished Mar 24 02:49:07 PM PDT 24
Peak memory 204248 kb
Host smart-29767906-b120-4eed-891a-a5bd09e7f4b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462938023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3462938023
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2192451157
Short name T182
Test name
Test status
Simulation time 10435444877 ps
CPU time 26.97 seconds
Started Mar 24 02:48:50 PM PDT 24
Finished Mar 24 02:49:17 PM PDT 24
Peak memory 221260 kb
Host smart-28d057a9-bfec-44e0-a9b6-b3274b6d8a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192451157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2192451157
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2641554803
Short name T281
Test name
Test status
Simulation time 23886965679 ps
CPU time 743.62 seconds
Started Mar 24 02:48:50 PM PDT 24
Finished Mar 24 03:01:14 PM PDT 24
Peak memory 3447216 kb
Host smart-d3cc420d-c335-4ccf-9616-4cecf9bde29a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641554803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2641554803
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1528026991
Short name T1099
Test name
Test status
Simulation time 2798459529 ps
CPU time 6.9 seconds
Started Mar 24 02:48:51 PM PDT 24
Finished Mar 24 02:48:58 PM PDT 24
Peak memory 212472 kb
Host smart-4ec946fe-6319-44e9-849a-aa79d1b267b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528026991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1528026991
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_unexp_stop.2205520416
Short name T48
Test name
Test status
Simulation time 2764514885 ps
CPU time 7.04 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:49:04 PM PDT 24
Peak memory 220420 kb
Host smart-f4143fa8-fb19-42f2-aab7-687ffa4209e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205520416 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.i2c_target_unexp_stop.2205520416
Directory /workspace/5.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3201129108
Short name T361
Test name
Test status
Simulation time 18244563 ps
CPU time 0.63 seconds
Started Mar 24 02:49:05 PM PDT 24
Finished Mar 24 02:49:06 PM PDT 24
Peak memory 203872 kb
Host smart-55e434fc-f504-474f-9394-cecac056dcb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201129108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3201129108
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3839361961
Short name T654
Test name
Test status
Simulation time 59472559 ps
CPU time 1.47 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:48:58 PM PDT 24
Peak memory 212492 kb
Host smart-26c91c41-a0cd-4b96-94ab-35edcc767ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839361961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3839361961
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.267704062
Short name T439
Test name
Test status
Simulation time 804046653 ps
CPU time 7.32 seconds
Started Mar 24 02:48:58 PM PDT 24
Finished Mar 24 02:49:05 PM PDT 24
Peak memory 268060 kb
Host smart-5e1105ec-cd52-4107-8994-a5dba3e2b8a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267704062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.267704062
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2922265625
Short name T29
Test name
Test status
Simulation time 5965477835 ps
CPU time 55.26 seconds
Started Mar 24 02:48:58 PM PDT 24
Finished Mar 24 02:49:53 PM PDT 24
Peak memory 606472 kb
Host smart-39fff279-c381-4138-8083-32d137ee65b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922265625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2922265625
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.426747410
Short name T876
Test name
Test status
Simulation time 155574159 ps
CPU time 1.15 seconds
Started Mar 24 02:48:55 PM PDT 24
Finished Mar 24 02:48:56 PM PDT 24
Peak memory 204184 kb
Host smart-9a54ebed-705b-417e-8ab2-24bfd0ad196d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426747410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.426747410
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1260185710
Short name T594
Test name
Test status
Simulation time 192573171 ps
CPU time 10.67 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:49:08 PM PDT 24
Peak memory 240776 kb
Host smart-6a9c1dd9-7c25-4a67-8878-0e12ddd61995
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260185710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1260185710
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2635530362
Short name T156
Test name
Test status
Simulation time 10469782555 ps
CPU time 122.36 seconds
Started Mar 24 02:48:54 PM PDT 24
Finished Mar 24 02:50:57 PM PDT 24
Peak memory 1299648 kb
Host smart-4d547a00-6ef3-4140-8a1a-1288d93beb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635530362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2635530362
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_override.1490742427
Short name T1022
Test name
Test status
Simulation time 33309936 ps
CPU time 0.65 seconds
Started Mar 24 02:48:57 PM PDT 24
Finished Mar 24 02:48:57 PM PDT 24
Peak memory 203840 kb
Host smart-2ad09d7d-979e-402f-9dbe-f19d73762733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490742427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1490742427
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2078612510
Short name T1097
Test name
Test status
Simulation time 3102305950 ps
CPU time 47.25 seconds
Started Mar 24 02:48:58 PM PDT 24
Finished Mar 24 02:49:45 PM PDT 24
Peak memory 332612 kb
Host smart-65f21d7d-6559-4c20-a1c9-1a09c8558521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078612510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2078612510
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3005601645
Short name T724
Test name
Test status
Simulation time 1391590213 ps
CPU time 74.87 seconds
Started Mar 24 02:48:56 PM PDT 24
Finished Mar 24 02:50:11 PM PDT 24
Peak memory 363860 kb
Host smart-175a6d0c-47f2-429f-a9cf-6012f76ef943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005601645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3005601645
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.645677277
Short name T367
Test name
Test status
Simulation time 1304673604 ps
CPU time 3.43 seconds
Started Mar 24 02:49:02 PM PDT 24
Finished Mar 24 02:49:06 PM PDT 24
Peak memory 204228 kb
Host smart-00ed69f7-892b-4196-86de-2597d37336fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645677277 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.645677277
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2293789816
Short name T527
Test name
Test status
Simulation time 10100751949 ps
CPU time 10.42 seconds
Started Mar 24 02:49:04 PM PDT 24
Finished Mar 24 02:49:14 PM PDT 24
Peak memory 256792 kb
Host smart-5180fcbe-93d3-44f0-a16d-76b3964407cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293789816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2293789816
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.323285990
Short name T347
Test name
Test status
Simulation time 10168829807 ps
CPU time 111.81 seconds
Started Mar 24 02:49:02 PM PDT 24
Finished Mar 24 02:50:53 PM PDT 24
Peak memory 740168 kb
Host smart-98204701-9d0c-470e-9f02-779c95f1e3f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323285990 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.323285990
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.549075055
Short name T189
Test name
Test status
Simulation time 1504437765 ps
CPU time 2.06 seconds
Started Mar 24 02:49:04 PM PDT 24
Finished Mar 24 02:49:06 PM PDT 24
Peak memory 204200 kb
Host smart-8e40e8af-7781-4258-93ab-ba631d18efb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549075055 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_hrst.549075055
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1384782944
Short name T890
Test name
Test status
Simulation time 2168418831 ps
CPU time 5.54 seconds
Started Mar 24 02:49:02 PM PDT 24
Finished Mar 24 02:49:07 PM PDT 24
Peak memory 212428 kb
Host smart-655172cf-8213-4a4f-a6f3-e135dd8ad0f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384782944 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1384782944
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1359670646
Short name T1077
Test name
Test status
Simulation time 2945567244 ps
CPU time 26.12 seconds
Started Mar 24 02:49:01 PM PDT 24
Finished Mar 24 02:49:28 PM PDT 24
Peak memory 220404 kb
Host smart-43a140c9-eef9-4905-9f64-72c05711c5a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359670646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1359670646
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2044768357
Short name T561
Test name
Test status
Simulation time 13978120474 ps
CPU time 8.6 seconds
Started Mar 24 02:48:58 PM PDT 24
Finished Mar 24 02:49:07 PM PDT 24
Peak memory 204180 kb
Host smart-88549254-be1f-4056-bf02-44e743ce7a4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044768357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2044768357
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2085275756
Short name T774
Test name
Test status
Simulation time 20631478183 ps
CPU time 22.83 seconds
Started Mar 24 02:49:01 PM PDT 24
Finished Mar 24 02:49:24 PM PDT 24
Peak memory 348120 kb
Host smart-ab6ba2b4-47a5-443a-b734-f3da2af4cdb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085275756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2085275756
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2464308984
Short name T288
Test name
Test status
Simulation time 1357408128 ps
CPU time 6.3 seconds
Started Mar 24 02:49:09 PM PDT 24
Finished Mar 24 02:49:15 PM PDT 24
Peak memory 209744 kb
Host smart-541d0a4e-7413-4b2b-a623-9d362e6afd77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464308984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2464308984
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.724309423
Short name T1009
Test name
Test status
Simulation time 17989021 ps
CPU time 0.62 seconds
Started Mar 24 02:49:11 PM PDT 24
Finished Mar 24 02:49:12 PM PDT 24
Peak memory 203952 kb
Host smart-769d4249-35f8-455c-a6fe-3aac73bbd4a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724309423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.724309423
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.684934064
Short name T715
Test name
Test status
Simulation time 87934322 ps
CPU time 1.32 seconds
Started Mar 24 02:49:03 PM PDT 24
Finished Mar 24 02:49:05 PM PDT 24
Peak memory 204172 kb
Host smart-53f18fe6-7fcc-4549-914e-e0350c1460e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684934064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.684934064
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3143336309
Short name T718
Test name
Test status
Simulation time 449707609 ps
CPU time 7.03 seconds
Started Mar 24 02:49:02 PM PDT 24
Finished Mar 24 02:49:09 PM PDT 24
Peak memory 226884 kb
Host smart-df26e040-6602-4b7c-b943-3717ac4030dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143336309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3143336309
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.391911103
Short name T940
Test name
Test status
Simulation time 1119272913 ps
CPU time 29.64 seconds
Started Mar 24 02:49:04 PM PDT 24
Finished Mar 24 02:49:34 PM PDT 24
Peak memory 318776 kb
Host smart-951f4509-1b9c-4074-a6cb-92d507eaf3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391911103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.391911103
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3509588083
Short name T84
Test name
Test status
Simulation time 2549216131 ps
CPU time 104.48 seconds
Started Mar 24 02:49:02 PM PDT 24
Finished Mar 24 02:50:47 PM PDT 24
Peak memory 555700 kb
Host smart-f8a33818-7980-48bf-b645-3b3bdb10785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509588083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3509588083
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.3217883723
Short name T1015
Test name
Test status
Simulation time 257632765 ps
CPU time 1.04 seconds
Started Mar 24 02:49:02 PM PDT 24
Finished Mar 24 02:49:03 PM PDT 24
Peak memory 203952 kb
Host smart-921d0720-d6f8-457b-b18a-9354d6d81607
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217883723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.3217883723
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1606964825
Short name T743
Test name
Test status
Simulation time 99730321 ps
CPU time 5.62 seconds
Started Mar 24 02:49:03 PM PDT 24
Finished Mar 24 02:49:09 PM PDT 24
Peak memory 217888 kb
Host smart-d8dae4a5-ec10-433f-b479-5d958b5c2058
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606964825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1606964825
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_override.360597948
Short name T500
Test name
Test status
Simulation time 23118119 ps
CPU time 0.65 seconds
Started Mar 24 02:49:02 PM PDT 24
Finished Mar 24 02:49:03 PM PDT 24
Peak memory 203828 kb
Host smart-b6e55dcc-8bbc-457c-ab24-cb06c5d5b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360597948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.360597948
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3896770618
Short name T37
Test name
Test status
Simulation time 30580499950 ps
CPU time 1465.76 seconds
Started Mar 24 02:49:01 PM PDT 24
Finished Mar 24 03:13:27 PM PDT 24
Peak memory 1126408 kb
Host smart-e8bcc766-4884-4f7c-8a91-62ff552eb0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896770618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3896770618
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1191897620
Short name T852
Test name
Test status
Simulation time 5189610051 ps
CPU time 81.64 seconds
Started Mar 24 02:49:01 PM PDT 24
Finished Mar 24 02:50:23 PM PDT 24
Peak memory 265924 kb
Host smart-a8f67186-7d5c-4e07-9a2d-8a2da02600dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191897620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1191897620
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3751092231
Short name T983
Test name
Test status
Simulation time 996311254 ps
CPU time 5.03 seconds
Started Mar 24 02:49:11 PM PDT 24
Finished Mar 24 02:49:16 PM PDT 24
Peak memory 204168 kb
Host smart-27dd8e38-6ec2-4476-938a-b8a1b4b68ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751092231 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3751092231
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.4116800768
Short name T485
Test name
Test status
Simulation time 10183735892 ps
CPU time 17.14 seconds
Started Mar 24 02:49:11 PM PDT 24
Finished Mar 24 02:49:28 PM PDT 24
Peak memory 300440 kb
Host smart-983faab0-2804-4162-aaa3-ab561fa9b5fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116800768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.4116800768
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1623363428
Short name T373
Test name
Test status
Simulation time 10039078225 ps
CPU time 88.98 seconds
Started Mar 24 02:49:10 PM PDT 24
Finished Mar 24 02:50:39 PM PDT 24
Peak memory 712200 kb
Host smart-893a1a0a-dfcd-4a2a-aaec-8a579f355496
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623363428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1623363428
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2750160548
Short name T569
Test name
Test status
Simulation time 1063595197 ps
CPU time 3.03 seconds
Started Mar 24 02:49:09 PM PDT 24
Finished Mar 24 02:49:12 PM PDT 24
Peak memory 204188 kb
Host smart-273837f0-e04f-4c80-9883-01a86061a096
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750160548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2750160548
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1941335226
Short name T760
Test name
Test status
Simulation time 5805061038 ps
CPU time 8.77 seconds
Started Mar 24 02:49:10 PM PDT 24
Finished Mar 24 02:49:19 PM PDT 24
Peak memory 221548 kb
Host smart-d9428fc1-6b66-47a5-b4af-b2b12966927f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941335226 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1941335226
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3403438383
Short name T611
Test name
Test status
Simulation time 4575543047 ps
CPU time 3.79 seconds
Started Mar 24 02:49:09 PM PDT 24
Finished Mar 24 02:49:13 PM PDT 24
Peak memory 204404 kb
Host smart-6aadb118-0eab-4e73-8706-713c4970921a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403438383 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3403438383
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1035706655
Short name T354
Test name
Test status
Simulation time 5344885282 ps
CPU time 21.11 seconds
Started Mar 24 02:49:03 PM PDT 24
Finished Mar 24 02:49:24 PM PDT 24
Peak memory 204244 kb
Host smart-fc78d450-786a-466b-9a40-52189b9bfa1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035706655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1035706655
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2731744754
Short name T621
Test name
Test status
Simulation time 2061669667 ps
CPU time 30.05 seconds
Started Mar 24 02:49:08 PM PDT 24
Finished Mar 24 02:49:38 PM PDT 24
Peak memory 225380 kb
Host smart-be7d771e-3369-4e9f-8afb-b887f50292b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731744754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2731744754
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2941305744
Short name T704
Test name
Test status
Simulation time 22794521707 ps
CPU time 1414.61 seconds
Started Mar 24 02:49:09 PM PDT 24
Finished Mar 24 03:12:44 PM PDT 24
Peak memory 2838892 kb
Host smart-1e41585f-44e3-4fd8-b0d2-5506576a4ec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941305744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2941305744
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.4131806182
Short name T425
Test name
Test status
Simulation time 1091681603 ps
CPU time 5.84 seconds
Started Mar 24 02:49:07 PM PDT 24
Finished Mar 24 02:49:13 PM PDT 24
Peak memory 212384 kb
Host smart-02829870-6981-49df-97a1-972da033c2ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131806182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.4131806182
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3207563232
Short name T553
Test name
Test status
Simulation time 23241132 ps
CPU time 0.69 seconds
Started Mar 24 02:49:18 PM PDT 24
Finished Mar 24 02:49:19 PM PDT 24
Peak memory 203960 kb
Host smart-4131769f-a65c-42c7-8cca-4fc5e935b2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207563232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3207563232
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.4230917400
Short name T438
Test name
Test status
Simulation time 66767070 ps
CPU time 1.32 seconds
Started Mar 24 02:49:15 PM PDT 24
Finished Mar 24 02:49:17 PM PDT 24
Peak memory 220508 kb
Host smart-8a01ebbf-7135-4de3-b90e-6b684ae4561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230917400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.4230917400
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1971797785
Short name T907
Test name
Test status
Simulation time 248149283 ps
CPU time 5.56 seconds
Started Mar 24 02:49:13 PM PDT 24
Finished Mar 24 02:49:19 PM PDT 24
Peak memory 252904 kb
Host smart-d021b1db-7b7b-44c1-9b2e-6987b0d375f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971797785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1971797785
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2565826967
Short name T1109
Test name
Test status
Simulation time 7372049186 ps
CPU time 67.19 seconds
Started Mar 24 02:49:14 PM PDT 24
Finished Mar 24 02:50:22 PM PDT 24
Peak memory 701872 kb
Host smart-288b35e8-7a1e-4a5b-8456-a6b80128a51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565826967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2565826967
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2718823020
Short name T495
Test name
Test status
Simulation time 4870002498 ps
CPU time 32.48 seconds
Started Mar 24 02:49:15 PM PDT 24
Finished Mar 24 02:49:48 PM PDT 24
Peak memory 380908 kb
Host smart-de0a02cd-e121-4bdd-bdbb-04dcff25848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718823020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2718823020
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3713487497
Short name T977
Test name
Test status
Simulation time 277414138 ps
CPU time 1.01 seconds
Started Mar 24 02:49:16 PM PDT 24
Finished Mar 24 02:49:17 PM PDT 24
Peak memory 203944 kb
Host smart-2b337194-53ba-433b-8764-2903801084b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713487497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3713487497
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3204073751
Short name T839
Test name
Test status
Simulation time 366894227 ps
CPU time 4.77 seconds
Started Mar 24 02:49:14 PM PDT 24
Finished Mar 24 02:49:19 PM PDT 24
Peak memory 239984 kb
Host smart-f247dec4-4ed1-49f8-b777-655f08bb288d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204073751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3204073751
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1086693842
Short name T905
Test name
Test status
Simulation time 7866393527 ps
CPU time 101.12 seconds
Started Mar 24 02:49:16 PM PDT 24
Finished Mar 24 02:50:57 PM PDT 24
Peak memory 1144672 kb
Host smart-4a1288ae-f1e5-4da4-8081-afda260bdaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086693842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1086693842
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_override.1324995346
Short name T176
Test name
Test status
Simulation time 17852602 ps
CPU time 0.68 seconds
Started Mar 24 02:49:16 PM PDT 24
Finished Mar 24 02:49:17 PM PDT 24
Peak memory 203836 kb
Host smart-997fa903-4392-45fa-871a-223974464499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324995346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1324995346
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1717186275
Short name T795
Test name
Test status
Simulation time 29725732952 ps
CPU time 1491.51 seconds
Started Mar 24 02:49:16 PM PDT 24
Finished Mar 24 03:14:08 PM PDT 24
Peak memory 1071192 kb
Host smart-60fd017d-ecea-47a9-a7fe-a2a801ee27d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717186275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1717186275
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.726155040
Short name T834
Test name
Test status
Simulation time 6854779903 ps
CPU time 104.87 seconds
Started Mar 24 02:49:15 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 376220 kb
Host smart-599e6138-aaf9-4920-9c02-5bc3bf4a6ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726155040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.726155040
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3690095350
Short name T632
Test name
Test status
Simulation time 2557046197 ps
CPU time 3.78 seconds
Started Mar 24 02:49:19 PM PDT 24
Finished Mar 24 02:49:24 PM PDT 24
Peak memory 204220 kb
Host smart-610ce081-2136-4910-9b8e-9a9220bee89c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690095350 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3690095350
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2267772524
Short name T255
Test name
Test status
Simulation time 10139975974 ps
CPU time 32.73 seconds
Started Mar 24 02:49:13 PM PDT 24
Finished Mar 24 02:49:46 PM PDT 24
Peak memory 417976 kb
Host smart-bf7955b9-00e4-421d-b6b8-aad5990bf3a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267772524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2267772524
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.177800264
Short name T369
Test name
Test status
Simulation time 10144686844 ps
CPU time 35.86 seconds
Started Mar 24 02:49:14 PM PDT 24
Finished Mar 24 02:49:50 PM PDT 24
Peak memory 468728 kb
Host smart-a2e0606f-df38-4997-badc-7c550d692826
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177800264 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.177800264
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.393659442
Short name T546
Test name
Test status
Simulation time 393977296 ps
CPU time 2.34 seconds
Started Mar 24 02:49:17 PM PDT 24
Finished Mar 24 02:49:20 PM PDT 24
Peak memory 204152 kb
Host smart-963f4221-61b2-49e2-810c-81d1c7acc0da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393659442 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.393659442
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.586117724
Short name T674
Test name
Test status
Simulation time 7611755778 ps
CPU time 3.63 seconds
Started Mar 24 02:49:13 PM PDT 24
Finished Mar 24 02:49:17 PM PDT 24
Peak memory 204268 kb
Host smart-d6fb12ae-a7df-4d13-a37e-c1f0ba3f99b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586117724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.586117724
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.180747505
Short name T413
Test name
Test status
Simulation time 20346500970 ps
CPU time 39.66 seconds
Started Mar 24 02:49:14 PM PDT 24
Finished Mar 24 02:49:54 PM PDT 24
Peak memory 204120 kb
Host smart-1b43ab9a-ba59-4a2d-b064-0b5df9621e64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180747505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.180747505
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1337667345
Short name T363
Test name
Test status
Simulation time 3264885410 ps
CPU time 10.15 seconds
Started Mar 24 02:49:14 PM PDT 24
Finished Mar 24 02:49:25 PM PDT 24
Peak memory 208704 kb
Host smart-4d3c3d4b-e886-43e9-aa3f-980f860fad28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337667345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1337667345
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.489252299
Short name T2
Test name
Test status
Simulation time 9112722415 ps
CPU time 18.07 seconds
Started Mar 24 02:49:12 PM PDT 24
Finished Mar 24 02:49:30 PM PDT 24
Peak memory 204240 kb
Host smart-3e17f0c2-0bc6-4a10-aec7-3d2719f48923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489252299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.489252299
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2884185371
Short name T335
Test name
Test status
Simulation time 1511372293 ps
CPU time 7.45 seconds
Started Mar 24 02:49:14 PM PDT 24
Finished Mar 24 02:49:22 PM PDT 24
Peak memory 215748 kb
Host smart-fdfb3655-3706-4c37-92f2-f71ad8a461b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884185371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2884185371
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1694972965
Short name T709
Test name
Test status
Simulation time 17324099 ps
CPU time 0.6 seconds
Started Mar 24 02:49:25 PM PDT 24
Finished Mar 24 02:49:26 PM PDT 24
Peak memory 203932 kb
Host smart-0bc8f378-74ea-4398-8a3e-c32b347150bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694972965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1694972965
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.4290382647
Short name T671
Test name
Test status
Simulation time 40211825 ps
CPU time 1.74 seconds
Started Mar 24 02:49:17 PM PDT 24
Finished Mar 24 02:49:19 PM PDT 24
Peak memory 212412 kb
Host smart-1f19cf77-b3b5-4c9a-8115-da4f7ebb9961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290382647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.4290382647
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3275363669
Short name T850
Test name
Test status
Simulation time 1069142389 ps
CPU time 10.79 seconds
Started Mar 24 02:49:20 PM PDT 24
Finished Mar 24 02:49:32 PM PDT 24
Peak memory 282944 kb
Host smart-767b2052-ade8-45af-89d3-977eb561f096
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275363669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3275363669
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3080522789
Short name T321
Test name
Test status
Simulation time 2194756306 ps
CPU time 75.52 seconds
Started Mar 24 02:49:21 PM PDT 24
Finished Mar 24 02:50:37 PM PDT 24
Peak memory 745324 kb
Host smart-5e45f078-4f08-407d-a3bd-c838963e2226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080522789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3080522789
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2066088183
Short name T846
Test name
Test status
Simulation time 5169491329 ps
CPU time 72.8 seconds
Started Mar 24 02:49:21 PM PDT 24
Finished Mar 24 02:50:35 PM PDT 24
Peak memory 694464 kb
Host smart-76bf5ce3-ab42-4add-8095-7bb022b682c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066088183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2066088183
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3861457866
Short name T1012
Test name
Test status
Simulation time 1433735694 ps
CPU time 1.02 seconds
Started Mar 24 02:49:19 PM PDT 24
Finished Mar 24 02:49:21 PM PDT 24
Peak memory 203952 kb
Host smart-498438a7-6395-47f1-bb39-0bb96e2f0ad1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861457866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3861457866
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2636671321
Short name T552
Test name
Test status
Simulation time 256168194 ps
CPU time 7.81 seconds
Started Mar 24 02:49:22 PM PDT 24
Finished Mar 24 02:49:30 PM PDT 24
Peak memory 227344 kb
Host smart-9d236401-71d6-4c5c-a0af-3b8e4c9028ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636671321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2636671321
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3671731906
Short name T450
Test name
Test status
Simulation time 5524620754 ps
CPU time 73.67 seconds
Started Mar 24 02:49:18 PM PDT 24
Finished Mar 24 02:50:32 PM PDT 24
Peak memory 863668 kb
Host smart-315599a7-21a3-4a9c-8f8c-21c8680ac033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671731906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3671731906
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_override.1402960222
Short name T554
Test name
Test status
Simulation time 17147683 ps
CPU time 0.64 seconds
Started Mar 24 02:49:18 PM PDT 24
Finished Mar 24 02:49:19 PM PDT 24
Peak memory 203860 kb
Host smart-e6bba23d-2b36-496e-ac0c-f20a50dfa7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402960222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1402960222
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1528337617
Short name T809
Test name
Test status
Simulation time 12496611723 ps
CPU time 2804.77 seconds
Started Mar 24 02:49:23 PM PDT 24
Finished Mar 24 03:36:08 PM PDT 24
Peak memory 797328 kb
Host smart-8c70a6c1-907e-4835-a89b-6e66b9bb8d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528337617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1528337617
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3499845264
Short name T1002
Test name
Test status
Simulation time 944267042 ps
CPU time 66.28 seconds
Started Mar 24 02:49:21 PM PDT 24
Finished Mar 24 02:50:28 PM PDT 24
Peak memory 262280 kb
Host smart-374c3679-5cf6-4982-b88e-eca38b7c6e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499845264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3499845264
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2798243955
Short name T898
Test name
Test status
Simulation time 5235664446 ps
CPU time 4.18 seconds
Started Mar 24 02:49:26 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 212476 kb
Host smart-cf1db3af-3172-44e7-9c23-dcfae00abc85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798243955 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2798243955
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2306152931
Short name T810
Test name
Test status
Simulation time 10127254846 ps
CPU time 28.92 seconds
Started Mar 24 02:49:26 PM PDT 24
Finished Mar 24 02:49:55 PM PDT 24
Peak memory 365384 kb
Host smart-9af6059a-e5f9-4e92-9170-44e74ae241ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306152931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2306152931
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2688466310
Short name T315
Test name
Test status
Simulation time 10128080133 ps
CPU time 43.74 seconds
Started Mar 24 02:49:25 PM PDT 24
Finished Mar 24 02:50:09 PM PDT 24
Peak memory 477112 kb
Host smart-7a5b4d68-2311-44a9-8faf-0141952ed02d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688466310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2688466310
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2231475542
Short name T1018
Test name
Test status
Simulation time 829559175 ps
CPU time 2.55 seconds
Started Mar 24 02:49:26 PM PDT 24
Finished Mar 24 02:49:29 PM PDT 24
Peak memory 204212 kb
Host smart-33ab480c-0ea9-472e-b34d-9e1e550cb52f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231475542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2231475542
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3720912809
Short name T969
Test name
Test status
Simulation time 3966840650 ps
CPU time 5.05 seconds
Started Mar 24 02:49:23 PM PDT 24
Finished Mar 24 02:49:28 PM PDT 24
Peak memory 212316 kb
Host smart-6094e11a-71a0-442d-a33c-8940e0aa6b8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720912809 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3720912809
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1316311879
Short name T772
Test name
Test status
Simulation time 860272665 ps
CPU time 11.56 seconds
Started Mar 24 02:49:19 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 204172 kb
Host smart-27655ecd-cbba-41e8-9c6f-a797433025fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316311879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1316311879
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1570924380
Short name T1013
Test name
Test status
Simulation time 314366368 ps
CPU time 4.74 seconds
Started Mar 24 02:49:22 PM PDT 24
Finished Mar 24 02:49:28 PM PDT 24
Peak memory 204040 kb
Host smart-f8405b17-9495-4f3c-95a5-2fef9679c877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570924380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1570924380
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2091734556
Short name T987
Test name
Test status
Simulation time 5621230951 ps
CPU time 17.98 seconds
Started Mar 24 02:49:19 PM PDT 24
Finished Mar 24 02:49:38 PM PDT 24
Peak memory 337196 kb
Host smart-8ccadc1e-66ce-4c76-b06a-1d4b007e23cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091734556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2091734556
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.193577511
Short name T421
Test name
Test status
Simulation time 4746125113 ps
CPU time 5.92 seconds
Started Mar 24 02:49:18 PM PDT 24
Finished Mar 24 02:49:24 PM PDT 24
Peak memory 212428 kb
Host smart-1cd85619-300c-4c64-b75a-a84db98459a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193577511 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.193577511
Directory /workspace/9.i2c_target_timeout/latest
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