Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2540462	1			T2	4640		T3	3		T6	8
all_values[1]	2540462	1			T2	4640		T3	3		T6	8
all_values[2]	2540462	1			T2	4640		T3	3		T6	8
all_values[3]	2540462	1			T2	4640		T3	3		T6	8
all_values[4]	2540462	1			T2	4640		T3	3		T6	8
all_values[5]	2540462	1			T2	4640		T3	3		T6	8
all_values[6]	2540462	1			T2	4640		T3	3		T6	8
all_values[7]	2540462	1			T2	4640		T3	3		T6	8
all_values[8]	2540462	1			T2	4640		T3	3		T6	8
all_values[9]	2540462	1			T2	4640		T3	3		T6	8
all_values[10]	2540462	1			T2	4640		T3	3		T6	8
all_values[11]	2540462	1			T2	4640		T3	3		T6	8
all_values[12]	2540462	1			T2	4640		T3	3		T6	8
all_values[13]	2540462	1			T2	4640		T3	3		T6	8
all_values[14]	2540462	1			T2	4640		T3	3		T6	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33289088

1

T2

60325

T3

38

T6

120

auto[1]

4817842

1

T2

9275

T3

7

T7

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35654226

1

T2

69600

T3

45

T6

120

auto[1]

2452704

1

T15

109

T86

467

T63

154917

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	663195	1			T2	5		T6	8		T7	1
all_values[0]	auto[0]	auto[1]	14818	1			T15	4		T86	10		T63	542
all_values[0]	auto[1]	auto[0]	1694556	1			T2	4635		T3	3		T7	2
all_values[0]	auto[1]	auto[1]	167893	1			T15	5		T86	21		T63	10522
all_values[1]	auto[0]	auto[0]	2357088	1			T2	4640		T3	3		T6	8
all_values[1]	auto[0]	auto[1]	182538	1			T15	6		T86	25		T63	11049
all_values[1]	auto[1]	auto[0]	666	1			T35	11		T231	18		T196	14
all_values[1]	auto[1]	auto[1]	170	1			T15	2		T86	7		T63	17
all_values[2]	auto[0]	auto[0]	2428992	1			T2	4640		T3	3		T6	8
all_values[2]	auto[0]	auto[1]	111334	1			T15	6		T86	26		T63	11064
all_values[2]	auto[1]	auto[1]	136	1			T15	1		T86	4		T63	1
all_values[3]	auto[0]	auto[0]	2357757	1			T2	4640		T3	3		T6	8
all_values[3]	auto[0]	auto[1]	182554	1			T15	7		T86	25		T63	11062
all_values[3]	auto[1]	auto[1]	151	1			T15	2		T86	7		T63	4
all_values[4]	auto[0]	auto[0]	2357742	1			T2	4640		T3	3		T6	8
all_values[4]	auto[0]	auto[1]	182542	1			T15	5		T86	25		T63	11063
all_values[4]	auto[1]	auto[0]	3	1			T31	3		-	-		-	-
all_values[4]	auto[1]	auto[1]	175	1			T15	4		T86	7		T63	3
all_values[5]	auto[0]	auto[0]	2357771	1			T2	4640		T3	3		T6	8
all_values[5]	auto[0]	auto[1]	182498	1			T15	6		T86	26		T63	11062
all_values[5]	auto[1]	auto[1]	193	1			T15	2		T86	6		T63	4
all_values[6]	auto[0]	auto[0]	2365333	1			T2	4640		T3	3		T6	8
all_values[6]	auto[0]	auto[1]	171331	1			T15	4		T86	23		T114	67161
all_values[6]	auto[1]	auto[0]	3493	1			T11	1		T12	1		T37	1
all_values[6]	auto[1]	auto[1]	305	1			T15	3		T86	7		T114	50
all_values[7]	auto[0]	auto[0]	1998265	1			T2	4640		T3	3		T6	8
all_values[7]	auto[0]	auto[1]	168632	1			T86	21		T63	9427		T114	64998
all_values[7]	auto[1]	auto[0]	359504	1			T7	1		T11	1		T12	1
all_values[7]	auto[1]	auto[1]	14061	1			T86	11		T63	1639		T114	2211
all_values[8]	auto[0]	auto[0]	2325823	1			T2	4638		T3	3		T6	8
all_values[8]	auto[0]	auto[1]	179946	1			T15	7		T86	23		T63	10833
all_values[8]	auto[1]	auto[0]	31930	1			T2	2		T7	1		T11	1
all_values[8]	auto[1]	auto[1]	2763	1			T15	2		T86	9		T63	233
all_values[9]	auto[0]	auto[0]	2493682	1			T2	4637		T3	2		T6	8
all_values[9]	auto[0]	auto[1]	44012	1			T15	7		T86	23		T63	11026
all_values[9]	auto[1]	auto[0]	2474	1			T2	3		T3	1		T7	1
all_values[9]	auto[1]	auto[1]	294	1			T15	2		T86	5		T63	40
all_values[10]	auto[0]	auto[0]	2357768	1			T2	4640		T3	3		T6	8
all_values[10]	auto[0]	auto[1]	182541	1			T15	6		T86	28		T63	11064
all_values[10]	auto[1]	auto[1]	153	1			T15	1		T86	4		T63	1
all_values[11]	auto[0]	auto[0]	1795	1			T2	5		T6	8		T7	1
all_values[11]	auto[0]	auto[1]	284	1			T86	10		T63	11		T114	26
all_values[11]	auto[1]	auto[0]	2355961	1			T2	4635		T3	3		T7	2
all_values[11]	auto[1]	auto[1]	182422	1			T86	22		T63	11055		T114	67185
all_values[12]	auto[0]	auto[0]	2424927	1			T2	4640		T3	3		T6	8
all_values[12]	auto[0]	auto[1]	115371	1			T15	7		T86	27		T63	11064
all_values[12]	auto[1]	auto[1]	164	1			T15	2		T86	5		T63	1
all_values[13]	auto[0]	auto[0]	2357747	1			T2	4640		T3	3		T6	8
all_values[13]	auto[0]	auto[1]	182521	1			T15	5		T86	25		T63	11062
all_values[13]	auto[1]	auto[0]	6	1			T26	1		T126	1		T232	1
all_values[13]	auto[1]	auto[1]	188	1			T15	4		T86	7		T63	3
all_values[14]	auto[0]	auto[0]	2357748	1			T2	4640		T3	3		T6	8
all_values[14]	auto[0]	auto[1]	182533	1			T15	7		T86	27		T63	11062
all_values[14]	auto[1]	auto[1]	181	1			T15	2		T86	1		T63	3