Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 60 0 60 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 15 0 15 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 60 0 60 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 2540462 1 T2 4640 T3 3 T6 8
all_pins[1] 2540462 1 T2 4640 T3 3 T6 8
all_pins[2] 2540462 1 T2 4640 T3 3 T6 8
all_pins[3] 2540462 1 T2 4640 T3 3 T6 8
all_pins[4] 2540462 1 T2 4640 T3 3 T6 8
all_pins[5] 2540462 1 T2 4640 T3 3 T6 8
all_pins[6] 2540462 1 T2 4640 T3 3 T6 8
all_pins[7] 2540462 1 T2 4640 T3 3 T6 8
all_pins[8] 2540462 1 T2 4640 T3 3 T6 8
all_pins[9] 2540462 1 T2 4640 T3 3 T6 8
all_pins[10] 2540462 1 T2 4640 T3 3 T6 8
all_pins[11] 2540462 1 T2 4640 T3 3 T6 8
all_pins[12] 2540462 1 T2 4640 T3 3 T6 8
all_pins[13] 2540462 1 T2 4640 T3 3 T6 8
all_pins[14] 2540462 1 T2 4640 T3 3 T6 8


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 33268393 1 T2 60323 T3 38 T6 120
values[0x1] 4838537 1 T2 9277 T3 7 T7 7
transitions[0x0=>0x1] 4822519 1 T2 9277 T3 7 T7 5
transitions[0x1=>0x0] 4821700 1 T2 9276 T3 6 T7 4


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 60 0 60 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 678105 1 T2 5 T6 8 T7 1
all_pins[0] values[0x1] 1862357 1 T2 4635 T3 3 T7 2
all_pins[0] transitions[0x0=>0x1] 1861524 1 T2 4635 T3 3 T7 2
all_pins[0] transitions[0x1=>0x0] 82 1 T86 2 T63 2 T114 3
all_pins[1] values[0x0] 2539547 1 T2 4640 T3 3 T6 8
all_pins[1] values[0x1] 915 1 T35 15 T231 26 T15 1
all_pins[1] transitions[0x0=>0x1] 895 1 T35 15 T231 26 T15 1
all_pins[1] transitions[0x1=>0x0] 54 1 T86 2 T114 3 T171 3
all_pins[2] values[0x0] 2540388 1 T2 4640 T3 3 T6 8
all_pins[2] values[0x1] 74 1 T86 2 T63 1 T114 3
all_pins[2] transitions[0x0=>0x1] 58 1 T86 2 T114 3 T171 3
all_pins[2] transitions[0x1=>0x0] 52 1 T86 1 T63 2 T114 4
all_pins[3] values[0x0] 2540394 1 T2 4640 T3 3 T6 8
all_pins[3] values[0x1] 68 1 T86 1 T63 3 T114 4
all_pins[3] transitions[0x0=>0x1] 53 1 T86 1 T63 3 T114 2
all_pins[3] transitions[0x1=>0x0] 87 1 T15 2 T86 6 T63 1
all_pins[4] values[0x0] 2540360 1 T2 4640 T3 3 T6 8
all_pins[4] values[0x1] 102 1 T15 2 T86 6 T63 1
all_pins[4] transitions[0x0=>0x1] 84 1 T15 2 T86 4 T114 6
all_pins[4] transitions[0x1=>0x0] 66 1 T63 1 T114 6 T171 4
all_pins[5] values[0x0] 2540378 1 T2 4640 T3 3 T6 8
all_pins[5] values[0x1] 84 1 T86 2 T63 2 T114 6
all_pins[5] transitions[0x0=>0x1] 58 1 T86 2 T63 2 T114 5
all_pins[5] transitions[0x1=>0x0] 4173 1 T2 1 T11 1 T12 1
all_pins[6] values[0x0] 2536263 1 T2 4639 T3 3 T6 8
all_pins[6] values[0x1] 4199 1 T2 1 T11 1 T12 1
all_pins[6] transitions[0x0=>0x1] 3188 1 T2 1 T37 1 T33 24
all_pins[6] transitions[0x1=>0x0] 389073 1 T7 1 T55 1 T87 1
all_pins[7] values[0x0] 2150378 1 T2 4640 T3 3 T6 8
all_pins[7] values[0x1] 390084 1 T7 1 T11 1 T12 1
all_pins[7] transitions[0x0=>0x1] 376435 1 T33 1968 T17 1343 T82 1434
all_pins[7] transitions[0x1=>0x0] 25508 1 T2 2 T33 239 T91 1
all_pins[8] values[0x0] 2501305 1 T2 4638 T3 3 T6 8
all_pins[8] values[0x1] 39157 1 T2 2 T7 1 T11 1
all_pins[8] transitions[0x0=>0x1] 38841 1 T2 2 T33 358 T17 58
all_pins[8] transitions[0x1=>0x0] 2584 1 T2 4 T3 1 T4 1
all_pins[9] values[0x0] 2537562 1 T2 4636 T3 2 T6 8
all_pins[9] values[0x1] 2900 1 T2 4 T3 1 T7 1
all_pins[9] transitions[0x0=>0x1] 2887 1 T2 4 T3 1 T7 1
all_pins[9] transitions[0x1=>0x0] 59 1 T86 1 T114 2 T171 4
all_pins[10] values[0x0] 2540390 1 T2 4640 T3 3 T6 8
all_pins[10] values[0x1] 72 1 T86 1 T114 4 T171 5
all_pins[10] transitions[0x0=>0x1] 54 1 T114 3 T171 3 T244 2
all_pins[10] transitions[0x1=>0x0] 2538254 1 T2 4635 T3 3 T7 2
all_pins[11] values[0x0] 2190 1 T2 5 T6 8 T7 1
all_pins[11] values[0x1] 2538272 1 T2 4635 T3 3 T7 2
all_pins[11] transitions[0x0=>0x1] 2538252 1 T2 4635 T3 3 T7 2
all_pins[11] transitions[0x1=>0x0] 51 1 T86 1 T63 1 T114 2
all_pins[12] values[0x0] 2540391 1 T2 4640 T3 3 T6 8
all_pins[12] values[0x1] 71 1 T86 2 T63 1 T114 3
all_pins[12] transitions[0x0=>0x1] 50 1 T86 2 T63 1 T114 3
all_pins[12] transitions[0x1=>0x0] 83 1 T26 1 T15 4 T126 1
all_pins[13] values[0x0] 2540358 1 T2 4640 T3 3 T6 8
all_pins[13] values[0x1] 104 1 T26 1 T15 4 T126 1
all_pins[13] transitions[0x0=>0x1] 92 1 T26 1 T15 3 T126 1
all_pins[13] transitions[0x1=>0x0] 66 1 T63 1 T114 4 T171 2
all_pins[14] values[0x0] 2540384 1 T2 4640 T3 3 T6 8
all_pins[14] values[0x1] 78 1 T15 1 T63 1 T114 5
all_pins[14] transitions[0x0=>0x1] 48 1 T63 1 T114 3 T171 1
all_pins[14] transitions[0x1=>0x0] 1861508 1 T2 4634 T3 2 T7 1

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