Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	386	1			T15	4		T86	14		T63	4
all_values[1]	386	1			T15	4		T86	14		T63	4
all_values[2]	386	1			T15	4		T86	14		T63	4
all_values[3]	386	1			T15	4		T86	14		T63	4
all_values[4]	386	1			T15	4		T86	14		T63	4
all_values[5]	386	1			T15	4		T86	14		T63	4
all_values[6]	386	1			T15	4		T86	14		T63	4
all_values[7]	386	1			T15	4		T86	14		T63	4
all_values[8]	386	1			T15	4		T86	14		T63	4
all_values[9]	386	1			T15	4		T86	14		T63	4
all_values[10]	386	1			T15	4		T86	14		T63	4
all_values[11]	386	1			T15	4		T86	14		T63	4
all_values[12]	386	1			T15	4		T86	14		T63	4
all_values[13]	386	1			T15	4		T86	14		T63	4
all_values[14]	386	1			T15	4		T86	14		T63	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3141

1

T15

32

T86

88

T63

28

auto[1]

2649

1

T15

28

T86

122

T63

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T15

16

T86

13

T63

11

auto[1]

4801

1

T15

44

T86

197

T63

49

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3457

1

T15

41

T86

131

T63

37

auto[1]

2333

1

T15

19

T86

79

T63

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	42	1			T221	1		T215	1		T245	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T15	1		T86	1		T63	1
all_values[0]	auto[0]	auto[1]	auto[0]	22	1			T86	1		T63	2		T246	4
all_values[0]	auto[0]	auto[1]	auto[1]	84	1			T15	1		T86	5		T114	3
all_values[0]	auto[1]	auto[0]	auto[1]	100	1			T15	2		T86	3		T63	1
all_values[0]	auto[1]	auto[1]	auto[1]	62	1			T86	4		T114	4		T171	7
all_values[1]	auto[0]	auto[0]	auto[0]	32	1			T215	2		T247	1		T189	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T15	1		T86	5		T114	4
all_values[1]	auto[0]	auto[1]	auto[0]	33	1			T15	1		T186	2		T246	2
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T86	2		T63	1		T114	6
all_values[1]	auto[1]	auto[0]	auto[1]	72	1			T86	3		T63	1		T114	3
all_values[1]	auto[1]	auto[1]	auto[1]	82	1			T15	2		T86	4		T63	2
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T171	2		T244	1		T246	1
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T15	1		T86	3		T114	4
all_values[2]	auto[0]	auto[1]	auto[0]	36	1			T15	2		T86	2		T63	1
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T86	5		T63	2		T114	6
all_values[2]	auto[1]	auto[0]	auto[1]	74	1			T15	1		T86	3		T114	5
all_values[2]	auto[1]	auto[1]	auto[1]	62	1			T86	1		T63	1		T114	1
all_values[3]	auto[0]	auto[0]	auto[0]	36	1			T244	1		T221	1		T186	1
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T15	2		T86	4		T114	3
all_values[3]	auto[0]	auto[1]	auto[0]	29	1			T171	2		T187	1		T188	3
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T15	1		T86	4		T63	2
all_values[3]	auto[1]	auto[0]	auto[1]	92	1			T15	1		T86	3		T63	1
all_values[3]	auto[1]	auto[1]	auto[1]	65	1			T86	3		T63	1		T114	6
all_values[4]	auto[0]	auto[0]	auto[0]	38	1			T171	2		T244	4		T221	2
all_values[4]	auto[0]	auto[0]	auto[1]	75	1			T15	1		T86	1		T63	2
all_values[4]	auto[0]	auto[1]	auto[0]	20	1			T188	1		T248	1		T249	1
all_values[4]	auto[0]	auto[1]	auto[1]	94	1			T15	1		T86	7		T114	8
all_values[4]	auto[1]	auto[0]	auto[1]	81	1			T15	2		T86	1		T63	1
all_values[4]	auto[1]	auto[1]	auto[1]	78	1			T86	5		T63	1		T114	5
all_values[5]	auto[0]	auto[0]	auto[0]	45	1			T15	1		T171	2		T246	4
all_values[5]	auto[0]	auto[0]	auto[1]	79	1			T15	1		T86	4		T63	1
all_values[5]	auto[0]	auto[1]	auto[0]	34	1			T114	1		T171	1		T186	3
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T86	2		T63	1		T114	4
all_values[5]	auto[1]	auto[0]	auto[1]	92	1			T15	1		T86	5		T63	1
all_values[5]	auto[1]	auto[1]	auto[1]	65	1			T15	1		T86	3		T63	1
all_values[6]	auto[0]	auto[0]	auto[0]	48	1			T15	2		T63	2		T171	1
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T86	1		T114	5		T171	7
all_values[6]	auto[0]	auto[1]	auto[0]	28	1			T86	2		T63	2		T246	2
all_values[6]	auto[0]	auto[1]	auto[1]	94	1			T15	1		T86	6		T114	7
all_values[6]	auto[1]	auto[0]	auto[1]	71	1			T86	3		T114	2		T171	5
all_values[6]	auto[1]	auto[1]	auto[1]	67	1			T15	1		T86	2		T114	4
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T15	2		T244	3		T221	2
all_values[7]	auto[0]	auto[0]	auto[1]	94	1			T86	3		T63	1		T114	5
all_values[7]	auto[0]	auto[1]	auto[0]	34	1			T15	2		T114	2		T171	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T86	4		T114	3		T171	9
all_values[7]	auto[1]	auto[0]	auto[1]	86	1			T86	6		T63	2		T114	3
all_values[7]	auto[1]	auto[1]	auto[1]	60	1			T86	1		T63	1		T114	5
all_values[8]	auto[0]	auto[0]	auto[0]	38	1			T244	1		T215	1		T245	1
all_values[8]	auto[0]	auto[0]	auto[1]	90	1			T15	1		T86	3		T63	3
all_values[8]	auto[0]	auto[1]	auto[0]	27	1			T114	1		T171	1		T245	1
all_values[8]	auto[0]	auto[1]	auto[1]	77	1			T15	2		T86	7		T114	6
all_values[8]	auto[1]	auto[0]	auto[1]	72	1			T86	1		T114	3		T171	3
all_values[8]	auto[1]	auto[1]	auto[1]	82	1			T15	1		T86	3		T63	1
all_values[9]	auto[0]	auto[0]	auto[0]	31	1			T114	1		T171	1		T244	1
all_values[9]	auto[0]	auto[0]	auto[1]	82	1			T15	1		T86	3		T63	2
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T86	4		T114	3		T215	3
all_values[9]	auto[0]	auto[1]	auto[1]	90	1			T15	2		T86	4		T63	1
all_values[9]	auto[1]	auto[0]	auto[1]	93	1			T15	1		T114	1		T171	8
all_values[9]	auto[1]	auto[1]	auto[1]	64	1			T86	3		T63	1		T114	6
all_values[10]	auto[0]	auto[0]	auto[0]	49	1			T15	2		T63	1		T171	1
all_values[10]	auto[0]	auto[0]	auto[1]	80	1			T15	1		T86	4		T114	5
all_values[10]	auto[0]	auto[1]	auto[0]	27	1			T114	1		T221	1		T187	1
all_values[10]	auto[0]	auto[1]	auto[1]	77	1			T86	6		T63	2		T114	2
all_values[10]	auto[1]	auto[0]	auto[1]	84	1			T15	1		T86	1		T63	1
all_values[10]	auto[1]	auto[1]	auto[1]	69	1			T86	3		T114	6		T171	5
all_values[11]	auto[0]	auto[0]	auto[0]	36	1			T15	1		T171	1		T221	2
all_values[11]	auto[0]	auto[0]	auto[1]	84	1			T86	5		T63	1		T114	10
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T15	3		T246	1		T250	2
all_values[11]	auto[0]	auto[1]	auto[1]	70	1			T86	3		T63	2		T114	3
all_values[11]	auto[1]	auto[0]	auto[1]	97	1			T86	3		T63	1		T114	1
all_values[11]	auto[1]	auto[1]	auto[1]	74	1			T86	3		T114	4		T171	2
all_values[12]	auto[0]	auto[0]	auto[0]	33	1			T114	2		T171	1		T215	1
all_values[12]	auto[0]	auto[0]	auto[1]	96	1			T15	1		T86	3		T114	3
all_values[12]	auto[0]	auto[1]	auto[0]	22	1			T63	1		T114	5		T186	2
all_values[12]	auto[0]	auto[1]	auto[1]	71	1			T15	1		T86	6		T63	2
all_values[12]	auto[1]	auto[0]	auto[1]	99	1			T15	2		T86	2		T114	3
all_values[12]	auto[1]	auto[1]	auto[1]	65	1			T86	3		T63	1		T114	4
all_values[13]	auto[0]	auto[0]	auto[0]	39	1			T63	1		T244	4		T186	1
all_values[13]	auto[0]	auto[0]	auto[1]	80	1			T86	5		T114	5		T171	12
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T114	1		T186	2		T187	1
all_values[13]	auto[0]	auto[1]	auto[1]	77	1			T15	2		T86	4		T63	1
all_values[13]	auto[1]	auto[0]	auto[1]	97	1			T86	2		T63	1		T114	7
all_values[13]	auto[1]	auto[1]	auto[1]	69	1			T15	2		T86	3		T63	1
all_values[14]	auto[0]	auto[0]	auto[0]	32	1			T86	3		T63	1		T221	1
all_values[14]	auto[0]	auto[0]	auto[1]	91	1			T15	2		T86	3		T63	1
all_values[14]	auto[0]	auto[1]	auto[0]	26	1			T86	1		T114	1		T246	2
all_values[14]	auto[0]	auto[1]	auto[1]	78	1			T15	1		T86	5		T114	7
all_values[14]	auto[1]	auto[0]	auto[1]	89	1			T86	1		T63	1		T114	5
all_values[14]	auto[1]	auto[1]	auto[1]	70	1			T15	1		T86	1		T63	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal