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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.31 97.09 91.06 97.65 42.58 94.36 98.44 90.02


Total test records in report: 1206
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T1070 /workspace/coverage/default/22.i2c_target_bad_addr.3489123358 Mar 26 01:15:31 PM PDT 24 Mar 26 01:15:36 PM PDT 24 3514197700 ps
T1071 /workspace/coverage/default/12.i2c_target_fifo_reset_tx.4237784918 Mar 26 01:13:57 PM PDT 24 Mar 26 01:15:24 PM PDT 24 10039414234 ps
T1072 /workspace/coverage/default/46.i2c_target_smoke.2305383973 Mar 26 01:19:07 PM PDT 24 Mar 26 01:19:27 PM PDT 24 1171092332 ps
T1073 /workspace/coverage/default/33.i2c_host_fifo_watermark.3422629644 Mar 26 01:17:15 PM PDT 24 Mar 26 01:19:45 PM PDT 24 11656193330 ps
T1074 /workspace/coverage/default/5.i2c_target_hrst.2410754881 Mar 26 01:12:52 PM PDT 24 Mar 26 01:12:55 PM PDT 24 786792764 ps
T1075 /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2382659895 Mar 26 01:19:11 PM PDT 24 Mar 26 01:20:54 PM PDT 24 10069054505 ps
T1076 /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3419506308 Mar 26 01:12:44 PM PDT 24 Mar 26 01:14:03 PM PDT 24 10156005175 ps
T1077 /workspace/coverage/default/42.i2c_host_override.619309757 Mar 26 01:18:34 PM PDT 24 Mar 26 01:18:34 PM PDT 24 17756465 ps
T1078 /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.359771988 Mar 26 01:13:34 PM PDT 24 Mar 26 01:13:40 PM PDT 24 5704375265 ps
T1079 /workspace/coverage/default/22.i2c_target_smoke.2628125046 Mar 26 01:15:33 PM PDT 24 Mar 26 01:15:47 PM PDT 24 5056332790 ps
T1080 /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2117224925 Mar 26 01:16:14 PM PDT 24 Mar 26 01:16:18 PM PDT 24 3039472357 ps
T1081 /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1970145542 Mar 26 01:15:17 PM PDT 24 Mar 26 01:15:22 PM PDT 24 172703293 ps
T215 /workspace/coverage/default/2.i2c_host_stress_all.279562337 Mar 26 01:12:31 PM PDT 24 Mar 26 01:29:05 PM PDT 24 20371232553 ps
T1082 /workspace/coverage/default/6.i2c_target_intr_smoke.48109001 Mar 26 01:12:56 PM PDT 24 Mar 26 01:13:01 PM PDT 24 7748951763 ps
T1083 /workspace/coverage/default/44.i2c_host_override.1638493537 Mar 26 01:18:54 PM PDT 24 Mar 26 01:18:56 PM PDT 24 19901736 ps
T1084 /workspace/coverage/default/28.i2c_host_fifo_watermark.3378536775 Mar 26 01:16:25 PM PDT 24 Mar 26 01:20:35 PM PDT 24 7228290363 ps
T1085 /workspace/coverage/default/19.i2c_target_hrst.3299558911 Mar 26 01:15:03 PM PDT 24 Mar 26 01:15:06 PM PDT 24 1800913410 ps
T1086 /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2165556002 Mar 26 01:12:54 PM PDT 24 Mar 26 01:12:55 PM PDT 24 196793621 ps
T1087 /workspace/coverage/default/21.i2c_target_hrst.3035193513 Mar 26 01:15:29 PM PDT 24 Mar 26 01:15:31 PM PDT 24 675441717 ps
T1088 /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3888024007 Mar 26 01:18:34 PM PDT 24 Mar 26 01:18:35 PM PDT 24 938773346 ps
T1089 /workspace/coverage/default/16.i2c_target_bad_addr.2194706520 Mar 26 01:14:43 PM PDT 24 Mar 26 01:14:46 PM PDT 24 1656960902 ps
T1090 /workspace/coverage/default/38.i2c_host_fifo_full.2481673795 Mar 26 01:17:57 PM PDT 24 Mar 26 01:19:45 PM PDT 24 34988064591 ps
T1091 /workspace/coverage/default/25.i2c_host_fifo_overflow.3501001439 Mar 26 01:15:57 PM PDT 24 Mar 26 01:18:04 PM PDT 24 7895404200 ps
T1092 /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1461370381 Mar 26 01:13:57 PM PDT 24 Mar 26 01:13:58 PM PDT 24 324500957 ps
T1093 /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1450122643 Mar 26 01:14:00 PM PDT 24 Mar 26 01:14:07 PM PDT 24 628541929 ps
T119 /workspace/coverage/default/4.i2c_sec_cm.3547622345 Mar 26 01:12:54 PM PDT 24 Mar 26 01:12:55 PM PDT 24 37577788 ps
T1094 /workspace/coverage/default/7.i2c_host_perf.966383861 Mar 26 01:13:06 PM PDT 24 Mar 26 01:23:42 PM PDT 24 5038168707 ps
T1095 /workspace/coverage/default/25.i2c_target_timeout.1654841026 Mar 26 01:16:01 PM PDT 24 Mar 26 01:16:08 PM PDT 24 3793809258 ps
T1096 /workspace/coverage/default/32.i2c_host_fifo_watermark.3704066666 Mar 26 01:16:59 PM PDT 24 Mar 26 01:20:58 PM PDT 24 6515147912 ps
T1097 /workspace/coverage/default/11.i2c_target_timeout.4220857134 Mar 26 01:13:48 PM PDT 24 Mar 26 01:13:55 PM PDT 24 5264474398 ps
T32 /workspace/coverage/default/40.i2c_host_error_intr.3818469996 Mar 26 01:18:09 PM PDT 24 Mar 26 01:18:11 PM PDT 24 118806435 ps
T1098 /workspace/coverage/default/6.i2c_target_timeout.2687279865 Mar 26 01:12:58 PM PDT 24 Mar 26 01:13:06 PM PDT 24 1443262135 ps
T187 /workspace/coverage/default/19.i2c_host_stress_all.2998802075 Mar 26 01:15:04 PM PDT 24 Mar 26 01:38:10 PM PDT 24 56450838531 ps
T1099 /workspace/coverage/default/37.i2c_target_hrst.3004243913 Mar 26 01:17:56 PM PDT 24 Mar 26 01:17:59 PM PDT 24 583285125 ps
T1100 /workspace/coverage/default/45.i2c_target_timeout.1502083422 Mar 26 01:19:01 PM PDT 24 Mar 26 01:19:09 PM PDT 24 4248141307 ps
T1101 /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1429819981 Mar 26 01:16:37 PM PDT 24 Mar 26 01:17:13 PM PDT 24 10162745508 ps
T1102 /workspace/coverage/default/48.i2c_target_hrst.3954404272 Mar 26 01:19:32 PM PDT 24 Mar 26 01:19:35 PM PDT 24 979799938 ps
T1103 /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.4141336646 Mar 26 01:13:46 PM PDT 24 Mar 26 01:13:57 PM PDT 24 214501302 ps
T1104 /workspace/coverage/default/46.i2c_target_fifo_reset_tx.757041672 Mar 26 01:19:07 PM PDT 24 Mar 26 01:19:24 PM PDT 24 10292137455 ps
T1105 /workspace/coverage/default/4.i2c_target_stress_rd.4168535039 Mar 26 01:12:45 PM PDT 24 Mar 26 01:13:04 PM PDT 24 4502911779 ps
T1106 /workspace/coverage/default/28.i2c_target_intr_smoke.3395828257 Mar 26 01:16:27 PM PDT 24 Mar 26 01:16:32 PM PDT 24 1076986496 ps
T83 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3619573369 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 242866771 ps
T84 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4275794154 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:38 PM PDT 24 64833644 ps
T85 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3530320515 Mar 26 01:21:26 PM PDT 24 Mar 26 01:21:27 PM PDT 24 32491288 ps
T165 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3290770746 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 191769292 ps
T188 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3499775158 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:11 PM PDT 24 84648131 ps
T245 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3130455590 Mar 26 01:21:54 PM PDT 24 Mar 26 01:21:55 PM PDT 24 16971600 ps
T152 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3594511740 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:24 PM PDT 24 20425091 ps
T1107 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2654303887 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 39198949 ps
T111 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.669472792 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 102098414 ps
T166 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.400637466 Mar 26 01:21:33 PM PDT 24 Mar 26 01:21:34 PM PDT 24 70013505 ps
T247 /workspace/coverage/cover_reg_top/43.i2c_intr_test.318434949 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:05 PM PDT 24 17442139 ps
T167 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2617264161 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:38 PM PDT 24 52501686 ps
T172 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.397642683 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 42019859 ps
T189 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2409750176 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:13 PM PDT 24 21728694 ps
T112 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3289342270 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:36 PM PDT 24 900275614 ps
T113 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1608062100 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:38 PM PDT 24 187868077 ps
T250 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2086285412 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:12 PM PDT 24 26498941 ps
T129 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1825657294 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 23970475 ps
T130 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.909369263 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:36 PM PDT 24 152413951 ps
T153 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1590675870 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 18425032 ps
T133 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3838082340 Mar 26 01:21:44 PM PDT 24 Mar 26 01:21:46 PM PDT 24 52959682 ps
T134 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3611670589 Mar 26 01:21:43 PM PDT 24 Mar 26 01:21:44 PM PDT 24 43512194 ps
T150 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.728214116 Mar 26 01:21:44 PM PDT 24 Mar 26 01:21:45 PM PDT 24 34225092 ps
T131 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.272091411 Mar 26 01:21:48 PM PDT 24 Mar 26 01:21:49 PM PDT 24 45999932 ps
T168 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1869046768 Mar 26 01:21:27 PM PDT 24 Mar 26 01:21:28 PM PDT 24 24452490 ps
T151 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2329970260 Mar 26 01:22:14 PM PDT 24 Mar 26 01:22:15 PM PDT 24 283716083 ps
T135 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2715805625 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:39 PM PDT 24 32945009 ps
T146 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.595580334 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:24 PM PDT 24 72031447 ps
T190 /workspace/coverage/cover_reg_top/42.i2c_intr_test.3522736737 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:14 PM PDT 24 52682401 ps
T142 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3936520613 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:25 PM PDT 24 249476735 ps
T154 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1400766186 Mar 26 01:21:33 PM PDT 24 Mar 26 01:21:34 PM PDT 24 169471678 ps
T169 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.386137862 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:47 PM PDT 24 31010172 ps
T170 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1610356860 Mar 26 01:21:26 PM PDT 24 Mar 26 01:21:27 PM PDT 24 83677604 ps
T132 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2497707878 Mar 26 01:21:33 PM PDT 24 Mar 26 01:21:35 PM PDT 24 167233887 ps
T1108 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2351135259 Mar 26 01:21:44 PM PDT 24 Mar 26 01:21:45 PM PDT 24 61280847 ps
T1109 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3056592501 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:07 PM PDT 24 20843655 ps
T1110 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1685112305 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 46752925 ps
T191 /workspace/coverage/cover_reg_top/38.i2c_intr_test.692037597 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:11 PM PDT 24 17022874 ps
T155 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2479143552 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 71229285 ps
T248 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2783248511 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:11 PM PDT 24 39366987 ps
T156 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1820021622 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:47 PM PDT 24 52887370 ps
T140 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3425776772 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 52243765 ps
T173 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2747848888 Mar 26 01:21:50 PM PDT 24 Mar 26 01:21:51 PM PDT 24 20203726 ps
T1111 /workspace/coverage/cover_reg_top/48.i2c_intr_test.539420686 Mar 26 01:22:07 PM PDT 24 Mar 26 01:22:08 PM PDT 24 25708395 ps
T1112 /workspace/coverage/cover_reg_top/26.i2c_intr_test.3556450348 Mar 26 01:22:02 PM PDT 24 Mar 26 01:22:03 PM PDT 24 29729488 ps
T1113 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1943019226 Mar 26 01:21:44 PM PDT 24 Mar 26 01:21:45 PM PDT 24 48320765 ps
T157 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.396791417 Mar 26 01:21:33 PM PDT 24 Mar 26 01:21:34 PM PDT 24 59914266 ps
T249 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3430994868 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:48 PM PDT 24 35486998 ps
T183 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1036384383 Mar 26 01:21:42 PM PDT 24 Mar 26 01:21:43 PM PDT 24 75834710 ps
T1114 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1014486341 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 70191539 ps
T1115 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1000331207 Mar 26 01:22:13 PM PDT 24 Mar 26 01:22:14 PM PDT 24 50162923 ps
T143 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1979105823 Mar 26 01:21:33 PM PDT 24 Mar 26 01:21:35 PM PDT 24 1141374613 ps
T184 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.876788298 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:39 PM PDT 24 532227664 ps
T1116 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1859520195 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:48 PM PDT 24 35142778 ps
T233 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3593061273 Mar 26 01:21:50 PM PDT 24 Mar 26 01:21:52 PM PDT 24 112264728 ps
T185 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2354607657 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:50 PM PDT 24 198760977 ps
T1117 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2728453568 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 26245737 ps
T1118 /workspace/coverage/cover_reg_top/29.i2c_intr_test.941067146 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:05 PM PDT 24 49615248 ps
T147 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3112586838 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:47 PM PDT 24 27545655 ps
T1119 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1818472944 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:39 PM PDT 24 44162653 ps
T136 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2674071622 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:48 PM PDT 24 253744380 ps
T1120 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3279190748 Mar 26 01:22:01 PM PDT 24 Mar 26 01:22:02 PM PDT 24 21594845 ps
T1121 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2149341706 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:38 PM PDT 24 64500968 ps
T158 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3142365091 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:39 PM PDT 24 198447022 ps
T1122 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1633490285 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:48 PM PDT 24 125429421 ps
T1123 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1453126705 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:06 PM PDT 24 52106758 ps
T1124 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.4292040927 Mar 26 01:21:32 PM PDT 24 Mar 26 01:21:34 PM PDT 24 131987698 ps
T1125 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1042969979 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:07 PM PDT 24 34600400 ps
T1126 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.963209241 Mar 26 01:22:06 PM PDT 24 Mar 26 01:22:08 PM PDT 24 73067587 ps
T1127 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3044114320 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 49045896 ps
T1128 /workspace/coverage/cover_reg_top/35.i2c_intr_test.506774698 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:06 PM PDT 24 14289829 ps
T1129 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2967675311 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:25 PM PDT 24 33329737 ps
T1130 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3451638136 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:46 PM PDT 24 34892904 ps
T1131 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1480664211 Mar 26 01:21:44 PM PDT 24 Mar 26 01:21:45 PM PDT 24 47097491 ps
T139 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1431949390 Mar 26 01:21:46 PM PDT 24 Mar 26 01:21:48 PM PDT 24 94957094 ps
T1132 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4224542601 Mar 26 01:21:46 PM PDT 24 Mar 26 01:21:48 PM PDT 24 24243740 ps
T1133 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.259389481 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:47 PM PDT 24 20812003 ps
T1134 /workspace/coverage/cover_reg_top/13.i2c_intr_test.974833237 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:48 PM PDT 24 25861202 ps
T1135 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.127158176 Mar 26 01:21:28 PM PDT 24 Mar 26 01:21:31 PM PDT 24 252522238 ps
T1136 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.111278340 Mar 26 01:21:49 PM PDT 24 Mar 26 01:21:51 PM PDT 24 49702891 ps
T1137 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.314556850 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 84565745 ps
T1138 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1037227893 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:48 PM PDT 24 61383940 ps
T1139 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4150768595 Mar 26 01:22:03 PM PDT 24 Mar 26 01:22:03 PM PDT 24 17396936 ps
T1140 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3724988834 Mar 26 01:21:26 PM PDT 24 Mar 26 01:21:27 PM PDT 24 192903608 ps
T1141 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1717883853 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:23 PM PDT 24 66228657 ps
T1142 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2762914692 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 232299091 ps
T1143 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4270818572 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 25774110 ps
T137 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1951979489 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:25 PM PDT 24 317658231 ps
T1144 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3730550216 Mar 26 01:21:32 PM PDT 24 Mar 26 01:21:32 PM PDT 24 130719499 ps
T1145 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3988606206 Mar 26 01:21:26 PM PDT 24 Mar 26 01:21:29 PM PDT 24 50823886 ps
T159 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3321824442 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 27077808 ps
T160 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1971181678 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:25 PM PDT 24 36909412 ps
T1146 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3609144079 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 28199917 ps
T1147 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4245790837 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:47 PM PDT 24 292665844 ps
T1148 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.773463978 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:48 PM PDT 24 83910897 ps
T1149 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2216418030 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:12 PM PDT 24 15706043 ps
T161 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.679158717 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 41613448 ps
T1150 /workspace/coverage/cover_reg_top/44.i2c_intr_test.690078190 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 43050412 ps
T1151 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1477681286 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:05 PM PDT 24 36777474 ps
T1152 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2230766649 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 180217421 ps
T1153 /workspace/coverage/cover_reg_top/49.i2c_intr_test.681101578 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:12 PM PDT 24 49527082 ps
T1154 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3542882521 Mar 26 01:22:01 PM PDT 24 Mar 26 01:22:01 PM PDT 24 51918125 ps
T1155 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.135523242 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:48 PM PDT 24 78529836 ps
T1156 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.742306505 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 33717361 ps
T228 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.672638906 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:24 PM PDT 24 27087085 ps
T1157 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.291112815 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 115459177 ps
T1158 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2738565616 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 18302473 ps
T1159 /workspace/coverage/cover_reg_top/32.i2c_intr_test.689334440 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 21730298 ps
T1160 /workspace/coverage/cover_reg_top/21.i2c_intr_test.3498849203 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:12 PM PDT 24 18022646 ps
T1161 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.605554654 Mar 26 01:21:43 PM PDT 24 Mar 26 01:21:44 PM PDT 24 115419829 ps
T1162 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.511122482 Mar 26 01:21:49 PM PDT 24 Mar 26 01:21:51 PM PDT 24 46047923 ps
T1163 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2946708555 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 28242177 ps
T1164 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.402468385 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 136365215 ps
T1165 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4124416584 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:26 PM PDT 24 175366896 ps
T1166 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3996407668 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 33023583 ps
T1167 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2649761703 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 26144605 ps
T1168 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1954975903 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 55544916 ps
T1169 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3220940790 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:48 PM PDT 24 1781072668 ps
T1170 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.498236830 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:37 PM PDT 24 475590522 ps
T162 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1857478061 Mar 26 01:21:38 PM PDT 24 Mar 26 01:21:39 PM PDT 24 72864415 ps
T1171 /workspace/coverage/cover_reg_top/45.i2c_intr_test.4105542500 Mar 26 01:22:10 PM PDT 24 Mar 26 01:22:11 PM PDT 24 32898111 ps
T1172 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3153713113 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 31595250 ps
T1173 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1541425232 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 76501594 ps
T1174 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1284848616 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:38 PM PDT 24 133876018 ps
T144 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2874448857 Mar 26 01:21:44 PM PDT 24 Mar 26 01:21:46 PM PDT 24 437560950 ps
T1175 /workspace/coverage/cover_reg_top/0.i2c_intr_test.4002485276 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 44671242 ps
T1176 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.57899708 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:47 PM PDT 24 20387665 ps
T1177 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.380328060 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:38 PM PDT 24 229213102 ps
T1178 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3360501134 Mar 26 01:21:37 PM PDT 24 Mar 26 01:21:39 PM PDT 24 132423848 ps
T1179 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.77456337 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 177830502 ps
T1180 /workspace/coverage/cover_reg_top/31.i2c_intr_test.933743319 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:09 PM PDT 24 17186124 ps
T138 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2441782985 Mar 26 01:21:25 PM PDT 24 Mar 26 01:21:27 PM PDT 24 436688992 ps
T1181 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1221552075 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:05 PM PDT 24 52174212 ps
T1182 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3289269778 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:26 PM PDT 24 244893415 ps
T1183 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2574514758 Mar 26 01:21:26 PM PDT 24 Mar 26 01:21:27 PM PDT 24 25763465 ps
T1184 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3371278472 Mar 26 01:22:09 PM PDT 24 Mar 26 01:22:10 PM PDT 24 58491743 ps
T163 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4085315800 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:24 PM PDT 24 72704580 ps
T1185 /workspace/coverage/cover_reg_top/6.i2c_intr_test.299432320 Mar 26 01:21:34 PM PDT 24 Mar 26 01:21:35 PM PDT 24 16307249 ps
T1186 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1367703642 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:11 PM PDT 24 78726437 ps
T229 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.139066852 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:24 PM PDT 24 32735878 ps
T1187 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1405608515 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:37 PM PDT 24 38034797 ps
T1188 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4003809934 Mar 26 01:22:11 PM PDT 24 Mar 26 01:22:12 PM PDT 24 57632333 ps
T1189 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4049027669 Mar 26 01:21:44 PM PDT 24 Mar 26 01:21:45 PM PDT 24 26651115 ps
T1190 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1637413517 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:06 PM PDT 24 21249542 ps
T1191 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2923784799 Mar 26 01:21:45 PM PDT 24 Mar 26 01:21:48 PM PDT 24 243353573 ps
T1192 /workspace/coverage/cover_reg_top/14.i2c_intr_test.76474425 Mar 26 01:21:48 PM PDT 24 Mar 26 01:21:49 PM PDT 24 17375251 ps
T148 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.165541657 Mar 26 01:21:47 PM PDT 24 Mar 26 01:21:49 PM PDT 24 483013021 ps
T1193 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3899823887 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:37 PM PDT 24 87459219 ps
T164 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3831704911 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:25 PM PDT 24 55113899 ps
T1194 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4101043601 Mar 26 01:21:33 PM PDT 24 Mar 26 01:21:34 PM PDT 24 47262219 ps
T1195 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2619421721 Mar 26 01:21:27 PM PDT 24 Mar 26 01:21:29 PM PDT 24 151636914 ps
T145 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1224852660 Mar 26 01:21:27 PM PDT 24 Mar 26 01:21:29 PM PDT 24 48811440 ps
T1196 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1702397435 Mar 26 01:21:24 PM PDT 24 Mar 26 01:21:29 PM PDT 24 117612941 ps
T1197 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.327384243 Mar 26 01:21:46 PM PDT 24 Mar 26 01:21:47 PM PDT 24 73923199 ps
T1198 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.786159395 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:37 PM PDT 24 115441551 ps
T1199 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.480568516 Mar 26 01:21:36 PM PDT 24 Mar 26 01:21:38 PM PDT 24 98967374 ps
T149 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2574983361 Mar 26 01:21:23 PM PDT 24 Mar 26 01:21:25 PM PDT 24 145813596 ps
T1200 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1398850037 Mar 26 01:22:04 PM PDT 24 Mar 26 01:22:04 PM PDT 24 51487772 ps
T1201 /workspace/coverage/cover_reg_top/24.i2c_intr_test.421400427 Mar 26 01:22:01 PM PDT 24 Mar 26 01:22:02 PM PDT 24 172938664 ps
T1202 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3334781033 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 18517752 ps
T1203 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3334029716 Mar 26 01:21:30 PM PDT 24 Mar 26 01:21:33 PM PDT 24 1095666498 ps
T1204 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3895384722 Mar 26 01:21:48 PM PDT 24 Mar 26 01:21:48 PM PDT 24 20453348 ps
T1205 /workspace/coverage/cover_reg_top/23.i2c_intr_test.3667434459 Mar 26 01:22:08 PM PDT 24 Mar 26 01:22:08 PM PDT 24 24652442 ps
T141 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4235903527 Mar 26 01:22:05 PM PDT 24 Mar 26 01:22:07 PM PDT 24 248315568 ps
T1206 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2188785859 Mar 26 01:21:35 PM PDT 24 Mar 26 01:21:36 PM PDT 24 20395143 ps

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1678875905
Short name T12
Test name
Test status
Simulation time 4046854377 ps
CPU time 93.02 seconds
Started Mar 26 01:14:40 PM PDT 24
Finished Mar 26 01:16:13 PM PDT 24
Peak memory 1190756 kb
Host smart-d6735006-d5f9-4669-928a-71443609fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678875905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1678875905
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3067805153
Short name T10
Test name
Test status
Simulation time 1096278914 ps
CPU time 5.88 seconds
Started Mar 26 01:18:20 PM PDT 24
Finished Mar 26 01:18:27 PM PDT 24
Peak memory 218780 kb
Host smart-7a815178-7ee0-4b99-b2c7-17f00babd22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067805153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3067805153
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3950454370
Short name T86
Test name
Test status
Simulation time 4937044050 ps
CPU time 162.75 seconds
Started Mar 26 01:13:49 PM PDT 24
Finished Mar 26 01:16:32 PM PDT 24
Peak memory 1070964 kb
Host smart-e0ef8cf7-b77b-4ab2-bcc1-d62a81755feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950454370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3950454370
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.728214116
Short name T150
Test name
Test status
Simulation time 34225092 ps
CPU time 0.93 seconds
Started Mar 26 01:21:44 PM PDT 24
Finished Mar 26 01:21:45 PM PDT 24
Peak memory 203604 kb
Host smart-620fcfad-06fc-41fa-a87c-d34e57886542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728214116 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.728214116
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.4097874067
Short name T15
Test name
Test status
Simulation time 103774095368 ps
CPU time 320.21 seconds
Started Mar 26 01:14:40 PM PDT 24
Finished Mar 26 01:20:01 PM PDT 24
Peak memory 645060 kb
Host smart-d4c0c910-e209-4c42-add7-190f5b9c831b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097874067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.4097874067
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2897258057
Short name T65
Test name
Test status
Simulation time 3340226090 ps
CPU time 113.75 seconds
Started Mar 26 01:18:28 PM PDT 24
Finished Mar 26 01:20:22 PM PDT 24
Peak memory 603740 kb
Host smart-c3ff5a2f-265c-47e4-ab5e-703dd76942f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897258057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2897258057
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_override.3469709223
Short name T20
Test name
Test status
Simulation time 30104518 ps
CPU time 0.65 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:13:47 PM PDT 24
Peak memory 203672 kb
Host smart-cafa0686-2160-4dfc-bbe2-8b4b71a95d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469709223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3469709223
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.909369263
Short name T130
Test name
Test status
Simulation time 152413951 ps
CPU time 2.02 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203672 kb
Host smart-1678a412-b1a1-478e-9d82-4cb4b94f171e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909369263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.909369263
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2274889481
Short name T67
Test name
Test status
Simulation time 10070483327 ps
CPU time 79.96 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 01:16:37 PM PDT 24
Peak memory 580208 kb
Host smart-515a6171-ee58-4873-aa52-09760ea212d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274889481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2274889481
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.122486713
Short name T24
Test name
Test status
Simulation time 911218999 ps
CPU time 5.53 seconds
Started Mar 26 01:14:53 PM PDT 24
Finished Mar 26 01:14:58 PM PDT 24
Peak memory 206452 kb
Host smart-7e3accd2-e843-43f2-be5b-d4b907b81e03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122486713 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_unexp_stop.122486713
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1527757676
Short name T115
Test name
Test status
Simulation time 68130655 ps
CPU time 0.97 seconds
Started Mar 26 01:12:30 PM PDT 24
Finished Mar 26 01:12:31 PM PDT 24
Peak memory 222344 kb
Host smart-1dba6943-f7e3-4930-8be3-c15abd02a100
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527757676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1527757676
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.2434839676
Short name T186
Test name
Test status
Simulation time 28894075311 ps
CPU time 735.34 seconds
Started Mar 26 01:18:45 PM PDT 24
Finished Mar 26 01:31:01 PM PDT 24
Peak memory 951924 kb
Host smart-3e2a3177-893e-4520-9ba4-262579b7cb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434839676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.2434839676
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3322493478
Short name T21
Test name
Test status
Simulation time 3145021509 ps
CPU time 3.78 seconds
Started Mar 26 01:13:27 PM PDT 24
Finished Mar 26 01:13:31 PM PDT 24
Peak memory 212428 kb
Host smart-a2bdf997-67be-4e56-8f5a-2b12fa06c50a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322493478 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3322493478
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3619573369
Short name T83
Test name
Test status
Simulation time 242866771 ps
CPU time 0.71 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203376 kb
Host smart-1c5acdb3-6821-4f05-b52e-e7316bf89e96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619573369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3619573369
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.421899926
Short name T37
Test name
Test status
Simulation time 331949082 ps
CPU time 0.99 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:12:17 PM PDT 24
Peak memory 203928 kb
Host smart-4f218e7d-09e6-46c2-a0f6-7cc092658b72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421899926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.421899926
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1764554408
Short name T114
Test name
Test status
Simulation time 13329764324 ps
CPU time 1464.8 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:40:51 PM PDT 24
Peak memory 1244276 kb
Host smart-1cde1ea4-4d40-4621-a873-70ee15d17028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764554408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1764554408
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3838082340
Short name T133
Test name
Test status
Simulation time 52959682 ps
CPU time 1.67 seconds
Started Mar 26 01:21:44 PM PDT 24
Finished Mar 26 01:21:46 PM PDT 24
Peak memory 203616 kb
Host smart-3a32efee-0e7e-44cb-a275-7f3d05bd6e5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838082340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3838082340
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2782032487
Short name T516
Test name
Test status
Simulation time 663314022 ps
CPU time 2.88 seconds
Started Mar 26 01:14:26 PM PDT 24
Finished Mar 26 01:14:29 PM PDT 24
Peak memory 204016 kb
Host smart-58dc2fa0-7f6e-488f-ae66-62a40ad55a42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782032487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2782032487
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.279562337
Short name T215
Test name
Test status
Simulation time 20371232553 ps
CPU time 994.34 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:29:05 PM PDT 24
Peak memory 2192928 kb
Host smart-92ba6f35-a6ab-4e97-9ab5-7d4c17c214a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279562337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.279562337
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3097719292
Short name T35
Test name
Test status
Simulation time 1054641304 ps
CPU time 63.37 seconds
Started Mar 26 01:17:45 PM PDT 24
Finished Mar 26 01:18:48 PM PDT 24
Peak memory 271448 kb
Host smart-afea4c31-d83b-4a39-8d87-807514974cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097719292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3097719292
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.50751619
Short name T88
Test name
Test status
Simulation time 9512087186 ps
CPU time 83.99 seconds
Started Mar 26 01:12:56 PM PDT 24
Finished Mar 26 01:14:20 PM PDT 24
Peak memory 720788 kb
Host smart-e2ce5121-e4e5-4929-a817-ec58dd09edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50751619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.50751619
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1917798169
Short name T263
Test name
Test status
Simulation time 18252360 ps
CPU time 0.63 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:12:32 PM PDT 24
Peak memory 203716 kb
Host smart-b91b1e47-e918-49ff-9734-0b03277d7a22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917798169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1917798169
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2447526606
Short name T31
Test name
Test status
Simulation time 667490197 ps
CPU time 6.05 seconds
Started Mar 26 01:14:11 PM PDT 24
Finished Mar 26 01:14:18 PM PDT 24
Peak memory 212304 kb
Host smart-959e16c2-bfc2-418c-9d2e-d8c0b2d4425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447526606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2447526606
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_target_unexp_stop.3121781477
Short name T25
Test name
Test status
Simulation time 2152423281 ps
CPU time 6.21 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:19:26 PM PDT 24
Peak memory 212388 kb
Host smart-538807d1-be4d-4840-a35b-e17c6bf15a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121781477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.i2c_target_unexp_stop.3121781477
Directory /workspace/47.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3549758281
Short name T55
Test name
Test status
Simulation time 171393467 ps
CPU time 6.66 seconds
Started Mar 26 01:14:38 PM PDT 24
Finished Mar 26 01:14:46 PM PDT 24
Peak memory 223032 kb
Host smart-9af48d8a-322c-429b-af5f-aa7871d17563
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549758281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3549758281
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_perf.620736637
Short name T17
Test name
Test status
Simulation time 1891972839 ps
CPU time 26.65 seconds
Started Mar 26 01:15:51 PM PDT 24
Finished Mar 26 01:16:18 PM PDT 24
Peak memory 235004 kb
Host smart-d9921249-1a4d-4528-a808-fd6dcfb21eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620736637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.620736637
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3701145021
Short name T71
Test name
Test status
Simulation time 10162707295 ps
CPU time 102.51 seconds
Started Mar 26 01:14:13 PM PDT 24
Finished Mar 26 01:15:56 PM PDT 24
Peak memory 596224 kb
Host smart-d7d4a825-168a-446e-9577-bf01d7b5ae82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701145021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3701145021
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2124970222
Short name T62
Test name
Test status
Simulation time 7658939449 ps
CPU time 69.22 seconds
Started Mar 26 01:15:15 PM PDT 24
Finished Mar 26 01:16:25 PM PDT 24
Peak memory 682444 kb
Host smart-7e4d0c73-81e8-4345-9388-e9ca74e386f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124970222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2124970222
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1951979489
Short name T137
Test name
Test status
Simulation time 317658231 ps
CPU time 2.05 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203440 kb
Host smart-148e5423-dfaf-4d4b-bcec-bd0466a1238f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951979489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1951979489
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3499775158
Short name T188
Test name
Test status
Simulation time 84648131 ps
CPU time 0.7 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:11 PM PDT 24
Peak memory 203456 kb
Host smart-1511f9ba-f58f-4e0f-ba59-131eb52cd5dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499775158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3499775158
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3915394087
Short name T874
Test name
Test status
Simulation time 673947356 ps
CPU time 1.13 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:12:18 PM PDT 24
Peak memory 204064 kb
Host smart-d5bec202-e715-4067-8756-9ab820697c1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915394087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3915394087
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1362965068
Short name T232
Test name
Test status
Simulation time 1032965162 ps
CPU time 1.91 seconds
Started Mar 26 01:13:49 PM PDT 24
Finished Mar 26 01:13:52 PM PDT 24
Peak memory 204200 kb
Host smart-8f5c13f8-88e4-49ce-8260-60e82c2b4e09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362965068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1362965068
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_host_override.61486689
Short name T227
Test name
Test status
Simulation time 15001023 ps
CPU time 0.63 seconds
Started Mar 26 01:13:49 PM PDT 24
Finished Mar 26 01:13:50 PM PDT 24
Peak memory 203620 kb
Host smart-7fe45a53-e509-4f3e-b96d-4fa75f3e714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61486689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.61486689
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3013242957
Short name T256
Test name
Test status
Simulation time 14379066295 ps
CPU time 254.67 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:18:27 PM PDT 24
Peak memory 1842140 kb
Host smart-be131606-5a95-404a-811d-082caa2622c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013242957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3013242957
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3831124139
Short name T224
Test name
Test status
Simulation time 43342469 ps
CPU time 1.24 seconds
Started Mar 26 01:14:26 PM PDT 24
Finished Mar 26 01:14:27 PM PDT 24
Peak memory 212292 kb
Host smart-2ed3e27d-69d0-441b-b8c6-6197cd4eef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831124139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3831124139
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.825197678
Short name T220
Test name
Test status
Simulation time 254926754885 ps
CPU time 2636.33 seconds
Started Mar 26 01:15:58 PM PDT 24
Finished Mar 26 01:59:55 PM PDT 24
Peak memory 2981268 kb
Host smart-cf202db8-6c05-41b0-a862-46244900e6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825197678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.825197678
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3112586838
Short name T147
Test name
Test status
Simulation time 27545655 ps
CPU time 1.23 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:47 PM PDT 24
Peak memory 203616 kb
Host smart-af161c47-347d-4a59-afaf-4d5a119a11c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112586838 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3112586838
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.672638906
Short name T228
Test name
Test status
Simulation time 27087085 ps
CPU time 0.71 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:24 PM PDT 24
Peak memory 203368 kb
Host smart-0057c296-38b2-4e2a-a8fb-b6d9fb741284
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672638906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.672638906
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2588224225
Short name T238
Test name
Test status
Simulation time 12608314693 ps
CPU time 165.36 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:16:19 PM PDT 24
Peak memory 832600 kb
Host smart-9f050951-3dac-411e-a673-0bdb343104b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588224225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2588224225
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2236440560
Short name T235
Test name
Test status
Simulation time 3019180677 ps
CPU time 196.18 seconds
Started Mar 26 01:13:49 PM PDT 24
Finished Mar 26 01:17:06 PM PDT 24
Peak memory 924628 kb
Host smart-27908d92-fc7c-470b-93ed-3e558dc3b256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236440560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2236440560
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1515944050
Short name T855
Test name
Test status
Simulation time 10862129001 ps
CPU time 5.73 seconds
Started Mar 26 01:16:18 PM PDT 24
Finished Mar 26 01:16:24 PM PDT 24
Peak memory 259960 kb
Host smart-fc13a045-ffe8-482f-8186-e0cb51502824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515944050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1515944050
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3469514974
Short name T241
Test name
Test status
Simulation time 6379216710 ps
CPU time 62.11 seconds
Started Mar 26 01:13:26 PM PDT 24
Finished Mar 26 01:14:28 PM PDT 24
Peak memory 815476 kb
Host smart-a09503a3-ba37-481f-9ade-4178039883c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469514974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3469514974
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2574983361
Short name T149
Test name
Test status
Simulation time 145813596 ps
CPU time 2 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203520 kb
Host smart-b55478cc-f898-439e-bc96-047d8c948de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574983361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2574983361
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3425776772
Short name T140
Test name
Test status
Simulation time 52243765 ps
CPU time 1.2 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203576 kb
Host smart-f1b86312-ce36-4cc8-a298-295529234126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425776772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3425776772
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2874448857
Short name T144
Test name
Test status
Simulation time 437560950 ps
CPU time 2.14 seconds
Started Mar 26 01:21:44 PM PDT 24
Finished Mar 26 01:21:46 PM PDT 24
Peak memory 203508 kb
Host smart-db4ff1b9-35ef-493a-9408-a7f727ad5c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874448857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2874448857
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1401483344
Short name T29
Test name
Test status
Simulation time 38120642 ps
CPU time 1.71 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:12:18 PM PDT 24
Peak memory 212344 kb
Host smart-1d5cb842-f545-4776-8255-33c00109780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401483344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1401483344
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1446186867
Short name T1049
Test name
Test status
Simulation time 10518741038 ps
CPU time 11.12 seconds
Started Mar 26 01:14:05 PM PDT 24
Finished Mar 26 01:14:16 PM PDT 24
Peak memory 280868 kb
Host smart-db463428-06ec-475a-8149-d514367a4210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446186867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1446186867
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1971181678
Short name T160
Test name
Test status
Simulation time 36909412 ps
CPU time 1.62 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203528 kb
Host smart-1a546f32-ed1e-44b0-95e2-df77087c405e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971181678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1971181678
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1702397435
Short name T1196
Test name
Test status
Simulation time 117612941 ps
CPU time 4.53 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:29 PM PDT 24
Peak memory 203624 kb
Host smart-830a1e30-f670-4a96-a913-88a44f659025
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702397435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1702397435
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.397642683
Short name T172
Test name
Test status
Simulation time 42019859 ps
CPU time 0.66 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203148 kb
Host smart-a7be52cc-96f2-416e-8605-00d114bf5c67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397642683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.397642683
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.314556850
Short name T1137
Test name
Test status
Simulation time 84565745 ps
CPU time 0.79 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203508 kb
Host smart-4c399de6-390f-4591-94f1-83acbdfbefc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314556850 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.314556850
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3594511740
Short name T152
Test name
Test status
Simulation time 20425091 ps
CPU time 0.66 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:24 PM PDT 24
Peak memory 203444 kb
Host smart-6a61acff-17d9-4f52-9ac2-180d33fc79e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594511740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3594511740
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.4002485276
Short name T1175
Test name
Test status
Simulation time 44671242 ps
CPU time 0.67 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203324 kb
Host smart-736d506d-b0c1-496d-b765-06b727aacac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002485276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.4002485276
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3724988834
Short name T1140
Test name
Test status
Simulation time 192903608 ps
CPU time 1.07 seconds
Started Mar 26 01:21:26 PM PDT 24
Finished Mar 26 01:21:27 PM PDT 24
Peak memory 203436 kb
Host smart-c0946c41-b935-4baf-a345-1f67882f06dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724988834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3724988834
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2619421721
Short name T1195
Test name
Test status
Simulation time 151636914 ps
CPU time 2.06 seconds
Started Mar 26 01:21:27 PM PDT 24
Finished Mar 26 01:21:29 PM PDT 24
Peak memory 203496 kb
Host smart-63391703-7bc0-45dc-8b50-aeeee42425a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619421721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2619421721
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2441782985
Short name T138
Test name
Test status
Simulation time 436688992 ps
CPU time 1.96 seconds
Started Mar 26 01:21:25 PM PDT 24
Finished Mar 26 01:21:27 PM PDT 24
Peak memory 203588 kb
Host smart-45dee3e6-051b-41f0-9dd0-abc32a7b64e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441782985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2441782985
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3831704911
Short name T164
Test name
Test status
Simulation time 55113899 ps
CPU time 1.15 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203540 kb
Host smart-9e9f571a-e3e1-487f-94dd-9a9ec1b21191
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831704911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3831704911
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.3289269778
Short name T1182
Test name
Test status
Simulation time 244893415 ps
CPU time 2.75 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:26 PM PDT 24
Peak memory 203472 kb
Host smart-85a6b4d2-6eb0-4b26-a5db-c618d4915b5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289269778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3289269778
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.679158717
Short name T161
Test name
Test status
Simulation time 41613448 ps
CPU time 0.79 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203524 kb
Host smart-fd3363c8-bce8-4bc5-937d-baeb7751283e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679158717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.679158717
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.595580334
Short name T146
Test name
Test status
Simulation time 72031447 ps
CPU time 1.11 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:24 PM PDT 24
Peak memory 203476 kb
Host smart-b4179ef8-c5ba-442a-b92c-0607de985b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595580334 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.595580334
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4085315800
Short name T163
Test name
Test status
Simulation time 72704580 ps
CPU time 0.73 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:24 PM PDT 24
Peak memory 203312 kb
Host smart-269515c5-b9ff-427f-af02-c7d6c64d7a98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085315800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.4085315800
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3996407668
Short name T1166
Test name
Test status
Simulation time 33023583 ps
CPU time 0.69 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203416 kb
Host smart-5db8f9f0-768d-4f1e-b115-7dcb71117aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996407668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3996407668
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1610356860
Short name T170
Test name
Test status
Simulation time 83677604 ps
CPU time 0.97 seconds
Started Mar 26 01:21:26 PM PDT 24
Finished Mar 26 01:21:27 PM PDT 24
Peak memory 203632 kb
Host smart-b0bf8929-43c1-4f81-9b05-99366558e762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610356860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1610356860
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2967675311
Short name T1129
Test name
Test status
Simulation time 33329737 ps
CPU time 1.47 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203540 kb
Host smart-eaa49450-227b-4455-aeab-6f9a3520ef58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967675311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2967675311
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2715805625
Short name T135
Test name
Test status
Simulation time 32945009 ps
CPU time 1.44 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:39 PM PDT 24
Peak memory 203740 kb
Host smart-8c9aa903-4085-4e95-8956-84881e666f4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715805625 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2715805625
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3321824442
Short name T159
Test name
Test status
Simulation time 27077808 ps
CPU time 0.72 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203408 kb
Host smart-352b5b67-b84d-4ba6-a38f-e898939fe986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321824442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3321824442
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1405608515
Short name T1187
Test name
Test status
Simulation time 38034797 ps
CPU time 0.66 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203348 kb
Host smart-4c210332-bd5d-4e6a-a9cb-6bf5e91dcac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405608515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1405608515
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2230766649
Short name T1152
Test name
Test status
Simulation time 180217421 ps
CPU time 1.04 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203476 kb
Host smart-b7121a0a-80b3-451a-924c-9f8b55a4f169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230766649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2230766649
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1608062100
Short name T113
Test name
Test status
Simulation time 187868077 ps
CPU time 1.11 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:38 PM PDT 24
Peak memory 203588 kb
Host smart-996d0db7-19ec-4628-ba29-406964c0fec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608062100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1608062100
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3360501134
Short name T1178
Test name
Test status
Simulation time 132423848 ps
CPU time 2.06 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:39 PM PDT 24
Peak memory 203652 kb
Host smart-4285bb3b-036b-4a24-a78a-65424a93884b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360501134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3360501134
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2762914692
Short name T1142
Test name
Test status
Simulation time 232299091 ps
CPU time 0.95 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203560 kb
Host smart-9ab2316a-d222-4e31-ac9e-7de016f03180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762914692 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2762914692
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2479143552
Short name T155
Test name
Test status
Simulation time 71229285 ps
CPU time 0.64 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203360 kb
Host smart-3efebc5d-8f0a-4b30-b291-029c0f687201
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479143552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2479143552
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1954975903
Short name T1168
Test name
Test status
Simulation time 55544916 ps
CPU time 0.65 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203352 kb
Host smart-b00c4aed-852d-46cd-97a2-851ad8cae18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954975903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1954975903
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3290770746
Short name T165
Test name
Test status
Simulation time 191769292 ps
CPU time 1.02 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203616 kb
Host smart-f6a326ed-619c-49c5-baa3-235c98498513
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290770746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.3290770746
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.669472792
Short name T111
Test name
Test status
Simulation time 102098414 ps
CPU time 1.18 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203604 kb
Host smart-250b8cf3-7d77-4dc0-82ce-8745059c8e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669472792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.669472792
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.111278340
Short name T1136
Test name
Test status
Simulation time 49702891 ps
CPU time 0.75 seconds
Started Mar 26 01:21:49 PM PDT 24
Finished Mar 26 01:21:51 PM PDT 24
Peak memory 203488 kb
Host smart-804a6ab3-447f-42b6-a807-ff49c5dda25f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111278340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.111278340
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3130455590
Short name T245
Test name
Test status
Simulation time 16971600 ps
CPU time 0.64 seconds
Started Mar 26 01:21:54 PM PDT 24
Finished Mar 26 01:21:55 PM PDT 24
Peak memory 203348 kb
Host smart-f4ee4b3f-931a-4b73-ba26-e8d8891fcf94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130455590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3130455590
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.386137862
Short name T169
Test name
Test status
Simulation time 31010172 ps
CPU time 0.84 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:47 PM PDT 24
Peak memory 203408 kb
Host smart-a5c64735-9870-4c7a-acb3-b7dd9a4ceb65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386137862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.386137862
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2354607657
Short name T185
Test name
Test status
Simulation time 198760977 ps
CPU time 2.13 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:50 PM PDT 24
Peak memory 203648 kb
Host smart-5626b111-8d9a-475d-881b-83d153a2c089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354607657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2354607657
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.773463978
Short name T1148
Test name
Test status
Simulation time 83910897 ps
CPU time 1.94 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203560 kb
Host smart-51bdcc27-6f3a-4811-86b3-0e21590aa246
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773463978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.773463978
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1036384383
Short name T183
Test name
Test status
Simulation time 75834710 ps
CPU time 0.76 seconds
Started Mar 26 01:21:42 PM PDT 24
Finished Mar 26 01:21:43 PM PDT 24
Peak memory 203480 kb
Host smart-eca88e46-84d8-42e7-afb8-9648a49a2cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036384383 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1036384383
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.57899708
Short name T1176
Test name
Test status
Simulation time 20387665 ps
CPU time 0.69 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:47 PM PDT 24
Peak memory 203384 kb
Host smart-47dbb1fe-9d3a-4cdd-8f3f-e9c1ad04e19a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57899708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.57899708
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.974833237
Short name T1134
Test name
Test status
Simulation time 25861202 ps
CPU time 0.68 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203292 kb
Host smart-3e8d0024-63a0-44c7-80f2-f7118e0a637d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974833237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.974833237
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.4049027669
Short name T1189
Test name
Test status
Simulation time 26651115 ps
CPU time 1.01 seconds
Started Mar 26 01:21:44 PM PDT 24
Finished Mar 26 01:21:45 PM PDT 24
Peak memory 203636 kb
Host smart-21e53de0-ba15-47fe-afaf-eca29d803fa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049027669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.4049027669
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.272091411
Short name T131
Test name
Test status
Simulation time 45999932 ps
CPU time 1.28 seconds
Started Mar 26 01:21:48 PM PDT 24
Finished Mar 26 01:21:49 PM PDT 24
Peak memory 203476 kb
Host smart-82e9632e-4063-4dbd-9b61-5ff4a9200db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272091411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.272091411
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3593061273
Short name T233
Test name
Test status
Simulation time 112264728 ps
CPU time 1.3 seconds
Started Mar 26 01:21:50 PM PDT 24
Finished Mar 26 01:21:52 PM PDT 24
Peak memory 203496 kb
Host smart-f93de410-3534-4e00-b7e7-ee8dc8d7f02a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593061273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3593061273
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2747848888
Short name T173
Test name
Test status
Simulation time 20203726 ps
CPU time 0.7 seconds
Started Mar 26 01:21:50 PM PDT 24
Finished Mar 26 01:21:51 PM PDT 24
Peak memory 203436 kb
Host smart-fc72db76-f678-4782-ad29-1f9d7595f1f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747848888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2747848888
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.76474425
Short name T1192
Test name
Test status
Simulation time 17375251 ps
CPU time 0.66 seconds
Started Mar 26 01:21:48 PM PDT 24
Finished Mar 26 01:21:49 PM PDT 24
Peak memory 203284 kb
Host smart-3877c0f2-1637-44c7-8ae1-e8260dbf814f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76474425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.76474425
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2351135259
Short name T1108
Test name
Test status
Simulation time 61280847 ps
CPU time 0.86 seconds
Started Mar 26 01:21:44 PM PDT 24
Finished Mar 26 01:21:45 PM PDT 24
Peak memory 203404 kb
Host smart-aaf1b817-cc06-4448-b62f-abb18bfe7016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351135259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2351135259
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1859520195
Short name T1116
Test name
Test status
Simulation time 35142778 ps
CPU time 1.65 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203732 kb
Host smart-9afd7de8-de5e-4be8-9e15-a8cf15a6d0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859520195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1859520195
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1431949390
Short name T139
Test name
Test status
Simulation time 94957094 ps
CPU time 2.01 seconds
Started Mar 26 01:21:46 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203540 kb
Host smart-45d2c7d5-57cf-48be-9bb0-51587264cca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431949390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1431949390
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1633490285
Short name T1122
Test name
Test status
Simulation time 125429421 ps
CPU time 0.96 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203608 kb
Host smart-b8c384a7-b141-4eaf-abfc-394ec678001a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633490285 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1633490285
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.259389481
Short name T1133
Test name
Test status
Simulation time 20812003 ps
CPU time 0.76 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:47 PM PDT 24
Peak memory 203408 kb
Host smart-2d13fc0b-89da-424a-8964-4fb0194fe3b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259389481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.259389481
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3451638136
Short name T1130
Test name
Test status
Simulation time 34892904 ps
CPU time 0.6 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:46 PM PDT 24
Peak memory 202916 kb
Host smart-749f517e-fc70-4dfd-ba9e-383afef2cd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451638136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3451638136
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.327384243
Short name T1197
Test name
Test status
Simulation time 73923199 ps
CPU time 1.1 seconds
Started Mar 26 01:21:46 PM PDT 24
Finished Mar 26 01:21:47 PM PDT 24
Peak memory 203580 kb
Host smart-74c1cad9-4a00-4033-825b-e876c49ae65d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327384243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.327384243
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.165541657
Short name T148
Test name
Test status
Simulation time 483013021 ps
CPU time 2.2 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:49 PM PDT 24
Peak memory 203696 kb
Host smart-6ebcaed6-bd8c-4203-8034-76eea87e4cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165541657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.165541657
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3611670589
Short name T134
Test name
Test status
Simulation time 43512194 ps
CPU time 0.91 seconds
Started Mar 26 01:21:43 PM PDT 24
Finished Mar 26 01:21:44 PM PDT 24
Peak memory 203504 kb
Host smart-9595416d-7811-4a0e-9d8d-7c2913c1a7ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611670589 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3611670589
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1820021622
Short name T156
Test name
Test status
Simulation time 52887370 ps
CPU time 0.69 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:47 PM PDT 24
Peak memory 203332 kb
Host smart-f3fcd20a-6181-44e3-a5a3-edd7ef81d868
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820021622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1820021622
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1943019226
Short name T1113
Test name
Test status
Simulation time 48320765 ps
CPU time 0.67 seconds
Started Mar 26 01:21:44 PM PDT 24
Finished Mar 26 01:21:45 PM PDT 24
Peak memory 203452 kb
Host smart-e00bc996-5831-433a-9ec0-824739c7c11c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943019226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1943019226
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1480664211
Short name T1131
Test name
Test status
Simulation time 47097491 ps
CPU time 1 seconds
Started Mar 26 01:21:44 PM PDT 24
Finished Mar 26 01:21:45 PM PDT 24
Peak memory 203580 kb
Host smart-300a810c-a5a1-46c2-8e92-63fdff02f9c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480664211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1480664211
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2923784799
Short name T1191
Test name
Test status
Simulation time 243353573 ps
CPU time 2.52 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203684 kb
Host smart-2f83cd33-feb9-4155-b049-e91911dcb3c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923784799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2923784799
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3220940790
Short name T1169
Test name
Test status
Simulation time 1781072668 ps
CPU time 2.19 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203676 kb
Host smart-7848b089-4fc4-437c-8772-7455d153ec31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220940790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3220940790
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.4224542601
Short name T1132
Test name
Test status
Simulation time 24243740 ps
CPU time 0.97 seconds
Started Mar 26 01:21:46 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203568 kb
Host smart-b313ded8-2e9b-4990-83ec-3b2da7d966d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224542601 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.4224542601
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3895384722
Short name T1204
Test name
Test status
Simulation time 20453348 ps
CPU time 0.7 seconds
Started Mar 26 01:21:48 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203376 kb
Host smart-f9769534-fc79-4de3-ab12-49ccb7562928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895384722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3895384722
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1037227893
Short name T1138
Test name
Test status
Simulation time 61383940 ps
CPU time 0.68 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203480 kb
Host smart-05b96d80-1502-48ea-81fa-764b7f2f632e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037227893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1037227893
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.605554654
Short name T1161
Test name
Test status
Simulation time 115419829 ps
CPU time 0.79 seconds
Started Mar 26 01:21:43 PM PDT 24
Finished Mar 26 01:21:44 PM PDT 24
Peak memory 203508 kb
Host smart-468d9d5a-3363-47a8-919f-e8c161d5ad33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605554654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.605554654
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4245790837
Short name T1147
Test name
Test status
Simulation time 292665844 ps
CPU time 1.68 seconds
Started Mar 26 01:21:45 PM PDT 24
Finished Mar 26 01:21:47 PM PDT 24
Peak memory 203524 kb
Host smart-4c4ffea4-a3e5-43b1-bd04-339bee277555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245790837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.4245790837
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.402468385
Short name T1164
Test name
Test status
Simulation time 136365215 ps
CPU time 1.06 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203464 kb
Host smart-3bcee203-ed53-4c7c-b935-6326621063c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402468385 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.402468385
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.135523242
Short name T1155
Test name
Test status
Simulation time 78529836 ps
CPU time 0.74 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203380 kb
Host smart-9492032d-790c-4a4c-a7cb-a5ba25cfe4dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135523242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.135523242
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3430994868
Short name T249
Test name
Test status
Simulation time 35486998 ps
CPU time 0.64 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203440 kb
Host smart-bbfde1e8-1b32-4ddd-b70f-447d74b0a122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430994868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3430994868
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4003809934
Short name T1188
Test name
Test status
Simulation time 57632333 ps
CPU time 0.86 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:12 PM PDT 24
Peak memory 203532 kb
Host smart-522059c1-5f75-416f-a506-19c397876bc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003809934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.4003809934
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.511122482
Short name T1162
Test name
Test status
Simulation time 46047923 ps
CPU time 1.22 seconds
Started Mar 26 01:21:49 PM PDT 24
Finished Mar 26 01:21:51 PM PDT 24
Peak memory 203464 kb
Host smart-d7b6476e-5257-4c61-a19b-7c73756b8540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511122482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.511122482
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2674071622
Short name T136
Test name
Test status
Simulation time 253744380 ps
CPU time 1.3 seconds
Started Mar 26 01:21:47 PM PDT 24
Finished Mar 26 01:21:48 PM PDT 24
Peak memory 203564 kb
Host smart-ab04672d-4f9a-4b31-9c0b-19877ae3f5fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674071622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2674071622
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2329970260
Short name T151
Test name
Test status
Simulation time 283716083 ps
CPU time 0.8 seconds
Started Mar 26 01:22:14 PM PDT 24
Finished Mar 26 01:22:15 PM PDT 24
Peak memory 203444 kb
Host smart-16db0538-30d0-4b23-8cb8-b958aa9bd20f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329970260 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2329970260
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3542882521
Short name T1154
Test name
Test status
Simulation time 51918125 ps
CPU time 0.65 seconds
Started Mar 26 01:22:01 PM PDT 24
Finished Mar 26 01:22:01 PM PDT 24
Peak memory 203364 kb
Host smart-3971b091-2a41-430f-9f0f-6e0946a03921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542882521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3542882521
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3056592501
Short name T1109
Test name
Test status
Simulation time 20843655 ps
CPU time 0.64 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:07 PM PDT 24
Peak memory 203364 kb
Host smart-c9b07c33-34cf-4f77-b138-c36984136156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056592501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3056592501
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3371278472
Short name T1184
Test name
Test status
Simulation time 58491743 ps
CPU time 0.84 seconds
Started Mar 26 01:22:09 PM PDT 24
Finished Mar 26 01:22:10 PM PDT 24
Peak memory 203420 kb
Host smart-d0baaf70-fde6-43eb-9487-ad85bccfad94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371278472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3371278472
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.963209241
Short name T1126
Test name
Test status
Simulation time 73067587 ps
CPU time 2.09 seconds
Started Mar 26 01:22:06 PM PDT 24
Finished Mar 26 01:22:08 PM PDT 24
Peak memory 203520 kb
Host smart-fdc6f8f9-f984-428e-abef-f42ca0f3e916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963209241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.963209241
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4235903527
Short name T141
Test name
Test status
Simulation time 248315568 ps
CPU time 2.12 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:07 PM PDT 24
Peak memory 203568 kb
Host smart-b190c2c7-844a-45a2-938c-05cc3dd3869b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235903527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4235903527
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3609144079
Short name T1146
Test name
Test status
Simulation time 28199917 ps
CPU time 1.13 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203496 kb
Host smart-2dba87d9-d399-40b7-a4b9-f26cce36a064
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609144079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3609144079
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.127158176
Short name T1135
Test name
Test status
Simulation time 252522238 ps
CPU time 2.77 seconds
Started Mar 26 01:21:28 PM PDT 24
Finished Mar 26 01:21:31 PM PDT 24
Peak memory 203524 kb
Host smart-77397ec9-3f88-4412-94e3-32515de63669
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127158176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.127158176
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.4124416584
Short name T1165
Test name
Test status
Simulation time 175366896 ps
CPU time 1.64 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:26 PM PDT 24
Peak memory 203640 kb
Host smart-10221ca1-f4b3-4df2-809c-553a1deeda5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124416584 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.4124416584
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1869046768
Short name T168
Test name
Test status
Simulation time 24452490 ps
CPU time 0.72 seconds
Started Mar 26 01:21:27 PM PDT 24
Finished Mar 26 01:21:28 PM PDT 24
Peak memory 203496 kb
Host smart-a6768ebc-fcb7-4725-9c08-5a070898cc09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869046768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1869046768
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1717883853
Short name T1141
Test name
Test status
Simulation time 66228657 ps
CPU time 0.64 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:23 PM PDT 24
Peak memory 203296 kb
Host smart-39326fea-0bc6-453f-b48f-f4c04b8b3033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717883853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1717883853
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3530320515
Short name T85
Test name
Test status
Simulation time 32491288 ps
CPU time 0.75 seconds
Started Mar 26 01:21:26 PM PDT 24
Finished Mar 26 01:21:27 PM PDT 24
Peak memory 203532 kb
Host smart-575d19be-94f2-4e91-9ef2-6d007e577d93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530320515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3530320515
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3936520613
Short name T142
Test name
Test status
Simulation time 249476735 ps
CPU time 1.75 seconds
Started Mar 26 01:21:23 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203548 kb
Host smart-96d754a3-556d-4e20-a376-68fbe242bec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936520613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3936520613
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2216418030
Short name T1149
Test name
Test status
Simulation time 15706043 ps
CPU time 0.64 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:12 PM PDT 24
Peak memory 203324 kb
Host smart-b096811d-ed5c-4207-baf6-750ea5d63a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216418030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2216418030
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.3498849203
Short name T1160
Test name
Test status
Simulation time 18022646 ps
CPU time 0.66 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:12 PM PDT 24
Peak memory 203352 kb
Host smart-91d034bc-c09e-4147-a252-ef2370a78e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498849203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3498849203
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1221552075
Short name T1181
Test name
Test status
Simulation time 52174212 ps
CPU time 0.65 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:05 PM PDT 24
Peak memory 203296 kb
Host smart-27f084df-0b6f-42d5-a624-076df123d83a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221552075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1221552075
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3667434459
Short name T1205
Test name
Test status
Simulation time 24652442 ps
CPU time 0.66 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:08 PM PDT 24
Peak memory 203576 kb
Host smart-c2887b39-cc4f-454f-be9e-53c16c59fb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667434459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3667434459
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.421400427
Short name T1201
Test name
Test status
Simulation time 172938664 ps
CPU time 0.67 seconds
Started Mar 26 01:22:01 PM PDT 24
Finished Mar 26 01:22:02 PM PDT 24
Peak memory 203320 kb
Host smart-c43ccb22-f3ff-4577-bc6a-cbbf03f54aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421400427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.421400427
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3556450348
Short name T1112
Test name
Test status
Simulation time 29729488 ps
CPU time 0.68 seconds
Started Mar 26 01:22:02 PM PDT 24
Finished Mar 26 01:22:03 PM PDT 24
Peak memory 203448 kb
Host smart-b880696b-9250-4d25-b49c-e634085b6a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556450348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3556450348
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2783248511
Short name T248
Test name
Test status
Simulation time 39366987 ps
CPU time 0.65 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:11 PM PDT 24
Peak memory 203352 kb
Host smart-ee94545d-c9b8-4b64-9cf5-7c287df8607f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783248511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2783248511
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2086285412
Short name T250
Test name
Test status
Simulation time 26498941 ps
CPU time 0.64 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:12 PM PDT 24
Peak memory 203352 kb
Host smart-2eab8cea-4a63-4c7d-9496-e5c0dba7151c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086285412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2086285412
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.941067146
Short name T1118
Test name
Test status
Simulation time 49615248 ps
CPU time 0.66 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:05 PM PDT 24
Peak memory 203292 kb
Host smart-e89b4109-9619-4da4-a4c9-1851ef187bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941067146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.941067146
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1400766186
Short name T154
Test name
Test status
Simulation time 169471678 ps
CPU time 1.12 seconds
Started Mar 26 01:21:33 PM PDT 24
Finished Mar 26 01:21:34 PM PDT 24
Peak memory 203556 kb
Host smart-8aed05d2-d9aa-4a29-a849-efcc617eb486
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400766186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1400766186
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3334029716
Short name T1203
Test name
Test status
Simulation time 1095666498 ps
CPU time 2.66 seconds
Started Mar 26 01:21:30 PM PDT 24
Finished Mar 26 01:21:33 PM PDT 24
Peak memory 203504 kb
Host smart-c5d852e6-4b87-4a6c-9a6e-eaea79b9a39e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334029716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3334029716
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.139066852
Short name T229
Test name
Test status
Simulation time 32735878 ps
CPU time 0.69 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:24 PM PDT 24
Peak memory 203392 kb
Host smart-76a9c791-841c-4c6f-b9ec-4c4cc07b0596
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139066852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.139066852
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.291112815
Short name T1157
Test name
Test status
Simulation time 115459177 ps
CPU time 1.07 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203524 kb
Host smart-67d96dd9-9e05-4c0e-97f8-b289d48b6cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291112815 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.291112815
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2574514758
Short name T1183
Test name
Test status
Simulation time 25763465 ps
CPU time 0.78 seconds
Started Mar 26 01:21:26 PM PDT 24
Finished Mar 26 01:21:27 PM PDT 24
Peak memory 203384 kb
Host smart-3009cee9-5cd3-4d06-9c12-fee842b11c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574514758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2574514758
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1541425232
Short name T1173
Test name
Test status
Simulation time 76501594 ps
CPU time 0.66 seconds
Started Mar 26 01:21:24 PM PDT 24
Finished Mar 26 01:21:25 PM PDT 24
Peak memory 203436 kb
Host smart-c354ecff-d9e3-4b9a-890a-01970ca61f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541425232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1541425232
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1014486341
Short name T1114
Test name
Test status
Simulation time 70191539 ps
CPU time 1 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203820 kb
Host smart-e74c0aa3-9696-46c2-bf45-95e8ab432e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014486341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1014486341
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3988606206
Short name T1145
Test name
Test status
Simulation time 50823886 ps
CPU time 2.46 seconds
Started Mar 26 01:21:26 PM PDT 24
Finished Mar 26 01:21:29 PM PDT 24
Peak memory 203580 kb
Host smart-e9be67a2-7420-4617-9658-e79687375cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988606206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3988606206
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1224852660
Short name T145
Test name
Test status
Simulation time 48811440 ps
CPU time 1.35 seconds
Started Mar 26 01:21:27 PM PDT 24
Finished Mar 26 01:21:29 PM PDT 24
Peak memory 203484 kb
Host smart-1d79a12c-fb72-4d8b-81c2-169e9617746f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224852660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1224852660
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1637413517
Short name T1190
Test name
Test status
Simulation time 21249542 ps
CPU time 0.69 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:06 PM PDT 24
Peak memory 203348 kb
Host smart-1c82bad9-df51-4b80-985c-2b0de7174f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637413517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1637413517
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.933743319
Short name T1180
Test name
Test status
Simulation time 17186124 ps
CPU time 0.64 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203352 kb
Host smart-ae6ccb64-0c23-4468-b9cc-6772c0f4fb08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933743319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.933743319
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.689334440
Short name T1159
Test name
Test status
Simulation time 21730298 ps
CPU time 0.65 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203308 kb
Host smart-7f2107d0-6bb8-42b5-9fb4-c022a7ba4db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689334440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.689334440
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1477681286
Short name T1151
Test name
Test status
Simulation time 36777474 ps
CPU time 0.65 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:05 PM PDT 24
Peak memory 203436 kb
Host smart-95765df6-ba4b-412a-b4bb-3b628d4bbb9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477681286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1477681286
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1367703642
Short name T1186
Test name
Test status
Simulation time 78726437 ps
CPU time 0.65 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:11 PM PDT 24
Peak memory 203320 kb
Host smart-500a2811-fdae-4029-938d-62744cddb7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367703642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1367703642
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.506774698
Short name T1128
Test name
Test status
Simulation time 14289829 ps
CPU time 0.69 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:06 PM PDT 24
Peak memory 203392 kb
Host smart-3221f1f8-8f54-47e4-aace-339c1c03f368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506774698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.506774698
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1042969979
Short name T1125
Test name
Test status
Simulation time 34600400 ps
CPU time 0.69 seconds
Started Mar 26 01:22:05 PM PDT 24
Finished Mar 26 01:22:07 PM PDT 24
Peak memory 203396 kb
Host smart-c386aba4-3a1f-45fa-a6e7-a088af9bba94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042969979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1042969979
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3279190748
Short name T1120
Test name
Test status
Simulation time 21594845 ps
CPU time 0.68 seconds
Started Mar 26 01:22:01 PM PDT 24
Finished Mar 26 01:22:02 PM PDT 24
Peak memory 203280 kb
Host smart-43e6a5c2-3d15-413e-ad3e-3b471f0a37fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279190748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3279190748
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.692037597
Short name T191
Test name
Test status
Simulation time 17022874 ps
CPU time 0.67 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:11 PM PDT 24
Peak memory 203444 kb
Host smart-727349d8-3a07-49a1-9e34-addcc76c07ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692037597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.692037597
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1398850037
Short name T1200
Test name
Test status
Simulation time 51487772 ps
CPU time 0.64 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:04 PM PDT 24
Peak memory 203384 kb
Host smart-17df8a1c-76bd-409a-8983-f610791f7423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398850037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1398850037
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3142365091
Short name T158
Test name
Test status
Simulation time 198447022 ps
CPU time 1.1 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:39 PM PDT 24
Peak memory 203540 kb
Host smart-a3ac8c57-e517-43ba-9e0c-ea7db637e4cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142365091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3142365091
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.4275794154
Short name T84
Test name
Test status
Simulation time 64833644 ps
CPU time 2.51 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:38 PM PDT 24
Peak memory 203504 kb
Host smart-3e8ab18b-4876-4112-a750-c5ac5e0fe35a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275794154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.4275794154
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.396791417
Short name T157
Test name
Test status
Simulation time 59914266 ps
CPU time 0.76 seconds
Started Mar 26 01:21:33 PM PDT 24
Finished Mar 26 01:21:34 PM PDT 24
Peak memory 203540 kb
Host smart-5cf84e99-dff2-4925-9c50-eb7c870bdb39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396791417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.396791417
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1284848616
Short name T1174
Test name
Test status
Simulation time 133876018 ps
CPU time 1.12 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:38 PM PDT 24
Peak memory 203560 kb
Host smart-aa1ca065-7c37-4cb6-9dd3-0db1f82bb700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284848616 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1284848616
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2649761703
Short name T1167
Test name
Test status
Simulation time 26144605 ps
CPU time 0.72 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203496 kb
Host smart-102580af-dbb6-4c62-b3de-033fa0af109d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649761703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2649761703
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3334781033
Short name T1202
Test name
Test status
Simulation time 18517752 ps
CPU time 0.66 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203344 kb
Host smart-7433fb50-2dad-4791-8a13-bb05f63f5d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334781033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3334781033
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.77456337
Short name T1179
Test name
Test status
Simulation time 177830502 ps
CPU time 1.01 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203476 kb
Host smart-2f64b234-c98c-43e0-9a41-f95d96b73a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77456337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outs
tanding.77456337
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3899823887
Short name T1193
Test name
Test status
Simulation time 87459219 ps
CPU time 1.99 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203560 kb
Host smart-fad11f3e-6648-4517-8098-2997a754bf47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899823887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3899823887
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4150768595
Short name T1139
Test name
Test status
Simulation time 17396936 ps
CPU time 0.68 seconds
Started Mar 26 01:22:03 PM PDT 24
Finished Mar 26 01:22:03 PM PDT 24
Peak memory 203348 kb
Host smart-0ce528e6-8190-4f0c-9826-02263c31e955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150768595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4150768595
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1000331207
Short name T1115
Test name
Test status
Simulation time 50162923 ps
CPU time 0.67 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 203360 kb
Host smart-30478055-73df-4ab7-b4d6-ba437e0b2c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000331207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1000331207
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.3522736737
Short name T190
Test name
Test status
Simulation time 52682401 ps
CPU time 0.64 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 203336 kb
Host smart-0b2b27c7-a28f-4a79-9e94-725b8db0e722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522736737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3522736737
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.318434949
Short name T247
Test name
Test status
Simulation time 17442139 ps
CPU time 0.65 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:05 PM PDT 24
Peak memory 203340 kb
Host smart-1518e27c-21cf-4df5-9653-cb25d6cc78b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318434949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.318434949
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.690078190
Short name T1150
Test name
Test status
Simulation time 43050412 ps
CPU time 0.66 seconds
Started Mar 26 01:22:08 PM PDT 24
Finished Mar 26 01:22:09 PM PDT 24
Peak memory 203324 kb
Host smart-26110ddb-f297-41c0-b975-d7e2799b8ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690078190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.690078190
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.4105542500
Short name T1171
Test name
Test status
Simulation time 32898111 ps
CPU time 0.66 seconds
Started Mar 26 01:22:10 PM PDT 24
Finished Mar 26 01:22:11 PM PDT 24
Peak memory 203352 kb
Host smart-8f4467cc-abb9-4be9-861d-596cbd3025eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105542500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.4105542500
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1453126705
Short name T1123
Test name
Test status
Simulation time 52106758 ps
CPU time 0.71 seconds
Started Mar 26 01:22:04 PM PDT 24
Finished Mar 26 01:22:06 PM PDT 24
Peak memory 203384 kb
Host smart-78199f2a-55a8-4279-a30c-5c9dd894168a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453126705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1453126705
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2409750176
Short name T189
Test name
Test status
Simulation time 21728694 ps
CPU time 0.67 seconds
Started Mar 26 01:22:13 PM PDT 24
Finished Mar 26 01:22:13 PM PDT 24
Peak memory 203336 kb
Host smart-1e78a19e-7fb6-4443-b228-26e569eb5215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409750176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2409750176
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.539420686
Short name T1111
Test name
Test status
Simulation time 25708395 ps
CPU time 0.61 seconds
Started Mar 26 01:22:07 PM PDT 24
Finished Mar 26 01:22:08 PM PDT 24
Peak memory 202940 kb
Host smart-f18eda14-08b8-4f4a-ab54-bbcb99b2d104
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539420686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.539420686
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.681101578
Short name T1153
Test name
Test status
Simulation time 49527082 ps
CPU time 0.65 seconds
Started Mar 26 01:22:11 PM PDT 24
Finished Mar 26 01:22:12 PM PDT 24
Peak memory 203308 kb
Host smart-9bf497c1-2573-4b4a-92ef-91857d1fcccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681101578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.681101578
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2149341706
Short name T1121
Test name
Test status
Simulation time 64500968 ps
CPU time 0.94 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:38 PM PDT 24
Peak memory 203512 kb
Host smart-1563e3a8-269f-4dd6-98b6-01ea60b6da95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149341706 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2149341706
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3153713113
Short name T1172
Test name
Test status
Simulation time 31595250 ps
CPU time 0.66 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203416 kb
Host smart-ef0e2b06-5911-4b65-a846-314ce7b4981d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153713113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3153713113
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4101043601
Short name T1194
Test name
Test status
Simulation time 47262219 ps
CPU time 1.06 seconds
Started Mar 26 01:21:33 PM PDT 24
Finished Mar 26 01:21:34 PM PDT 24
Peak memory 203472 kb
Host smart-2cbc52eb-bbb9-4801-8548-71b31534a6f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101043601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4101043601
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.4292040927
Short name T1124
Test name
Test status
Simulation time 131987698 ps
CPU time 1.15 seconds
Started Mar 26 01:21:32 PM PDT 24
Finished Mar 26 01:21:34 PM PDT 24
Peak memory 203576 kb
Host smart-0d2ed9fa-21d9-4940-b82d-034184eb5d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292040927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.4292040927
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2497707878
Short name T132
Test name
Test status
Simulation time 167233887 ps
CPU time 1.99 seconds
Started Mar 26 01:21:33 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203552 kb
Host smart-39453b64-dfac-4531-96b2-d015f4b3a8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497707878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2497707878
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.742306505
Short name T1156
Test name
Test status
Simulation time 33717361 ps
CPU time 1.39 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203628 kb
Host smart-4b487298-2a87-4c33-9f1b-3d631aa563cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742306505 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.742306505
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1590675870
Short name T153
Test name
Test status
Simulation time 18425032 ps
CPU time 0.76 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203640 kb
Host smart-336d5fee-9131-4563-b590-52180daf50a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590675870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1590675870
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.299432320
Short name T1185
Test name
Test status
Simulation time 16307249 ps
CPU time 0.65 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203420 kb
Host smart-5fbb9df4-02ab-43af-98b4-e67cc4179e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299432320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.299432320
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.786159395
Short name T1198
Test name
Test status
Simulation time 115441551 ps
CPU time 0.98 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203636 kb
Host smart-85bebf11-78c3-4a0e-93f7-bc90aaf669c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786159395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.786159395
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.480568516
Short name T1199
Test name
Test status
Simulation time 98967374 ps
CPU time 1.39 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:38 PM PDT 24
Peak memory 203624 kb
Host smart-1eef99d2-b467-4ad6-99bd-472f15790909
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480568516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.480568516
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.876788298
Short name T184
Test name
Test status
Simulation time 532227664 ps
CPU time 2.29 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:39 PM PDT 24
Peak memory 203548 kb
Host smart-6f09e9c1-14b5-4a9a-98bb-8887c3987b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876788298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.876788298
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1685112305
Short name T1110
Test name
Test status
Simulation time 46752925 ps
CPU time 1.16 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203652 kb
Host smart-de7b143f-fdc0-46a0-869d-22f4a1a7cf76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685112305 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1685112305
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2188785859
Short name T1206
Test name
Test status
Simulation time 20395143 ps
CPU time 0.68 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203140 kb
Host smart-e9292026-3392-42ef-b91f-0ddacf855d36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188785859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2188785859
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2654303887
Short name T1107
Test name
Test status
Simulation time 39198949 ps
CPU time 0.63 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203436 kb
Host smart-b975b4d8-bbf7-49e3-964d-0fdf94a0ef67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654303887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2654303887
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.400637466
Short name T166
Test name
Test status
Simulation time 70013505 ps
CPU time 0.79 seconds
Started Mar 26 01:21:33 PM PDT 24
Finished Mar 26 01:21:34 PM PDT 24
Peak memory 203344 kb
Host smart-54a5025b-3e87-4a17-8a03-889f67e7e46c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400637466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.400637466
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.380328060
Short name T1177
Test name
Test status
Simulation time 229213102 ps
CPU time 2.43 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:38 PM PDT 24
Peak memory 203560 kb
Host smart-8480d2f8-3c3d-41ed-b439-d89dc9aaf2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380328060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.380328060
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.498236830
Short name T1170
Test name
Test status
Simulation time 475590522 ps
CPU time 1.29 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203540 kb
Host smart-4698c4d2-0325-4aa3-900b-b5b0cac8c12b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498236830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.498236830
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2728453568
Short name T1117
Test name
Test status
Simulation time 26245737 ps
CPU time 1.11 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203584 kb
Host smart-12c37a3e-d2f5-48c3-8eda-2d303ecd43c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728453568 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2728453568
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1857478061
Short name T162
Test name
Test status
Simulation time 72864415 ps
CPU time 0.76 seconds
Started Mar 26 01:21:38 PM PDT 24
Finished Mar 26 01:21:39 PM PDT 24
Peak memory 203512 kb
Host smart-0552e1bf-037a-4279-82b5-d6c0c0cdb482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857478061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1857478061
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3044114320
Short name T1127
Test name
Test status
Simulation time 49045896 ps
CPU time 0.65 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203244 kb
Host smart-d866add3-a09d-4778-9ce5-fae8fe6b3195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044114320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3044114320
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2946708555
Short name T1163
Test name
Test status
Simulation time 28242177 ps
CPU time 1.09 seconds
Started Mar 26 01:21:35 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203580 kb
Host smart-c37fd162-6340-46a6-8fe0-78f84f4df750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946708555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2946708555
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1825657294
Short name T129
Test name
Test status
Simulation time 23970475 ps
CPU time 1.07 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203588 kb
Host smart-4ccca4b8-cfca-459b-9c43-ecec30104527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825657294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1825657294
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1979105823
Short name T143
Test name
Test status
Simulation time 1141374613 ps
CPU time 2.03 seconds
Started Mar 26 01:21:33 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203508 kb
Host smart-a92a9727-8bd7-4a41-a728-81c43f25ccf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979105823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1979105823
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4270818572
Short name T1143
Test name
Test status
Simulation time 25774110 ps
CPU time 1.21 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:35 PM PDT 24
Peak memory 203612 kb
Host smart-3143a838-ab51-4e67-ba03-03b97a5ad265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270818572 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.4270818572
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3730550216
Short name T1144
Test name
Test status
Simulation time 130719499 ps
CPU time 0.65 seconds
Started Mar 26 01:21:32 PM PDT 24
Finished Mar 26 01:21:32 PM PDT 24
Peak memory 203172 kb
Host smart-9b8b2d8e-ee7f-4616-a36b-0b2bea515711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730550216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3730550216
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2738565616
Short name T1158
Test name
Test status
Simulation time 18302473 ps
CPU time 0.64 seconds
Started Mar 26 01:21:36 PM PDT 24
Finished Mar 26 01:21:37 PM PDT 24
Peak memory 203336 kb
Host smart-faffca76-da86-44c6-992d-afb72d717710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738565616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2738565616
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2617264161
Short name T167
Test name
Test status
Simulation time 52501686 ps
CPU time 1.08 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:38 PM PDT 24
Peak memory 203512 kb
Host smart-acfb832c-a146-4ac4-b5d2-41e967730ffd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617264161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2617264161
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1818472944
Short name T1119
Test name
Test status
Simulation time 44162653 ps
CPU time 2.35 seconds
Started Mar 26 01:21:37 PM PDT 24
Finished Mar 26 01:21:39 PM PDT 24
Peak memory 203608 kb
Host smart-7ceacabe-67d5-44bf-9a35-8ed156c3e038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818472944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1818472944
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3289342270
Short name T112
Test name
Test status
Simulation time 900275614 ps
CPU time 2.08 seconds
Started Mar 26 01:21:34 PM PDT 24
Finished Mar 26 01:21:36 PM PDT 24
Peak memory 203548 kb
Host smart-c36b5c57-b0ed-4db0-99ca-551175609459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289342270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3289342270
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.931311765
Short name T819
Test name
Test status
Simulation time 18824205 ps
CPU time 0.62 seconds
Started Mar 26 01:12:13 PM PDT 24
Finished Mar 26 01:12:13 PM PDT 24
Peak memory 203720 kb
Host smart-d89eab99-9304-4bb8-afe6-b307e3de1d37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931311765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.931311765
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.72344661
Short name T127
Test name
Test status
Simulation time 371054175 ps
CPU time 4.2 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:12:19 PM PDT 24
Peak memory 229660 kb
Host smart-66a8ba9e-7d13-49e6-aa51-4e6ed7c64cff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72344661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.72344661
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2494074718
Short name T66
Test name
Test status
Simulation time 3573848868 ps
CPU time 114.02 seconds
Started Mar 26 01:12:18 PM PDT 24
Finished Mar 26 01:14:12 PM PDT 24
Peak memory 605088 kb
Host smart-7080e8b1-de6c-4847-97d5-ea820a363e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494074718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2494074718
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2025882581
Short name T959
Test name
Test status
Simulation time 11048437845 ps
CPU time 82.35 seconds
Started Mar 26 01:12:15 PM PDT 24
Finished Mar 26 01:13:37 PM PDT 24
Peak memory 756392 kb
Host smart-2be1bf61-adbe-496f-82b9-054157b9b497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025882581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2025882581
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2853030994
Short name T937
Test name
Test status
Simulation time 138764944 ps
CPU time 7.5 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:12:23 PM PDT 24
Peak memory 204096 kb
Host smart-c21ce15b-5177-48c2-a0b8-fe742a75c114
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853030994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2853030994
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1229342583
Short name T743
Test name
Test status
Simulation time 18188797409 ps
CPU time 89.5 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:13:46 PM PDT 24
Peak memory 929624 kb
Host smart-c78288a9-f864-4410-8dbb-912ceac17bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229342583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1229342583
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_override.1955483555
Short name T396
Test name
Test status
Simulation time 176927521 ps
CPU time 0.67 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:12:17 PM PDT 24
Peak memory 203720 kb
Host smart-d9421f0e-5af9-435c-baa7-ec92020f5f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955483555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1955483555
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1760629772
Short name T44
Test name
Test status
Simulation time 12635248880 ps
CPU time 330.36 seconds
Started Mar 26 01:12:15 PM PDT 24
Finished Mar 26 01:17:45 PM PDT 24
Peak memory 537448 kb
Host smart-d85991d0-ab8a-4032-8cb6-7a5497d5d9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760629772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1760629772
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1693191871
Short name T576
Test name
Test status
Simulation time 1660716038 ps
CPU time 79.93 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:13:34 PM PDT 24
Peak memory 363088 kb
Host smart-827e148f-b0e5-404e-b166-1ffd72e03679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693191871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1693191871
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.4114301104
Short name T118
Test name
Test status
Simulation time 70865692 ps
CPU time 0.83 seconds
Started Mar 26 01:12:15 PM PDT 24
Finished Mar 26 01:12:16 PM PDT 24
Peak memory 221280 kb
Host smart-1ed932a1-9bd8-483c-adcd-128cf4d277b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114301104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.4114301104
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3066467454
Short name T988
Test name
Test status
Simulation time 3825460355 ps
CPU time 2.92 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:12:19 PM PDT 24
Peak memory 204332 kb
Host smart-fd12db97-9fd2-4082-baa8-8d0d4799e316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066467454 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3066467454
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3200463026
Short name T496
Test name
Test status
Simulation time 10146758855 ps
CPU time 83.9 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:13:38 PM PDT 24
Peak memory 609580 kb
Host smart-cd8b6259-445b-4a95-a31b-e156c5088949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200463026 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3200463026
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3805749753
Short name T581
Test name
Test status
Simulation time 10078355019 ps
CPU time 13.94 seconds
Started Mar 26 01:12:13 PM PDT 24
Finished Mar 26 01:12:27 PM PDT 24
Peak memory 308176 kb
Host smart-4727d237-5eeb-4516-97e4-4dbf316c40c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805749753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3805749753
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3691746691
Short name T230
Test name
Test status
Simulation time 1142812689 ps
CPU time 3.27 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:12:17 PM PDT 24
Peak memory 204164 kb
Host smart-464b8c67-3a7f-4945-aa70-06b588a619dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691746691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3691746691
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1077228092
Short name T54
Test name
Test status
Simulation time 5029356301 ps
CPU time 6.74 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:12:21 PM PDT 24
Peak memory 212508 kb
Host smart-f584994a-1a5d-4e73-8034-ab7999d375ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077228092 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1077228092
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.561911503
Short name T703
Test name
Test status
Simulation time 4506836184 ps
CPU time 39.44 seconds
Started Mar 26 01:12:15 PM PDT 24
Finished Mar 26 01:12:55 PM PDT 24
Peak memory 204152 kb
Host smart-7055f888-a62f-4cdf-93ea-443bcb7f5e63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561911503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targ
et_smoke.561911503
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2416882714
Short name T505
Test name
Test status
Simulation time 1694045681 ps
CPU time 38.43 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:12:53 PM PDT 24
Peak memory 204128 kb
Host smart-dc0d3193-a59e-4fcc-8076-6639038d707e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416882714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2416882714
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2078094262
Short name T300
Test name
Test status
Simulation time 17089603730 ps
CPU time 258.99 seconds
Started Mar 26 01:12:15 PM PDT 24
Finished Mar 26 01:16:35 PM PDT 24
Peak memory 2132824 kb
Host smart-31d62fe2-d0b2-43cf-a61b-2b37f9e92661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078094262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2078094262
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.687074632
Short name T346
Test name
Test status
Simulation time 1160920773 ps
CPU time 6.39 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:12:23 PM PDT 24
Peak memory 204136 kb
Host smart-77ee8345-5389-4d15-b612-0765940fd599
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687074632 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.687074632
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3387050019
Short name T18
Test name
Test status
Simulation time 49447519 ps
CPU time 1.63 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:12:18 PM PDT 24
Peak memory 212324 kb
Host smart-1a1ab226-f21b-42d3-b54e-ade5cd52eaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387050019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3387050019
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2148939097
Short name T647
Test name
Test status
Simulation time 344581445 ps
CPU time 3.35 seconds
Started Mar 26 01:12:20 PM PDT 24
Finished Mar 26 01:12:23 PM PDT 24
Peak memory 237676 kb
Host smart-628962b7-0e63-4915-a053-3801f95280f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148939097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2148939097
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.358463125
Short name T73
Test name
Test status
Simulation time 9717872283 ps
CPU time 181.3 seconds
Started Mar 26 01:12:16 PM PDT 24
Finished Mar 26 01:15:18 PM PDT 24
Peak memory 786352 kb
Host smart-3d550288-9e49-4815-b032-ac87db3c3558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358463125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.358463125
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1498057952
Short name T549
Test name
Test status
Simulation time 7907998826 ps
CPU time 137.9 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:14:32 PM PDT 24
Peak memory 657648 kb
Host smart-63b77e4b-122e-49eb-805b-4273d7cc95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498057952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1498057952
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3215977864
Short name T1048
Test name
Test status
Simulation time 150562018 ps
CPU time 7.86 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:12:22 PM PDT 24
Peak memory 204040 kb
Host smart-d9997fe1-6fe2-4b2c-bb90-25255dba727d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215977864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3215977864
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2176324564
Short name T606
Test name
Test status
Simulation time 3353174931 ps
CPU time 238.12 seconds
Started Mar 26 01:12:15 PM PDT 24
Finished Mar 26 01:16:13 PM PDT 24
Peak memory 1004920 kb
Host smart-80322083-79ca-4f60-99f1-938a69c64b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176324564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2176324564
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_override.937167698
Short name T1012
Test name
Test status
Simulation time 70900496 ps
CPU time 0.65 seconds
Started Mar 26 01:12:18 PM PDT 24
Finished Mar 26 01:12:19 PM PDT 24
Peak memory 203792 kb
Host smart-5301d20b-a961-4d86-8090-8739e8c395e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937167698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.937167698
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.479953129
Short name T42
Test name
Test status
Simulation time 574893875 ps
CPU time 5.8 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:12:20 PM PDT 24
Peak memory 220508 kb
Host smart-20e30398-09b1-4936-b615-69ef88592403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479953129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.479953129
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3900849707
Short name T847
Test name
Test status
Simulation time 2561550126 ps
CPU time 39.18 seconds
Started Mar 26 01:12:18 PM PDT 24
Finished Mar 26 01:12:58 PM PDT 24
Peak memory 308884 kb
Host smart-74d67a37-a08d-4f41-8b34-a1f5c744154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900849707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3900849707
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.3035288924
Short name T171
Test name
Test status
Simulation time 12291335529 ps
CPU time 247.63 seconds
Started Mar 26 01:12:20 PM PDT 24
Finished Mar 26 01:16:27 PM PDT 24
Peak memory 619544 kb
Host smart-f9227224-fb1c-4af3-b6ab-ae5e2adda7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035288924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.3035288924
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2386807188
Short name T117
Test name
Test status
Simulation time 66745060 ps
CPU time 0.94 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:12:30 PM PDT 24
Peak memory 222300 kb
Host smart-ccf2efe5-a3f4-4ae5-a610-74c428cfd21c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386807188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2386807188
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1500067746
Short name T23
Test name
Test status
Simulation time 1098351431 ps
CPU time 4.89 seconds
Started Mar 26 01:12:19 PM PDT 24
Finished Mar 26 01:12:24 PM PDT 24
Peak memory 204108 kb
Host smart-4f30543d-efb6-4576-ad99-fe6dce849cc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500067746 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1500067746
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3110399974
Short name T692
Test name
Test status
Simulation time 10059415072 ps
CPU time 77.25 seconds
Started Mar 26 01:12:21 PM PDT 24
Finished Mar 26 01:13:38 PM PDT 24
Peak memory 580256 kb
Host smart-e31085e3-1da3-4e5e-b5ad-432973712877
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110399974 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3110399974
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.685196444
Short name T567
Test name
Test status
Simulation time 10855521070 ps
CPU time 7.23 seconds
Started Mar 26 01:12:20 PM PDT 24
Finished Mar 26 01:12:28 PM PDT 24
Peak memory 266996 kb
Host smart-d9b1d783-2b35-4a04-b89f-c78e8a39568a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685196444 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.685196444
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.1413533267
Short name T412
Test name
Test status
Simulation time 1725458315 ps
CPU time 2.6 seconds
Started Mar 26 01:12:20 PM PDT 24
Finished Mar 26 01:12:22 PM PDT 24
Peak memory 204172 kb
Host smart-992d80a1-1f77-41f7-ad83-542b74f33a67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413533267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.1413533267
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.228603670
Short name T588
Test name
Test status
Simulation time 4513716289 ps
CPU time 5.58 seconds
Started Mar 26 01:12:20 PM PDT 24
Finished Mar 26 01:12:26 PM PDT 24
Peak memory 210324 kb
Host smart-12e42220-7c6d-4c7a-a0cd-0a6056478d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228603670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.228603670
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3902801867
Short name T546
Test name
Test status
Simulation time 947351806 ps
CPU time 11.73 seconds
Started Mar 26 01:12:19 PM PDT 24
Finished Mar 26 01:12:31 PM PDT 24
Peak memory 204176 kb
Host smart-7510f718-64f0-4510-bfa3-f1ffa293fc56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902801867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3902801867
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2881251446
Short name T726
Test name
Test status
Simulation time 1026036717 ps
CPU time 18.25 seconds
Started Mar 26 01:12:20 PM PDT 24
Finished Mar 26 01:12:38 PM PDT 24
Peak memory 210212 kb
Host smart-cae61d84-6596-4890-807b-733af6294b10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881251446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2881251446
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2005754399
Short name T360
Test name
Test status
Simulation time 29185945986 ps
CPU time 185.62 seconds
Started Mar 26 01:12:14 PM PDT 24
Finished Mar 26 01:15:20 PM PDT 24
Peak memory 1650480 kb
Host smart-d96fa25d-1c13-44b9-a715-f925cfcc33ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005754399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2005754399
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1502309133
Short name T1039
Test name
Test status
Simulation time 1207865691 ps
CPU time 7.01 seconds
Started Mar 26 01:12:20 PM PDT 24
Finished Mar 26 01:12:28 PM PDT 24
Peak memory 211104 kb
Host smart-c3ef87e3-9a34-41a3-9978-4b01640186c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502309133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1502309133
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3336681229
Short name T750
Test name
Test status
Simulation time 17953998 ps
CPU time 0.62 seconds
Started Mar 26 01:13:45 PM PDT 24
Finished Mar 26 01:13:45 PM PDT 24
Peak memory 203728 kb
Host smart-16ab075a-ea83-4353-abce-add3296fcf06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336681229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3336681229
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2551626466
Short name T992
Test name
Test status
Simulation time 156330544 ps
CPU time 1.44 seconds
Started Mar 26 01:13:35 PM PDT 24
Finished Mar 26 01:13:36 PM PDT 24
Peak memory 212396 kb
Host smart-e9b5af99-699a-4a92-bdb6-460edd69aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551626466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2551626466
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.359771988
Short name T1078
Test name
Test status
Simulation time 5704375265 ps
CPU time 5.85 seconds
Started Mar 26 01:13:34 PM PDT 24
Finished Mar 26 01:13:40 PM PDT 24
Peak memory 262940 kb
Host smart-e37fc9cf-c58e-4c96-94a3-d1bf761ff8f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359771988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.359771988
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.44969557
Short name T359
Test name
Test status
Simulation time 3516904215 ps
CPU time 119.77 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:15:33 PM PDT 24
Peak memory 643140 kb
Host smart-4e420fcf-7a8c-4f52-a446-65f5cada2e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44969557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.44969557
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.3290553798
Short name T433
Test name
Test status
Simulation time 9196614938 ps
CPU time 89.7 seconds
Started Mar 26 01:13:35 PM PDT 24
Finished Mar 26 01:15:05 PM PDT 24
Peak memory 778592 kb
Host smart-6c24b2f1-9292-4d0f-a2c9-e564f2ca4e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290553798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.3290553798
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.4243982295
Short name T1030
Test name
Test status
Simulation time 165592462 ps
CPU time 0.97 seconds
Started Mar 26 01:13:34 PM PDT 24
Finished Mar 26 01:13:35 PM PDT 24
Peak memory 203928 kb
Host smart-f99995fa-77b4-45fa-ba20-8c586c1f614e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243982295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.4243982295
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1344518980
Short name T100
Test name
Test status
Simulation time 353755151 ps
CPU time 4.18 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:13:37 PM PDT 24
Peak memory 234332 kb
Host smart-46b07eb4-7a4d-4241-a2da-ed7277dfbc47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344518980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1344518980
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_override.2590028213
Short name T315
Test name
Test status
Simulation time 25390679 ps
CPU time 0.64 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:13:34 PM PDT 24
Peak memory 203776 kb
Host smart-1ea1083f-b050-4ef7-8a62-25910e7cb384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590028213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2590028213
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.2405420878
Short name T696
Test name
Test status
Simulation time 604069237 ps
CPU time 5.97 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:13:39 PM PDT 24
Peak memory 220600 kb
Host smart-52fabec8-1d4e-493f-be52-d5ec776f3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405420878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2405420878
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.114413234
Short name T1054
Test name
Test status
Simulation time 1506868202 ps
CPU time 126.74 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:15:40 PM PDT 24
Peak memory 289728 kb
Host smart-14ff7527-a08b-4bbe-ba71-00d0dbd6346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114413234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.114413234
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2832198549
Short name T572
Test name
Test status
Simulation time 8670461699 ps
CPU time 2.55 seconds
Started Mar 26 01:13:51 PM PDT 24
Finished Mar 26 01:13:54 PM PDT 24
Peak memory 204324 kb
Host smart-c69db1eb-9ecd-47c0-9bb8-cb10bd3d16b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832198549 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2832198549
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1054481118
Short name T863
Test name
Test status
Simulation time 10248824058 ps
CPU time 33.84 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:14:07 PM PDT 24
Peak memory 407400 kb
Host smart-5fad1e7c-a156-4b6f-8aad-ebf1753fa831
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054481118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1054481118
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.27968041
Short name T76
Test name
Test status
Simulation time 10612889245 ps
CPU time 15.99 seconds
Started Mar 26 01:13:34 PM PDT 24
Finished Mar 26 01:13:50 PM PDT 24
Peak memory 343544 kb
Host smart-0cff7f36-4512-4118-8c39-1d7f5fb4920c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968041 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_fifo_reset_tx.27968041
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1153382539
Short name T957
Test name
Test status
Simulation time 5430268334 ps
CPU time 6.96 seconds
Started Mar 26 01:13:36 PM PDT 24
Finished Mar 26 01:13:43 PM PDT 24
Peak memory 219000 kb
Host smart-2ca5dfee-ffa7-46d6-9036-e5dabd302796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153382539 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1153382539
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2186017030
Short name T717
Test name
Test status
Simulation time 3551155023 ps
CPU time 14.11 seconds
Started Mar 26 01:13:34 PM PDT 24
Finished Mar 26 01:13:48 PM PDT 24
Peak memory 204228 kb
Host smart-d1f8c826-c4fc-4526-b7ba-c67bc9a035d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186017030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2186017030
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2713013908
Short name T4
Test name
Test status
Simulation time 1101488773 ps
CPU time 4.55 seconds
Started Mar 26 01:13:32 PM PDT 24
Finished Mar 26 01:13:37 PM PDT 24
Peak memory 204172 kb
Host smart-032b6e40-0637-4185-9f5e-d35eae2bfba6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713013908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2713013908
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.258496535
Short name T791
Test name
Test status
Simulation time 36867331185 ps
CPU time 953.75 seconds
Started Mar 26 01:13:36 PM PDT 24
Finished Mar 26 01:29:30 PM PDT 24
Peak memory 2164200 kb
Host smart-762c8d63-7aee-49f0-8d1b-d00e8baed8a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258496535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.258496535
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2341206637
Short name T744
Test name
Test status
Simulation time 4643455908 ps
CPU time 6.6 seconds
Started Mar 26 01:13:32 PM PDT 24
Finished Mar 26 01:13:39 PM PDT 24
Peak memory 210528 kb
Host smart-e14c5e19-c547-401e-8a0c-0fb9476ab489
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341206637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2341206637
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2155397599
Short name T868
Test name
Test status
Simulation time 18750333 ps
CPU time 0.62 seconds
Started Mar 26 01:13:52 PM PDT 24
Finished Mar 26 01:13:53 PM PDT 24
Peak memory 203700 kb
Host smart-8fd0dbdd-9375-45c6-87fc-db0cbdd27208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155397599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2155397599
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.455358520
Short name T302
Test name
Test status
Simulation time 49352357 ps
CPU time 1.44 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:13:48 PM PDT 24
Peak memory 212236 kb
Host smart-3a7982d2-3243-46a8-86a5-d9e029967e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455358520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.455358520
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2361059916
Short name T349
Test name
Test status
Simulation time 286257604 ps
CPU time 5.19 seconds
Started Mar 26 01:13:55 PM PDT 24
Finished Mar 26 01:14:01 PM PDT 24
Peak memory 261876 kb
Host smart-942f9bb0-f74d-4fb7-bd80-509401ffc08e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361059916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2361059916
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.693298029
Short name T982
Test name
Test status
Simulation time 2108370804 ps
CPU time 152.12 seconds
Started Mar 26 01:13:44 PM PDT 24
Finished Mar 26 01:16:16 PM PDT 24
Peak memory 712064 kb
Host smart-162d90ec-cd8d-45e9-8def-8b500fa8bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693298029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.693298029
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3027422997
Short name T669
Test name
Test status
Simulation time 1946294508 ps
CPU time 67.38 seconds
Started Mar 26 01:13:47 PM PDT 24
Finished Mar 26 01:14:54 PM PDT 24
Peak memory 668112 kb
Host smart-027d73fb-a407-466d-9451-3f54b1c54496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027422997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3027422997
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2383101269
Short name T334
Test name
Test status
Simulation time 270784606 ps
CPU time 0.99 seconds
Started Mar 26 01:13:45 PM PDT 24
Finished Mar 26 01:13:47 PM PDT 24
Peak memory 203820 kb
Host smart-eb7dbfdb-57ce-4625-a3c4-6e2f7c922274
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383101269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2383101269
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3526691377
Short name T877
Test name
Test status
Simulation time 130956539 ps
CPU time 3.21 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:13:49 PM PDT 24
Peak memory 224968 kb
Host smart-115f43d6-a81f-4039-8c51-45e0c9b1a2b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526691377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3526691377
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1700188288
Short name T181
Test name
Test status
Simulation time 18827896562 ps
CPU time 113 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:15:39 PM PDT 24
Peak memory 1283272 kb
Host smart-28b7173a-6ac4-43ad-8531-b4c93f4c13f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700188288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1700188288
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_perf.613340729
Short name T925
Test name
Test status
Simulation time 502346129 ps
CPU time 8.17 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:13:54 PM PDT 24
Peak memory 212368 kb
Host smart-4a63e5a9-2df4-4219-adc4-da4fcfd9e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613340729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.613340729
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.4285637650
Short name T872
Test name
Test status
Simulation time 6469289674 ps
CPU time 66.63 seconds
Started Mar 26 01:13:48 PM PDT 24
Finished Mar 26 01:14:55 PM PDT 24
Peak memory 317140 kb
Host smart-73c19297-215d-4383-a50f-73187c192fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285637650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.4285637650
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1906497474
Short name T602
Test name
Test status
Simulation time 1220596710 ps
CPU time 5.25 seconds
Started Mar 26 01:13:47 PM PDT 24
Finished Mar 26 01:13:52 PM PDT 24
Peak memory 212380 kb
Host smart-e7e2f198-e709-4e62-ab60-aba92739c51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906497474 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1906497474
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2778558954
Short name T829
Test name
Test status
Simulation time 10414103641 ps
CPU time 10.9 seconds
Started Mar 26 01:13:52 PM PDT 24
Finished Mar 26 01:14:03 PM PDT 24
Peak memory 281192 kb
Host smart-fa4187c0-8ce1-4d23-862a-4b920caa8597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778558954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2778558954
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3574543068
Short name T443
Test name
Test status
Simulation time 10114132668 ps
CPU time 13 seconds
Started Mar 26 01:13:45 PM PDT 24
Finished Mar 26 01:13:58 PM PDT 24
Peak memory 317196 kb
Host smart-e2592264-4a1a-43f1-83ed-407f6afb5595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574543068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3574543068
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2124182071
Short name T388
Test name
Test status
Simulation time 492870717 ps
CPU time 2.66 seconds
Started Mar 26 01:13:47 PM PDT 24
Finished Mar 26 01:13:50 PM PDT 24
Peak memory 204156 kb
Host smart-f1a6c62d-a9f1-4974-9791-f4ed39e8227d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124182071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2124182071
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3996871809
Short name T81
Test name
Test status
Simulation time 4372469680 ps
CPU time 4.46 seconds
Started Mar 26 01:13:51 PM PDT 24
Finished Mar 26 01:13:56 PM PDT 24
Peak memory 204300 kb
Host smart-6a4a2969-696c-4e8b-8973-2b55622f5e15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996871809 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3996871809
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.1938039926
Short name T926
Test name
Test status
Simulation time 2184457536 ps
CPU time 23.1 seconds
Started Mar 26 01:13:47 PM PDT 24
Finished Mar 26 01:14:10 PM PDT 24
Peak memory 204276 kb
Host smart-c563106f-ac38-4055-9539-bf8c0ea9a761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938039926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.1938039926
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.4107815384
Short name T894
Test name
Test status
Simulation time 4481336117 ps
CPU time 11.38 seconds
Started Mar 26 01:13:55 PM PDT 24
Finished Mar 26 01:14:07 PM PDT 24
Peak memory 206436 kb
Host smart-f23370d1-6dea-4ae0-851c-256d7b32d561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107815384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.4107815384
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.3136298932
Short name T579
Test name
Test status
Simulation time 11454360349 ps
CPU time 24.12 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:14:10 PM PDT 24
Peak memory 204152 kb
Host smart-462d3bf1-72d6-4217-9773-1f96bdc555ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136298932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.3136298932
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1496652523
Short name T788
Test name
Test status
Simulation time 5339566445 ps
CPU time 129 seconds
Started Mar 26 01:13:51 PM PDT 24
Finished Mar 26 01:16:01 PM PDT 24
Peak memory 725392 kb
Host smart-313943ca-e646-4edb-8f48-5f730e9c0ed7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496652523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1496652523
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.4220857134
Short name T1097
Test name
Test status
Simulation time 5264474398 ps
CPU time 6.51 seconds
Started Mar 26 01:13:48 PM PDT 24
Finished Mar 26 01:13:55 PM PDT 24
Peak memory 212560 kb
Host smart-56134450-b9d7-49f8-a518-437d7b1b9558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220857134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.4220857134
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3227397151
Short name T395
Test name
Test status
Simulation time 15121746 ps
CPU time 0.6 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:13:58 PM PDT 24
Peak memory 203564 kb
Host smart-f2608617-2fba-4f63-8652-011dbe168ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227397151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3227397151
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3539066380
Short name T972
Test name
Test status
Simulation time 29107124 ps
CPU time 1.33 seconds
Started Mar 26 01:13:59 PM PDT 24
Finished Mar 26 01:14:00 PM PDT 24
Peak memory 212340 kb
Host smart-100740c6-760b-402d-81bc-932db6381eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539066380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3539066380
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.4141336646
Short name T1103
Test name
Test status
Simulation time 214501302 ps
CPU time 10.92 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:13:57 PM PDT 24
Peak memory 245344 kb
Host smart-944ffc37-c282-4e53-bc35-bf5aa3c88b84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141336646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.4141336646
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2949633214
Short name T16
Test name
Test status
Simulation time 1419084069 ps
CPU time 73.37 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:14:59 PM PDT 24
Peak memory 336416 kb
Host smart-f5963a05-3772-4a16-98e9-09f311d57205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949633214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2949633214
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3358809968
Short name T757
Test name
Test status
Simulation time 3841172740 ps
CPU time 55.98 seconds
Started Mar 26 01:13:47 PM PDT 24
Finished Mar 26 01:14:44 PM PDT 24
Peak memory 664328 kb
Host smart-cf0b6dd5-1db9-494e-87ce-e3e6e6aaa42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358809968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3358809968
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3754579339
Short name T879
Test name
Test status
Simulation time 69607211 ps
CPU time 0.86 seconds
Started Mar 26 01:13:51 PM PDT 24
Finished Mar 26 01:13:52 PM PDT 24
Peak memory 203960 kb
Host smart-c5b0407e-6d4b-4efd-a268-b7844acd11ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754579339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3754579339
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2143471746
Short name T1055
Test name
Test status
Simulation time 662577460 ps
CPU time 3.54 seconds
Started Mar 26 01:13:55 PM PDT 24
Finished Mar 26 01:13:59 PM PDT 24
Peak memory 226368 kb
Host smart-05c64932-2e42-439b-abbe-4c212c4ca420
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143471746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2143471746
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_perf.592712599
Short name T463
Test name
Test status
Simulation time 12643407716 ps
CPU time 292.86 seconds
Started Mar 26 01:13:46 PM PDT 24
Finished Mar 26 01:18:39 PM PDT 24
Peak memory 216940 kb
Host smart-0f3399dc-b60c-48e1-8d0d-b5a3a541aa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592712599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.592712599
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1560152257
Short name T994
Test name
Test status
Simulation time 18088794357 ps
CPU time 62.88 seconds
Started Mar 26 01:13:48 PM PDT 24
Finished Mar 26 01:14:52 PM PDT 24
Peak memory 324636 kb
Host smart-66a49162-8b92-4cda-86e0-94a64e52910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560152257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1560152257
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1588095194
Short name T1018
Test name
Test status
Simulation time 10963013406 ps
CPU time 4.18 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:14:02 PM PDT 24
Peak memory 204180 kb
Host smart-21a830c7-fdcf-4569-bbbb-826d808b94d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588095194 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1588095194
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.4237784918
Short name T1071
Test name
Test status
Simulation time 10039414234 ps
CPU time 87.04 seconds
Started Mar 26 01:13:57 PM PDT 24
Finished Mar 26 01:15:24 PM PDT 24
Peak memory 707288 kb
Host smart-2d2a773b-1b67-4b3f-b9dc-32f119249359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237784918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.4237784918
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3489362382
Short name T680
Test name
Test status
Simulation time 923056221 ps
CPU time 1.85 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:13:59 PM PDT 24
Peak memory 204040 kb
Host smart-383adf2f-31bd-4112-9311-271d145222bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489362382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3489362382
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.888746296
Short name T930
Test name
Test status
Simulation time 1054134861 ps
CPU time 4.88 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:14:04 PM PDT 24
Peak memory 205652 kb
Host smart-e16704ae-fee5-4f28-9ad1-f0977f2ded21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888746296 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.888746296
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3646796962
Short name T464
Test name
Test status
Simulation time 3830347413 ps
CPU time 4.53 seconds
Started Mar 26 01:13:59 PM PDT 24
Finished Mar 26 01:14:04 PM PDT 24
Peak memory 204352 kb
Host smart-76fcd5ff-a538-403d-8533-f9bdac0beab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646796962 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3646796962
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2113036913
Short name T108
Test name
Test status
Simulation time 4739292192 ps
CPU time 47.37 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:14:46 PM PDT 24
Peak memory 204184 kb
Host smart-96a67571-2441-457e-b951-7db4ff8c910c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113036913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2113036913
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.38011601
Short name T553
Test name
Test status
Simulation time 5656465715 ps
CPU time 26.75 seconds
Started Mar 26 01:13:59 PM PDT 24
Finished Mar 26 01:14:26 PM PDT 24
Peak memory 220264 kb
Host smart-b64c8cbf-d003-4057-942b-b8837a79827b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38011601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stress_rd.38011601
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1245421600
Short name T421
Test name
Test status
Simulation time 21551797642 ps
CPU time 12.66 seconds
Started Mar 26 01:14:05 PM PDT 24
Finished Mar 26 01:14:17 PM PDT 24
Peak memory 204192 kb
Host smart-6e1456e2-c006-430b-aca6-2cdeb7e492ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245421600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1245421600
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3541515580
Short name T272
Test name
Test status
Simulation time 30194472496 ps
CPU time 331.1 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:19:29 PM PDT 24
Peak memory 1142220 kb
Host smart-944433c3-0bab-4c4d-a1fa-0ecb9bb12c53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541515580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3541515580
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3106207123
Short name T592
Test name
Test status
Simulation time 1359134301 ps
CPU time 7.99 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:14:06 PM PDT 24
Peak memory 220296 kb
Host smart-39de5c0f-ce27-4d27-b834-283a0d0bc750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106207123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3106207123
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2104365693
Short name T494
Test name
Test status
Simulation time 17675227 ps
CPU time 0.6 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:14:12 PM PDT 24
Peak memory 203788 kb
Host smart-022f2577-f9d9-4abe-af8c-438425e0e88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104365693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2104365693
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3353183240
Short name T27
Test name
Test status
Simulation time 294660290 ps
CPU time 1.22 seconds
Started Mar 26 01:13:56 PM PDT 24
Finished Mar 26 01:13:57 PM PDT 24
Peak memory 212268 kb
Host smart-ee06b50c-2531-471c-b61d-6c2d60a59263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353183240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3353183240
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.120792052
Short name T947
Test name
Test status
Simulation time 819032443 ps
CPU time 7.48 seconds
Started Mar 26 01:14:05 PM PDT 24
Finished Mar 26 01:14:13 PM PDT 24
Peak memory 292428 kb
Host smart-8f0232b4-76cd-4225-a896-b1bd0dad6416
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120792052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.120792052
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1980392187
Short name T964
Test name
Test status
Simulation time 4453536627 ps
CPU time 108.72 seconds
Started Mar 26 01:13:57 PM PDT 24
Finished Mar 26 01:15:46 PM PDT 24
Peak memory 556436 kb
Host smart-b70ddec8-3f1c-49a5-9301-9c80aeb8c22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980392187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1980392187
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1750339508
Short name T809
Test name
Test status
Simulation time 1194782576 ps
CPU time 79.97 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:15:19 PM PDT 24
Peak memory 493932 kb
Host smart-f212e19b-942e-4020-8e8f-f501e182a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750339508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1750339508
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.1461370381
Short name T1092
Test name
Test status
Simulation time 324500957 ps
CPU time 0.84 seconds
Started Mar 26 01:13:57 PM PDT 24
Finished Mar 26 01:13:58 PM PDT 24
Peak memory 203888 kb
Host smart-332fc7ae-57fc-43af-b21b-eed9c6579599
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461370381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.1461370381
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1450122643
Short name T1093
Test name
Test status
Simulation time 628541929 ps
CPU time 7.7 seconds
Started Mar 26 01:14:00 PM PDT 24
Finished Mar 26 01:14:07 PM PDT 24
Peak memory 204076 kb
Host smart-ae77e60b-c671-46de-9311-ed11447f7168
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450122643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1450122643
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3563471276
Short name T239
Test name
Test status
Simulation time 5688035764 ps
CPU time 77.17 seconds
Started Mar 26 01:13:56 PM PDT 24
Finished Mar 26 01:15:13 PM PDT 24
Peak memory 926348 kb
Host smart-8f9ebeba-add3-4ad2-840e-e6b200a36887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563471276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3563471276
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_override.2699123024
Short name T56
Test name
Test status
Simulation time 39309755 ps
CPU time 0.65 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:13:59 PM PDT 24
Peak memory 203760 kb
Host smart-2b622468-a58f-4a61-bad2-e79be2e7dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699123024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2699123024
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2703192261
Short name T211
Test name
Test status
Simulation time 317026627 ps
CPU time 20.73 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:14:19 PM PDT 24
Peak memory 228656 kb
Host smart-39d7fa58-677d-4836-9bf1-6eee2b75b627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703192261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2703192261
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2288898593
Short name T638
Test name
Test status
Simulation time 1270122705 ps
CPU time 36.28 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:14:35 PM PDT 24
Peak memory 278840 kb
Host smart-34f40c1c-0825-499a-b594-22fbe128317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288898593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2288898593
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.355610730
Short name T246
Test name
Test status
Simulation time 26177624737 ps
CPU time 280.87 seconds
Started Mar 26 01:13:58 PM PDT 24
Finished Mar 26 01:18:40 PM PDT 24
Peak memory 1225908 kb
Host smart-4677f87a-476f-476f-84a6-77bf2a82e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355610730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.355610730
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.924513971
Short name T1036
Test name
Test status
Simulation time 520484587 ps
CPU time 3.05 seconds
Started Mar 26 01:14:11 PM PDT 24
Finished Mar 26 01:14:14 PM PDT 24
Peak memory 204168 kb
Host smart-26ea2aa6-326e-4f8b-9175-a260471a76ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924513971 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.924513971
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3215188239
Short name T657
Test name
Test status
Simulation time 10058635028 ps
CPU time 37.98 seconds
Started Mar 26 01:14:14 PM PDT 24
Finished Mar 26 01:14:52 PM PDT 24
Peak memory 475940 kb
Host smart-eedb6377-89b7-4d87-9992-55bc5bc416c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215188239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3215188239
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1229855640
Short name T1014
Test name
Test status
Simulation time 549634973 ps
CPU time 3.01 seconds
Started Mar 26 01:14:11 PM PDT 24
Finished Mar 26 01:14:14 PM PDT 24
Peak memory 204212 kb
Host smart-28673908-2487-4615-85c5-e5c8c8a8f4c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229855640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1229855640
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.23401037
Short name T834
Test name
Test status
Simulation time 1557990946 ps
CPU time 4.37 seconds
Started Mar 26 01:14:13 PM PDT 24
Finished Mar 26 01:14:18 PM PDT 24
Peak memory 204140 kb
Host smart-e323c24c-9e0a-433c-a310-30890f8ac84d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23401037 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.23401037
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1815265943
Short name T492
Test name
Test status
Simulation time 1280792717 ps
CPU time 20.03 seconds
Started Mar 26 01:14:05 PM PDT 24
Finished Mar 26 01:14:25 PM PDT 24
Peak memory 204068 kb
Host smart-67214ee7-f715-4805-9faf-8b566fb7a861
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815265943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1815265943
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.181380291
Short name T333
Test name
Test status
Simulation time 1541530075 ps
CPU time 13.21 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:14:25 PM PDT 24
Peak memory 207248 kb
Host smart-aec58d8f-1822-49d2-9fa6-3d016ff1705a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181380291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.181380291
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.4078173042
Short name T128
Test name
Test status
Simulation time 30886837985 ps
CPU time 2358.89 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:53:31 PM PDT 24
Peak memory 7500420 kb
Host smart-79928f07-a6c5-4c2d-9702-3f285d173577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078173042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.4078173042
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3206817795
Short name T8
Test name
Test status
Simulation time 1251229480 ps
CPU time 6.84 seconds
Started Mar 26 01:14:11 PM PDT 24
Finished Mar 26 01:14:18 PM PDT 24
Peak memory 217504 kb
Host smart-93c7b6b5-4ea9-48e4-8ac3-2c50833a1617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206817795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3206817795
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.3718757558
Short name T508
Test name
Test status
Simulation time 4624777854 ps
CPU time 5.32 seconds
Started Mar 26 01:14:11 PM PDT 24
Finished Mar 26 01:14:17 PM PDT 24
Peak memory 208104 kb
Host smart-d4bea659-ed50-46a3-b9bc-9c4fcdec2f1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718757558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.3718757558
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2343379550
Short name T949
Test name
Test status
Simulation time 26170237 ps
CPU time 0.62 seconds
Started Mar 26 01:14:33 PM PDT 24
Finished Mar 26 01:14:34 PM PDT 24
Peak memory 203684 kb
Host smart-2f465745-1694-45cd-9961-4734b643ce0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343379550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2343379550
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3855315528
Short name T569
Test name
Test status
Simulation time 277191408 ps
CPU time 1.17 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:14:13 PM PDT 24
Peak memory 212308 kb
Host smart-4d47bbfe-1bff-4961-9a3c-97f76389338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855315528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3855315528
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3451468667
Short name T678
Test name
Test status
Simulation time 272469333 ps
CPU time 14.56 seconds
Started Mar 26 01:14:13 PM PDT 24
Finished Mar 26 01:14:28 PM PDT 24
Peak memory 260484 kb
Host smart-a2f36ab9-a165-4b49-88b1-0e87973945cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451468667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3451468667
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3536350047
Short name T792
Test name
Test status
Simulation time 8879270137 ps
CPU time 58.66 seconds
Started Mar 26 01:14:14 PM PDT 24
Finished Mar 26 01:15:13 PM PDT 24
Peak memory 471712 kb
Host smart-435cd972-c52a-43a3-b2af-3fa66b915f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536350047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3536350047
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3539998239
Short name T786
Test name
Test status
Simulation time 9376733308 ps
CPU time 58.56 seconds
Started Mar 26 01:14:13 PM PDT 24
Finished Mar 26 01:15:12 PM PDT 24
Peak memory 625512 kb
Host smart-de04ea02-5653-4e60-acb0-5e210c7e6fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539998239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3539998239
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.3967713909
Short name T378
Test name
Test status
Simulation time 157472402 ps
CPU time 1.13 seconds
Started Mar 26 01:14:11 PM PDT 24
Finished Mar 26 01:14:13 PM PDT 24
Peak memory 204144 kb
Host smart-4929443f-046d-42a8-a15e-1b88ed38e198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967713909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.3967713909
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3616287829
Short name T328
Test name
Test status
Simulation time 147216946 ps
CPU time 3.17 seconds
Started Mar 26 01:14:13 PM PDT 24
Finished Mar 26 01:14:16 PM PDT 24
Peak memory 204052 kb
Host smart-837c24e4-351f-4a23-8346-b1c5402c9780
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616287829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3616287829
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2211841551
Short name T11
Test name
Test status
Simulation time 9194361505 ps
CPU time 60.12 seconds
Started Mar 26 01:14:11 PM PDT 24
Finished Mar 26 01:15:12 PM PDT 24
Peak memory 754164 kb
Host smart-3ceddbae-d641-4b4c-8639-f23199a43459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211841551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2211841551
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_override.3703189126
Short name T1044
Test name
Test status
Simulation time 145668484 ps
CPU time 0.64 seconds
Started Mar 26 01:14:14 PM PDT 24
Finished Mar 26 01:14:14 PM PDT 24
Peak memory 203856 kb
Host smart-e5482bd8-fb0d-453b-9965-5941d91f243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703189126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3703189126
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3590972689
Short name T1009
Test name
Test status
Simulation time 6888376617 ps
CPU time 80.36 seconds
Started Mar 26 01:14:17 PM PDT 24
Finished Mar 26 01:15:37 PM PDT 24
Peak memory 342448 kb
Host smart-58bbc5d8-316e-4885-9e62-0766fe3819a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590972689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3590972689
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.4097473458
Short name T837
Test name
Test status
Simulation time 1228107787 ps
CPU time 2.97 seconds
Started Mar 26 01:14:26 PM PDT 24
Finished Mar 26 01:14:29 PM PDT 24
Peak memory 204148 kb
Host smart-a5c33f24-7485-4229-85fc-525bc1a23a1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097473458 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.4097473458
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.64465073
Short name T1068
Test name
Test status
Simulation time 10066783810 ps
CPU time 69.27 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:15:36 PM PDT 24
Peak memory 537352 kb
Host smart-e60daed7-7de0-46a9-a4e1-2077d792351c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64465073 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_acq.64465073
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3995113148
Short name T490
Test name
Test status
Simulation time 10105238403 ps
CPU time 39.85 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:15:07 PM PDT 24
Peak memory 466784 kb
Host smart-ce07d398-20a0-48db-aab8-96ae176a7464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995113148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3995113148
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.618573997
Short name T507
Test name
Test status
Simulation time 1986268207 ps
CPU time 3.07 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:14:30 PM PDT 24
Peak memory 204124 kb
Host smart-c8c5aa3a-cd13-4c33-a29f-b96f61ab54af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618573997 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.618573997
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3441320590
Short name T778
Test name
Test status
Simulation time 649914886 ps
CPU time 3.37 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:14:15 PM PDT 24
Peak memory 204120 kb
Host smart-47325ab4-9404-4428-bcc1-94fcb319a3c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441320590 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3441320590
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1713762406
Short name T963
Test name
Test status
Simulation time 905911940 ps
CPU time 14.71 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:14:27 PM PDT 24
Peak memory 204224 kb
Host smart-ec0e5388-fc28-454d-b74d-40fb40c5528a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713762406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1713762406
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.2117016369
Short name T824
Test name
Test status
Simulation time 713054248 ps
CPU time 7.75 seconds
Started Mar 26 01:14:12 PM PDT 24
Finished Mar 26 01:14:20 PM PDT 24
Peak memory 208048 kb
Host smart-99fdf9c8-9c51-47ac-ac7e-fcfaf6452f1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117016369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.2117016369
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.4037005492
Short name T681
Test name
Test status
Simulation time 9390477466 ps
CPU time 6.92 seconds
Started Mar 26 01:14:26 PM PDT 24
Finished Mar 26 01:14:34 PM PDT 24
Peak memory 209776 kb
Host smart-1aa29a89-3d1e-47d1-838d-b014abcf05f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037005492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.4037005492
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3764738467
Short name T80
Test name
Test status
Simulation time 122404502 ps
CPU time 0.63 seconds
Started Mar 26 01:14:25 PM PDT 24
Finished Mar 26 01:14:26 PM PDT 24
Peak memory 203704 kb
Host smart-57a4e12e-7ef9-426d-87b6-59a679d441ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764738467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3764738467
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1655252464
Short name T1006
Test name
Test status
Simulation time 359150135 ps
CPU time 18.89 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:14:46 PM PDT 24
Peak memory 282440 kb
Host smart-ec4c305f-e56a-45c6-9cff-6d8b92588419
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655252464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1655252464
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1649816798
Short name T407
Test name
Test status
Simulation time 6839639082 ps
CPU time 72.7 seconds
Started Mar 26 01:14:25 PM PDT 24
Finished Mar 26 01:15:38 PM PDT 24
Peak memory 456016 kb
Host smart-1edf7685-1d61-4eda-873a-3fc05eeb59c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649816798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1649816798
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1097965431
Short name T991
Test name
Test status
Simulation time 4829912851 ps
CPU time 75.23 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:15:42 PM PDT 24
Peak memory 795512 kb
Host smart-7bebac54-8bc0-4655-b995-3f97b45328eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097965431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1097965431
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1312149392
Short name T1063
Test name
Test status
Simulation time 262339980 ps
CPU time 0.94 seconds
Started Mar 26 01:14:29 PM PDT 24
Finished Mar 26 01:14:30 PM PDT 24
Peak memory 203844 kb
Host smart-4a59a319-c593-43d4-9d6f-a3eac586746e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312149392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1312149392
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2882334301
Short name T603
Test name
Test status
Simulation time 532870275 ps
CPU time 3.18 seconds
Started Mar 26 01:14:26 PM PDT 24
Finished Mar 26 01:14:29 PM PDT 24
Peak memory 204116 kb
Host smart-362dfcfb-cedc-4b36-b9df-b2fc13e4c716
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882334301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2882334301
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3580016295
Short name T1031
Test name
Test status
Simulation time 17166386089 ps
CPU time 130.75 seconds
Started Mar 26 01:14:29 PM PDT 24
Finished Mar 26 01:16:40 PM PDT 24
Peak memory 1201072 kb
Host smart-5c7389e2-3d63-445e-8bb3-5e8ca92fe274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580016295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3580016295
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_override.1917562660
Short name T226
Test name
Test status
Simulation time 17072938 ps
CPU time 0.66 seconds
Started Mar 26 01:14:24 PM PDT 24
Finished Mar 26 01:14:25 PM PDT 24
Peak memory 203788 kb
Host smart-17d98fd9-7b74-409d-ba60-51be47ae2bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917562660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1917562660
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1395219851
Short name T735
Test name
Test status
Simulation time 806447585 ps
CPU time 6.5 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:14:34 PM PDT 24
Peak memory 228724 kb
Host smart-c15bf257-b11c-47b2-808c-1a302108cbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395219851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1395219851
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.744558113
Short name T587
Test name
Test status
Simulation time 922992014 ps
CPU time 33.54 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:15:00 PM PDT 24
Peak memory 327256 kb
Host smart-8c8d71f2-8220-4893-8b35-f1e053554f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744558113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.744558113
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.4243190235
Short name T437
Test name
Test status
Simulation time 1282569938 ps
CPU time 3.15 seconds
Started Mar 26 01:14:28 PM PDT 24
Finished Mar 26 01:14:31 PM PDT 24
Peak memory 204172 kb
Host smart-dc945545-2a48-4946-b0a4-8f43231cbf4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243190235 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.4243190235
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1141112206
Short name T1011
Test name
Test status
Simulation time 10338293338 ps
CPU time 13.21 seconds
Started Mar 26 01:14:24 PM PDT 24
Finished Mar 26 01:14:38 PM PDT 24
Peak memory 277744 kb
Host smart-e55625a1-961d-44df-a765-df9d35997c28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141112206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.1141112206
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2770392884
Short name T367
Test name
Test status
Simulation time 10732597378 ps
CPU time 4.87 seconds
Started Mar 26 01:14:25 PM PDT 24
Finished Mar 26 01:14:30 PM PDT 24
Peak memory 238608 kb
Host smart-3974f45e-a3be-49b3-b8d9-b506fc2059c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770392884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2770392884
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3525648762
Short name T1002
Test name
Test status
Simulation time 608048157 ps
CPU time 3.67 seconds
Started Mar 26 01:14:26 PM PDT 24
Finished Mar 26 01:14:30 PM PDT 24
Peak memory 204116 kb
Host smart-5cfeb446-5145-47d8-9303-8c75df15abb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525648762 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3525648762
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1950380763
Short name T610
Test name
Test status
Simulation time 3613860816 ps
CPU time 13.44 seconds
Started Mar 26 01:14:24 PM PDT 24
Finished Mar 26 01:14:38 PM PDT 24
Peak memory 204176 kb
Host smart-50184814-cfca-4e89-b918-3ea304316f0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950380763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1950380763
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.366283162
Short name T534
Test name
Test status
Simulation time 6154156258 ps
CPU time 25.66 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:14:53 PM PDT 24
Peak memory 232876 kb
Host smart-f285fef1-b082-45ad-80b2-1df7b34d0413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366283162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.366283162
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1140666543
Short name T416
Test name
Test status
Simulation time 34679824641 ps
CPU time 740.68 seconds
Started Mar 26 01:14:25 PM PDT 24
Finished Mar 26 01:26:46 PM PDT 24
Peak memory 1955608 kb
Host smart-ee898d11-38b9-400e-99c4-db914ced2376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140666543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1140666543
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.1181116503
Short name T390
Test name
Test status
Simulation time 5045163998 ps
CPU time 6.36 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:14:34 PM PDT 24
Peak memory 204364 kb
Host smart-67d57e6f-70d8-4f07-a69d-75ad0913dd6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181116503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.1181116503
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.497310051
Short name T764
Test name
Test status
Simulation time 19058647 ps
CPU time 0.63 seconds
Started Mar 26 01:14:42 PM PDT 24
Finished Mar 26 01:14:43 PM PDT 24
Peak memory 203792 kb
Host smart-c1c0b1d9-7e41-4cbb-8701-6783bac42718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497310051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.497310051
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.4031066406
Short name T845
Test name
Test status
Simulation time 111038621 ps
CPU time 1.18 seconds
Started Mar 26 01:14:42 PM PDT 24
Finished Mar 26 01:14:43 PM PDT 24
Peak memory 212352 kb
Host smart-2c6cd1c0-c58c-4a07-a0c9-9b9b36b2adf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031066406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.4031066406
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.276864414
Short name T884
Test name
Test status
Simulation time 1067628031 ps
CPU time 12.65 seconds
Started Mar 26 01:14:37 PM PDT 24
Finished Mar 26 01:14:50 PM PDT 24
Peak memory 252292 kb
Host smart-9b5c698f-49e6-42ca-92af-7220cc2f9f87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276864414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.276864414
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1686393952
Short name T481
Test name
Test status
Simulation time 2295754327 ps
CPU time 74.69 seconds
Started Mar 26 01:14:37 PM PDT 24
Finished Mar 26 01:15:52 PM PDT 24
Peak memory 489936 kb
Host smart-fcdba931-a26b-48a6-9475-982e22894319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686393952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1686393952
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3274748740
Short name T57
Test name
Test status
Simulation time 9239247402 ps
CPU time 166.48 seconds
Started Mar 26 01:14:39 PM PDT 24
Finished Mar 26 01:17:26 PM PDT 24
Peak memory 734784 kb
Host smart-83fa4a35-b374-4198-a33c-4eb2bed20995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274748740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3274748740
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1264261289
Short name T968
Test name
Test status
Simulation time 565393396 ps
CPU time 1.09 seconds
Started Mar 26 01:14:38 PM PDT 24
Finished Mar 26 01:14:39 PM PDT 24
Peak memory 203920 kb
Host smart-21783f13-77dd-4539-bd1f-7c6698af856c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264261289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1264261289
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2552922299
Short name T236
Test name
Test status
Simulation time 4032005235 ps
CPU time 302.19 seconds
Started Mar 26 01:14:42 PM PDT 24
Finished Mar 26 01:19:44 PM PDT 24
Peak memory 1166696 kb
Host smart-13ed9cc4-c73b-4b1f-bdb4-590fb49c92b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552922299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2552922299
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_override.2527096470
Short name T19
Test name
Test status
Simulation time 26032790 ps
CPU time 0.65 seconds
Started Mar 26 01:14:38 PM PDT 24
Finished Mar 26 01:14:39 PM PDT 24
Peak memory 203732 kb
Host smart-e98f2e67-45c6-4151-a5ee-5f14c4799fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527096470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2527096470
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.494235749
Short name T620
Test name
Test status
Simulation time 480851832 ps
CPU time 28.39 seconds
Started Mar 26 01:14:40 PM PDT 24
Finished Mar 26 01:15:09 PM PDT 24
Peak memory 231116 kb
Host smart-faf7accb-5cbf-45d2-90f5-365017b26f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494235749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.494235749
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1709863875
Short name T927
Test name
Test status
Simulation time 3204002038 ps
CPU time 61.8 seconds
Started Mar 26 01:14:27 PM PDT 24
Finished Mar 26 01:15:29 PM PDT 24
Peak memory 346752 kb
Host smart-226172d0-e0c4-45e8-aa4a-825fe4d5345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709863875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1709863875
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2194706520
Short name T1089
Test name
Test status
Simulation time 1656960902 ps
CPU time 2.24 seconds
Started Mar 26 01:14:43 PM PDT 24
Finished Mar 26 01:14:46 PM PDT 24
Peak memory 204092 kb
Host smart-195aad1c-14c3-4d5f-8880-9e106b1be5d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194706520 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2194706520
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.481275843
Short name T195
Test name
Test status
Simulation time 10201580028 ps
CPU time 11.97 seconds
Started Mar 26 01:14:45 PM PDT 24
Finished Mar 26 01:14:57 PM PDT 24
Peak memory 282548 kb
Host smart-58e6ce25-7bc9-4e44-a5be-fba6732e5657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481275843 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.481275843
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2651855688
Short name T540
Test name
Test status
Simulation time 10300721193 ps
CPU time 5.98 seconds
Started Mar 26 01:14:40 PM PDT 24
Finished Mar 26 01:14:47 PM PDT 24
Peak memory 259660 kb
Host smart-7bf31943-46e5-4fef-8211-b1a624098f60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651855688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2651855688
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2828213462
Short name T197
Test name
Test status
Simulation time 489198201 ps
CPU time 2.23 seconds
Started Mar 26 01:14:42 PM PDT 24
Finished Mar 26 01:14:44 PM PDT 24
Peak memory 204156 kb
Host smart-0f3a9f87-0e33-47f1-bd60-f4c58f7dd2e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828213462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2828213462
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2916524672
Short name T756
Test name
Test status
Simulation time 746498248 ps
CPU time 3.94 seconds
Started Mar 26 01:14:39 PM PDT 24
Finished Mar 26 01:14:44 PM PDT 24
Peak memory 206480 kb
Host smart-9906bcfa-5e50-4434-98da-38c17c19bd7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916524672 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2916524672
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.736860181
Short name T280
Test name
Test status
Simulation time 3578847786 ps
CPU time 32.32 seconds
Started Mar 26 01:14:43 PM PDT 24
Finished Mar 26 01:15:15 PM PDT 24
Peak memory 204168 kb
Host smart-c478fcf0-a324-481b-bfde-18cd39d27d9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736860181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.736860181
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.4193196563
Short name T273
Test name
Test status
Simulation time 3609505603 ps
CPU time 30.19 seconds
Started Mar 26 01:14:40 PM PDT 24
Finished Mar 26 01:15:11 PM PDT 24
Peak memory 227036 kb
Host smart-b133d834-4f3e-4ee2-9478-44fc5acc6832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193196563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.4193196563
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3980707217
Short name T637
Test name
Test status
Simulation time 12011794696 ps
CPU time 204.84 seconds
Started Mar 26 01:14:42 PM PDT 24
Finished Mar 26 01:18:07 PM PDT 24
Peak memory 1580272 kb
Host smart-188ff627-7582-47bb-b140-b3fe325ff2ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980707217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3980707217
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3306490763
Short name T679
Test name
Test status
Simulation time 1478429144 ps
CPU time 7.72 seconds
Started Mar 26 01:14:39 PM PDT 24
Finished Mar 26 01:14:48 PM PDT 24
Peak memory 216188 kb
Host smart-f39cbdc6-50c4-4223-a4af-6baaf67fc6c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306490763 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3306490763
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.1095704122
Short name T918
Test name
Test status
Simulation time 28343418 ps
CPU time 0.59 seconds
Started Mar 26 01:14:53 PM PDT 24
Finished Mar 26 01:14:54 PM PDT 24
Peak memory 203708 kb
Host smart-83be15b0-72aa-4d72-a35e-eaa3ed8e2a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095704122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.1095704122
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.4146505036
Short name T311
Test name
Test status
Simulation time 47444491 ps
CPU time 1.35 seconds
Started Mar 26 01:14:38 PM PDT 24
Finished Mar 26 01:14:40 PM PDT 24
Peak memory 212280 kb
Host smart-22624eb1-930e-4860-a444-ce0b0f20df93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146505036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.4146505036
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.4227725315
Short name T525
Test name
Test status
Simulation time 349735354 ps
CPU time 7.47 seconds
Started Mar 26 01:14:41 PM PDT 24
Finished Mar 26 01:14:48 PM PDT 24
Peak memory 278804 kb
Host smart-164ae3d3-57c8-48e4-a9d7-98b754bf0798
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227725315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.4227725315
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.903604677
Short name T676
Test name
Test status
Simulation time 2105191891 ps
CPU time 60.95 seconds
Started Mar 26 01:14:44 PM PDT 24
Finished Mar 26 01:15:45 PM PDT 24
Peak memory 644356 kb
Host smart-91001164-992f-452a-a8fe-2b9ebd17c038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903604677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.903604677
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.1637634651
Short name T456
Test name
Test status
Simulation time 1377098963 ps
CPU time 35.97 seconds
Started Mar 26 01:14:42 PM PDT 24
Finished Mar 26 01:15:18 PM PDT 24
Peak memory 528520 kb
Host smart-08d20e0b-21c6-4d94-849a-94e18534135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637634651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1637634651
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1623888339
Short name T303
Test name
Test status
Simulation time 239930989 ps
CPU time 1.01 seconds
Started Mar 26 01:14:38 PM PDT 24
Finished Mar 26 01:14:39 PM PDT 24
Peak memory 203928 kb
Host smart-64a725ad-2536-40b8-970b-df914e57113d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623888339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1623888339
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.2806428687
Short name T98
Test name
Test status
Simulation time 181863066 ps
CPU time 5.12 seconds
Started Mar 26 01:14:44 PM PDT 24
Finished Mar 26 01:14:49 PM PDT 24
Peak memory 236300 kb
Host smart-13397db9-be86-41fa-8fb8-4ed09ed4b6d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806428687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.2806428687
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_override.3947968080
Short name T900
Test name
Test status
Simulation time 17573415 ps
CPU time 0.64 seconds
Started Mar 26 01:14:37 PM PDT 24
Finished Mar 26 01:14:38 PM PDT 24
Peak memory 203716 kb
Host smart-677cd82e-8d66-4913-ac1d-9624f9f4c3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947968080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3947968080
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.536635552
Short name T14
Test name
Test status
Simulation time 7060754571 ps
CPU time 993.45 seconds
Started Mar 26 01:14:38 PM PDT 24
Finished Mar 26 01:31:12 PM PDT 24
Peak memory 588236 kb
Host smart-852f5674-55da-415a-830a-1f4c4b364ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536635552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.536635552
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.696054192
Short name T33
Test name
Test status
Simulation time 1529863598 ps
CPU time 70.92 seconds
Started Mar 26 01:14:41 PM PDT 24
Finished Mar 26 01:15:52 PM PDT 24
Peak memory 341584 kb
Host smart-acc1c18c-83fa-40d3-9bf3-294e751a4395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696054192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.696054192
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3271849304
Short name T446
Test name
Test status
Simulation time 481087049 ps
CPU time 2.47 seconds
Started Mar 26 01:14:52 PM PDT 24
Finished Mar 26 01:14:55 PM PDT 24
Peak memory 204120 kb
Host smart-4e6fd094-4fde-4e7f-9a89-e9beef1e2bff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271849304 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3271849304
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2644558926
Short name T774
Test name
Test status
Simulation time 10131838964 ps
CPU time 73.05 seconds
Started Mar 26 01:14:51 PM PDT 24
Finished Mar 26 01:16:04 PM PDT 24
Peak memory 587664 kb
Host smart-41f8b7f3-8dea-4015-88be-db643938ae8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644558926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2644558926
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.672484644
Short name T476
Test name
Test status
Simulation time 10061830799 ps
CPU time 34.54 seconds
Started Mar 26 01:14:51 PM PDT 24
Finished Mar 26 01:15:25 PM PDT 24
Peak memory 431728 kb
Host smart-7796fc89-73fc-4ca7-8844-00c086eebff4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672484644 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.672484644
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.2577133181
Short name T929
Test name
Test status
Simulation time 1324449219 ps
CPU time 2.03 seconds
Started Mar 26 01:14:55 PM PDT 24
Finished Mar 26 01:14:57 PM PDT 24
Peak memory 204116 kb
Host smart-a11e31c3-b5d9-4d7b-b19f-52f0fac819ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577133181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.2577133181
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3991556862
Short name T956
Test name
Test status
Simulation time 9067338452 ps
CPU time 5.3 seconds
Started Mar 26 01:14:50 PM PDT 24
Finished Mar 26 01:14:55 PM PDT 24
Peak memory 204268 kb
Host smart-4c305c1a-a75a-417c-99ef-48b8bccd5e2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991556862 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3991556862
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1173321587
Short name T990
Test name
Test status
Simulation time 10383304816 ps
CPU time 5.37 seconds
Started Mar 26 01:14:51 PM PDT 24
Finished Mar 26 01:14:57 PM PDT 24
Peak memory 204264 kb
Host smart-2fe91cb0-985e-41e5-af00-9483049035b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173321587 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1173321587
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3243173118
Short name T760
Test name
Test status
Simulation time 3322584102 ps
CPU time 20.6 seconds
Started Mar 26 01:14:39 PM PDT 24
Finished Mar 26 01:15:01 PM PDT 24
Peak memory 204276 kb
Host smart-1e988992-956e-4664-8df5-833f6ab788c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243173118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3243173118
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2168187695
Short name T633
Test name
Test status
Simulation time 6227217618 ps
CPU time 31.3 seconds
Started Mar 26 01:14:43 PM PDT 24
Finished Mar 26 01:15:14 PM PDT 24
Peak memory 226704 kb
Host smart-0a9bd18d-2d60-4281-b606-f0fed64cb4e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168187695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2168187695
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3541210245
Short name T662
Test name
Test status
Simulation time 18899364535 ps
CPU time 1468.87 seconds
Started Mar 26 01:14:54 PM PDT 24
Finished Mar 26 01:39:23 PM PDT 24
Peak memory 4540868 kb
Host smart-c734a043-3f8c-42ba-8844-746c42dda326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541210245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3541210245
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.858186145
Short name T804
Test name
Test status
Simulation time 18143516405 ps
CPU time 6.89 seconds
Started Mar 26 01:14:52 PM PDT 24
Finished Mar 26 01:14:59 PM PDT 24
Peak memory 220464 kb
Host smart-bc1fd0fd-ca98-4900-b4d5-ecaa4d54d067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858186145 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.858186145
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.4145195170
Short name T514
Test name
Test status
Simulation time 35890730 ps
CPU time 0.59 seconds
Started Mar 26 01:15:03 PM PDT 24
Finished Mar 26 01:15:04 PM PDT 24
Peak memory 203708 kb
Host smart-4482804d-8b99-44fd-a27c-aeb35750af96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145195170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.4145195170
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3297049250
Short name T1024
Test name
Test status
Simulation time 44885096 ps
CPU time 1.41 seconds
Started Mar 26 01:14:54 PM PDT 24
Finished Mar 26 01:14:56 PM PDT 24
Peak memory 212432 kb
Host smart-893b62c4-732a-460c-8421-79c8ed80dab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297049250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3297049250
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2182487672
Short name T667
Test name
Test status
Simulation time 220870925 ps
CPU time 3.91 seconds
Started Mar 26 01:14:52 PM PDT 24
Finished Mar 26 01:14:56 PM PDT 24
Peak memory 245828 kb
Host smart-020a8ead-ac07-4ceb-9467-0d1f219692ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182487672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2182487672
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1075693416
Short name T240
Test name
Test status
Simulation time 7730013286 ps
CPU time 65.23 seconds
Started Mar 26 01:14:55 PM PDT 24
Finished Mar 26 01:16:00 PM PDT 24
Peak memory 667360 kb
Host smart-9a4515a2-a87c-4dd0-84c3-88a63da7aa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075693416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1075693416
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3643202112
Short name T477
Test name
Test status
Simulation time 5068398206 ps
CPU time 90.31 seconds
Started Mar 26 01:14:53 PM PDT 24
Finished Mar 26 01:16:23 PM PDT 24
Peak memory 520704 kb
Host smart-01bb36e0-b1ec-4d72-b911-e68a9c9a45a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643202112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3643202112
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.4148749276
Short name T374
Test name
Test status
Simulation time 403011808 ps
CPU time 1.11 seconds
Started Mar 26 01:14:51 PM PDT 24
Finished Mar 26 01:14:53 PM PDT 24
Peak memory 204092 kb
Host smart-877a57c2-83cd-4de3-a6d5-71c35ec515bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148749276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.4148749276
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1855955330
Short name T1033
Test name
Test status
Simulation time 505923056 ps
CPU time 9.04 seconds
Started Mar 26 01:14:54 PM PDT 24
Finished Mar 26 01:15:03 PM PDT 24
Peak memory 234416 kb
Host smart-bae4ccd2-fe4c-4a4f-933c-f5e19b6d79b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855955330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1855955330
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2664117094
Short name T495
Test name
Test status
Simulation time 10867097507 ps
CPU time 59.82 seconds
Started Mar 26 01:14:52 PM PDT 24
Finished Mar 26 01:15:52 PM PDT 24
Peak memory 746864 kb
Host smart-97063031-d85b-4095-beef-3c8baa284cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664117094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2664117094
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_override.2921367566
Short name T316
Test name
Test status
Simulation time 18146823 ps
CPU time 0.66 seconds
Started Mar 26 01:14:50 PM PDT 24
Finished Mar 26 01:14:51 PM PDT 24
Peak memory 203712 kb
Host smart-1ee46d8d-cd42-4c27-994e-98a0394c3637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921367566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2921367566
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3672680235
Short name T938
Test name
Test status
Simulation time 6226595129 ps
CPU time 47.23 seconds
Started Mar 26 01:14:51 PM PDT 24
Finished Mar 26 01:15:38 PM PDT 24
Peak memory 204236 kb
Host smart-d635c980-7290-4aec-8e9f-969af26e67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672680235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3672680235
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3981817560
Short name T258
Test name
Test status
Simulation time 3244304898 ps
CPU time 78.1 seconds
Started Mar 26 01:14:51 PM PDT 24
Finished Mar 26 01:16:10 PM PDT 24
Peak memory 364024 kb
Host smart-82b003f5-a861-4450-89a6-6446942ce41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981817560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3981817560
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3144672752
Short name T867
Test name
Test status
Simulation time 3042947804 ps
CPU time 3.66 seconds
Started Mar 26 01:14:56 PM PDT 24
Finished Mar 26 01:15:00 PM PDT 24
Peak memory 204236 kb
Host smart-b6279e48-090d-4664-a190-68648f4674a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144672752 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3144672752
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1916520987
Short name T971
Test name
Test status
Simulation time 10065684161 ps
CPU time 80.22 seconds
Started Mar 26 01:14:51 PM PDT 24
Finished Mar 26 01:16:11 PM PDT 24
Peak memory 549360 kb
Host smart-faa8df13-f516-4671-8022-71441424209a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916520987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1916520987
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.1297608474
Short name T1064
Test name
Test status
Simulation time 10336367756 ps
CPU time 33.97 seconds
Started Mar 26 01:14:52 PM PDT 24
Finished Mar 26 01:15:26 PM PDT 24
Peak memory 462228 kb
Host smart-043de8fd-3d48-4d3c-8bd5-d5ae9ca17ba3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297608474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.1297608474
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1941194299
Short name T892
Test name
Test status
Simulation time 422447802 ps
CPU time 2.49 seconds
Started Mar 26 01:14:53 PM PDT 24
Finished Mar 26 01:14:56 PM PDT 24
Peak memory 204040 kb
Host smart-9f097d11-6216-47a9-9122-d1c8ed735739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941194299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1941194299
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3893658323
Short name T853
Test name
Test status
Simulation time 3152044731 ps
CPU time 4.71 seconds
Started Mar 26 01:14:50 PM PDT 24
Finished Mar 26 01:14:55 PM PDT 24
Peak memory 205996 kb
Host smart-42f6fe98-40e0-48be-be19-cac76b312b81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893658323 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3893658323
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3970611394
Short name T785
Test name
Test status
Simulation time 6087514143 ps
CPU time 4.62 seconds
Started Mar 26 01:14:53 PM PDT 24
Finished Mar 26 01:14:58 PM PDT 24
Peak memory 204248 kb
Host smart-30cc8cfe-eba7-4278-bfb1-44557d8abf55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970611394 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3970611394
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3535968235
Short name T1027
Test name
Test status
Simulation time 1332861700 ps
CPU time 21.28 seconds
Started Mar 26 01:14:52 PM PDT 24
Finished Mar 26 01:15:14 PM PDT 24
Peak memory 204088 kb
Host smart-78a14283-ae76-420c-ad0d-c340e3ae2804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535968235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3535968235
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.624473268
Short name T3
Test name
Test status
Simulation time 1210165695 ps
CPU time 22.95 seconds
Started Mar 26 01:14:56 PM PDT 24
Finished Mar 26 01:15:19 PM PDT 24
Peak memory 218332 kb
Host smart-649b7c2f-814e-468a-b1e9-87325ac30474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624473268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.624473268
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.4293348059
Short name T766
Test name
Test status
Simulation time 29436933144 ps
CPU time 2349.38 seconds
Started Mar 26 01:14:52 PM PDT 24
Finished Mar 26 01:54:02 PM PDT 24
Peak memory 6995416 kb
Host smart-341563f0-564e-462c-8b84-b43715395cd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293348059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.4293348059
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3830525617
Short name T279
Test name
Test status
Simulation time 1319185935 ps
CPU time 6.92 seconds
Started Mar 26 01:14:47 PM PDT 24
Finished Mar 26 01:14:54 PM PDT 24
Peak memory 209312 kb
Host smart-86e6e999-10b4-4fab-8952-f123ecdef750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830525617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3830525617
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3900990494
Short name T506
Test name
Test status
Simulation time 16460754 ps
CPU time 0.62 seconds
Started Mar 26 01:15:07 PM PDT 24
Finished Mar 26 01:15:08 PM PDT 24
Peak memory 203752 kb
Host smart-33f5241d-d0d0-41f1-8b43-45fdfbe9a66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900990494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3900990494
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3617143150
Short name T342
Test name
Test status
Simulation time 34435341 ps
CPU time 1.17 seconds
Started Mar 26 01:15:05 PM PDT 24
Finished Mar 26 01:15:06 PM PDT 24
Peak memory 220376 kb
Host smart-a235078a-1680-4ac5-8127-c92778e8d897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617143150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3617143150
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.232423348
Short name T266
Test name
Test status
Simulation time 300803941 ps
CPU time 14.7 seconds
Started Mar 26 01:15:06 PM PDT 24
Finished Mar 26 01:15:21 PM PDT 24
Peak memory 251072 kb
Host smart-7642a5f9-a33e-4c39-9100-d27d8c7dec56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232423348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.232423348
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1898887403
Short name T826
Test name
Test status
Simulation time 1917884120 ps
CPU time 51.94 seconds
Started Mar 26 01:15:03 PM PDT 24
Finished Mar 26 01:15:55 PM PDT 24
Peak memory 456136 kb
Host smart-f3a166e2-6e36-43fb-aa52-1474f1a1988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898887403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1898887403
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3823750137
Short name T734
Test name
Test status
Simulation time 4597620437 ps
CPU time 68.43 seconds
Started Mar 26 01:15:03 PM PDT 24
Finished Mar 26 01:16:12 PM PDT 24
Peak memory 702768 kb
Host smart-bae16e0e-b575-4c72-8e12-2e94b7a5cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823750137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3823750137
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.4241005247
Short name T312
Test name
Test status
Simulation time 375842107 ps
CPU time 0.89 seconds
Started Mar 26 01:15:05 PM PDT 24
Finished Mar 26 01:15:06 PM PDT 24
Peak memory 203856 kb
Host smart-4e1a35c1-d3fb-423f-9199-3aa5b8c2b250
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241005247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.4241005247
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.979493115
Short name T354
Test name
Test status
Simulation time 220024722 ps
CPU time 2.86 seconds
Started Mar 26 01:15:04 PM PDT 24
Finished Mar 26 01:15:07 PM PDT 24
Peak memory 204076 kb
Host smart-ae006050-3f32-4399-a17a-ee3a722a8268
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979493115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
979493115
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1519241757
Short name T178
Test name
Test status
Simulation time 73211749238 ps
CPU time 90.24 seconds
Started Mar 26 01:15:02 PM PDT 24
Finished Mar 26 01:16:32 PM PDT 24
Peak memory 1056108 kb
Host smart-637b0b95-4d9a-481e-b0a1-e5ada4cc8674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519241757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1519241757
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_override.4247709969
Short name T201
Test name
Test status
Simulation time 16834578 ps
CPU time 0.67 seconds
Started Mar 26 01:15:02 PM PDT 24
Finished Mar 26 01:15:03 PM PDT 24
Peak memory 203716 kb
Host smart-50e74278-56f5-40a2-b8fd-c8a3af320e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247709969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.4247709969
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.3346200667
Short name T707
Test name
Test status
Simulation time 7386224857 ps
CPU time 267.58 seconds
Started Mar 26 01:15:03 PM PDT 24
Finished Mar 26 01:19:31 PM PDT 24
Peak memory 479792 kb
Host smart-8fc5bcd2-7268-41ce-ada4-fe2ab74a8602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346200667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3346200667
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1430710675
Short name T709
Test name
Test status
Simulation time 1641140507 ps
CPU time 22.23 seconds
Started Mar 26 01:15:04 PM PDT 24
Finished Mar 26 01:15:26 PM PDT 24
Peak memory 272480 kb
Host smart-6ec88ff7-e880-4fc3-ad3f-e8d7233c6679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430710675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1430710675
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2998802075
Short name T187
Test name
Test status
Simulation time 56450838531 ps
CPU time 1385.04 seconds
Started Mar 26 01:15:04 PM PDT 24
Finished Mar 26 01:38:10 PM PDT 24
Peak memory 1307672 kb
Host smart-1f25d717-1646-4d44-a4bf-2c17de61a508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998802075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2998802075
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2223239623
Short name T886
Test name
Test status
Simulation time 891098393 ps
CPU time 4.46 seconds
Started Mar 26 01:15:05 PM PDT 24
Finished Mar 26 01:15:10 PM PDT 24
Peak memory 204160 kb
Host smart-51d7fe98-193a-4a5f-9fdf-b86b30701694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223239623 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2223239623
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.495632851
Short name T639
Test name
Test status
Simulation time 10153519044 ps
CPU time 15.65 seconds
Started Mar 26 01:15:09 PM PDT 24
Finished Mar 26 01:15:25 PM PDT 24
Peak memory 304576 kb
Host smart-bfda8d4e-3ea5-4d1f-bc92-e47f634a5c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495632851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.495632851
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3061333928
Short name T747
Test name
Test status
Simulation time 10362145132 ps
CPU time 4.9 seconds
Started Mar 26 01:15:05 PM PDT 24
Finished Mar 26 01:15:10 PM PDT 24
Peak memory 244468 kb
Host smart-ed9d3ef5-24c8-40b8-9402-03cc16d1c467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061333928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3061333928
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3299558911
Short name T1085
Test name
Test status
Simulation time 1800913410 ps
CPU time 2.38 seconds
Started Mar 26 01:15:03 PM PDT 24
Finished Mar 26 01:15:06 PM PDT 24
Peak memory 204092 kb
Host smart-69973738-589c-476f-8563-4ddb44c6b16c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299558911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3299558911
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.880962458
Short name T320
Test name
Test status
Simulation time 6780023558 ps
CPU time 6.99 seconds
Started Mar 26 01:15:04 PM PDT 24
Finished Mar 26 01:15:11 PM PDT 24
Peak memory 212332 kb
Host smart-af053294-b6d0-41c9-8dc8-5110248730ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880962458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.880962458
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.4147200876
Short name T627
Test name
Test status
Simulation time 4697291480 ps
CPU time 8.15 seconds
Started Mar 26 01:15:05 PM PDT 24
Finished Mar 26 01:15:13 PM PDT 24
Peak memory 204288 kb
Host smart-746c210e-bc60-4fc8-847e-2c5be6c67ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147200876 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.4147200876
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3550121102
Short name T480
Test name
Test status
Simulation time 999972741 ps
CPU time 15.02 seconds
Started Mar 26 01:15:05 PM PDT 24
Finished Mar 26 01:15:20 PM PDT 24
Peak memory 203900 kb
Host smart-e7249c4a-b1a2-42a8-80d3-5f32c5873839
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550121102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3550121102
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1119963938
Short name T330
Test name
Test status
Simulation time 781474985 ps
CPU time 32.66 seconds
Started Mar 26 01:15:01 PM PDT 24
Finished Mar 26 01:15:34 PM PDT 24
Peak memory 204072 kb
Host smart-2fbbfcec-8a48-4cf4-9a07-157b8881a57a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119963938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1119963938
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.348037508
Short name T9
Test name
Test status
Simulation time 6169981056 ps
CPU time 7.62 seconds
Started Mar 26 01:15:06 PM PDT 24
Finished Mar 26 01:15:14 PM PDT 24
Peak memory 217088 kb
Host smart-3f0090c1-04da-42e5-8920-1e1880c94c98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348037508 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.348037508
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.4181565753
Short name T261
Test name
Test status
Simulation time 19263055 ps
CPU time 0.64 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:12:30 PM PDT 24
Peak memory 203692 kb
Host smart-d5d0d16f-4fdf-4457-b014-3b6485c4a1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181565753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.4181565753
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3741857153
Short name T223
Test name
Test status
Simulation time 28130651 ps
CPU time 1.23 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:12:32 PM PDT 24
Peak memory 212424 kb
Host smart-b850b0a9-1be1-4c5e-97fd-bd04685904ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741857153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3741857153
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.856104550
Short name T584
Test name
Test status
Simulation time 2730793577 ps
CPU time 14.72 seconds
Started Mar 26 01:12:30 PM PDT 24
Finished Mar 26 01:12:44 PM PDT 24
Peak memory 264364 kb
Host smart-b3cd2796-1118-4359-8ec5-09406edabd57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856104550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.856104550
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.4136686340
Short name T1013
Test name
Test status
Simulation time 2564584693 ps
CPU time 34.73 seconds
Started Mar 26 01:12:33 PM PDT 24
Finished Mar 26 01:13:08 PM PDT 24
Peak memory 475856 kb
Host smart-ccfc5e28-7c3b-4abe-a56f-a252f47352ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136686340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.4136686340
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3078664759
Short name T521
Test name
Test status
Simulation time 18468966998 ps
CPU time 80.07 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:13:49 PM PDT 24
Peak memory 758416 kb
Host smart-b4026c67-937e-4157-9c61-d3e68eb317e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078664759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3078664759
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3659667373
Short name T322
Test name
Test status
Simulation time 130215576 ps
CPU time 1.28 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:12:31 PM PDT 24
Peak memory 204064 kb
Host smart-e7ac79f6-dcaf-476d-b085-284f61ec7b68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659667373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3659667373
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3972782374
Short name T624
Test name
Test status
Simulation time 659808635 ps
CPU time 4.98 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:12:36 PM PDT 24
Peak memory 233752 kb
Host smart-48765548-2a42-47bc-8964-6fc437acea39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972782374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3972782374
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.823248614
Short name T283
Test name
Test status
Simulation time 2821561132 ps
CPU time 77.79 seconds
Started Mar 26 01:12:30 PM PDT 24
Finished Mar 26 01:13:48 PM PDT 24
Peak memory 884500 kb
Host smart-4977c3db-3b1c-4e7a-9e4c-10fe0284cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823248614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.823248614
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_override.2564294974
Short name T451
Test name
Test status
Simulation time 51324225 ps
CPU time 0.65 seconds
Started Mar 26 01:12:28 PM PDT 24
Finished Mar 26 01:12:29 PM PDT 24
Peak memory 203908 kb
Host smart-95d6a0cd-e38f-4a9e-81be-53aad0253e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564294974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2564294974
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.654088481
Short name T722
Test name
Test status
Simulation time 27977361844 ps
CPU time 1354.13 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:35:04 PM PDT 24
Peak memory 204184 kb
Host smart-5796d216-ce58-4798-9ad8-2905826d950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654088481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.654088481
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1192146465
Short name T767
Test name
Test status
Simulation time 3765931912 ps
CPU time 42.32 seconds
Started Mar 26 01:12:30 PM PDT 24
Finished Mar 26 01:13:13 PM PDT 24
Peak memory 309796 kb
Host smart-99f2bdbf-7d12-4578-9786-184427497b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192146465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1192146465
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1145134993
Short name T1045
Test name
Test status
Simulation time 808462534 ps
CPU time 2.27 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:12:33 PM PDT 24
Peak memory 204212 kb
Host smart-1186779f-fbe5-4972-946a-7966656b7036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145134993 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1145134993
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.68017823
Short name T398
Test name
Test status
Simulation time 10187968701 ps
CPU time 16.72 seconds
Started Mar 26 01:12:28 PM PDT 24
Finished Mar 26 01:12:44 PM PDT 24
Peak memory 313892 kb
Host smart-abc983e3-225e-43ca-9d98-4ef12449abfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68017823 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_acq.68017823
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1226091659
Short name T983
Test name
Test status
Simulation time 10402189693 ps
CPU time 4.64 seconds
Started Mar 26 01:12:30 PM PDT 24
Finished Mar 26 01:12:35 PM PDT 24
Peak memory 236648 kb
Host smart-c7e52a84-a2ab-462f-8370-2462263452ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226091659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1226091659
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.32435418
Short name T687
Test name
Test status
Simulation time 400623826 ps
CPU time 2.56 seconds
Started Mar 26 01:12:33 PM PDT 24
Finished Mar 26 01:12:35 PM PDT 24
Peak memory 204052 kb
Host smart-cb336d8e-a591-421e-b7d2-163991a69196
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32435418 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.i2c_target_hrst.32435418
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1375278220
Short name T364
Test name
Test status
Simulation time 1366921448 ps
CPU time 7.07 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:12:36 PM PDT 24
Peak memory 207496 kb
Host smart-8161b35d-c765-4d59-b7c0-0ce4ec2652bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375278220 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1375278220
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1466496348
Short name T291
Test name
Test status
Simulation time 2686084525 ps
CPU time 26.14 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:12:57 PM PDT 24
Peak memory 204240 kb
Host smart-f739ca51-05a6-4b49-bf55-e1c729cb34da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466496348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1466496348
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1572426823
Short name T906
Test name
Test status
Simulation time 22523455356 ps
CPU time 29.91 seconds
Started Mar 26 01:12:32 PM PDT 24
Finished Mar 26 01:13:02 PM PDT 24
Peak memory 238852 kb
Host smart-5a023c51-fb06-4711-b595-e88a23b6d135
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572426823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1572426823
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2152653004
Short name T459
Test name
Test status
Simulation time 10157045155 ps
CPU time 23.55 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:12:55 PM PDT 24
Peak memory 204216 kb
Host smart-c88614cf-4951-400b-b6b2-5d15ac64b011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152653004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2152653004
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.69303058
Short name T716
Test name
Test status
Simulation time 4713124314 ps
CPU time 5.84 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:12:35 PM PDT 24
Peak memory 204308 kb
Host smart-63e44829-9ed1-42e6-9229-247cdd142881
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69303058 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_timeout.69303058
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1180070282
Short name T701
Test name
Test status
Simulation time 32817619 ps
CPU time 0.57 seconds
Started Mar 26 01:15:16 PM PDT 24
Finished Mar 26 01:15:16 PM PDT 24
Peak memory 203756 kb
Host smart-418643c2-76da-459f-9401-41310b10516a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180070282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1180070282
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.1806281314
Short name T28
Test name
Test status
Simulation time 44031171 ps
CPU time 1.86 seconds
Started Mar 26 01:15:19 PM PDT 24
Finished Mar 26 01:15:21 PM PDT 24
Peak memory 212352 kb
Host smart-02d3a08a-cef5-4f9c-8f80-c0ad53c271f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806281314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1806281314
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2113899399
Short name T370
Test name
Test status
Simulation time 138020194 ps
CPU time 7.32 seconds
Started Mar 26 01:15:16 PM PDT 24
Finished Mar 26 01:15:24 PM PDT 24
Peak memory 228256 kb
Host smart-4d9cd933-d869-413c-9684-6b7591722e2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113899399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2113899399
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2827942887
Short name T34
Test name
Test status
Simulation time 1634579635 ps
CPU time 107.43 seconds
Started Mar 26 01:15:18 PM PDT 24
Finished Mar 26 01:17:05 PM PDT 24
Peak memory 593944 kb
Host smart-5bc09def-0773-4dcc-83ce-08dd046f8124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827942887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2827942887
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.308685664
Short name T304
Test name
Test status
Simulation time 5088771407 ps
CPU time 152.07 seconds
Started Mar 26 01:15:15 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 686928 kb
Host smart-6d3ee298-0778-4bfb-93dc-6b704d5b69e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308685664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.308685664
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1533945888
Short name T1008
Test name
Test status
Simulation time 121607078 ps
CPU time 1.04 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 01:15:18 PM PDT 24
Peak memory 204100 kb
Host smart-6958fe0b-5f2b-4273-90c1-1bac9f981782
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533945888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1533945888
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.794746670
Short name T393
Test name
Test status
Simulation time 133627001 ps
CPU time 7.74 seconds
Started Mar 26 01:15:15 PM PDT 24
Finished Mar 26 01:15:23 PM PDT 24
Peak memory 226148 kb
Host smart-cf3e0ebe-441e-4f56-9ff5-f9e4d8f55cd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794746670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
794746670
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2811989507
Short name T176
Test name
Test status
Simulation time 14565864223 ps
CPU time 81.72 seconds
Started Mar 26 01:15:14 PM PDT 24
Finished Mar 26 01:16:37 PM PDT 24
Peak memory 1022772 kb
Host smart-afe575ea-7106-4864-ab18-572106c4e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811989507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2811989507
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_override.1024637044
Short name T981
Test name
Test status
Simulation time 45038494 ps
CPU time 0.62 seconds
Started Mar 26 01:15:21 PM PDT 24
Finished Mar 26 01:15:21 PM PDT 24
Peak memory 203848 kb
Host smart-515e87f7-8f7d-45ad-9614-1d2c41c30b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024637044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1024637044
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2676108561
Short name T712
Test name
Test status
Simulation time 6857222208 ps
CPU time 1640.01 seconds
Started Mar 26 01:15:14 PM PDT 24
Finished Mar 26 01:42:34 PM PDT 24
Peak memory 741400 kb
Host smart-fb9f867b-086f-45c2-a480-59321a817e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676108561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2676108561
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1334080603
Short name T257
Test name
Test status
Simulation time 9611562958 ps
CPU time 52.34 seconds
Started Mar 26 01:15:15 PM PDT 24
Finished Mar 26 01:16:07 PM PDT 24
Peak memory 285064 kb
Host smart-cd2e831e-cb13-41eb-b56f-6db33c7f3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334080603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1334080603
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2318184513
Short name T22
Test name
Test status
Simulation time 585047707 ps
CPU time 3.14 seconds
Started Mar 26 01:15:16 PM PDT 24
Finished Mar 26 01:15:19 PM PDT 24
Peak memory 204052 kb
Host smart-3192c234-004f-4480-bb1b-7f19aee7e9a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318184513 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2318184513
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.590797811
Short name T849
Test name
Test status
Simulation time 10097298498 ps
CPU time 91.2 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 01:16:48 PM PDT 24
Peak memory 752524 kb
Host smart-b9b123b8-912a-4c35-b8a8-e7050d853237
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590797811 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.590797811
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3872967025
Short name T404
Test name
Test status
Simulation time 471223651 ps
CPU time 2.76 seconds
Started Mar 26 01:15:20 PM PDT 24
Finished Mar 26 01:15:23 PM PDT 24
Peak memory 204144 kb
Host smart-aab811d9-b5d8-44d4-8ea7-fac57405a497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872967025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3872967025
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1405713103
Short name T488
Test name
Test status
Simulation time 7947766245 ps
CPU time 4.14 seconds
Started Mar 26 01:15:15 PM PDT 24
Finished Mar 26 01:15:19 PM PDT 24
Peak memory 204444 kb
Host smart-72b9813d-6c19-41ef-8d94-3666cb61d684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405713103 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1405713103
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3945151049
Short name T400
Test name
Test status
Simulation time 21477634352 ps
CPU time 7.09 seconds
Started Mar 26 01:15:18 PM PDT 24
Finished Mar 26 01:15:25 PM PDT 24
Peak memory 204148 kb
Host smart-63f5d821-377a-4551-be96-ec6224104cc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945151049 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3945151049
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1447744757
Short name T564
Test name
Test status
Simulation time 2677200037 ps
CPU time 10.85 seconds
Started Mar 26 01:15:14 PM PDT 24
Finished Mar 26 01:15:26 PM PDT 24
Peak memory 204216 kb
Host smart-eb6450c6-999d-4fbc-b59b-3ab56ba74f09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447744757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1447744757
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2036079096
Short name T831
Test name
Test status
Simulation time 564364793 ps
CPU time 8.99 seconds
Started Mar 26 01:15:18 PM PDT 24
Finished Mar 26 01:15:27 PM PDT 24
Peak memory 205076 kb
Host smart-7d88e1b7-c27d-493f-b119-451f1f787414
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036079096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2036079096
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.1219356986
Short name T924
Test name
Test status
Simulation time 41575379011 ps
CPU time 3570.9 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 02:14:48 PM PDT 24
Peak memory 5003676 kb
Host smart-1d8292c8-e87c-4cdb-b5c0-77feed363aaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219356986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.1219356986
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.96207515
Short name T1007
Test name
Test status
Simulation time 5079443396 ps
CPU time 6.78 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 01:15:24 PM PDT 24
Peak memory 220552 kb
Host smart-a169e9c3-f7ce-42ae-9a56-7b11387c6362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96207515 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_timeout.96207515
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1828133319
Short name T277
Test name
Test status
Simulation time 59289171 ps
CPU time 0.6 seconds
Started Mar 26 01:15:32 PM PDT 24
Finished Mar 26 01:15:33 PM PDT 24
Peak memory 203688 kb
Host smart-0dbcf8ca-2045-49c4-8e83-e06eeb4229f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828133319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1828133319
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2523675247
Short name T670
Test name
Test status
Simulation time 178071604 ps
CPU time 1.27 seconds
Started Mar 26 01:15:18 PM PDT 24
Finished Mar 26 01:15:20 PM PDT 24
Peak memory 212308 kb
Host smart-6ea6e5f2-15d8-437a-9e6d-8fc25271dcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523675247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2523675247
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2633645050
Short name T547
Test name
Test status
Simulation time 1389349705 ps
CPU time 7.93 seconds
Started Mar 26 01:15:19 PM PDT 24
Finished Mar 26 01:15:28 PM PDT 24
Peak memory 281400 kb
Host smart-5b3933c9-5f77-45a4-93bb-add5bfcab760
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633645050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2633645050
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1016085944
Short name T814
Test name
Test status
Simulation time 8170587498 ps
CPU time 57.96 seconds
Started Mar 26 01:15:16 PM PDT 24
Finished Mar 26 01:16:14 PM PDT 24
Peak memory 640144 kb
Host smart-7d9305fd-f800-4f0a-97cb-89e8e6632ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016085944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1016085944
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3615300561
Short name T599
Test name
Test status
Simulation time 1357176397 ps
CPU time 0.95 seconds
Started Mar 26 01:15:15 PM PDT 24
Finished Mar 26 01:15:17 PM PDT 24
Peak memory 204028 kb
Host smart-f32286ad-ef81-4837-8d56-b6546bb66d2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615300561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3615300561
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.1970145542
Short name T1081
Test name
Test status
Simulation time 172703293 ps
CPU time 4.77 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 01:15:22 PM PDT 24
Peak memory 234256 kb
Host smart-579b61f1-8862-402d-920f-0a56b26cda6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970145542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.1970145542
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3358257042
Short name T90
Test name
Test status
Simulation time 12498808247 ps
CPU time 82.7 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 01:16:40 PM PDT 24
Peak memory 889584 kb
Host smart-fa117697-3f20-425b-8b23-d4e99228f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358257042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3358257042
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_override.3407540787
Short name T205
Test name
Test status
Simulation time 26711131 ps
CPU time 0.66 seconds
Started Mar 26 01:15:16 PM PDT 24
Finished Mar 26 01:15:17 PM PDT 24
Peak memory 203724 kb
Host smart-aa1fe25e-653b-4a58-9eb1-f2e5fb6d55cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407540787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3407540787
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1708813690
Short name T512
Test name
Test status
Simulation time 3272805642 ps
CPU time 12.83 seconds
Started Mar 26 01:15:17 PM PDT 24
Finished Mar 26 01:15:31 PM PDT 24
Peak memory 223268 kb
Host smart-df8385d8-2bd2-49a9-8d14-cb403d3b2653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708813690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1708813690
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.173855686
Short name T526
Test name
Test status
Simulation time 7628725205 ps
CPU time 145.65 seconds
Started Mar 26 01:15:14 PM PDT 24
Finished Mar 26 01:17:40 PM PDT 24
Peak memory 315348 kb
Host smart-e360d7b2-1390-4250-a1b1-30df6f70458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173855686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.173855686
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3775605475
Short name T951
Test name
Test status
Simulation time 1948345758 ps
CPU time 4.58 seconds
Started Mar 26 01:15:33 PM PDT 24
Finished Mar 26 01:15:39 PM PDT 24
Peak memory 213552 kb
Host smart-8f210693-729f-490f-adaa-6af609cdb4b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775605475 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3775605475
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.14275592
Short name T68
Test name
Test status
Simulation time 10186557290 ps
CPU time 14.32 seconds
Started Mar 26 01:15:29 PM PDT 24
Finished Mar 26 01:15:44 PM PDT 24
Peak memory 294844 kb
Host smart-5bf2c48c-5bc6-4a4b-b0f8-b90a07d14c8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14275592 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_acq.14275592
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3680954439
Short name T287
Test name
Test status
Simulation time 10257385016 ps
CPU time 10.72 seconds
Started Mar 26 01:15:31 PM PDT 24
Finished Mar 26 01:15:42 PM PDT 24
Peak memory 292520 kb
Host smart-81db62ec-92b3-489c-ab79-6472cc8f59a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680954439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3680954439
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3035193513
Short name T1087
Test name
Test status
Simulation time 675441717 ps
CPU time 2.15 seconds
Started Mar 26 01:15:29 PM PDT 24
Finished Mar 26 01:15:31 PM PDT 24
Peak memory 204156 kb
Host smart-dd689a0e-97f2-4361-beca-8f3c799fa829
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035193513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3035193513
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3640324202
Short name T331
Test name
Test status
Simulation time 6109768800 ps
CPU time 7.34 seconds
Started Mar 26 01:15:29 PM PDT 24
Finished Mar 26 01:15:37 PM PDT 24
Peak memory 212428 kb
Host smart-043d6417-e1bc-47ff-aa0b-bca10d2b92af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640324202 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3640324202
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2730160498
Short name T1034
Test name
Test status
Simulation time 4417963606 ps
CPU time 7.33 seconds
Started Mar 26 01:15:30 PM PDT 24
Finished Mar 26 01:15:37 PM PDT 24
Peak memory 204176 kb
Host smart-4a4c8393-002a-477a-ba15-164225b3a21c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730160498 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2730160498
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.4037614661
Short name T812
Test name
Test status
Simulation time 951247407 ps
CPU time 10.41 seconds
Started Mar 26 01:15:15 PM PDT 24
Finished Mar 26 01:15:26 PM PDT 24
Peak memory 204072 kb
Host smart-7b04c210-61da-4b37-83f2-4056f8b759a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037614661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.4037614661
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.811348965
Short name T1026
Test name
Test status
Simulation time 1010584421 ps
CPU time 4.31 seconds
Started Mar 26 01:15:16 PM PDT 24
Finished Mar 26 01:15:20 PM PDT 24
Peak memory 204156 kb
Host smart-8298c6b6-ae44-4118-a747-fe35b12fe6ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811348965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.811348965
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.234719888
Short name T329
Test name
Test status
Simulation time 21110495120 ps
CPU time 1379.57 seconds
Started Mar 26 01:15:21 PM PDT 24
Finished Mar 26 01:38:21 PM PDT 24
Peak memory 4319556 kb
Host smart-624f12a2-edbe-4a6c-9f9e-5f6202deebab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234719888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.234719888
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1403809426
Short name T1043
Test name
Test status
Simulation time 1377626973 ps
CPU time 7.16 seconds
Started Mar 26 01:15:31 PM PDT 24
Finished Mar 26 01:15:38 PM PDT 24
Peak memory 204116 kb
Host smart-6a38668e-9bf2-4edb-a85b-dc74015bb134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403809426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1403809426
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1427419136
Short name T336
Test name
Test status
Simulation time 17181298 ps
CPU time 0.58 seconds
Started Mar 26 01:15:43 PM PDT 24
Finished Mar 26 01:15:44 PM PDT 24
Peak memory 203804 kb
Host smart-8f1b6401-3984-463d-ad0c-08999aafd950
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427419136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1427419136
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.482400809
Short name T50
Test name
Test status
Simulation time 31809263 ps
CPU time 1.35 seconds
Started Mar 26 01:15:34 PM PDT 24
Finished Mar 26 01:15:36 PM PDT 24
Peak memory 220504 kb
Host smart-880a9612-438c-4251-a48f-67b6f76eb53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482400809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.482400809
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3869900317
Short name T626
Test name
Test status
Simulation time 577965476 ps
CPU time 5.12 seconds
Started Mar 26 01:15:30 PM PDT 24
Finished Mar 26 01:15:35 PM PDT 24
Peak memory 249120 kb
Host smart-20e2a817-7660-469b-a2a9-f722939add7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869900317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3869900317
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3905628241
Short name T993
Test name
Test status
Simulation time 5188887534 ps
CPU time 68.96 seconds
Started Mar 26 01:15:30 PM PDT 24
Finished Mar 26 01:16:39 PM PDT 24
Peak memory 722552 kb
Host smart-98dfe5b8-ef39-43c6-9f0b-8377dc04dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905628241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3905628241
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1123737965
Short name T332
Test name
Test status
Simulation time 2584166911 ps
CPU time 90.96 seconds
Started Mar 26 01:15:30 PM PDT 24
Finished Mar 26 01:17:02 PM PDT 24
Peak memory 504868 kb
Host smart-22175eaf-a87c-44cc-8371-02183728a4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123737965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1123737965
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.804198723
Short name T677
Test name
Test status
Simulation time 406903841 ps
CPU time 0.88 seconds
Started Mar 26 01:15:33 PM PDT 24
Finished Mar 26 01:15:34 PM PDT 24
Peak memory 203860 kb
Host smart-9c59eae7-a2dd-460f-9b67-789121f6ceb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804198723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.804198723
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3253624825
Short name T946
Test name
Test status
Simulation time 164051130 ps
CPU time 9.65 seconds
Started Mar 26 01:15:32 PM PDT 24
Finished Mar 26 01:15:42 PM PDT 24
Peak memory 234536 kb
Host smart-7f866b25-4c7c-41cc-9180-138c614151d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253624825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3253624825
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1181030154
Short name T651
Test name
Test status
Simulation time 5275912182 ps
CPU time 165.04 seconds
Started Mar 26 01:15:31 PM PDT 24
Finished Mar 26 01:18:16 PM PDT 24
Peak memory 834748 kb
Host smart-5fb4b2d8-eae1-496c-bc7e-c101538a7587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181030154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1181030154
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_override.2951081168
Short name T908
Test name
Test status
Simulation time 30260952 ps
CPU time 0.63 seconds
Started Mar 26 01:15:31 PM PDT 24
Finished Mar 26 01:15:32 PM PDT 24
Peak memory 203788 kb
Host smart-6f1b7e3a-14f8-49aa-a1d1-a7f01f704c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951081168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2951081168
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1344808864
Short name T40
Test name
Test status
Simulation time 73294415283 ps
CPU time 2255.26 seconds
Started Mar 26 01:15:30 PM PDT 24
Finished Mar 26 01:53:06 PM PDT 24
Peak memory 1307308 kb
Host smart-cd2c0168-d20b-4ae0-94df-da9cd59c99c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344808864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1344808864
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1002860200
Short name T724
Test name
Test status
Simulation time 859116094 ps
CPU time 56.69 seconds
Started Mar 26 01:15:30 PM PDT 24
Finished Mar 26 01:16:27 PM PDT 24
Peak memory 253232 kb
Host smart-5a517c02-3824-45c8-ba1f-33928e62c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002860200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1002860200
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3489123358
Short name T1070
Test name
Test status
Simulation time 3514197700 ps
CPU time 4.37 seconds
Started Mar 26 01:15:31 PM PDT 24
Finished Mar 26 01:15:36 PM PDT 24
Peak memory 204296 kb
Host smart-bf969d75-db7f-497c-9bb2-5f1f1b3d2c67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489123358 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3489123358
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3857671935
Short name T75
Test name
Test status
Simulation time 10261534132 ps
CPU time 6.82 seconds
Started Mar 26 01:15:32 PM PDT 24
Finished Mar 26 01:15:39 PM PDT 24
Peak memory 239752 kb
Host smart-89b02e8a-1334-42c5-96b1-a4ef8aa3fa94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857671935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3857671935
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2700078007
Short name T107
Test name
Test status
Simulation time 10278081346 ps
CPU time 16.9 seconds
Started Mar 26 01:15:32 PM PDT 24
Finished Mar 26 01:15:49 PM PDT 24
Peak memory 346860 kb
Host smart-9903a880-add7-42c5-9779-2fbb9551f773
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700078007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2700078007
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.3936957216
Short name T484
Test name
Test status
Simulation time 1398499618 ps
CPU time 2.2 seconds
Started Mar 26 01:15:44 PM PDT 24
Finished Mar 26 01:15:47 PM PDT 24
Peak memory 204212 kb
Host smart-822f0ee9-b4f8-40ac-b1f1-a9e930384077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936957216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.3936957216
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1673339758
Short name T582
Test name
Test status
Simulation time 5115092805 ps
CPU time 7.29 seconds
Started Mar 26 01:15:32 PM PDT 24
Finished Mar 26 01:15:39 PM PDT 24
Peak memory 216980 kb
Host smart-8e40ef0b-1d27-48e6-850e-c8f7ecd734be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673339758 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1673339758
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1934384727
Short name T999
Test name
Test status
Simulation time 7641304921 ps
CPU time 4.69 seconds
Started Mar 26 01:15:31 PM PDT 24
Finished Mar 26 01:15:36 PM PDT 24
Peak memory 204244 kb
Host smart-53c25a23-77f2-4ff2-a339-425d35e74f28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934384727 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1934384727
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.2628125046
Short name T1079
Test name
Test status
Simulation time 5056332790 ps
CPU time 14.23 seconds
Started Mar 26 01:15:33 PM PDT 24
Finished Mar 26 01:15:47 PM PDT 24
Peak memory 204148 kb
Host smart-a193e4b0-7b45-4d18-9f99-a93fbb9c97a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628125046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.2628125046
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3649582206
Short name T658
Test name
Test status
Simulation time 2014015949 ps
CPU time 18.79 seconds
Started Mar 26 01:15:32 PM PDT 24
Finished Mar 26 01:15:51 PM PDT 24
Peak memory 204180 kb
Host smart-35d85b04-5899-48e7-a87a-12ab7111c136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649582206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3649582206
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.777731576
Short name T306
Test name
Test status
Simulation time 24465580316 ps
CPU time 898.44 seconds
Started Mar 26 01:15:29 PM PDT 24
Finished Mar 26 01:30:27 PM PDT 24
Peak memory 2214904 kb
Host smart-c01767a0-6e56-49bf-b9f7-adb88ed7086d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777731576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.777731576
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.267116739
Short name T794
Test name
Test status
Simulation time 1314537009 ps
CPU time 6.64 seconds
Started Mar 26 01:15:34 PM PDT 24
Finished Mar 26 01:15:41 PM PDT 24
Peak memory 204156 kb
Host smart-c078d846-e47c-43e8-830c-2dd3bbd8cbb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267116739 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.267116739
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.4012699032
Short name T199
Test name
Test status
Simulation time 22488738 ps
CPU time 0.58 seconds
Started Mar 26 01:15:44 PM PDT 24
Finished Mar 26 01:15:45 PM PDT 24
Peak memory 203816 kb
Host smart-846d7790-915a-4bd1-8f15-b98bd4aed73e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012699032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.4012699032
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1293979356
Short name T386
Test name
Test status
Simulation time 104928396 ps
CPU time 0.95 seconds
Started Mar 26 01:15:43 PM PDT 24
Finished Mar 26 01:15:45 PM PDT 24
Peak memory 212284 kb
Host smart-a324aad7-ed2c-4f79-8c52-d0fd51ec9880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293979356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1293979356
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.1334789460
Short name T915
Test name
Test status
Simulation time 968325314 ps
CPU time 4.93 seconds
Started Mar 26 01:15:44 PM PDT 24
Finished Mar 26 01:15:49 PM PDT 24
Peak memory 255372 kb
Host smart-a282ab9c-44fa-460f-8013-9c57e43492ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334789460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.1334789460
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.925057056
Short name T780
Test name
Test status
Simulation time 8688645519 ps
CPU time 149.99 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:18:16 PM PDT 24
Peak memory 725404 kb
Host smart-1067f83a-7cfe-4cc0-aaf7-842276d6ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925057056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.925057056
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1474201280
Short name T876
Test name
Test status
Simulation time 2026445000 ps
CPU time 153.08 seconds
Started Mar 26 01:15:44 PM PDT 24
Finished Mar 26 01:18:17 PM PDT 24
Peak memory 707576 kb
Host smart-7f11f770-30d6-49f5-8b62-70a32115db84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474201280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1474201280
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3991305652
Short name T39
Test name
Test status
Simulation time 229384068 ps
CPU time 1.03 seconds
Started Mar 26 01:15:48 PM PDT 24
Finished Mar 26 01:15:49 PM PDT 24
Peak memory 204092 kb
Host smart-d3f9c245-d432-4980-aefd-e80e6c59c4ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991305652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3991305652
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1256829659
Short name T645
Test name
Test status
Simulation time 121385544 ps
CPU time 3.16 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:15:51 PM PDT 24
Peak memory 204088 kb
Host smart-dab5fbd9-e930-4faa-8f34-444518d50df9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256829659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1256829659
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3665432564
Short name T411
Test name
Test status
Simulation time 55120210513 ps
CPU time 321.13 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:21:08 PM PDT 24
Peak memory 1157940 kb
Host smart-545bb548-4a92-4732-8cb3-e046ebdc5910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665432564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3665432564
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_override.3248396618
Short name T718
Test name
Test status
Simulation time 69822289 ps
CPU time 0.64 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:15:46 PM PDT 24
Peak memory 203800 kb
Host smart-bad94da9-22fe-4f99-9a6c-12c4ae3b57cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248396618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3248396618
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3059157455
Short name T1065
Test name
Test status
Simulation time 4213963210 ps
CPU time 33.85 seconds
Started Mar 26 01:15:46 PM PDT 24
Finished Mar 26 01:16:20 PM PDT 24
Peak memory 279996 kb
Host smart-6fb93c0a-75bb-4dfa-b5a8-c86f1e9a575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059157455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3059157455
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1489018104
Short name T1056
Test name
Test status
Simulation time 12333492184 ps
CPU time 572.62 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:25:18 PM PDT 24
Peak memory 2837168 kb
Host smart-0d4df6ef-ca74-4e65-8651-0b5bcf3bb659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489018104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1489018104
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1531021900
Short name T967
Test name
Test status
Simulation time 854761149 ps
CPU time 4.06 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:15:49 PM PDT 24
Peak memory 204188 kb
Host smart-5239d5ec-e581-471f-a2cb-c75cf7248a5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531021900 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1531021900
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2086220174
Short name T60
Test name
Test status
Simulation time 10369306015 ps
CPU time 13.49 seconds
Started Mar 26 01:15:51 PM PDT 24
Finished Mar 26 01:16:05 PM PDT 24
Peak memory 289216 kb
Host smart-358e1756-9509-4d6f-8af1-f4ea40ab8af6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086220174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2086220174
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3250769557
Short name T70
Test name
Test status
Simulation time 10202800411 ps
CPU time 15.64 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:16:01 PM PDT 24
Peak memory 341548 kb
Host smart-ad0ae308-0ad4-4b33-95c6-8b177bb7a716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250769557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3250769557
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3956829682
Short name T659
Test name
Test status
Simulation time 1268157618 ps
CPU time 1.96 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:15:47 PM PDT 24
Peak memory 204464 kb
Host smart-7fd5efe3-64f3-485e-a957-34514cf48802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956829682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3956829682
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1818476163
Short name T121
Test name
Test status
Simulation time 1016952020 ps
CPU time 4.93 seconds
Started Mar 26 01:15:49 PM PDT 24
Finished Mar 26 01:15:54 PM PDT 24
Peak memory 210036 kb
Host smart-8ac9961a-47d0-4869-bb1f-9988ecd92316
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818476163 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1818476163
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2236075463
Short name T723
Test name
Test status
Simulation time 7666517125 ps
CPU time 12.5 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:15:57 PM PDT 24
Peak memory 204252 kb
Host smart-053923ee-5d45-4b5d-846f-998e30cd3fda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236075463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2236075463
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1102187310
Short name T368
Test name
Test status
Simulation time 1101449078 ps
CPU time 47.88 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:16:35 PM PDT 24
Peak memory 204096 kb
Host smart-f97db52b-8a7a-4512-8a0c-958cc67a34b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102187310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1102187310
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3320648509
Short name T542
Test name
Test status
Simulation time 25275431656 ps
CPU time 1259.64 seconds
Started Mar 26 01:15:44 PM PDT 24
Finished Mar 26 01:36:45 PM PDT 24
Peak memory 2985104 kb
Host smart-ba69551c-c43a-4da9-93cd-058245f725b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320648509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3320648509
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3203853571
Short name T616
Test name
Test status
Simulation time 2705834924 ps
CPU time 6.36 seconds
Started Mar 26 01:15:44 PM PDT 24
Finished Mar 26 01:15:51 PM PDT 24
Peak memory 212560 kb
Host smart-f7740f94-1adb-43e1-8cd7-bac02dbf2942
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203853571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3203853571
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.4287695680
Short name T323
Test name
Test status
Simulation time 28603985 ps
CPU time 0.63 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:00 PM PDT 24
Peak memory 203660 kb
Host smart-c518211a-90d0-4ae0-a382-45d7e110e6ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287695680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.4287695680
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3378003964
Short name T225
Test name
Test status
Simulation time 85494781 ps
CPU time 1.22 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:15:48 PM PDT 24
Peak memory 212432 kb
Host smart-d2a9f066-0cb1-45e0-b807-870e04e54488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378003964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3378003964
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3511069235
Short name T106
Test name
Test status
Simulation time 192474013 ps
CPU time 9.56 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:15:56 PM PDT 24
Peak memory 239584 kb
Host smart-11f5e826-3dd3-4293-a80e-2a5fcbecd8e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511069235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3511069235
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.184371833
Short name T661
Test name
Test status
Simulation time 17051892130 ps
CPU time 72.49 seconds
Started Mar 26 01:15:45 PM PDT 24
Finished Mar 26 01:16:58 PM PDT 24
Peak memory 379296 kb
Host smart-d0188dd7-14d8-4642-bd8d-77c4d774d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184371833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.184371833
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3876528556
Short name T58
Test name
Test status
Simulation time 6733555439 ps
CPU time 43.32 seconds
Started Mar 26 01:15:43 PM PDT 24
Finished Mar 26 01:16:26 PM PDT 24
Peak memory 565556 kb
Host smart-8b99e775-2ec1-4c72-900b-8943ecdbc8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876528556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3876528556
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3455176840
Short name T685
Test name
Test status
Simulation time 99045228 ps
CPU time 0.95 seconds
Started Mar 26 01:15:49 PM PDT 24
Finished Mar 26 01:15:50 PM PDT 24
Peak memory 203456 kb
Host smart-66f05979-59bb-4e88-9c1f-70ec6c21cb2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455176840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3455176840
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2098407406
Short name T708
Test name
Test status
Simulation time 412028408 ps
CPU time 2.82 seconds
Started Mar 26 01:15:50 PM PDT 24
Finished Mar 26 01:15:53 PM PDT 24
Peak memory 204108 kb
Host smart-3f5afa3f-e762-4201-b782-c500fa720e11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098407406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2098407406
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3809987219
Short name T838
Test name
Test status
Simulation time 3084483869 ps
CPU time 183 seconds
Started Mar 26 01:15:44 PM PDT 24
Finished Mar 26 01:18:48 PM PDT 24
Peak memory 855704 kb
Host smart-43c5b7a0-5241-462e-9b92-70f0ae430bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809987219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3809987219
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_override.1858651153
Short name T208
Test name
Test status
Simulation time 19687769 ps
CPU time 0.65 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:15:48 PM PDT 24
Peak memory 203756 kb
Host smart-5c6afcc4-5c7a-451a-837c-6c2ea75f028a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858651153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1858651153
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2868761573
Short name T844
Test name
Test status
Simulation time 71440764790 ps
CPU time 615.85 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:26:03 PM PDT 24
Peak memory 216720 kb
Host smart-e59209f4-cd24-4239-9f64-fac3ba693672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868761573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2868761573
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.646172259
Short name T615
Test name
Test status
Simulation time 21043590161 ps
CPU time 142.24 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:18:09 PM PDT 24
Peak memory 313880 kb
Host smart-cfd90a5b-c5c7-43a9-92a5-43e816971e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646172259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.646172259
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.3018626036
Short name T221
Test name
Test status
Simulation time 39681406432 ps
CPU time 2415.04 seconds
Started Mar 26 01:15:47 PM PDT 24
Finished Mar 26 01:56:02 PM PDT 24
Peak memory 2752380 kb
Host smart-29adf7ee-c5bb-490f-a84a-9a0f5a762e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018626036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.3018626036
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.854374557
Short name T859
Test name
Test status
Simulation time 1901201038 ps
CPU time 2.7 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:02 PM PDT 24
Peak memory 204108 kb
Host smart-9ae64b31-b8c9-4dab-9308-0543e7db94a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854374557 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.854374557
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.820048236
Short name T469
Test name
Test status
Simulation time 12354596703 ps
CPU time 3.3 seconds
Started Mar 26 01:16:05 PM PDT 24
Finished Mar 26 01:16:09 PM PDT 24
Peak memory 217696 kb
Host smart-1cbd8929-5794-47bc-93a1-f576b6e83327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820048236 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.820048236
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.3323242452
Short name T630
Test name
Test status
Simulation time 10119701855 ps
CPU time 39.05 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:38 PM PDT 24
Peak memory 452960 kb
Host smart-bea0f755-048c-462e-9857-565ebaade524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323242452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.3323242452
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.3262162279
Short name T46
Test name
Test status
Simulation time 2100575310 ps
CPU time 3.15 seconds
Started Mar 26 01:16:00 PM PDT 24
Finished Mar 26 01:16:03 PM PDT 24
Peak memory 204132 kb
Host smart-90a9baeb-3736-4530-b202-c5102f55f371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262162279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.3262162279
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1109018036
Short name T625
Test name
Test status
Simulation time 646662870 ps
CPU time 3.89 seconds
Started Mar 26 01:16:01 PM PDT 24
Finished Mar 26 01:16:04 PM PDT 24
Peak memory 204164 kb
Host smart-dcf304e4-2ad2-4619-bfb3-9b9cc700a8a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109018036 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1109018036
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1359377387
Short name T414
Test name
Test status
Simulation time 2607858286 ps
CPU time 28.33 seconds
Started Mar 26 01:15:48 PM PDT 24
Finished Mar 26 01:16:17 PM PDT 24
Peak memory 204236 kb
Host smart-85a2d9bf-1665-4699-b121-2d98e77a2a0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359377387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1359377387
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2050469179
Short name T798
Test name
Test status
Simulation time 1773617549 ps
CPU time 39.46 seconds
Started Mar 26 01:15:46 PM PDT 24
Finished Mar 26 01:16:26 PM PDT 24
Peak memory 204060 kb
Host smart-7ceb049c-e9f3-4368-86ce-93aa946152c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050469179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2050469179
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2036446937
Short name T293
Test name
Test status
Simulation time 6226956241 ps
CPU time 25.29 seconds
Started Mar 26 01:15:57 PM PDT 24
Finished Mar 26 01:16:22 PM PDT 24
Peak memory 472792 kb
Host smart-da7f7f28-0c05-4121-a35e-9a8af95bcb8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036446937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2036446937
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1077479723
Short name T352
Test name
Test status
Simulation time 2693565402 ps
CPU time 7.03 seconds
Started Mar 26 01:16:01 PM PDT 24
Finished Mar 26 01:16:08 PM PDT 24
Peak memory 214156 kb
Host smart-d4437628-137d-4fc4-a705-21502f3ae0cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077479723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1077479723
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.3317047562
Short name T222
Test name
Test status
Simulation time 1109601844 ps
CPU time 7.46 seconds
Started Mar 26 01:15:58 PM PDT 24
Finished Mar 26 01:16:05 PM PDT 24
Peak memory 204068 kb
Host smart-3c5be256-63fb-40cc-b4f1-1098790dbe85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317047562 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.i2c_target_unexp_stop.3317047562
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.4177816527
Short name T102
Test name
Test status
Simulation time 55608433 ps
CPU time 0.62 seconds
Started Mar 26 01:16:12 PM PDT 24
Finished Mar 26 01:16:13 PM PDT 24
Peak memory 203700 kb
Host smart-0d4a4c13-3681-4ec8-827c-a1c7576a8154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177816527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.4177816527
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2334666815
Short name T668
Test name
Test status
Simulation time 31137255 ps
CPU time 1.54 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:00 PM PDT 24
Peak memory 212304 kb
Host smart-86bfadbb-6d11-43a8-aa71-d4b43960b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334666815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2334666815
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2298980162
Short name T511
Test name
Test status
Simulation time 1105353790 ps
CPU time 11.48 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:10 PM PDT 24
Peak memory 247596 kb
Host smart-ea60770e-5af7-4740-98c9-40833e93e6a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298980162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2298980162
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3446083369
Short name T324
Test name
Test status
Simulation time 1658804498 ps
CPU time 95.3 seconds
Started Mar 26 01:15:58 PM PDT 24
Finished Mar 26 01:17:34 PM PDT 24
Peak memory 463076 kb
Host smart-bd609ecd-b8d8-4ac6-914b-d65b5973e91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446083369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3446083369
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3501001439
Short name T1091
Test name
Test status
Simulation time 7895404200 ps
CPU time 126.84 seconds
Started Mar 26 01:15:57 PM PDT 24
Finished Mar 26 01:18:04 PM PDT 24
Peak memory 528244 kb
Host smart-8bfd8ddb-94c9-4f0c-b8f4-20ae2e665e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501001439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3501001439
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1824137888
Short name T1052
Test name
Test status
Simulation time 1548552100 ps
CPU time 0.93 seconds
Started Mar 26 01:15:58 PM PDT 24
Finished Mar 26 01:15:59 PM PDT 24
Peak memory 203868 kb
Host smart-9c0a1029-5ce4-49af-9605-667e5195db0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824137888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1824137888
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3102932303
Short name T454
Test name
Test status
Simulation time 627349078 ps
CPU time 7.14 seconds
Started Mar 26 01:15:58 PM PDT 24
Finished Mar 26 01:16:05 PM PDT 24
Peak memory 223888 kb
Host smart-5f990c85-79fa-4759-8d57-8bea31ecfe61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102932303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3102932303
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3878674950
Short name T817
Test name
Test status
Simulation time 6853040899 ps
CPU time 229.95 seconds
Started Mar 26 01:16:01 PM PDT 24
Finished Mar 26 01:19:51 PM PDT 24
Peak memory 962876 kb
Host smart-cf180932-ec0c-4897-afff-78274b8c317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878674950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3878674950
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_override.1933111516
Short name T387
Test name
Test status
Simulation time 82574802 ps
CPU time 0.65 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:00 PM PDT 24
Peak memory 203808 kb
Host smart-6af0888b-7b1e-4648-ae1b-7ac6f3f7427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933111516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1933111516
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2535467992
Short name T1042
Test name
Test status
Simulation time 7539280084 ps
CPU time 782.22 seconds
Started Mar 26 01:15:56 PM PDT 24
Finished Mar 26 01:28:58 PM PDT 24
Peak memory 797004 kb
Host smart-7b90a159-b133-4e8b-8f28-e7dd6cce1be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535467992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2535467992
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.3160751117
Short name T986
Test name
Test status
Simulation time 3538059626 ps
CPU time 28.74 seconds
Started Mar 26 01:15:58 PM PDT 24
Finished Mar 26 01:16:27 PM PDT 24
Peak memory 262544 kb
Host smart-993db998-a151-4ade-b492-b7605a5457ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160751117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.3160751117
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1874768376
Short name T371
Test name
Test status
Simulation time 629815729 ps
CPU time 3.51 seconds
Started Mar 26 01:16:13 PM PDT 24
Finished Mar 26 01:16:17 PM PDT 24
Peak memory 212252 kb
Host smart-cd2841de-0fcd-4a51-a14d-258cfe025033
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874768376 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1874768376
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.68775246
Short name T431
Test name
Test status
Simulation time 10330185237 ps
CPU time 8.75 seconds
Started Mar 26 01:16:01 PM PDT 24
Finished Mar 26 01:16:10 PM PDT 24
Peak memory 254336 kb
Host smart-737d940a-5fe2-459b-b0b1-9a5349fd8397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68775246 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_acq.68775246
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1639448452
Short name T952
Test name
Test status
Simulation time 10856173041 ps
CPU time 6.85 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:06 PM PDT 24
Peak memory 268112 kb
Host smart-e547809a-821c-4107-91cc-204c61377327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639448452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1639448452
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.4236029595
Short name T125
Test name
Test status
Simulation time 1720628820 ps
CPU time 2.1 seconds
Started Mar 26 01:16:11 PM PDT 24
Finished Mar 26 01:16:13 PM PDT 24
Peak memory 204096 kb
Host smart-e3bd901c-6b46-4549-9432-8f14275969ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236029595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.4236029595
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1696228387
Short name T771
Test name
Test status
Simulation time 2550605366 ps
CPU time 3.35 seconds
Started Mar 26 01:15:58 PM PDT 24
Finished Mar 26 01:16:02 PM PDT 24
Peak memory 204188 kb
Host smart-19769e57-b540-4a10-be8d-e6cced65f114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696228387 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1696228387
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.228246132
Short name T710
Test name
Test status
Simulation time 3833495796 ps
CPU time 10.05 seconds
Started Mar 26 01:15:59 PM PDT 24
Finished Mar 26 01:16:09 PM PDT 24
Peak memory 204176 kb
Host smart-b99e2269-e54e-44a1-8d90-54a66e7f4486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228246132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.228246132
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.154640284
Short name T820
Test name
Test status
Simulation time 1667644583 ps
CPU time 32.19 seconds
Started Mar 26 01:16:00 PM PDT 24
Finished Mar 26 01:16:33 PM PDT 24
Peak memory 223680 kb
Host smart-b297ac9e-28d2-495e-aac2-eb70b61a549a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154640284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.154640284
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1891900289
Short name T609
Test name
Test status
Simulation time 38500313503 ps
CPU time 237.45 seconds
Started Mar 26 01:15:57 PM PDT 24
Finished Mar 26 01:19:54 PM PDT 24
Peak memory 2165376 kb
Host smart-ac9ef4f1-2acd-4ad4-947f-0eec03f92286
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891900289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1891900289
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.1654841026
Short name T1095
Test name
Test status
Simulation time 3793809258 ps
CPU time 7.2 seconds
Started Mar 26 01:16:01 PM PDT 24
Finished Mar 26 01:16:08 PM PDT 24
Peak memory 212320 kb
Host smart-c22239bf-fde8-479c-8428-5cfa2903ec54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654841026 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.1654841026
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.1110922736
Short name T928
Test name
Test status
Simulation time 41742486 ps
CPU time 0.61 seconds
Started Mar 26 01:16:18 PM PDT 24
Finished Mar 26 01:16:18 PM PDT 24
Peak memory 203748 kb
Host smart-89147659-adc7-4aba-8c49-c19be7395fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110922736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.1110922736
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2566676381
Short name T656
Test name
Test status
Simulation time 28325043 ps
CPU time 1.3 seconds
Started Mar 26 01:16:15 PM PDT 24
Finished Mar 26 01:16:16 PM PDT 24
Peak memory 212280 kb
Host smart-02bc3662-8d23-4faa-b442-44da8afecdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566676381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2566676381
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3015257768
Short name T1051
Test name
Test status
Simulation time 239439234 ps
CPU time 5.42 seconds
Started Mar 26 01:16:13 PM PDT 24
Finished Mar 26 01:16:19 PM PDT 24
Peak memory 247876 kb
Host smart-e4ce1e5a-8664-4978-8718-4d6a4d09f9fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015257768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3015257768
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.4080276806
Short name T559
Test name
Test status
Simulation time 2035560313 ps
CPU time 77.13 seconds
Started Mar 26 01:16:16 PM PDT 24
Finished Mar 26 01:17:33 PM PDT 24
Peak memory 705744 kb
Host smart-5a537a21-4bb4-435f-8032-8764d8e42491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080276806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.4080276806
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1033190768
Short name T702
Test name
Test status
Simulation time 3164389748 ps
CPU time 45.31 seconds
Started Mar 26 01:16:21 PM PDT 24
Finished Mar 26 01:17:07 PM PDT 24
Peak memory 583384 kb
Host smart-4f596c55-3e2a-4f33-b6af-6adda6627e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033190768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1033190768
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2136475476
Short name T1028
Test name
Test status
Simulation time 1214331278 ps
CPU time 1.11 seconds
Started Mar 26 01:16:12 PM PDT 24
Finished Mar 26 01:16:13 PM PDT 24
Peak memory 204012 kb
Host smart-9fd8101c-3f87-4ffd-bb88-f3da2847f175
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136475476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2136475476
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2117224925
Short name T1080
Test name
Test status
Simulation time 3039472357 ps
CPU time 4.03 seconds
Started Mar 26 01:16:14 PM PDT 24
Finished Mar 26 01:16:18 PM PDT 24
Peak memory 204308 kb
Host smart-479742d7-69ec-4eb7-93bf-5ca6bd80d1e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117224925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2117224925
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.735398700
Short name T175
Test name
Test status
Simulation time 23838478056 ps
CPU time 99.44 seconds
Started Mar 26 01:16:17 PM PDT 24
Finished Mar 26 01:17:57 PM PDT 24
Peak memory 1119376 kb
Host smart-159c7482-62d7-41b0-9bff-203fb306c0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735398700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.735398700
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_override.4021532354
Short name T805
Test name
Test status
Simulation time 17438172 ps
CPU time 0.64 seconds
Started Mar 26 01:16:15 PM PDT 24
Finished Mar 26 01:16:16 PM PDT 24
Peak memory 203760 kb
Host smart-152c8fc7-b10e-4132-9934-123e36aefcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021532354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4021532354
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1103844652
Short name T860
Test name
Test status
Simulation time 602614439 ps
CPU time 26.85 seconds
Started Mar 26 01:16:15 PM PDT 24
Finished Mar 26 01:16:42 PM PDT 24
Peak memory 220524 kb
Host smart-9bd6facd-7dd7-4e32-a8b3-2a5485b1fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103844652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1103844652
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1241304963
Short name T231
Test name
Test status
Simulation time 4820481879 ps
CPU time 89.31 seconds
Started Mar 26 01:16:13 PM PDT 24
Finished Mar 26 01:17:43 PM PDT 24
Peak memory 277504 kb
Host smart-607b2e71-1364-4b33-a2e6-7bf9963fe5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241304963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1241304963
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.748108207
Short name T575
Test name
Test status
Simulation time 1138474613 ps
CPU time 4.76 seconds
Started Mar 26 01:16:15 PM PDT 24
Finished Mar 26 01:16:20 PM PDT 24
Peak memory 204256 kb
Host smart-29af711d-17ee-4485-ac68-9c2c363bdf33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748108207 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.748108207
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3307098718
Short name T632
Test name
Test status
Simulation time 10283044807 ps
CPU time 15.44 seconds
Started Mar 26 01:16:16 PM PDT 24
Finished Mar 26 01:16:32 PM PDT 24
Peak memory 307084 kb
Host smart-8beef194-d07a-4a67-9491-55b85b46f1e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307098718 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3307098718
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1454157495
Short name T26
Test name
Test status
Simulation time 445214594 ps
CPU time 2.12 seconds
Started Mar 26 01:16:17 PM PDT 24
Finished Mar 26 01:16:19 PM PDT 24
Peak memory 204056 kb
Host smart-8bccfaea-5f10-4b52-b36c-0c5a56f05a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454157495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1454157495
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1028305017
Short name T745
Test name
Test status
Simulation time 1126782702 ps
CPU time 5.23 seconds
Started Mar 26 01:16:21 PM PDT 24
Finished Mar 26 01:16:26 PM PDT 24
Peak memory 212356 kb
Host smart-4e257e0e-780a-4c68-983f-a86f15fbbdd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028305017 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1028305017
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1024144230
Short name T830
Test name
Test status
Simulation time 822494730 ps
CPU time 29.87 seconds
Started Mar 26 01:16:14 PM PDT 24
Finished Mar 26 01:16:44 PM PDT 24
Peak memory 204112 kb
Host smart-40fc4ad6-e794-48e3-b38b-e5151e4fa7c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024144230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1024144230
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3175017691
Short name T943
Test name
Test status
Simulation time 1445877699 ps
CPU time 11.45 seconds
Started Mar 26 01:16:19 PM PDT 24
Finished Mar 26 01:16:30 PM PDT 24
Peak memory 208840 kb
Host smart-cfb95e10-e9f5-4b86-967b-47e507242fa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175017691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3175017691
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.329457403
Short name T381
Test name
Test status
Simulation time 1304411556 ps
CPU time 7.53 seconds
Started Mar 26 01:16:18 PM PDT 24
Finished Mar 26 01:16:25 PM PDT 24
Peak memory 220308 kb
Host smart-899a2320-bb8a-46eb-8fa8-cb3611f6868e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329457403 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.329457403
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2589025306
Short name T675
Test name
Test status
Simulation time 29547631 ps
CPU time 0.61 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:16:26 PM PDT 24
Peak memory 203776 kb
Host smart-c753a5fe-04fa-4def-923e-af923cef8848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589025306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2589025306
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2229667758
Short name T363
Test name
Test status
Simulation time 376906967 ps
CPU time 1.54 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:16:27 PM PDT 24
Peak memory 212332 kb
Host smart-7da61285-6165-4395-a9f4-e109f00bd7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229667758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2229667758
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3825041651
Short name T674
Test name
Test status
Simulation time 986210760 ps
CPU time 12.74 seconds
Started Mar 26 01:16:18 PM PDT 24
Finished Mar 26 01:16:31 PM PDT 24
Peak memory 244808 kb
Host smart-cf2fd54f-5a52-47ee-a4b0-6c4596e50502
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825041651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3825041651
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.655660960
Short name T762
Test name
Test status
Simulation time 3661806965 ps
CPU time 50.74 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:17:16 PM PDT 24
Peak memory 487484 kb
Host smart-ed5e0c19-b027-4240-b6c3-20d709660dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655660960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.655660960
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1614208398
Short name T1061
Test name
Test status
Simulation time 2165752085 ps
CPU time 64.63 seconds
Started Mar 26 01:16:22 PM PDT 24
Finished Mar 26 01:17:26 PM PDT 24
Peak memory 379672 kb
Host smart-e90c72f5-d43e-492a-8001-2a1dfcc5dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614208398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1614208398
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.4288959585
Short name T375
Test name
Test status
Simulation time 106840171 ps
CPU time 1.01 seconds
Started Mar 26 01:16:22 PM PDT 24
Finished Mar 26 01:16:23 PM PDT 24
Peak memory 203804 kb
Host smart-386d83a8-20c8-431b-aeec-b365923efd21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288959585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.4288959585
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1330436366
Short name T305
Test name
Test status
Simulation time 736197585 ps
CPU time 3.21 seconds
Started Mar 26 01:16:19 PM PDT 24
Finished Mar 26 01:16:22 PM PDT 24
Peak memory 224464 kb
Host smart-b46ceec7-0eb8-4ea9-8055-93ae3040d6bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330436366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1330436366
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2884482609
Short name T243
Test name
Test status
Simulation time 12199255987 ps
CPU time 174.29 seconds
Started Mar 26 01:16:20 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 873356 kb
Host smart-7fc54bde-ef61-422e-8329-751de91ef300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884482609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2884482609
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_override.1031728276
Short name T974
Test name
Test status
Simulation time 34620123 ps
CPU time 0.63 seconds
Started Mar 26 01:16:17 PM PDT 24
Finished Mar 26 01:16:18 PM PDT 24
Peak memory 203768 kb
Host smart-6ad314ad-67a9-4dfe-9182-9a430142570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031728276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1031728276
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.258857231
Short name T1067
Test name
Test status
Simulation time 544253907 ps
CPU time 43.36 seconds
Started Mar 26 01:16:18 PM PDT 24
Finished Mar 26 01:17:02 PM PDT 24
Peak memory 246776 kb
Host smart-377eadc6-d535-4a4a-b2f3-ce930f5ad209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258857231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.258857231
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.4089973750
Short name T545
Test name
Test status
Simulation time 1703572469 ps
CPU time 79.39 seconds
Started Mar 26 01:16:19 PM PDT 24
Finished Mar 26 01:17:39 PM PDT 24
Peak memory 356084 kb
Host smart-498913d1-4253-4f7f-81b3-ab79c5c8fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089973750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.4089973750
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2116931508
Short name T30
Test name
Test status
Simulation time 58379860323 ps
CPU time 715.44 seconds
Started Mar 26 01:16:23 PM PDT 24
Finished Mar 26 01:28:19 PM PDT 24
Peak memory 1380656 kb
Host smart-f5ed36cb-a543-4d06-ab39-a3d403a631af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116931508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2116931508
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3371805492
Short name T825
Test name
Test status
Simulation time 860057287 ps
CPU time 4.24 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:16:30 PM PDT 24
Peak memory 204128 kb
Host smart-2f0cb9e1-15d5-48ef-a053-00e492ed46be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371805492 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3371805492
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3722473596
Short name T739
Test name
Test status
Simulation time 10051032688 ps
CPU time 75.66 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:17:42 PM PDT 24
Peak memory 610184 kb
Host smart-d45cba62-c8aa-452e-91a1-874eda38c846
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722473596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3722473596
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.4129633504
Short name T836
Test name
Test status
Simulation time 10282330987 ps
CPU time 18.8 seconds
Started Mar 26 01:16:24 PM PDT 24
Finished Mar 26 01:16:43 PM PDT 24
Peak memory 343140 kb
Host smart-f3879715-9ce9-4fdf-a59e-1b57af1074e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129633504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.4129633504
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1675893534
Short name T289
Test name
Test status
Simulation time 970308154 ps
CPU time 3.03 seconds
Started Mar 26 01:16:24 PM PDT 24
Finished Mar 26 01:16:27 PM PDT 24
Peak memory 204216 kb
Host smart-fcb4d434-a637-48fa-803f-c637a513682b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675893534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1675893534
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2759081630
Short name T379
Test name
Test status
Simulation time 1565401168 ps
CPU time 4.21 seconds
Started Mar 26 01:16:24 PM PDT 24
Finished Mar 26 01:16:29 PM PDT 24
Peak memory 204124 kb
Host smart-36ec5bf4-1a12-497f-bc77-98dc3cec65d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759081630 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2759081630
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3220112828
Short name T478
Test name
Test status
Simulation time 4023637130 ps
CPU time 3.11 seconds
Started Mar 26 01:16:23 PM PDT 24
Finished Mar 26 01:16:26 PM PDT 24
Peak memory 204144 kb
Host smart-faf115bb-cf71-4008-aff8-8eb263a2c80b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220112828 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3220112828
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2323577665
Short name T694
Test name
Test status
Simulation time 4223168279 ps
CPU time 15.38 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:16:41 PM PDT 24
Peak memory 204308 kb
Host smart-c837cbb2-1bea-4bba-a67e-02447027cc56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323577665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2323577665
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1758227085
Short name T1016
Test name
Test status
Simulation time 1575315229 ps
CPU time 24.21 seconds
Started Mar 26 01:16:23 PM PDT 24
Finished Mar 26 01:16:47 PM PDT 24
Peak memory 220416 kb
Host smart-e9faaf87-39dd-4777-a64a-a242534ed118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758227085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1758227085
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.568740520
Short name T259
Test name
Test status
Simulation time 8152060466 ps
CPU time 105.55 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:18:12 PM PDT 24
Peak memory 635064 kb
Host smart-ff4d15ab-43fa-48bf-9323-47073cacb9bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568740520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_t
arget_stretch.568740520
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.195006033
Short name T1060
Test name
Test status
Simulation time 1484410936 ps
CPU time 6.89 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:16:33 PM PDT 24
Peak memory 218600 kb
Host smart-b78f7d71-2988-459e-ba1f-d4849214d4b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195006033 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.195006033
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2961719896
Short name T1
Test name
Test status
Simulation time 15486129 ps
CPU time 0.62 seconds
Started Mar 26 01:16:34 PM PDT 24
Finished Mar 26 01:16:34 PM PDT 24
Peak memory 203680 kb
Host smart-0b125639-f3d6-4457-850c-88fd2f99798b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961719896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2961719896
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1242556902
Short name T857
Test name
Test status
Simulation time 33469338 ps
CPU time 1.06 seconds
Started Mar 26 01:16:27 PM PDT 24
Finished Mar 26 01:16:28 PM PDT 24
Peak memory 212316 kb
Host smart-8163c44b-8f6b-40d2-b3b5-9d22bfa58126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242556902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1242556902
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.620551674
Short name T297
Test name
Test status
Simulation time 3558572875 ps
CPU time 11.45 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:16:38 PM PDT 24
Peak memory 249192 kb
Host smart-2ecae66e-df1e-4738-9ec5-d4c53abe020d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620551674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.620551674
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.4072410869
Short name T64
Test name
Test status
Simulation time 4668544938 ps
CPU time 60.18 seconds
Started Mar 26 01:16:27 PM PDT 24
Finished Mar 26 01:17:27 PM PDT 24
Peak memory 426676 kb
Host smart-5f104edc-5579-4c7b-90c5-2518f71fed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072410869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.4072410869
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.419585337
Short name T600
Test name
Test status
Simulation time 2392615992 ps
CPU time 77.97 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:17:43 PM PDT 24
Peak memory 752376 kb
Host smart-180304ce-7f21-4bf7-a269-11db65e207b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419585337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.419585337
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3605362515
Short name T428
Test name
Test status
Simulation time 396221177 ps
CPU time 0.96 seconds
Started Mar 26 01:16:24 PM PDT 24
Finished Mar 26 01:16:25 PM PDT 24
Peak memory 203924 kb
Host smart-361c0df9-94b9-4dc8-afa7-ac378aac8bcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605362515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3605362515
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1535443539
Short name T882
Test name
Test status
Simulation time 300491568 ps
CPU time 3.43 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:16:29 PM PDT 24
Peak memory 204084 kb
Host smart-24a25b21-fb32-4742-8846-92ec819a7f03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535443539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1535443539
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3378536775
Short name T1084
Test name
Test status
Simulation time 7228290363 ps
CPU time 250.76 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:20:35 PM PDT 24
Peak memory 1068524 kb
Host smart-87e533df-cf61-4fdb-aa4f-60625ec41072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378536775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3378536775
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_override.1764563749
Short name T893
Test name
Test status
Simulation time 51214816 ps
CPU time 0.68 seconds
Started Mar 26 01:16:25 PM PDT 24
Finished Mar 26 01:16:26 PM PDT 24
Peak memory 203804 kb
Host smart-cbc03268-f5b0-464e-97f2-c2f78c3ac49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764563749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1764563749
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.4010728348
Short name T781
Test name
Test status
Simulation time 26514326945 ps
CPU time 3004.95 seconds
Started Mar 26 01:16:24 PM PDT 24
Finished Mar 26 02:06:29 PM PDT 24
Peak memory 890784 kb
Host smart-262f8e17-c3a1-4d24-ac85-446c874a710b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010728348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4010728348
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1356971406
Short name T372
Test name
Test status
Simulation time 2923634402 ps
CPU time 70.69 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:17:36 PM PDT 24
Peak memory 351808 kb
Host smart-341f66d8-60a3-457e-9474-5502b6e4715b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356971406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1356971406
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.414297215
Short name T327
Test name
Test status
Simulation time 704446678 ps
CPU time 3.85 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:16:30 PM PDT 24
Peak memory 212236 kb
Host smart-e317ddfb-f21d-40e6-80bf-f8437243c260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414297215 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.414297215
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2820628143
Short name T198
Test name
Test status
Simulation time 10082033776 ps
CPU time 14.41 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:16:40 PM PDT 24
Peak memory 292408 kb
Host smart-d5a7e6b3-5230-4afa-8092-c152b65cda5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820628143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2820628143
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3224081817
Short name T214
Test name
Test status
Simulation time 10235649405 ps
CPU time 35.29 seconds
Started Mar 26 01:16:27 PM PDT 24
Finished Mar 26 01:17:02 PM PDT 24
Peak memory 480396 kb
Host smart-e60fc181-ce9b-4423-a200-933ac948bf46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224081817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3224081817
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3844628826
Short name T473
Test name
Test status
Simulation time 1325885440 ps
CPU time 2.05 seconds
Started Mar 26 01:16:39 PM PDT 24
Finished Mar 26 01:16:41 PM PDT 24
Peak memory 204076 kb
Host smart-0d3854c1-453a-4b29-8855-b5e484e8b83f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844628826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3844628826
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.3395828257
Short name T1106
Test name
Test status
Simulation time 1076986496 ps
CPU time 5.42 seconds
Started Mar 26 01:16:27 PM PDT 24
Finished Mar 26 01:16:32 PM PDT 24
Peak memory 205000 kb
Host smart-76af9c6a-1393-4e93-b816-c7a49256b1c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395828257 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.3395828257
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.571969670
Short name T654
Test name
Test status
Simulation time 1207985591 ps
CPU time 29.71 seconds
Started Mar 26 01:16:26 PM PDT 24
Finished Mar 26 01:16:56 PM PDT 24
Peak memory 204172 kb
Host smart-d5dadb6e-8b17-46ff-873b-5e97d4abda76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571969670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.571969670
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3855431123
Short name T939
Test name
Test status
Simulation time 1027769318 ps
CPU time 11.04 seconds
Started Mar 26 01:16:24 PM PDT 24
Finished Mar 26 01:16:35 PM PDT 24
Peak memory 204160 kb
Host smart-bf7d4ae7-b78b-457a-afa9-9cdfd11c7b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855431123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3855431123
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1563905823
Short name T348
Test name
Test status
Simulation time 38862691447 ps
CPU time 2834.3 seconds
Started Mar 26 01:16:27 PM PDT 24
Finished Mar 26 02:03:42 PM PDT 24
Peak memory 4648320 kb
Host smart-95719649-170f-489d-ae85-8125db9447c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563905823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1563905823
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2671619018
Short name T888
Test name
Test status
Simulation time 1113345060 ps
CPU time 6.29 seconds
Started Mar 26 01:16:24 PM PDT 24
Finished Mar 26 01:16:30 PM PDT 24
Peak memory 210552 kb
Host smart-2b491c77-0453-4cd4-8dc4-a86a22b94e9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671619018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2671619018
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3040752529
Short name T438
Test name
Test status
Simulation time 23078417 ps
CPU time 0.61 seconds
Started Mar 26 01:16:39 PM PDT 24
Finished Mar 26 01:16:40 PM PDT 24
Peak memory 203676 kb
Host smart-f2ba098c-c20c-489b-9020-2d13353606c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040752529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3040752529
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2400875811
Short name T265
Test name
Test status
Simulation time 151485805 ps
CPU time 1.78 seconds
Started Mar 26 01:16:40 PM PDT 24
Finished Mar 26 01:16:42 PM PDT 24
Peak memory 212352 kb
Host smart-618917b6-be0a-4711-abdd-47c067952e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400875811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2400875811
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.652692502
Short name T487
Test name
Test status
Simulation time 963080525 ps
CPU time 6.07 seconds
Started Mar 26 01:16:38 PM PDT 24
Finished Mar 26 01:16:44 PM PDT 24
Peak memory 255736 kb
Host smart-4e9f7845-dd86-44ab-969c-7634f967ef97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652692502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.652692502
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3630269689
Short name T890
Test name
Test status
Simulation time 4413464554 ps
CPU time 34.66 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:17:10 PM PDT 24
Peak memory 332016 kb
Host smart-2ec96c04-4073-4464-93e4-09b61a3d72fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630269689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3630269689
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3140870151
Short name T578
Test name
Test status
Simulation time 5728628810 ps
CPU time 52.17 seconds
Started Mar 26 01:16:40 PM PDT 24
Finished Mar 26 01:17:32 PM PDT 24
Peak memory 590236 kb
Host smart-26b490f2-a913-4aa2-839a-c0b55a6b6970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140870151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3140870151
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.4060163414
Short name T466
Test name
Test status
Simulation time 473229530 ps
CPU time 0.99 seconds
Started Mar 26 01:16:37 PM PDT 24
Finished Mar 26 01:16:38 PM PDT 24
Peak memory 203788 kb
Host smart-44010c8a-2cc7-42af-a2af-decaba18907e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060163414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.4060163414
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2439299736
Short name T271
Test name
Test status
Simulation time 566852345 ps
CPU time 2.89 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:16:39 PM PDT 24
Peak memory 204012 kb
Host smart-3d465840-2def-468f-9675-42c0e07f25bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439299736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2439299736
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1575100756
Short name T640
Test name
Test status
Simulation time 7638590745 ps
CPU time 131.46 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:18:48 PM PDT 24
Peak memory 718172 kb
Host smart-5cf61d9b-34ef-409b-afb8-66ef07434d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575100756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1575100756
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_override.4001758621
Short name T912
Test name
Test status
Simulation time 17653699 ps
CPU time 0.64 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:16:37 PM PDT 24
Peak memory 203840 kb
Host smart-08af67e7-3eeb-44a3-8382-392cd0cf2f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001758621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4001758621
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3136384638
Short name T839
Test name
Test status
Simulation time 12763958298 ps
CPU time 1134.47 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:35:31 PM PDT 24
Peak memory 993856 kb
Host smart-43419552-e023-4d93-8f30-3ebe7a26f135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136384638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3136384638
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1989218381
Short name T700
Test name
Test status
Simulation time 1279980878 ps
CPU time 41.31 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:17:17 PM PDT 24
Peak memory 306632 kb
Host smart-df0bb02f-6d1a-41ac-a978-ce2ccd75c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989218381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1989218381
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1674533418
Short name T529
Test name
Test status
Simulation time 991374140 ps
CPU time 3.68 seconds
Started Mar 26 01:16:34 PM PDT 24
Finished Mar 26 01:16:38 PM PDT 24
Peak memory 204184 kb
Host smart-ec29ecd7-8247-4d87-924a-3fa49d804374
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674533418 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1674533418
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2731317227
Short name T213
Test name
Test status
Simulation time 10243457879 ps
CPU time 14.25 seconds
Started Mar 26 01:16:38 PM PDT 24
Finished Mar 26 01:16:53 PM PDT 24
Peak memory 283976 kb
Host smart-51fbe192-a12f-4bec-91d1-cdabb087ce16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731317227 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2731317227
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.1429819981
Short name T1101
Test name
Test status
Simulation time 10162745508 ps
CPU time 35.98 seconds
Started Mar 26 01:16:37 PM PDT 24
Finished Mar 26 01:17:13 PM PDT 24
Peak memory 455012 kb
Host smart-3c0dc3b9-284a-47a7-a13c-a0451e1f2bad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429819981 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.1429819981
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.1548059850
Short name T419
Test name
Test status
Simulation time 520722712 ps
CPU time 3.03 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:16:39 PM PDT 24
Peak memory 204028 kb
Host smart-a290d9ff-2f70-4a4a-bec0-394f6bdb31e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548059850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.1548059850
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2427626233
Short name T1003
Test name
Test status
Simulation time 3905892416 ps
CPU time 3.3 seconds
Started Mar 26 01:16:40 PM PDT 24
Finished Mar 26 01:16:43 PM PDT 24
Peak memory 204244 kb
Host smart-5c033b6b-2978-4120-8e14-bf880666d313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427626233 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2427626233
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2331743500
Short name T850
Test name
Test status
Simulation time 823230255 ps
CPU time 14.66 seconds
Started Mar 26 01:16:39 PM PDT 24
Finished Mar 26 01:16:54 PM PDT 24
Peak memory 204228 kb
Host smart-d0b43693-af88-4941-95c4-4109a4aa21cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331743500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2331743500
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.2109637032
Short name T885
Test name
Test status
Simulation time 2865392956 ps
CPU time 12.26 seconds
Started Mar 26 01:16:38 PM PDT 24
Finished Mar 26 01:16:50 PM PDT 24
Peak memory 206584 kb
Host smart-47abf296-2e25-412c-8992-1259147c3777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109637032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.2109637032
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1163437812
Short name T401
Test name
Test status
Simulation time 36414349660 ps
CPU time 3355.84 seconds
Started Mar 26 01:16:37 PM PDT 24
Finished Mar 26 02:12:33 PM PDT 24
Peak memory 8658476 kb
Host smart-ab3957d7-7de0-4532-a80a-b1aafaf2339a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163437812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1163437812
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.62007727
Short name T535
Test name
Test status
Simulation time 5453646568 ps
CPU time 7.44 seconds
Started Mar 26 01:16:38 PM PDT 24
Finished Mar 26 01:16:46 PM PDT 24
Peak memory 211432 kb
Host smart-1dcf87ea-0858-4848-9299-bab27e14be30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62007727 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_timeout.62007727
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.901830154
Short name T909
Test name
Test status
Simulation time 26858071 ps
CPU time 0.59 seconds
Started Mar 26 01:12:42 PM PDT 24
Finished Mar 26 01:12:43 PM PDT 24
Peak memory 203796 kb
Host smart-f0a7900a-e754-4c49-9a2b-ab328f925324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901830154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.901830154
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.204965686
Short name T264
Test name
Test status
Simulation time 164464313 ps
CPU time 1.79 seconds
Started Mar 26 01:12:35 PM PDT 24
Finished Mar 26 01:12:37 PM PDT 24
Peak memory 220584 kb
Host smart-c6bc297b-b9e6-481d-96ce-12b95474a126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204965686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.204965686
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1951693151
Short name T296
Test name
Test status
Simulation time 261041440 ps
CPU time 4.49 seconds
Started Mar 26 01:12:33 PM PDT 24
Finished Mar 26 01:12:37 PM PDT 24
Peak memory 241916 kb
Host smart-ead026a1-92e6-4075-a45f-0cee562e50e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951693151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1951693151
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.309196499
Short name T643
Test name
Test status
Simulation time 2844559206 ps
CPU time 54.47 seconds
Started Mar 26 01:12:32 PM PDT 24
Finished Mar 26 01:13:27 PM PDT 24
Peak memory 579668 kb
Host smart-3dc472b9-234a-4635-aee4-bb290b31b8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309196499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.309196499
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.4144504029
Short name T966
Test name
Test status
Simulation time 25470485225 ps
CPU time 36.2 seconds
Started Mar 26 01:12:33 PM PDT 24
Finished Mar 26 01:13:09 PM PDT 24
Peak memory 521980 kb
Host smart-72c888f3-5ae6-48ea-a7fc-b22261ac1dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144504029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.4144504029
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.4050836826
Short name T394
Test name
Test status
Simulation time 147853314 ps
CPU time 0.84 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:12:30 PM PDT 24
Peak memory 203836 kb
Host smart-7cd7d5d7-1946-42f7-862c-c26ad503a408
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050836826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.4050836826
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.116720761
Short name T345
Test name
Test status
Simulation time 1223016145 ps
CPU time 6.03 seconds
Started Mar 26 01:12:35 PM PDT 24
Finished Mar 26 01:12:41 PM PDT 24
Peak memory 204208 kb
Host smart-5a2892ae-633a-49cc-9224-51ab8dd5063d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116720761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.116720761
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1916250449
Short name T862
Test name
Test status
Simulation time 3201476141 ps
CPU time 232.13 seconds
Started Mar 26 01:12:32 PM PDT 24
Finished Mar 26 01:16:25 PM PDT 24
Peak memory 1000680 kb
Host smart-fe1baf4b-925e-4a48-8156-42a458c7b92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916250449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1916250449
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_override.3048225726
Short name T858
Test name
Test status
Simulation time 24159972 ps
CPU time 0.68 seconds
Started Mar 26 01:12:29 PM PDT 24
Finished Mar 26 01:12:30 PM PDT 24
Peak memory 203844 kb
Host smart-03fb62b0-8759-4cb8-9565-55ab2cf3a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048225726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3048225726
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.3550640497
Short name T622
Test name
Test status
Simulation time 12289155244 ps
CPU time 104.62 seconds
Started Mar 26 01:12:31 PM PDT 24
Finished Mar 26 01:14:16 PM PDT 24
Peak memory 353132 kb
Host smart-232ff2da-563a-4cdb-92d0-f55fd0e16549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550640497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.3550640497
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1670491744
Short name T790
Test name
Test status
Simulation time 1495507368 ps
CPU time 117.07 seconds
Started Mar 26 01:12:28 PM PDT 24
Finished Mar 26 01:14:26 PM PDT 24
Peak memory 285700 kb
Host smart-cdec4fd2-9028-4d1e-8b18-cdaeac55ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670491744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1670491744
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1259218819
Short name T116
Test name
Test status
Simulation time 46914160 ps
CPU time 0.89 seconds
Started Mar 26 01:12:42 PM PDT 24
Finished Mar 26 01:12:43 PM PDT 24
Peak memory 221224 kb
Host smart-c6d15cc8-6388-4f54-913f-3bf1db134106
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259218819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1259218819
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.4271861927
Short name T424
Test name
Test status
Simulation time 1612716063 ps
CPU time 3.59 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:12:46 PM PDT 24
Peak memory 204124 kb
Host smart-89a3e97e-4e2c-44c5-bd53-8fcca3a87e15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271861927 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.4271861927
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3605719010
Short name T97
Test name
Test status
Simulation time 10551557199 ps
CPU time 11.2 seconds
Started Mar 26 01:12:40 PM PDT 24
Finished Mar 26 01:12:52 PM PDT 24
Peak memory 288864 kb
Host smart-c3c82b3c-eb1d-4358-83ca-953678f04581
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605719010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3605719010
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2615019832
Short name T753
Test name
Test status
Simulation time 10027662315 ps
CPU time 87.92 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:14:12 PM PDT 24
Peak memory 669152 kb
Host smart-6d95ff5d-8d91-474a-9b8b-2588715195eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615019832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2615019832
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.3760783772
Short name T539
Test name
Test status
Simulation time 2187378370 ps
CPU time 2.87 seconds
Started Mar 26 01:12:41 PM PDT 24
Finished Mar 26 01:12:44 PM PDT 24
Peak memory 204220 kb
Host smart-b5db2085-9ac2-48df-abbf-5594328957fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760783772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.3760783772
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2359611467
Short name T53
Test name
Test status
Simulation time 4056298013 ps
CPU time 5.13 seconds
Started Mar 26 01:12:41 PM PDT 24
Finished Mar 26 01:12:46 PM PDT 24
Peak memory 215516 kb
Host smart-378556dd-e49e-474a-aa0b-309dd7169e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359611467 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2359611467
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.182731241
Short name T761
Test name
Test status
Simulation time 5847305781 ps
CPU time 4.29 seconds
Started Mar 26 01:12:41 PM PDT 24
Finished Mar 26 01:12:45 PM PDT 24
Peak memory 204280 kb
Host smart-02cad1ac-63d2-4474-8f3e-5ca47accc4dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182731241 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.182731241
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2208329755
Short name T472
Test name
Test status
Simulation time 3442859616 ps
CPU time 12.17 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:12:55 PM PDT 24
Peak memory 204188 kb
Host smart-9199af25-f20a-4b8d-b860-4e88f1f4f1e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208329755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2208329755
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2960707507
Short name T618
Test name
Test status
Simulation time 1002840717 ps
CPU time 17.19 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:13:01 PM PDT 24
Peak memory 211840 kb
Host smart-74654f73-3552-4dd7-abf6-7d611f6fac69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960707507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2960707507
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.920139925
Short name T856
Test name
Test status
Simulation time 6241541169 ps
CPU time 131.63 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:14:56 PM PDT 24
Peak memory 1561288 kb
Host smart-519f21fe-8328-422d-88df-69382bc7e858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920139925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_ta
rget_stretch.920139925
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3114029751
Short name T1023
Test name
Test status
Simulation time 1156023139 ps
CPU time 7.47 seconds
Started Mar 26 01:12:42 PM PDT 24
Finished Mar 26 01:12:49 PM PDT 24
Peak memory 216456 kb
Host smart-d9aaaa84-b764-4d2a-b310-d66a2e9857d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114029751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3114029751
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.283204598
Short name T875
Test name
Test status
Simulation time 40502143 ps
CPU time 0.6 seconds
Started Mar 26 01:16:49 PM PDT 24
Finished Mar 26 01:16:50 PM PDT 24
Peak memory 203712 kb
Host smart-c6d54692-922f-4ae7-b1d1-564816d1d772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283204598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.283204598
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3657588196
Short name T461
Test name
Test status
Simulation time 98733181 ps
CPU time 1.42 seconds
Started Mar 26 01:16:39 PM PDT 24
Finished Mar 26 01:16:41 PM PDT 24
Peak memory 212344 kb
Host smart-16bcddd4-4beb-4987-8ee5-fe658be00168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657588196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3657588196
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1514321681
Short name T338
Test name
Test status
Simulation time 859679277 ps
CPU time 6.26 seconds
Started Mar 26 01:16:40 PM PDT 24
Finished Mar 26 01:16:47 PM PDT 24
Peak memory 220032 kb
Host smart-7772ae75-0825-4794-a3e5-f29d019ddbf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514321681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1514321681
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2441409927
Short name T935
Test name
Test status
Simulation time 2770680492 ps
CPU time 36.49 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:17:13 PM PDT 24
Peak memory 462444 kb
Host smart-32394534-633e-418d-a66b-565989b606c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441409927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2441409927
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1889252031
Short name T597
Test name
Test status
Simulation time 2048123267 ps
CPU time 142.64 seconds
Started Mar 26 01:16:37 PM PDT 24
Finished Mar 26 01:19:00 PM PDT 24
Peak memory 693064 kb
Host smart-0c70f756-af0d-4492-81cb-6b9d1b60772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889252031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1889252031
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.543346135
Short name T217
Test name
Test status
Simulation time 229655192 ps
CPU time 0.91 seconds
Started Mar 26 01:16:35 PM PDT 24
Finished Mar 26 01:16:36 PM PDT 24
Peak memory 203816 kb
Host smart-4be0f8be-e006-4593-a8e4-49ac43b4fc3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543346135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fm
t.543346135
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.819662071
Short name T513
Test name
Test status
Simulation time 92856208 ps
CPU time 5.01 seconds
Started Mar 26 01:16:39 PM PDT 24
Finished Mar 26 01:16:44 PM PDT 24
Peak memory 204124 kb
Host smart-a3476316-3c1e-472f-9d09-9bfeadb8e799
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819662071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
819662071
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3370331721
Short name T519
Test name
Test status
Simulation time 2918064133 ps
CPU time 196 seconds
Started Mar 26 01:16:36 PM PDT 24
Finished Mar 26 01:19:52 PM PDT 24
Peak memory 895160 kb
Host smart-2796e031-7905-4563-ab57-17de15bd5368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370331721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3370331721
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_override.2593731148
Short name T284
Test name
Test status
Simulation time 165019397 ps
CPU time 0.71 seconds
Started Mar 26 01:16:38 PM PDT 24
Finished Mar 26 01:16:39 PM PDT 24
Peak memory 203764 kb
Host smart-64ee4ccf-7422-427f-806f-d27c9f5e1332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593731148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2593731148
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3341655254
Short name T922
Test name
Test status
Simulation time 2630000947 ps
CPU time 168.42 seconds
Started Mar 26 01:16:39 PM PDT 24
Finished Mar 26 01:19:28 PM PDT 24
Peak memory 477952 kb
Host smart-dca257a4-36e6-4b1b-84d6-58adb5a5053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341655254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3341655254
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.95456217
Short name T455
Test name
Test status
Simulation time 3396814775 ps
CPU time 69.29 seconds
Started Mar 26 01:16:38 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 262964 kb
Host smart-e0fedc3a-b8c9-430d-b858-f52d1a966bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95456217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.95456217
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3010594646
Short name T309
Test name
Test status
Simulation time 2470235798 ps
CPU time 3.58 seconds
Started Mar 26 01:16:49 PM PDT 24
Finished Mar 26 01:16:53 PM PDT 24
Peak memory 212328 kb
Host smart-1ea253b9-7c88-4236-9149-b1670bd11ede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010594646 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3010594646
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.3081830431
Short name T77
Test name
Test status
Simulation time 10137575643 ps
CPU time 31.42 seconds
Started Mar 26 01:16:47 PM PDT 24
Finished Mar 26 01:17:18 PM PDT 24
Peak memory 373700 kb
Host smart-d1370da7-a2f3-4b3b-aef1-d0a9bfb38e93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081830431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.3081830431
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2274342626
Short name T619
Test name
Test status
Simulation time 10147830896 ps
CPU time 95.38 seconds
Started Mar 26 01:16:54 PM PDT 24
Finished Mar 26 01:18:29 PM PDT 24
Peak memory 746688 kb
Host smart-94c6784d-a4e5-477a-a35a-2d19751a0e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274342626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2274342626
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3919754173
Short name T47
Test name
Test status
Simulation time 834289751 ps
CPU time 2.48 seconds
Started Mar 26 01:16:50 PM PDT 24
Finished Mar 26 01:16:52 PM PDT 24
Peak memory 204036 kb
Host smart-d0a6e1e8-5d6e-4cc7-8cba-bb0dcb528934
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919754173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3919754173
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.4100266835
Short name T796
Test name
Test status
Simulation time 8338641773 ps
CPU time 5.67 seconds
Started Mar 26 01:16:50 PM PDT 24
Finished Mar 26 01:16:56 PM PDT 24
Peak memory 204192 kb
Host smart-5beff5ef-05fc-4e6b-b222-bb12667701b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100266835 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.4100266835
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.50289763
Short name T574
Test name
Test status
Simulation time 837111570 ps
CPU time 31.72 seconds
Started Mar 26 01:16:48 PM PDT 24
Finished Mar 26 01:17:20 PM PDT 24
Peak memory 204068 kb
Host smart-e99c65c2-4799-468d-b701-1a16e80bd99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50289763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_targ
et_smoke.50289763
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3828978685
Short name T799
Test name
Test status
Simulation time 1222044538 ps
CPU time 25.51 seconds
Started Mar 26 01:16:48 PM PDT 24
Finished Mar 26 01:17:14 PM PDT 24
Peak memory 204052 kb
Host smart-2f9d3547-00d7-4ec5-8a78-a8ff6f076a67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828978685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3828978685
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.788751309
Short name T340
Test name
Test status
Simulation time 9226003237 ps
CPU time 3.9 seconds
Started Mar 26 01:16:51 PM PDT 24
Finished Mar 26 01:16:55 PM PDT 24
Peak memory 204156 kb
Host smart-e92ea6f7-a484-43a2-9344-8ac31065e697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788751309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.788751309
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.300505491
Short name T361
Test name
Test status
Simulation time 17137459957 ps
CPU time 328.07 seconds
Started Mar 26 01:16:52 PM PDT 24
Finished Mar 26 01:22:21 PM PDT 24
Peak memory 2149920 kb
Host smart-8295c412-9281-469b-be02-0dbe99df5ea7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300505491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_t
arget_stretch.300505491
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3410151457
Short name T961
Test name
Test status
Simulation time 1382461034 ps
CPU time 6.54 seconds
Started Mar 26 01:16:47 PM PDT 24
Finished Mar 26 01:16:54 PM PDT 24
Peak memory 204232 kb
Host smart-a060d080-f463-4bdd-9dee-9b59cb8ff8fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410151457 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3410151457
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.224029898
Short name T509
Test name
Test status
Simulation time 36426421 ps
CPU time 0.63 seconds
Started Mar 26 01:16:59 PM PDT 24
Finished Mar 26 01:17:00 PM PDT 24
Peak memory 203808 kb
Host smart-246902f2-37d0-4bd7-8efe-e50d48440a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224029898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.224029898
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3823374930
Short name T501
Test name
Test status
Simulation time 45243554 ps
CPU time 1.41 seconds
Started Mar 26 01:16:47 PM PDT 24
Finished Mar 26 01:16:49 PM PDT 24
Peak memory 212356 kb
Host smart-b29bb856-2716-457e-9e3f-9a0ff8431eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823374930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3823374930
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2460504838
Short name T415
Test name
Test status
Simulation time 1061196303 ps
CPU time 14.94 seconds
Started Mar 26 01:16:52 PM PDT 24
Finished Mar 26 01:17:07 PM PDT 24
Peak memory 261500 kb
Host smart-b13487f3-ae30-4f57-96f9-c7673fed2000
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460504838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2460504838
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.195616486
Short name T234
Test name
Test status
Simulation time 2211422664 ps
CPU time 164.97 seconds
Started Mar 26 01:16:48 PM PDT 24
Finished Mar 26 01:19:33 PM PDT 24
Peak memory 748824 kb
Host smart-31b803a3-c2af-45cf-9250-bc4da4f9b0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195616486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.195616486
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2984237619
Short name T522
Test name
Test status
Simulation time 9669614200 ps
CPU time 69.68 seconds
Started Mar 26 01:16:52 PM PDT 24
Finished Mar 26 01:18:02 PM PDT 24
Peak memory 759976 kb
Host smart-9ea3d5d3-11e0-4b05-82cc-77b4e2b70db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984237619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2984237619
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3809404855
Short name T813
Test name
Test status
Simulation time 77364214 ps
CPU time 0.91 seconds
Started Mar 26 01:16:49 PM PDT 24
Finished Mar 26 01:16:50 PM PDT 24
Peak memory 203768 kb
Host smart-4a8b756d-9c67-4d94-b9c7-89a8aa45066f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809404855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3809404855
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1078471047
Short name T465
Test name
Test status
Simulation time 123810705 ps
CPU time 6.66 seconds
Started Mar 26 01:16:50 PM PDT 24
Finished Mar 26 01:16:57 PM PDT 24
Peak memory 204116 kb
Host smart-35a2a5aa-7b6f-492e-aa0c-1237a2179c38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078471047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1078471047
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.90144434
Short name T783
Test name
Test status
Simulation time 2781792296 ps
CPU time 72.48 seconds
Started Mar 26 01:16:50 PM PDT 24
Finished Mar 26 01:18:03 PM PDT 24
Peak memory 854208 kb
Host smart-365b5e44-4e54-4dc7-b373-cbc61132cbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90144434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.90144434
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_override.3406916298
Short name T203
Test name
Test status
Simulation time 29486600 ps
CPU time 0.66 seconds
Started Mar 26 01:16:48 PM PDT 24
Finished Mar 26 01:16:49 PM PDT 24
Peak memory 203836 kb
Host smart-a94cd620-0785-49c3-8f2c-fe0bd5f2e88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406916298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3406916298
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.616398882
Short name T987
Test name
Test status
Simulation time 9209178677 ps
CPU time 2866.03 seconds
Started Mar 26 01:16:47 PM PDT 24
Finished Mar 26 02:04:34 PM PDT 24
Peak memory 867672 kb
Host smart-2c67d246-ecc5-49ff-a430-7241c74b4134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616398882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.616398882
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2967826084
Short name T905
Test name
Test status
Simulation time 2093063422 ps
CPU time 36.87 seconds
Started Mar 26 01:16:48 PM PDT 24
Finished Mar 26 01:17:25 PM PDT 24
Peak memory 294504 kb
Host smart-473a3689-cba7-4c05-b3b8-e32c191fe5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967826084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2967826084
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.372315694
Short name T568
Test name
Test status
Simulation time 550451867 ps
CPU time 2.91 seconds
Started Mar 26 01:16:59 PM PDT 24
Finished Mar 26 01:17:02 PM PDT 24
Peak memory 204060 kb
Host smart-3b4006b0-aa66-4c91-8f2f-0cdd1f4db197
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372315694 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.372315694
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2891150586
Short name T555
Test name
Test status
Simulation time 10212830599 ps
CPU time 13.43 seconds
Started Mar 26 01:17:00 PM PDT 24
Finished Mar 26 01:17:14 PM PDT 24
Peak memory 298012 kb
Host smart-343e1476-6a4e-4260-93b0-e5b232be8765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891150586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2891150586
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2726520296
Short name T523
Test name
Test status
Simulation time 10042148525 ps
CPU time 100.82 seconds
Started Mar 26 01:17:06 PM PDT 24
Finished Mar 26 01:18:47 PM PDT 24
Peak memory 731724 kb
Host smart-d407f38c-d253-437a-ba82-30623b8186a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726520296 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2726520296
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2417685931
Short name T660
Test name
Test status
Simulation time 805965338 ps
CPU time 2.63 seconds
Started Mar 26 01:17:02 PM PDT 24
Finished Mar 26 01:17:05 PM PDT 24
Peak memory 204216 kb
Host smart-482a6db6-dd26-4781-95bc-bbf24581af74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417685931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2417685931
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3847249227
Short name T975
Test name
Test status
Simulation time 5209371315 ps
CPU time 6.4 seconds
Started Mar 26 01:17:02 PM PDT 24
Finished Mar 26 01:17:08 PM PDT 24
Peak memory 212424 kb
Host smart-2f243a70-54ab-4157-9aa6-9588df13428e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847249227 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3847249227
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1519069150
Short name T936
Test name
Test status
Simulation time 514317277 ps
CPU time 18.51 seconds
Started Mar 26 01:16:48 PM PDT 24
Finished Mar 26 01:17:06 PM PDT 24
Peak memory 204116 kb
Host smart-21d3bbc1-7697-4dee-a049-0bc242309761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519069150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1519069150
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1382982918
Short name T391
Test name
Test status
Simulation time 2184143817 ps
CPU time 19.02 seconds
Started Mar 26 01:16:48 PM PDT 24
Finished Mar 26 01:17:08 PM PDT 24
Peak memory 218808 kb
Host smart-078dfb8c-5f11-485c-b6d8-e1934fdd36c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382982918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1382982918
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.354392751
Short name T861
Test name
Test status
Simulation time 9630668213 ps
CPU time 358.22 seconds
Started Mar 26 01:17:00 PM PDT 24
Finished Mar 26 01:22:59 PM PDT 24
Peak memory 2520540 kb
Host smart-23756398-8d20-42db-af8a-1b58ff7fc8ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354392751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.354392751
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.505037156
Short name T292
Test name
Test status
Simulation time 5766445588 ps
CPU time 7.15 seconds
Started Mar 26 01:17:00 PM PDT 24
Finished Mar 26 01:17:08 PM PDT 24
Peak memory 216432 kb
Host smart-e411f5fe-7120-46a9-a920-d3e0ef24912f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505037156 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.505037156
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3217508796
Short name T1001
Test name
Test status
Simulation time 17493861 ps
CPU time 0.62 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:16 PM PDT 24
Peak memory 203680 kb
Host smart-24a48a2f-8e7e-48c7-9432-17d8c542e469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217508796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3217508796
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.407472114
Short name T533
Test name
Test status
Simulation time 42990364 ps
CPU time 1.15 seconds
Started Mar 26 01:17:01 PM PDT 24
Finished Mar 26 01:17:02 PM PDT 24
Peak memory 212336 kb
Host smart-abb04b4e-c98c-469e-9843-57f0bc2b6b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407472114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.407472114
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1701033447
Short name T623
Test name
Test status
Simulation time 1598446579 ps
CPU time 6.84 seconds
Started Mar 26 01:16:59 PM PDT 24
Finished Mar 26 01:17:06 PM PDT 24
Peak memory 271272 kb
Host smart-0be72284-03c9-4ef0-817d-2b3f2d8be388
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701033447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1701033447
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.4121686626
Short name T462
Test name
Test status
Simulation time 10785067260 ps
CPU time 170.81 seconds
Started Mar 26 01:17:02 PM PDT 24
Finished Mar 26 01:19:53 PM PDT 24
Peak memory 769600 kb
Host smart-53b957dd-64fe-4c74-aa1a-825c16adb59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121686626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.4121686626
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1793916580
Short name T530
Test name
Test status
Simulation time 20956958767 ps
CPU time 76.78 seconds
Started Mar 26 01:17:02 PM PDT 24
Finished Mar 26 01:18:19 PM PDT 24
Peak memory 422128 kb
Host smart-7031679b-8afd-4e8c-8d2e-bd8ee27c5bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793916580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1793916580
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.407024388
Short name T916
Test name
Test status
Simulation time 467432192 ps
CPU time 1.08 seconds
Started Mar 26 01:16:59 PM PDT 24
Finished Mar 26 01:17:01 PM PDT 24
Peak memory 204036 kb
Host smart-48aa009e-43c3-4c34-9c6b-5c6f68068aff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407024388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.407024388
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1671607065
Short name T7
Test name
Test status
Simulation time 515598042 ps
CPU time 7.41 seconds
Started Mar 26 01:17:00 PM PDT 24
Finished Mar 26 01:17:08 PM PDT 24
Peak memory 227324 kb
Host smart-2a3a6773-3889-43cd-a958-e1396caa093b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671607065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1671607065
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3704066666
Short name T1096
Test name
Test status
Simulation time 6515147912 ps
CPU time 239.57 seconds
Started Mar 26 01:16:59 PM PDT 24
Finished Mar 26 01:20:58 PM PDT 24
Peak memory 986792 kb
Host smart-195bf3a9-1d24-4e69-99c0-27b6596b3ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704066666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3704066666
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_override.3326284616
Short name T720
Test name
Test status
Simulation time 46043265 ps
CPU time 0.65 seconds
Started Mar 26 01:17:01 PM PDT 24
Finished Mar 26 01:17:02 PM PDT 24
Peak memory 203792 kb
Host smart-aedb5ed3-a825-41fc-a94f-b39af403ccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326284616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3326284616
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.673262796
Short name T45
Test name
Test status
Simulation time 24902265851 ps
CPU time 2786.39 seconds
Started Mar 26 01:17:03 PM PDT 24
Finished Mar 26 02:03:30 PM PDT 24
Peak memory 1473104 kb
Host smart-18095df5-227f-4b91-9ed0-26cf16ab8341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673262796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.673262796
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.348997270
Short name T558
Test name
Test status
Simulation time 2627851200 ps
CPU time 33.14 seconds
Started Mar 26 01:16:59 PM PDT 24
Finished Mar 26 01:17:33 PM PDT 24
Peak memory 269148 kb
Host smart-2b38fb6f-dda0-4e64-a05e-d06db87001ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348997270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.348997270
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.3799733937
Short name T180
Test name
Test status
Simulation time 21740012866 ps
CPU time 2007.02 seconds
Started Mar 26 01:16:59 PM PDT 24
Finished Mar 26 01:50:27 PM PDT 24
Peak memory 2698240 kb
Host smart-6fc36da2-bc40-4940-889a-8302a6c5248c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799733937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3799733937
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3980249053
Short name T827
Test name
Test status
Simulation time 9568920775 ps
CPU time 5.14 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:17:21 PM PDT 24
Peak memory 212548 kb
Host smart-f0623b68-e1c5-4cd2-83cb-5d904acce12d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980249053 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3980249053
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2598095681
Short name T920
Test name
Test status
Simulation time 10115677231 ps
CPU time 30.75 seconds
Started Mar 26 01:17:01 PM PDT 24
Finished Mar 26 01:17:32 PM PDT 24
Peak memory 413272 kb
Host smart-16734b06-b36c-416d-9230-195b54ed6f2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598095681 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2598095681
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3423485144
Short name T1015
Test name
Test status
Simulation time 10336513687 ps
CPU time 4.45 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:20 PM PDT 24
Peak memory 232068 kb
Host smart-50998bf9-31c4-485d-a8c6-85255f1404e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423485144 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3423485144
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3788921083
Short name T730
Test name
Test status
Simulation time 380069070 ps
CPU time 2.46 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:18 PM PDT 24
Peak memory 204172 kb
Host smart-0b0f14fd-62e6-4523-9b0f-f576ace329a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788921083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3788921083
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1880731888
Short name T5
Test name
Test status
Simulation time 929718292 ps
CPU time 5.33 seconds
Started Mar 26 01:17:03 PM PDT 24
Finished Mar 26 01:17:09 PM PDT 24
Peak memory 215396 kb
Host smart-e6835a3e-857a-4150-aad0-57e717d29794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880731888 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1880731888
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3372887300
Short name T298
Test name
Test status
Simulation time 1035602832 ps
CPU time 18.01 seconds
Started Mar 26 01:17:00 PM PDT 24
Finished Mar 26 01:17:18 PM PDT 24
Peak memory 204096 kb
Host smart-fcd61363-6a1d-4e16-929e-6bacb43c9a3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372887300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3372887300
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.167375702
Short name T808
Test name
Test status
Simulation time 656192333 ps
CPU time 12.62 seconds
Started Mar 26 01:17:00 PM PDT 24
Finished Mar 26 01:17:13 PM PDT 24
Peak memory 208636 kb
Host smart-824f2b52-5fe9-4c44-8330-d2e228b51501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167375702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.167375702
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3092117009
Short name T275
Test name
Test status
Simulation time 9316624637 ps
CPU time 97.91 seconds
Started Mar 26 01:17:03 PM PDT 24
Finished Mar 26 01:18:41 PM PDT 24
Peak memory 1265712 kb
Host smart-049018d7-1551-4152-a96d-11bc809e7ea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092117009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3092117009
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2115605207
Short name T561
Test name
Test status
Simulation time 3050850371 ps
CPU time 6.9 seconds
Started Mar 26 01:17:03 PM PDT 24
Finished Mar 26 01:17:10 PM PDT 24
Peak memory 220412 kb
Host smart-dd9337a5-17ed-4b58-960c-8a76e475cc15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115605207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2115605207
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2225528209
Short name T528
Test name
Test status
Simulation time 26186360 ps
CPU time 0.64 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:17:17 PM PDT 24
Peak memory 203732 kb
Host smart-94e8e13c-a66b-4d69-9eae-ce7bab437dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225528209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2225528209
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2463675423
Short name T923
Test name
Test status
Simulation time 84643050 ps
CPU time 1.35 seconds
Started Mar 26 01:17:18 PM PDT 24
Finished Mar 26 01:17:20 PM PDT 24
Peak memory 215748 kb
Host smart-321b1511-2fd2-43ee-9de0-f0e0805fdbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463675423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2463675423
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3303353663
Short name T321
Test name
Test status
Simulation time 593482491 ps
CPU time 6.4 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:17:23 PM PDT 24
Peak memory 266836 kb
Host smart-02d0a703-b5b5-45d8-bd2e-e1d649a2407d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303353663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3303353663
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.672947178
Short name T101
Test name
Test status
Simulation time 1808408582 ps
CPU time 60.8 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:18:17 PM PDT 24
Peak memory 653412 kb
Host smart-e4c0eb49-181b-4887-8339-f9786bb4344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672947178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.672947178
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.27129590
Short name T347
Test name
Test status
Simulation time 1123318499 ps
CPU time 33.09 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:17:49 PM PDT 24
Peak memory 444416 kb
Host smart-76fb3cd1-c1b4-415d-a78a-3b43768d42f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27129590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.27129590
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1727387421
Short name T498
Test name
Test status
Simulation time 433074440 ps
CPU time 1.21 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:17:17 PM PDT 24
Peak memory 204028 kb
Host smart-19b17259-5f19-42aa-bde1-ad3391dc57ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727387421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1727387421
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2205714663
Short name T460
Test name
Test status
Simulation time 349773700 ps
CPU time 3.71 seconds
Started Mar 26 01:17:18 PM PDT 24
Finished Mar 26 01:17:22 PM PDT 24
Peak memory 204100 kb
Host smart-35d21819-96fc-4293-9cbd-96161321d082
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205714663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2205714663
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3422629644
Short name T1073
Test name
Test status
Simulation time 11656193330 ps
CPU time 149.59 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:19:45 PM PDT 24
Peak memory 759740 kb
Host smart-4d068581-72d5-4d18-93a9-4f55ef046baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422629644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3422629644
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_override.3239743972
Short name T1017
Test name
Test status
Simulation time 46212134 ps
CPU time 0.64 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:16 PM PDT 24
Peak memory 203724 kb
Host smart-0131fcae-fb23-4e6f-bd80-b5f83ed96a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239743972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3239743972
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2950123475
Short name T932
Test name
Test status
Simulation time 11273803033 ps
CPU time 112.41 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:19:08 PM PDT 24
Peak memory 403028 kb
Host smart-1396278a-13b9-46fb-a25b-5d867c188e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950123475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2950123475
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1818355143
Short name T899
Test name
Test status
Simulation time 3944674038 ps
CPU time 4.56 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:20 PM PDT 24
Peak memory 204160 kb
Host smart-5c7aa824-b3a1-47e7-872d-1e77e521202f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818355143 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1818355143
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.4147934315
Short name T969
Test name
Test status
Simulation time 10086484241 ps
CPU time 57.4 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:18:14 PM PDT 24
Peak memory 529036 kb
Host smart-742bd9bd-8c04-41c1-bb2e-8b0f6607d8c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147934315 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.4147934315
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2247661324
Short name T554
Test name
Test status
Simulation time 11315018042 ps
CPU time 4.29 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:17:21 PM PDT 24
Peak memory 242640 kb
Host smart-1e19ee5d-f954-4963-b0ec-71215db3d453
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247661324 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2247661324
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1895034645
Short name T965
Test name
Test status
Simulation time 2552348102 ps
CPU time 1.96 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:17 PM PDT 24
Peak memory 204244 kb
Host smart-9f4e0c23-cd8a-428d-ab07-cfe38327c454
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895034645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1895034645
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.1066242036
Short name T763
Test name
Test status
Simulation time 4104102685 ps
CPU time 5.31 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:21 PM PDT 24
Peak memory 204236 kb
Host smart-d154ad38-9a0c-453e-9397-19b114277cc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066242036 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.1066242036
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.729725273
Short name T308
Test name
Test status
Simulation time 5330742265 ps
CPU time 4.11 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:19 PM PDT 24
Peak memory 204312 kb
Host smart-14670826-af0e-4a06-8da4-3e7670c261f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729725273 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.729725273
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1618136452
Short name T434
Test name
Test status
Simulation time 2628701610 ps
CPU time 29.49 seconds
Started Mar 26 01:17:18 PM PDT 24
Finished Mar 26 01:17:48 PM PDT 24
Peak memory 204184 kb
Host smart-60000ecc-2eed-4ced-9b9a-b76045f30075
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618136452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1618136452
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.1252988768
Short name T995
Test name
Test status
Simulation time 27679140961 ps
CPU time 34.97 seconds
Started Mar 26 01:17:17 PM PDT 24
Finished Mar 26 01:17:53 PM PDT 24
Peak memory 282920 kb
Host smart-be3e9e1e-07f1-4464-952b-76cf0527db20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252988768 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.1252988768
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1905113652
Short name T52
Test name
Test status
Simulation time 1256980857 ps
CPU time 18.57 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 01:17:35 PM PDT 24
Peak memory 223424 kb
Host smart-f9bb2b78-7bd7-4ca2-841e-ff6d2ba18438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905113652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1905113652
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1848264568
Short name T742
Test name
Test status
Simulation time 28351928049 ps
CPU time 2729.81 seconds
Started Mar 26 01:17:16 PM PDT 24
Finished Mar 26 02:02:46 PM PDT 24
Peak memory 6848364 kb
Host smart-da8ba45f-bc1e-4074-93c2-d9d74c179628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848264568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1848264568
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1830795987
Short name T818
Test name
Test status
Simulation time 3260710141 ps
CPU time 7.37 seconds
Started Mar 26 01:17:18 PM PDT 24
Finished Mar 26 01:17:26 PM PDT 24
Peak memory 204360 kb
Host smart-80f19e2e-a7be-4477-aad0-26d4a34435e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830795987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1830795987
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1279349479
Short name T110
Test name
Test status
Simulation time 23038159 ps
CPU time 0.6 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:17:30 PM PDT 24
Peak memory 203748 kb
Host smart-620c615f-59b7-4427-8d64-8b3b2d0a8fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279349479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1279349479
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.941948965
Short name T285
Test name
Test status
Simulation time 60034792 ps
CPU time 1.62 seconds
Started Mar 26 01:17:21 PM PDT 24
Finished Mar 26 01:17:24 PM PDT 24
Peak memory 212300 kb
Host smart-e3816319-24ae-421a-a3e3-58b03956f00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941948965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.941948965
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2561290445
Short name T384
Test name
Test status
Simulation time 184443915 ps
CPU time 3.59 seconds
Started Mar 26 01:17:15 PM PDT 24
Finished Mar 26 01:17:19 PM PDT 24
Peak memory 234680 kb
Host smart-80af4b75-1b94-4099-887e-e1531b2aac52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561290445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.2561290445
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.63288962
Short name T769
Test name
Test status
Simulation time 2480198461 ps
CPU time 78.03 seconds
Started Mar 26 01:17:21 PM PDT 24
Finished Mar 26 01:18:40 PM PDT 24
Peak memory 654352 kb
Host smart-a77052ac-e36a-4b33-98ad-eec4a4e39f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63288962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.63288962
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2079364018
Short name T383
Test name
Test status
Simulation time 4071479607 ps
CPU time 71.14 seconds
Started Mar 26 01:17:14 PM PDT 24
Finished Mar 26 01:18:25 PM PDT 24
Peak memory 692000 kb
Host smart-0639bc07-597e-45d6-9269-bc9628361e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079364018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2079364018
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1457965966
Short name T617
Test name
Test status
Simulation time 544112422 ps
CPU time 1.16 seconds
Started Mar 26 01:17:17 PM PDT 24
Finished Mar 26 01:17:19 PM PDT 24
Peak memory 204072 kb
Host smart-2ce6c2dc-a712-4260-8d04-a82c5b0ebd3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457965966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1457965966
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1946504640
Short name T91
Test name
Test status
Simulation time 125935419 ps
CPU time 3.27 seconds
Started Mar 26 01:17:17 PM PDT 24
Finished Mar 26 01:17:21 PM PDT 24
Peak memory 204108 kb
Host smart-c1383355-284b-4a2e-9e37-0887d7835f19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946504640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1946504640
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2968762816
Short name T527
Test name
Test status
Simulation time 3648538119 ps
CPU time 263.45 seconds
Started Mar 26 01:17:20 PM PDT 24
Finished Mar 26 01:21:44 PM PDT 24
Peak memory 1102616 kb
Host smart-a7c995b0-5b8b-49c3-b52f-0340e7fc8e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968762816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2968762816
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_override.3980070387
Short name T759
Test name
Test status
Simulation time 37623618 ps
CPU time 0.63 seconds
Started Mar 26 01:17:14 PM PDT 24
Finished Mar 26 01:17:15 PM PDT 24
Peak memory 203824 kb
Host smart-f5d81fb6-5601-48ea-957c-605737f11095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980070387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3980070387
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1509909355
Short name T705
Test name
Test status
Simulation time 3056744207 ps
CPU time 57.19 seconds
Started Mar 26 01:17:17 PM PDT 24
Finished Mar 26 01:18:14 PM PDT 24
Peak memory 353256 kb
Host smart-9d527399-8bf9-49f4-9fdc-b6146c728291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509909355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1509909355
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3123400973
Short name T571
Test name
Test status
Simulation time 3400278537 ps
CPU time 107.76 seconds
Started Mar 26 01:17:19 PM PDT 24
Finished Mar 26 01:19:07 PM PDT 24
Peak memory 261208 kb
Host smart-093b96d7-cd3e-45c3-b258-b0996afbe421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123400973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3123400973
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.36068207
Short name T704
Test name
Test status
Simulation time 3880647361 ps
CPU time 4.32 seconds
Started Mar 26 01:17:41 PM PDT 24
Finished Mar 26 01:17:46 PM PDT 24
Peak memory 212432 kb
Host smart-15d3d245-d903-4849-9b15-5d0e5f726a75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36068207 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_bad_addr.36068207
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1871290754
Short name T474
Test name
Test status
Simulation time 10042414253 ps
CPU time 45.67 seconds
Started Mar 26 01:17:18 PM PDT 24
Finished Mar 26 01:18:04 PM PDT 24
Peak memory 409728 kb
Host smart-575279fe-ee04-4b6b-b4b6-92f424db0889
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871290754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1871290754
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3061825653
Short name T74
Test name
Test status
Simulation time 10275429530 ps
CPU time 18.69 seconds
Started Mar 26 01:17:26 PM PDT 24
Finished Mar 26 01:17:44 PM PDT 24
Peak memory 335284 kb
Host smart-0a95b06a-4b96-4f86-8b27-b4d67420d993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061825653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3061825653
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1085403165
Short name T538
Test name
Test status
Simulation time 1300949739 ps
CPU time 2.54 seconds
Started Mar 26 01:17:24 PM PDT 24
Finished Mar 26 01:17:27 PM PDT 24
Peak memory 204200 kb
Host smart-fad79350-4841-46d8-ac0b-00f7866cb070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085403165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1085403165
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.742194970
Short name T784
Test name
Test status
Simulation time 1506415617 ps
CPU time 7.76 seconds
Started Mar 26 01:17:18 PM PDT 24
Finished Mar 26 01:17:26 PM PDT 24
Peak memory 220584 kb
Host smart-6a805f20-1938-4d6c-a3a1-a3466b88114b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742194970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.742194970
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.226798307
Short name T325
Test name
Test status
Simulation time 832747205 ps
CPU time 28.12 seconds
Started Mar 26 01:17:17 PM PDT 24
Finished Mar 26 01:17:46 PM PDT 24
Peak memory 204344 kb
Host smart-3d9c61b1-e666-44c5-8980-5a2268531506
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226798307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.226798307
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3672268374
Short name T440
Test name
Test status
Simulation time 2522338979 ps
CPU time 55.95 seconds
Started Mar 26 01:17:18 PM PDT 24
Finished Mar 26 01:18:14 PM PDT 24
Peak memory 206364 kb
Host smart-14b909e8-e0c5-451e-a3ea-0c58590d5145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672268374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3672268374
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1683183180
Short name T93
Test name
Test status
Simulation time 19436702340 ps
CPU time 10.51 seconds
Started Mar 26 01:17:21 PM PDT 24
Finished Mar 26 01:17:32 PM PDT 24
Peak memory 204204 kb
Host smart-5078dd77-162a-4907-970b-b05be5c9accc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683183180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1683183180
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.16709556
Short name T194
Test name
Test status
Simulation time 19213710161 ps
CPU time 6.85 seconds
Started Mar 26 01:17:17 PM PDT 24
Finished Mar 26 01:17:24 PM PDT 24
Peak memory 204268 kb
Host smart-460e8428-577a-45a2-8d95-57b318884c80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16709556 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_timeout.16709556
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3600106219
Short name T601
Test name
Test status
Simulation time 17580194 ps
CPU time 0.62 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:17:30 PM PDT 24
Peak memory 203680 kb
Host smart-e37acdf1-6956-40d7-b513-f4c7d5e75e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600106219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3600106219
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.4064847500
Short name T402
Test name
Test status
Simulation time 137000716 ps
CPU time 1.57 seconds
Started Mar 26 01:17:26 PM PDT 24
Finished Mar 26 01:17:28 PM PDT 24
Peak memory 212328 kb
Host smart-97c3aef5-9674-45a4-9682-74270bc343a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064847500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.4064847500
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2112291883
Short name T109
Test name
Test status
Simulation time 1915901588 ps
CPU time 10.44 seconds
Started Mar 26 01:17:28 PM PDT 24
Finished Mar 26 01:17:38 PM PDT 24
Peak memory 300852 kb
Host smart-ffce0407-dcc8-4fd0-b5a3-832069c893a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112291883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2112291883
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1343166411
Short name T491
Test name
Test status
Simulation time 8215777693 ps
CPU time 59.71 seconds
Started Mar 26 01:17:30 PM PDT 24
Finished Mar 26 01:18:29 PM PDT 24
Peak memory 673276 kb
Host smart-d6b04ebb-858c-447a-8612-fe8db59667ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343166411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1343166411
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3200820491
Short name T366
Test name
Test status
Simulation time 3310372039 ps
CPU time 51.37 seconds
Started Mar 26 01:17:28 PM PDT 24
Finished Mar 26 01:18:19 PM PDT 24
Peak memory 541924 kb
Host smart-cc443274-beca-4279-a9fe-5691730a5b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200820491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3200820491
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3877691900
Short name T773
Test name
Test status
Simulation time 185589872 ps
CPU time 1.01 seconds
Started Mar 26 01:17:27 PM PDT 24
Finished Mar 26 01:17:28 PM PDT 24
Peak memory 204160 kb
Host smart-9dbfb1a3-e5da-452e-8877-e87c6b10b5e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877691900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3877691900
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3788556219
Short name T697
Test name
Test status
Simulation time 139933790 ps
CPU time 3.55 seconds
Started Mar 26 01:17:41 PM PDT 24
Finished Mar 26 01:17:45 PM PDT 24
Peak memory 226220 kb
Host smart-29ee3291-4ed8-4a2e-b404-b2e7c30dba8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788556219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3788556219
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1316965196
Short name T242
Test name
Test status
Simulation time 5312068599 ps
CPU time 73.95 seconds
Started Mar 26 01:17:30 PM PDT 24
Finished Mar 26 01:18:44 PM PDT 24
Peak memory 847360 kb
Host smart-889207c3-92c0-4dd1-8796-a31e0340263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316965196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1316965196
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_override.675175191
Short name T1057
Test name
Test status
Simulation time 56877149 ps
CPU time 0.67 seconds
Started Mar 26 01:17:28 PM PDT 24
Finished Mar 26 01:17:29 PM PDT 24
Peak memory 203892 kb
Host smart-f5ae61ca-01d0-4bec-a785-e51d5ab25647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675175191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.675175191
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3905600972
Short name T950
Test name
Test status
Simulation time 6653456373 ps
CPU time 25.27 seconds
Started Mar 26 01:17:40 PM PDT 24
Finished Mar 26 01:18:05 PM PDT 24
Peak memory 212372 kb
Host smart-52ebfe5b-9391-4ced-a20f-3e8b3c152338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905600972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3905600972
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2345747770
Short name T570
Test name
Test status
Simulation time 1115643860 ps
CPU time 42.25 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:18:12 PM PDT 24
Peak memory 300332 kb
Host smart-21dd758a-e8e7-4a87-a3f3-f8d19a450e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345747770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2345747770
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3038013307
Short name T816
Test name
Test status
Simulation time 975438425 ps
CPU time 4.75 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:17:33 PM PDT 24
Peak memory 204064 kb
Host smart-ba6b584e-c639-4c25-99c0-8e80857d880b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038013307 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3038013307
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3976515001
Short name T95
Test name
Test status
Simulation time 10029378106 ps
CPU time 74.51 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:18:44 PM PDT 24
Peak memory 567776 kb
Host smart-ef054659-7b9b-47c6-849d-88ccd7712378
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976515001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3976515001
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3159256566
Short name T356
Test name
Test status
Simulation time 10174902823 ps
CPU time 22.18 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:17:52 PM PDT 24
Peak memory 397944 kb
Host smart-a2d8f78b-5efe-449f-83b1-50dc7a5e7d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159256566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3159256566
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.1590796911
Short name T641
Test name
Test status
Simulation time 411413970 ps
CPU time 2.33 seconds
Started Mar 26 01:17:25 PM PDT 24
Finished Mar 26 01:17:27 PM PDT 24
Peak memory 204176 kb
Host smart-429847af-33cb-4da1-8dc8-201d6194bfb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590796911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.1590796911
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1530033078
Short name T1022
Test name
Test status
Simulation time 3396813167 ps
CPU time 4.56 seconds
Started Mar 26 01:17:30 PM PDT 24
Finished Mar 26 01:17:35 PM PDT 24
Peak memory 205156 kb
Host smart-8ba0a186-e83a-47fe-b006-4d5ad24e7fe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530033078 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1530033078
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.445152361
Short name T499
Test name
Test status
Simulation time 2072844503 ps
CPU time 13.96 seconds
Started Mar 26 01:17:41 PM PDT 24
Finished Mar 26 01:17:55 PM PDT 24
Peak memory 204088 kb
Host smart-b34e05b4-153a-46d2-b662-0349d03d666a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445152361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.445152361
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.240753895
Short name T955
Test name
Test status
Simulation time 2794404172 ps
CPU time 13.67 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:17:43 PM PDT 24
Peak memory 204144 kb
Host smart-0bde9efa-6a10-4fc9-8bc0-5396b72876c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240753895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.240753895
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.3361048682
Short name T590
Test name
Test status
Simulation time 17610301349 ps
CPU time 96.97 seconds
Started Mar 26 01:17:27 PM PDT 24
Finished Mar 26 01:19:04 PM PDT 24
Peak memory 965016 kb
Host smart-3fb2a79a-7799-46ef-9325-ad304343d40f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361048682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.3361048682
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.156383866
Short name T341
Test name
Test status
Simulation time 1211464187 ps
CPU time 6.75 seconds
Started Mar 26 01:17:30 PM PDT 24
Finished Mar 26 01:17:37 PM PDT 24
Peak memory 219196 kb
Host smart-85d885b6-553a-45eb-a882-b3554449ab76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156383866 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.156383866
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2889366539
Short name T1047
Test name
Test status
Simulation time 44982113 ps
CPU time 0.58 seconds
Started Mar 26 01:17:43 PM PDT 24
Finished Mar 26 01:17:43 PM PDT 24
Peak memory 203764 kb
Host smart-18e1c8da-3d5c-4583-b011-da7d4d52eee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889366539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2889366539
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3503120544
Short name T426
Test name
Test status
Simulation time 166525418 ps
CPU time 1.43 seconds
Started Mar 26 01:17:44 PM PDT 24
Finished Mar 26 01:17:46 PM PDT 24
Peak memory 212324 kb
Host smart-06e14b61-77cb-4c41-81ec-7d245954d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503120544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3503120544
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.821207288
Short name T389
Test name
Test status
Simulation time 907731526 ps
CPU time 5.59 seconds
Started Mar 26 01:17:41 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 244980 kb
Host smart-2352100d-e4c4-47a7-bdf9-c5bb82da5806
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821207288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.821207288
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.501372111
Short name T604
Test name
Test status
Simulation time 1533018916 ps
CPU time 90.33 seconds
Started Mar 26 01:17:40 PM PDT 24
Finished Mar 26 01:19:11 PM PDT 24
Peak memory 550324 kb
Host smart-b76d8c1a-feb5-4a12-9434-b6a7bf434eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501372111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.501372111
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.748284786
Short name T733
Test name
Test status
Simulation time 4199281279 ps
CPU time 35.44 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:18:05 PM PDT 24
Peak memory 486812 kb
Host smart-aba9002f-2218-402f-821b-f1e99dbc2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748284786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.748284786
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3336923699
Short name T548
Test name
Test status
Simulation time 184006239 ps
CPU time 1.06 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:17:30 PM PDT 24
Peak memory 203868 kb
Host smart-d5ad8a14-45b7-4ce2-bbb9-21f79483ba16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336923699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3336923699
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.566619055
Short name T776
Test name
Test status
Simulation time 176936679 ps
CPU time 9.23 seconds
Started Mar 26 01:17:29 PM PDT 24
Finished Mar 26 01:17:38 PM PDT 24
Peak memory 204168 kb
Host smart-ad999ea8-bc00-4e4c-8720-0717a70cf007
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566619055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
566619055
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.3048691751
Short name T1046
Test name
Test status
Simulation time 17693680101 ps
CPU time 194.98 seconds
Started Mar 26 01:17:27 PM PDT 24
Finished Mar 26 01:20:42 PM PDT 24
Peak memory 897280 kb
Host smart-5c14f852-69e6-44bc-914e-60d23e2d242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048691751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.3048691751
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_override.3889726852
Short name T458
Test name
Test status
Simulation time 15632743 ps
CPU time 0.68 seconds
Started Mar 26 01:17:32 PM PDT 24
Finished Mar 26 01:17:33 PM PDT 24
Peak memory 203764 kb
Host smart-ac7c67c5-51de-43bb-90b2-8b6386e1dbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889726852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3889726852
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3828653369
Short name T210
Test name
Test status
Simulation time 2476964251 ps
CPU time 27.06 seconds
Started Mar 26 01:17:44 PM PDT 24
Finished Mar 26 01:18:11 PM PDT 24
Peak memory 258424 kb
Host smart-71d7fcf2-a7ce-4fac-b3b5-d7c6372296fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828653369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3828653369
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1431547686
Short name T748
Test name
Test status
Simulation time 1546541127 ps
CPU time 122.83 seconds
Started Mar 26 01:17:30 PM PDT 24
Finished Mar 26 01:19:33 PM PDT 24
Peak memory 294672 kb
Host smart-febf8437-25e2-451b-8864-7a301127bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431547686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1431547686
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1382182128
Short name T666
Test name
Test status
Simulation time 999045025 ps
CPU time 2.94 seconds
Started Mar 26 01:17:42 PM PDT 24
Finished Mar 26 01:17:46 PM PDT 24
Peak memory 204184 kb
Host smart-870bfda2-e565-4061-9bb7-868d6ebce740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382182128 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1382182128
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2005089521
Short name T251
Test name
Test status
Simulation time 10139949877 ps
CPU time 5.5 seconds
Started Mar 26 01:17:45 PM PDT 24
Finished Mar 26 01:17:51 PM PDT 24
Peak memory 234800 kb
Host smart-954b279a-68ae-457a-9fbd-b153451d22e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005089521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2005089521
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.3507519587
Short name T1019
Test name
Test status
Simulation time 10057047706 ps
CPU time 89.6 seconds
Started Mar 26 01:17:45 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 678112 kb
Host smart-e3020fc3-518e-47af-a132-acd0d845c08e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507519587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.3507519587
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3031633967
Short name T901
Test name
Test status
Simulation time 4193477511 ps
CPU time 3.15 seconds
Started Mar 26 01:17:44 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 204272 kb
Host smart-2454e7ae-a429-4c24-8906-b6abfdcb97a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031633967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3031633967
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3297555115
Short name T706
Test name
Test status
Simulation time 3976617243 ps
CPU time 4.44 seconds
Started Mar 26 01:17:41 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 204200 kb
Host smart-18adaeba-c10a-42e3-8e98-ebb88d3a1b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297555115 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3297555115
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1879608952
Short name T335
Test name
Test status
Simulation time 4246630287 ps
CPU time 17.9 seconds
Started Mar 26 01:17:44 PM PDT 24
Finished Mar 26 01:18:03 PM PDT 24
Peak memory 204464 kb
Host smart-d33ba701-8cff-460a-92ef-a798f684b5c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879608952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1879608952
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3550768840
Short name T810
Test name
Test status
Simulation time 1800885443 ps
CPU time 33.41 seconds
Started Mar 26 01:17:45 PM PDT 24
Finished Mar 26 01:18:18 PM PDT 24
Peak memory 229608 kb
Host smart-e7ebf0b8-8db9-4b5f-9d60-0d66df83200b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550768840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3550768840
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.4273695867
Short name T777
Test name
Test status
Simulation time 45607476684 ps
CPU time 780.53 seconds
Started Mar 26 01:17:42 PM PDT 24
Finished Mar 26 01:30:43 PM PDT 24
Peak memory 2163752 kb
Host smart-1d15ad59-e754-477b-a98e-3577d0ce5a40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273695867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.4273695867
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1195594508
Short name T267
Test name
Test status
Simulation time 1433344909 ps
CPU time 7.02 seconds
Started Mar 26 01:17:43 PM PDT 24
Finished Mar 26 01:17:51 PM PDT 24
Peak memory 208764 kb
Host smart-a31bc59d-550f-497b-97f0-7fd9e8b844ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195594508 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1195594508
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2587812683
Short name T556
Test name
Test status
Simulation time 41039238 ps
CPU time 0.61 seconds
Started Mar 26 01:18:00 PM PDT 24
Finished Mar 26 01:18:00 PM PDT 24
Peak memory 203776 kb
Host smart-080353a3-b58d-461e-9ae8-f2f155834e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587812683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2587812683
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1028833531
Short name T504
Test name
Test status
Simulation time 38151990 ps
CPU time 1.93 seconds
Started Mar 26 01:17:44 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 212240 kb
Host smart-8a68e509-990f-4da4-b7b6-762b48d79263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028833531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1028833531
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.2720917939
Short name T864
Test name
Test status
Simulation time 292970976 ps
CPU time 15.33 seconds
Started Mar 26 01:17:46 PM PDT 24
Finished Mar 26 01:18:01 PM PDT 24
Peak memory 263744 kb
Host smart-5ab5c1ba-e98c-4b2b-9f5c-5ff0966ec304
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720917939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.2720917939
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.4162536941
Short name T537
Test name
Test status
Simulation time 2429085842 ps
CPU time 77.76 seconds
Started Mar 26 01:17:45 PM PDT 24
Finished Mar 26 01:19:03 PM PDT 24
Peak memory 809216 kb
Host smart-20b082f8-2717-47a6-86db-17ff31237030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162536941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.4162536941
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.392376479
Short name T684
Test name
Test status
Simulation time 1473281454 ps
CPU time 48.01 seconds
Started Mar 26 01:17:43 PM PDT 24
Finished Mar 26 01:18:31 PM PDT 24
Peak memory 569896 kb
Host smart-1f7b887d-d56e-47ef-b25e-2bf596458980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392376479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.392376479
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.4084998727
Short name T593
Test name
Test status
Simulation time 127166055 ps
CPU time 1.06 seconds
Started Mar 26 01:17:42 PM PDT 24
Finished Mar 26 01:17:43 PM PDT 24
Peak memory 204044 kb
Host smart-6c657847-207d-4910-aa5c-f46559a39509
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084998727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.4084998727
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3115400120
Short name T883
Test name
Test status
Simulation time 206058768 ps
CPU time 5.61 seconds
Started Mar 26 01:17:41 PM PDT 24
Finished Mar 26 01:17:47 PM PDT 24
Peak memory 242712 kb
Host smart-85c200a4-4219-4e02-9a9e-530c4a43c81c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115400120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3115400120
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.412442464
Short name T940
Test name
Test status
Simulation time 3668222528 ps
CPU time 86.95 seconds
Started Mar 26 01:17:43 PM PDT 24
Finished Mar 26 01:19:10 PM PDT 24
Peak memory 1061452 kb
Host smart-238cf84b-9662-4609-b1b4-ac8a11e57215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412442464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.412442464
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_override.1108931389
Short name T373
Test name
Test status
Simulation time 15344500 ps
CPU time 0.63 seconds
Started Mar 26 01:17:45 PM PDT 24
Finished Mar 26 01:17:46 PM PDT 24
Peak memory 203764 kb
Host smart-6e0aa594-109a-4c85-9100-451cfc042464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108931389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1108931389
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3625648134
Short name T193
Test name
Test status
Simulation time 617900495 ps
CPU time 1.94 seconds
Started Mar 26 01:17:43 PM PDT 24
Finished Mar 26 01:17:45 PM PDT 24
Peak memory 212396 kb
Host smart-f59e771a-287f-43b7-b292-6b439847fd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625648134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3625648134
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.825121698
Short name T541
Test name
Test status
Simulation time 3821549187 ps
CPU time 4.28 seconds
Started Mar 26 01:17:59 PM PDT 24
Finished Mar 26 01:18:03 PM PDT 24
Peak memory 204260 kb
Host smart-db37a847-d0d8-4741-9023-7f932c74490e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825121698 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.825121698
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3225952912
Short name T61
Test name
Test status
Simulation time 10059009721 ps
CPU time 15.41 seconds
Started Mar 26 01:17:56 PM PDT 24
Finished Mar 26 01:18:12 PM PDT 24
Peak memory 306548 kb
Host smart-7c2a2d05-a77f-429e-ae03-0fe0a3465830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225952912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3225952912
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3757835553
Short name T948
Test name
Test status
Simulation time 10304446958 ps
CPU time 18.16 seconds
Started Mar 26 01:17:56 PM PDT 24
Finished Mar 26 01:18:14 PM PDT 24
Peak memory 333648 kb
Host smart-da80eea2-f1c0-457a-b598-7de5b6ff1d9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757835553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3757835553
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3004243913
Short name T1099
Test name
Test status
Simulation time 583285125 ps
CPU time 2.88 seconds
Started Mar 26 01:17:56 PM PDT 24
Finished Mar 26 01:17:59 PM PDT 24
Peak memory 204060 kb
Host smart-c9d7b197-8999-4c2e-8c54-5c574be8932e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004243913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3004243913
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2446475842
Short name T736
Test name
Test status
Simulation time 1330895767 ps
CPU time 3.88 seconds
Started Mar 26 01:17:59 PM PDT 24
Finished Mar 26 01:18:03 PM PDT 24
Peak memory 204364 kb
Host smart-6e8298e7-75f5-4b26-96f3-f8694f1976bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446475842 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2446475842
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1625609461
Short name T485
Test name
Test status
Simulation time 2008283115 ps
CPU time 17.12 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:18:14 PM PDT 24
Peak memory 204048 kb
Host smart-5f8857bf-709b-4e75-b4c5-40e030756960
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625609461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1625609461
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.416910506
Short name T122
Test name
Test status
Simulation time 4358929917 ps
CPU time 15.46 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:18:12 PM PDT 24
Peak memory 221188 kb
Host smart-7521cfd3-aaf5-40ff-9bc2-bbde70092325
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416910506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.416910506
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3261196470
Short name T650
Test name
Test status
Simulation time 40799708897 ps
CPU time 2818.26 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 02:04:56 PM PDT 24
Peak memory 4521024 kb
Host smart-dc3f44e6-6640-4342-9030-f4c3a51a2f25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261196470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3261196470
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3539910481
Short name T377
Test name
Test status
Simulation time 13709051631 ps
CPU time 7.36 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:18:04 PM PDT 24
Peak memory 214324 kb
Host smart-44496d5d-001d-4e0f-80c9-5c61553f70e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539910481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3539910481
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1008984935
Short name T365
Test name
Test status
Simulation time 32995497 ps
CPU time 0.6 seconds
Started Mar 26 01:18:16 PM PDT 24
Finished Mar 26 01:18:17 PM PDT 24
Peak memory 203720 kb
Host smart-2967f1ac-36c0-41dc-afbd-a4dd6fdc875e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008984935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1008984935
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3672394738
Short name T413
Test name
Test status
Simulation time 48149799 ps
CPU time 1.44 seconds
Started Mar 26 01:17:59 PM PDT 24
Finished Mar 26 01:18:01 PM PDT 24
Peak memory 220560 kb
Host smart-0f54ff2c-203b-4c64-825b-866b246a7c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672394738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3672394738
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3955797549
Short name T960
Test name
Test status
Simulation time 459967897 ps
CPU time 4.38 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:18:01 PM PDT 24
Peak memory 251008 kb
Host smart-726ac2fd-fd05-46b1-b2de-0a7a07c2916b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955797549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3955797549
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2481673795
Short name T1090
Test name
Test status
Simulation time 34988064591 ps
CPU time 107.96 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:19:45 PM PDT 24
Peak memory 499180 kb
Host smart-fc49e9e7-383e-4d74-a725-4c1f2133c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481673795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2481673795
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2566940410
Short name T585
Test name
Test status
Simulation time 7075503307 ps
CPU time 115.77 seconds
Started Mar 26 01:17:58 PM PDT 24
Finished Mar 26 01:19:54 PM PDT 24
Peak memory 410628 kb
Host smart-acd5979b-f12f-4026-970e-415f7c2726e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566940410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2566940410
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2393861242
Short name T518
Test name
Test status
Simulation time 328968190 ps
CPU time 0.92 seconds
Started Mar 26 01:17:58 PM PDT 24
Finished Mar 26 01:17:59 PM PDT 24
Peak memory 203920 kb
Host smart-3a200f75-9197-4ceb-b14a-9c5931bae0ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393861242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2393861242
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.3526158257
Short name T580
Test name
Test status
Simulation time 590018741 ps
CPU time 8.71 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:18:05 PM PDT 24
Peak memory 204100 kb
Host smart-39a92847-caa3-4fa1-9e0b-7e347824fbb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526158257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.3526158257
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1568594459
Short name T869
Test name
Test status
Simulation time 15770290319 ps
CPU time 83.83 seconds
Started Mar 26 01:17:56 PM PDT 24
Finished Mar 26 01:19:20 PM PDT 24
Peak memory 926976 kb
Host smart-295ff81a-c238-4258-9627-83088b205ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568594459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1568594459
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_override.2283096512
Short name T206
Test name
Test status
Simulation time 56319709 ps
CPU time 0.64 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:17:57 PM PDT 24
Peak memory 203888 kb
Host smart-4f1a52d6-1d1b-45bc-b94c-8a86fecbc291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283096512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2283096512
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3793632076
Short name T43
Test name
Test status
Simulation time 6176722948 ps
CPU time 182.92 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:21:00 PM PDT 24
Peak memory 449428 kb
Host smart-c87e4634-561c-4293-a342-caf21e63b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793632076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3793632076
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3373930360
Short name T1037
Test name
Test status
Simulation time 1082269188 ps
CPU time 36.37 seconds
Started Mar 26 01:17:59 PM PDT 24
Finished Mar 26 01:18:35 PM PDT 24
Peak memory 284412 kb
Host smart-28c8d9a4-ebf3-4a87-a18a-e8497aef5e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373930360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3373930360
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.255130019
Short name T281
Test name
Test status
Simulation time 468141162 ps
CPU time 2.48 seconds
Started Mar 26 01:17:58 PM PDT 24
Finished Mar 26 01:18:01 PM PDT 24
Peak memory 204152 kb
Host smart-ff038c4d-00fb-49e6-a4f7-fe608fed2973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255130019 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.255130019
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3884761019
Short name T425
Test name
Test status
Simulation time 10122751545 ps
CPU time 73.87 seconds
Started Mar 26 01:17:58 PM PDT 24
Finished Mar 26 01:19:12 PM PDT 24
Peak memory 613048 kb
Host smart-6039e30d-4ba6-4236-a3bc-ff0c7f2ced42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884761019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3884761019
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1345855218
Short name T607
Test name
Test status
Simulation time 10104378547 ps
CPU time 11.75 seconds
Started Mar 26 01:17:53 PM PDT 24
Finished Mar 26 01:18:04 PM PDT 24
Peak memory 325768 kb
Host smart-4d95b18a-c487-4845-a41a-0b621e097a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345855218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1345855218
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3111753464
Short name T48
Test name
Test status
Simulation time 511075431 ps
CPU time 2.81 seconds
Started Mar 26 01:17:59 PM PDT 24
Finished Mar 26 01:18:02 PM PDT 24
Peak memory 204116 kb
Host smart-410f4fa0-0fce-4109-ae7b-274e157ff00e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111753464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3111753464
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3266228769
Short name T343
Test name
Test status
Simulation time 862953728 ps
CPU time 4.48 seconds
Started Mar 26 01:17:56 PM PDT 24
Finished Mar 26 01:18:00 PM PDT 24
Peak memory 204764 kb
Host smart-1683d059-e340-4fd4-8605-7730d3eece1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266228769 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3266228769
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.4227509249
Short name T958
Test name
Test status
Simulation time 735920493 ps
CPU time 28.61 seconds
Started Mar 26 01:17:59 PM PDT 24
Finished Mar 26 01:18:28 PM PDT 24
Peak memory 204148 kb
Host smart-df48a26e-cc50-4727-af8d-4a8af33aa2ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227509249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.4227509249
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3952672607
Short name T904
Test name
Test status
Simulation time 343701795 ps
CPU time 6.23 seconds
Started Mar 26 01:17:58 PM PDT 24
Finished Mar 26 01:18:05 PM PDT 24
Peak memory 204120 kb
Host smart-b0659dd7-e4f4-409a-84dd-96643313624b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952672607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3952672607
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1666046304
Short name T430
Test name
Test status
Simulation time 20858285140 ps
CPU time 372.65 seconds
Started Mar 26 01:17:56 PM PDT 24
Finished Mar 26 01:24:09 PM PDT 24
Peak memory 1304340 kb
Host smart-b1f042c8-3d1e-4d9a-ace5-4f626e3b406b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666046304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1666046304
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1128032238
Short name T979
Test name
Test status
Simulation time 1966666264 ps
CPU time 5.83 seconds
Started Mar 26 01:17:57 PM PDT 24
Finished Mar 26 01:18:03 PM PDT 24
Peak memory 218016 kb
Host smart-084741ab-97eb-4fe6-ac9e-188b2679d9d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128032238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1128032238
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3151999320
Short name T409
Test name
Test status
Simulation time 48701858 ps
CPU time 0.62 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:18:10 PM PDT 24
Peak memory 203836 kb
Host smart-e7ae1e42-40a0-4f26-8a57-65ea69bcca30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151999320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3151999320
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3170876525
Short name T290
Test name
Test status
Simulation time 39012674 ps
CPU time 1.22 seconds
Started Mar 26 01:18:16 PM PDT 24
Finished Mar 26 01:18:17 PM PDT 24
Peak memory 212384 kb
Host smart-48d53432-11cd-4d25-9edb-8c177da8908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170876525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3170876525
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2137706286
Short name T470
Test name
Test status
Simulation time 2375816510 ps
CPU time 14.02 seconds
Started Mar 26 01:18:11 PM PDT 24
Finished Mar 26 01:18:25 PM PDT 24
Peak memory 249688 kb
Host smart-9608e8a5-3174-474d-830a-9054b3dcc724
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137706286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2137706286
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.4080052868
Short name T689
Test name
Test status
Simulation time 6203344737 ps
CPU time 46.9 seconds
Started Mar 26 01:18:10 PM PDT 24
Finished Mar 26 01:18:57 PM PDT 24
Peak memory 576144 kb
Host smart-e82a8f98-f01d-4d17-b4cb-27bb62a0f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080052868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.4080052868
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.668405398
Short name T475
Test name
Test status
Simulation time 5881068134 ps
CPU time 104.25 seconds
Started Mar 26 01:18:11 PM PDT 24
Finished Mar 26 01:19:55 PM PDT 24
Peak memory 517636 kb
Host smart-2d45a69b-a8fa-4601-9439-c5df10cc91c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668405398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.668405398
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1407633076
Short name T663
Test name
Test status
Simulation time 360358448 ps
CPU time 0.91 seconds
Started Mar 26 01:18:16 PM PDT 24
Finished Mar 26 01:18:17 PM PDT 24
Peak memory 203844 kb
Host smart-8a43a8b6-07ca-4fe8-b9e9-ace07d7166e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407633076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1407633076
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.4061087094
Short name T124
Test name
Test status
Simulation time 773516914 ps
CPU time 8.57 seconds
Started Mar 26 01:18:11 PM PDT 24
Finished Mar 26 01:18:19 PM PDT 24
Peak memory 204160 kb
Host smart-974cfce9-c3df-4446-9037-e24fed6c186c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061087094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.4061087094
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3128973618
Short name T179
Test name
Test status
Simulation time 14925114585 ps
CPU time 73.68 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:19:23 PM PDT 24
Peak memory 923056 kb
Host smart-a7c24f53-8661-4c20-9c33-25f4dd1056e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128973618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3128973618
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_override.1401296520
Short name T202
Test name
Test status
Simulation time 30530557 ps
CPU time 0.63 seconds
Started Mar 26 01:18:06 PM PDT 24
Finished Mar 26 01:18:07 PM PDT 24
Peak memory 203780 kb
Host smart-b2f255b0-573e-4f12-9b6a-9767642e6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401296520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1401296520
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2612511100
Short name T212
Test name
Test status
Simulation time 3141004661 ps
CPU time 13.86 seconds
Started Mar 26 01:18:17 PM PDT 24
Finished Mar 26 01:18:31 PM PDT 24
Peak memory 220304 kb
Host smart-7d793264-e73d-48d8-b0ea-b1e6c8adb838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612511100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2612511100
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3712165091
Short name T870
Test name
Test status
Simulation time 4443155933 ps
CPU time 36.72 seconds
Started Mar 26 01:18:10 PM PDT 24
Finished Mar 26 01:18:47 PM PDT 24
Peak memory 286844 kb
Host smart-94006fb9-6f53-46a1-97f1-2ec6988612fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712165091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3712165091
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1736530057
Short name T770
Test name
Test status
Simulation time 824895530 ps
CPU time 4.13 seconds
Started Mar 26 01:18:16 PM PDT 24
Finished Mar 26 01:18:20 PM PDT 24
Peak memory 204164 kb
Host smart-f3778d2f-1757-410c-a993-cc045efbcebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736530057 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1736530057
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2829159706
Short name T252
Test name
Test status
Simulation time 10122902997 ps
CPU time 14.93 seconds
Started Mar 26 01:18:12 PM PDT 24
Finished Mar 26 01:18:27 PM PDT 24
Peak memory 308448 kb
Host smart-6391b1dd-1731-4ef5-8bb1-415d9365cb9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829159706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2829159706
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2341379449
Short name T418
Test name
Test status
Simulation time 10147460124 ps
CPU time 96.33 seconds
Started Mar 26 01:18:10 PM PDT 24
Finished Mar 26 01:19:46 PM PDT 24
Peak memory 750136 kb
Host smart-165d4f0a-933d-4bfb-9bf1-283746b9cbc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341379449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2341379449
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1676369325
Short name T471
Test name
Test status
Simulation time 476886604 ps
CPU time 3.07 seconds
Started Mar 26 01:18:10 PM PDT 24
Finished Mar 26 01:18:13 PM PDT 24
Peak memory 204180 kb
Host smart-08a2c028-5df5-4049-af96-9860567b4995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676369325 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1676369325
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3261544636
Short name T828
Test name
Test status
Simulation time 1608131945 ps
CPU time 4.24 seconds
Started Mar 26 01:18:12 PM PDT 24
Finished Mar 26 01:18:17 PM PDT 24
Peak memory 206452 kb
Host smart-2e2cb010-6878-4394-b194-87b5f422cc12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261544636 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3261544636
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.4097766864
Short name T907
Test name
Test status
Simulation time 2196101253 ps
CPU time 20.57 seconds
Started Mar 26 01:18:11 PM PDT 24
Finished Mar 26 01:18:31 PM PDT 24
Peak memory 204148 kb
Host smart-40f35e55-2f5e-4c28-a324-4280f8b5d634
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097766864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.4097766864
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1525266067
Short name T865
Test name
Test status
Simulation time 1690010780 ps
CPU time 14.68 seconds
Started Mar 26 01:18:11 PM PDT 24
Finished Mar 26 01:18:25 PM PDT 24
Peak memory 207568 kb
Host smart-0144a3c4-a9fe-4d88-b293-78cae8e41110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525266067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1525266067
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3697512217
Short name T887
Test name
Test status
Simulation time 5792810034 ps
CPU time 7.24 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:18:16 PM PDT 24
Peak memory 211252 kb
Host smart-7fe5aae3-6ca1-4703-9600-6949f84fbb8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697512217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3697512217
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2106068702
Short name T1053
Test name
Test status
Simulation time 18862541 ps
CPU time 0.6 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:12:45 PM PDT 24
Peak memory 203524 kb
Host smart-00202494-8f13-4667-bbe5-6ec8114a5ec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106068702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2106068702
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2467332793
Short name T406
Test name
Test status
Simulation time 40119265 ps
CPU time 1.76 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:12:46 PM PDT 24
Peak memory 212384 kb
Host smart-ccca1cdc-8d9e-4f36-aa6c-9cc8ae7687ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467332793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2467332793
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2534276411
Short name T1041
Test name
Test status
Simulation time 2087146360 ps
CPU time 8.6 seconds
Started Mar 26 01:12:47 PM PDT 24
Finished Mar 26 01:12:56 PM PDT 24
Peak memory 289440 kb
Host smart-88e2a1b1-def1-4581-a5a3-38c23b2c735e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534276411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2534276411
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.855998230
Short name T1004
Test name
Test status
Simulation time 7321756442 ps
CPU time 130.43 seconds
Started Mar 26 01:12:49 PM PDT 24
Finished Mar 26 01:15:00 PM PDT 24
Peak memory 660828 kb
Host smart-58e7f60b-3413-4ac4-ac16-fe0bf73de76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855998230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.855998230
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.672044748
Short name T427
Test name
Test status
Simulation time 5596866924 ps
CPU time 94.66 seconds
Started Mar 26 01:12:41 PM PDT 24
Finished Mar 26 01:14:16 PM PDT 24
Peak memory 539320 kb
Host smart-112680dd-7baa-4b73-b204-d211d0f5754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672044748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.672044748
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.297521922
Short name T919
Test name
Test status
Simulation time 1168883932 ps
CPU time 0.89 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:12:46 PM PDT 24
Peak memory 203920 kb
Host smart-c3f0e5e2-41ed-4f58-aa88-fead97eee6d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297521922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.297521922
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.4002899312
Short name T997
Test name
Test status
Simulation time 514724260 ps
CPU time 3.71 seconds
Started Mar 26 01:12:45 PM PDT 24
Finished Mar 26 01:12:49 PM PDT 24
Peak memory 225256 kb
Host smart-63aa148a-cdd1-407f-b6a2-af24f65e88bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002899312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
4002899312
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.868090867
Short name T417
Test name
Test status
Simulation time 2388634761 ps
CPU time 66.94 seconds
Started Mar 26 01:12:42 PM PDT 24
Finished Mar 26 01:13:49 PM PDT 24
Peak memory 779884 kb
Host smart-ef135bcf-a8b0-4ffa-afe5-ffbaffb03149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868090867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.868090867
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_override.1253334047
Short name T1066
Test name
Test status
Simulation time 60764301 ps
CPU time 0.61 seconds
Started Mar 26 01:12:42 PM PDT 24
Finished Mar 26 01:12:43 PM PDT 24
Peak memory 203752 kb
Host smart-f2934b19-d774-4ea1-aadd-2a1fe06f54af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253334047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1253334047
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3328866064
Short name T445
Test name
Test status
Simulation time 7302368290 ps
CPU time 75.85 seconds
Started Mar 26 01:12:47 PM PDT 24
Finished Mar 26 01:14:03 PM PDT 24
Peak memory 220200 kb
Host smart-13fe7fba-9714-41b8-92bb-920504e76976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328866064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3328866064
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.577186629
Short name T665
Test name
Test status
Simulation time 6893165623 ps
CPU time 135.49 seconds
Started Mar 26 01:12:41 PM PDT 24
Finished Mar 26 01:14:56 PM PDT 24
Peak memory 317612 kb
Host smart-157d2549-8c67-47cb-8452-a2e0668efd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577186629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.577186629
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3547622345
Short name T119
Test name
Test status
Simulation time 37577788 ps
CPU time 0.87 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:12:55 PM PDT 24
Peak memory 221288 kb
Host smart-9b100727-8054-41b2-ad42-5844ea8f118d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547622345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3547622345
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.4130869409
Short name T392
Test name
Test status
Simulation time 4813905319 ps
CPU time 3.91 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:12:48 PM PDT 24
Peak memory 204068 kb
Host smart-c9a3fb4b-ba9a-4284-89d7-195c8f84fa36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130869409 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.4130869409
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3419506308
Short name T1076
Test name
Test status
Simulation time 10156005175 ps
CPU time 77.85 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:14:03 PM PDT 24
Peak memory 576948 kb
Host smart-0fdcaddf-fa4e-40b3-880e-1d9dffc54fe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419506308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3419506308
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.948835400
Short name T765
Test name
Test status
Simulation time 10312406489 ps
CPU time 17.4 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:13:02 PM PDT 24
Peak memory 331612 kb
Host smart-2c547dac-8a8e-4816-90c8-063d7f3a179c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948835400 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_tx.948835400
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2060010328
Short name T1025
Test name
Test status
Simulation time 392859655 ps
CPU time 2.61 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:12:47 PM PDT 24
Peak memory 204208 kb
Host smart-03e7ad73-6138-47e4-a406-648d215dfbe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060010328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2060010328
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.4057346492
Short name T686
Test name
Test status
Simulation time 791830100 ps
CPU time 4.19 seconds
Started Mar 26 01:12:45 PM PDT 24
Finished Mar 26 01:12:49 PM PDT 24
Peak memory 204100 kb
Host smart-7136c38c-71bf-4ff6-b1aa-7e3f287c3602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057346492 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.4057346492
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2775093114
Short name T933
Test name
Test status
Simulation time 2401901731 ps
CPU time 5.73 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:12:50 PM PDT 24
Peak memory 204304 kb
Host smart-f99d8fc9-2758-4286-98f9-993f2719d58e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775093114 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2775093114
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3161968650
Short name T278
Test name
Test status
Simulation time 583671321 ps
CPU time 19.23 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:13:03 PM PDT 24
Peak memory 204016 kb
Host smart-8a3e5f31-b6d9-4bfc-ac2b-956b6944b52f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161968650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3161968650
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.4168535039
Short name T1105
Test name
Test status
Simulation time 4502911779 ps
CPU time 18.84 seconds
Started Mar 26 01:12:45 PM PDT 24
Finished Mar 26 01:13:04 PM PDT 24
Peak memory 215844 kb
Host smart-f2b8cd1f-3e2c-4880-b8a3-df06c9c7ee8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168535039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.4168535039
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.889537998
Short name T423
Test name
Test status
Simulation time 18661878424 ps
CPU time 285.49 seconds
Started Mar 26 01:12:45 PM PDT 24
Finished Mar 26 01:17:31 PM PDT 24
Peak memory 2339068 kb
Host smart-9486daad-5cc1-48c5-a737-562ab030e9d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889537998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.889537998
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3383805154
Short name T682
Test name
Test status
Simulation time 6118555302 ps
CPU time 7.71 seconds
Started Mar 26 01:12:42 PM PDT 24
Finished Mar 26 01:12:50 PM PDT 24
Peak memory 220448 kb
Host smart-309879ae-d418-4822-91cc-acddd3fa6c72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383805154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3383805154
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2600056846
Short name T913
Test name
Test status
Simulation time 18421672 ps
CPU time 0.63 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:18:24 PM PDT 24
Peak memory 203740 kb
Host smart-27c5c363-7433-43b7-aa6e-94f07a6f1ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600056846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2600056846
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3818469996
Short name T32
Test name
Test status
Simulation time 118806435 ps
CPU time 1.67 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:18:11 PM PDT 24
Peak memory 212284 kb
Host smart-42bd47df-c727-4f6e-832a-356045e43ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818469996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3818469996
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2530993295
Short name T746
Test name
Test status
Simulation time 250709365 ps
CPU time 2.51 seconds
Started Mar 26 01:18:13 PM PDT 24
Finished Mar 26 01:18:15 PM PDT 24
Peak memory 224840 kb
Host smart-23f5dfdf-e825-4163-8fb7-5a562a53ae5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530993295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2530993295
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.4270230333
Short name T635
Test name
Test status
Simulation time 21999926084 ps
CPU time 82.51 seconds
Started Mar 26 01:18:16 PM PDT 24
Finished Mar 26 01:19:39 PM PDT 24
Peak memory 754348 kb
Host smart-8fffa5c2-7e9e-4a9d-a070-fe552db075b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270230333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.4270230333
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.351460570
Short name T510
Test name
Test status
Simulation time 3330485967 ps
CPU time 43.27 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:18:52 PM PDT 24
Peak memory 547928 kb
Host smart-823b6cbc-db87-4d52-aa1d-4e299b26e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351460570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.351460570
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.26621770
Short name T216
Test name
Test status
Simulation time 63744066 ps
CPU time 0.79 seconds
Started Mar 26 01:18:11 PM PDT 24
Finished Mar 26 01:18:12 PM PDT 24
Peak memory 203916 kb
Host smart-7a6cf021-12ed-4ac8-b439-e775a4fc0f1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26621770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt
.26621770
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1396185266
Short name T562
Test name
Test status
Simulation time 2019773073 ps
CPU time 5.91 seconds
Started Mar 26 01:18:08 PM PDT 24
Finished Mar 26 01:18:14 PM PDT 24
Peak memory 204244 kb
Host smart-a57cdd51-5296-4e4a-a614-e313184b2301
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396185266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1396185266
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3203908320
Short name T237
Test name
Test status
Simulation time 8351610400 ps
CPU time 290.95 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:23:01 PM PDT 24
Peak memory 1137012 kb
Host smart-af07fa0b-260d-4d95-a876-2450a5883eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203908320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3203908320
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_override.3046805563
Short name T878
Test name
Test status
Simulation time 60451172 ps
CPU time 0.69 seconds
Started Mar 26 01:18:16 PM PDT 24
Finished Mar 26 01:18:17 PM PDT 24
Peak memory 203836 kb
Host smart-aba88e47-c01f-415d-b182-475fa15f7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046805563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3046805563
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1547025325
Short name T209
Test name
Test status
Simulation time 4278888360 ps
CPU time 59.27 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:19:08 PM PDT 24
Peak memory 204284 kb
Host smart-ea9d3359-c70b-4953-8430-5276b4e299d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547025325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1547025325
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.4266138010
Short name T566
Test name
Test status
Simulation time 4095606032 ps
CPU time 35.16 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:18:44 PM PDT 24
Peak memory 275108 kb
Host smart-4227c546-314b-4d34-9e72-4015de52908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266138010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.4266138010
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3519198440
Short name T457
Test name
Test status
Simulation time 964385966 ps
CPU time 3.82 seconds
Started Mar 26 01:18:24 PM PDT 24
Finished Mar 26 01:18:28 PM PDT 24
Peak memory 204088 kb
Host smart-7394e535-c30e-4d47-81ff-1ee57363ccd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519198440 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3519198440
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1808033011
Short name T442
Test name
Test status
Simulation time 10130674995 ps
CPU time 15.55 seconds
Started Mar 26 01:18:23 PM PDT 24
Finished Mar 26 01:18:39 PM PDT 24
Peak memory 285952 kb
Host smart-aeb9d9f4-4fca-4965-b671-d71ea17295c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808033011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1808033011
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1529738830
Short name T299
Test name
Test status
Simulation time 10112885779 ps
CPU time 39.41 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:19:02 PM PDT 24
Peak memory 491156 kb
Host smart-a57d5df1-1863-443e-8e42-6641c6827e17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529738830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1529738830
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2724936733
Short name T980
Test name
Test status
Simulation time 1275422432 ps
CPU time 2.31 seconds
Started Mar 26 01:18:20 PM PDT 24
Finished Mar 26 01:18:22 PM PDT 24
Peak memory 204080 kb
Host smart-6cce0371-b206-4b1a-b54d-f25eab4fd68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724936733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2724936733
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3196555350
Short name T787
Test name
Test status
Simulation time 1141812930 ps
CPU time 5.47 seconds
Started Mar 26 01:18:12 PM PDT 24
Finished Mar 26 01:18:18 PM PDT 24
Peak memory 204092 kb
Host smart-8701ef51-2b68-4b82-9e70-771afd4e621f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196555350 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3196555350
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3915219750
Short name T583
Test name
Test status
Simulation time 1861212266 ps
CPU time 9.6 seconds
Started Mar 26 01:18:11 PM PDT 24
Finished Mar 26 01:18:21 PM PDT 24
Peak memory 204088 kb
Host smart-34f7ebe4-20a2-49eb-97ce-ca1ad3201f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915219750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3915219750
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2003284738
Short name T515
Test name
Test status
Simulation time 1004102322 ps
CPU time 41.94 seconds
Started Mar 26 01:18:09 PM PDT 24
Finished Mar 26 01:18:51 PM PDT 24
Peak memory 204116 kb
Host smart-a2810343-2e51-4024-91ee-1dfb9c41942e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003284738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2003284738
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3641767365
Short name T891
Test name
Test status
Simulation time 5659259090 ps
CPU time 38.15 seconds
Started Mar 26 01:19:17 PM PDT 24
Finished Mar 26 01:19:56 PM PDT 24
Peak memory 752340 kb
Host smart-4d917806-24c2-400e-9ef9-df47b2005271
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641767365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3641767365
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.598570837
Short name T672
Test name
Test status
Simulation time 1400431350 ps
CPU time 6.74 seconds
Started Mar 26 01:18:23 PM PDT 24
Finished Mar 26 01:18:30 PM PDT 24
Peak memory 204164 kb
Host smart-87f48247-1e3e-45bc-81f8-6819468b4813
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598570837 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.598570837
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3391658955
Short name T543
Test name
Test status
Simulation time 92532782 ps
CPU time 0.67 seconds
Started Mar 26 01:18:43 PM PDT 24
Finished Mar 26 01:18:44 PM PDT 24
Peak memory 203748 kb
Host smart-11d22b5c-c2ba-4255-8c02-46d757eb3d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391658955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3391658955
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3286798141
Short name T439
Test name
Test status
Simulation time 44374361 ps
CPU time 1.33 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:18:24 PM PDT 24
Peak memory 212392 kb
Host smart-1bab4ed0-952c-40b2-b2b5-3ae5c082e60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286798141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3286798141
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.643736694
Short name T262
Test name
Test status
Simulation time 417509933 ps
CPU time 20.53 seconds
Started Mar 26 01:18:24 PM PDT 24
Finished Mar 26 01:18:45 PM PDT 24
Peak memory 279260 kb
Host smart-1ce78d5d-09c8-43d0-8010-372629f8bb74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643736694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.643736694
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1098691616
Short name T973
Test name
Test status
Simulation time 5087777769 ps
CPU time 57.97 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:19:20 PM PDT 24
Peak memory 676112 kb
Host smart-33b12530-325b-4217-b3d2-fab2e00e436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098691616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1098691616
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.820930462
Short name T944
Test name
Test status
Simulation time 414335149 ps
CPU time 0.95 seconds
Started Mar 26 01:18:21 PM PDT 24
Finished Mar 26 01:18:22 PM PDT 24
Peak memory 204160 kb
Host smart-a5bb1890-c574-4793-ae8b-73f8cd5423f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820930462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.820930462
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3598807026
Short name T79
Test name
Test status
Simulation time 430827740 ps
CPU time 6.09 seconds
Started Mar 26 01:18:21 PM PDT 24
Finished Mar 26 01:18:27 PM PDT 24
Peak memory 221260 kb
Host smart-3f1db607-e322-4bd6-8d72-ee41ad4ded07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598807026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3598807026
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.3881550911
Short name T174
Test name
Test status
Simulation time 4003419391 ps
CPU time 92.46 seconds
Started Mar 26 01:18:23 PM PDT 24
Finished Mar 26 01:19:55 PM PDT 24
Peak memory 1146352 kb
Host smart-51cf1856-8313-43c5-a64d-918610bb7e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881550911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.3881550911
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_override.1621321172
Short name T436
Test name
Test status
Simulation time 22205927 ps
CPU time 0.63 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:18:23 PM PDT 24
Peak memory 203788 kb
Host smart-1bdb045a-044e-440b-8d9b-41fabbfda16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621321172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1621321172
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.311518049
Short name T1029
Test name
Test status
Simulation time 98747213054 ps
CPU time 733.81 seconds
Started Mar 26 01:18:23 PM PDT 24
Finished Mar 26 01:30:37 PM PDT 24
Peak memory 204292 kb
Host smart-b88ee397-b368-44f5-9666-05aa9dad3c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311518049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.311518049
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3108611368
Short name T1062
Test name
Test status
Simulation time 758941202 ps
CPU time 47.23 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:19:10 PM PDT 24
Peak memory 236964 kb
Host smart-81302071-e34c-45c4-996e-50e7201958e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108611368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3108611368
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.648374973
Short name T695
Test name
Test status
Simulation time 667469177 ps
CPU time 3.46 seconds
Started Mar 26 01:18:35 PM PDT 24
Finished Mar 26 01:18:39 PM PDT 24
Peak memory 212264 kb
Host smart-2946ff69-715c-4b79-ae2e-16155a975d7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648374973 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.648374973
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.4139721007
Short name T403
Test name
Test status
Simulation time 10088193194 ps
CPU time 76.87 seconds
Started Mar 26 01:18:21 PM PDT 24
Finished Mar 26 01:19:38 PM PDT 24
Peak memory 537560 kb
Host smart-2a8066ef-bd3a-4c1d-97db-2b3b737a216e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139721007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.4139721007
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3291259842
Short name T811
Test name
Test status
Simulation time 10109359782 ps
CPU time 33.24 seconds
Started Mar 26 01:18:38 PM PDT 24
Finished Mar 26 01:19:12 PM PDT 24
Peak memory 442080 kb
Host smart-24804884-29f4-4093-949e-15859e2d9d9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291259842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3291259842
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3597778791
Short name T740
Test name
Test status
Simulation time 438212875 ps
CPU time 2.56 seconds
Started Mar 26 01:18:36 PM PDT 24
Finished Mar 26 01:18:39 PM PDT 24
Peak memory 204408 kb
Host smart-4479cd1d-9123-41dc-8ce4-4e85423a339d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597778791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3597778791
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1788795603
Short name T536
Test name
Test status
Simulation time 4042704421 ps
CPU time 5.38 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:18:28 PM PDT 24
Peak memory 204200 kb
Host smart-352d1dfd-4bd1-439a-9d3d-3b97ce55b11b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788795603 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1788795603
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.1124095063
Short name T671
Test name
Test status
Simulation time 6584404549 ps
CPU time 4.78 seconds
Started Mar 26 01:18:23 PM PDT 24
Finished Mar 26 01:18:29 PM PDT 24
Peak memory 204160 kb
Host smart-f554448c-533b-4e72-9133-967ecb00697e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124095063 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1124095063
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1082876117
Short name T596
Test name
Test status
Simulation time 1310831739 ps
CPU time 53.33 seconds
Started Mar 26 01:18:21 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 204152 kb
Host smart-ddf545c5-5682-4377-8faa-5f1f88475721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082876117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1082876117
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2279078021
Short name T840
Test name
Test status
Simulation time 1233433098 ps
CPU time 18.11 seconds
Started Mar 26 01:18:22 PM PDT 24
Finished Mar 26 01:18:40 PM PDT 24
Peak memory 219832 kb
Host smart-4b19b63b-e271-40f8-b92b-1db4a06e5d70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279078021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2279078021
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.35521099
Short name T51
Test name
Test status
Simulation time 1658430688 ps
CPU time 5.36 seconds
Started Mar 26 01:18:23 PM PDT 24
Finished Mar 26 01:18:29 PM PDT 24
Peak memory 204180 kb
Host smart-330868d1-525a-42b7-94f7-783b6589e589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35521099 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_unexp_stop.35521099
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2862488137
Short name T711
Test name
Test status
Simulation time 15994608 ps
CPU time 0.69 seconds
Started Mar 26 01:18:38 PM PDT 24
Finished Mar 26 01:18:39 PM PDT 24
Peak memory 203772 kb
Host smart-0dc21a16-afd1-4846-9b83-7ba9bb205ac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862488137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2862488137
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2746270216
Short name T1059
Test name
Test status
Simulation time 84996449 ps
CPU time 1.69 seconds
Started Mar 26 01:18:35 PM PDT 24
Finished Mar 26 01:18:37 PM PDT 24
Peak memory 212352 kb
Host smart-29ee3e14-d674-4d10-8283-1c891996be0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746270216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2746270216
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1601313326
Short name T532
Test name
Test status
Simulation time 374050579 ps
CPU time 7.47 seconds
Started Mar 26 01:18:33 PM PDT 24
Finished Mar 26 01:18:41 PM PDT 24
Peak memory 286876 kb
Host smart-c08b91bf-349a-4e85-b5e4-1cce0471762f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601313326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1601313326
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1695262040
Short name T731
Test name
Test status
Simulation time 42861091526 ps
CPU time 155.86 seconds
Started Mar 26 01:18:35 PM PDT 24
Finished Mar 26 01:21:11 PM PDT 24
Peak memory 739860 kb
Host smart-ec5b2374-a9b6-4c2d-9ea3-fdbcaf68e716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695262040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1695262040
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2391485050
Short name T652
Test name
Test status
Simulation time 2158313307 ps
CPU time 68.62 seconds
Started Mar 26 01:18:39 PM PDT 24
Finished Mar 26 01:19:48 PM PDT 24
Peak memory 676584 kb
Host smart-155e1ce5-a775-46e7-baae-159f40a7ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391485050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2391485050
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3888024007
Short name T1088
Test name
Test status
Simulation time 938773346 ps
CPU time 0.93 seconds
Started Mar 26 01:18:34 PM PDT 24
Finished Mar 26 01:18:35 PM PDT 24
Peak memory 203836 kb
Host smart-7a0369e8-c9bd-4e71-8530-66f333aaa064
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888024007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3888024007
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.2186327384
Short name T1020
Test name
Test status
Simulation time 195777104 ps
CPU time 2.63 seconds
Started Mar 26 01:18:36 PM PDT 24
Finished Mar 26 01:18:39 PM PDT 24
Peak memory 217408 kb
Host smart-be47d263-63a1-4883-8332-2e6cec1c6893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186327384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.2186327384
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.898828274
Short name T351
Test name
Test status
Simulation time 13018636506 ps
CPU time 209.84 seconds
Started Mar 26 01:18:36 PM PDT 24
Finished Mar 26 01:22:06 PM PDT 24
Peak memory 932228 kb
Host smart-94e4fa6a-8a69-46d1-aa33-2a06c6db4727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898828274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.898828274
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_override.619309757
Short name T1077
Test name
Test status
Simulation time 17756465 ps
CPU time 0.62 seconds
Started Mar 26 01:18:34 PM PDT 24
Finished Mar 26 01:18:34 PM PDT 24
Peak memory 204156 kb
Host smart-491bdefc-974e-4ee0-ae64-2efdf3e1ca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619309757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.619309757
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2512098144
Short name T13
Test name
Test status
Simulation time 7003843328 ps
CPU time 94.77 seconds
Started Mar 26 01:18:39 PM PDT 24
Finished Mar 26 01:20:14 PM PDT 24
Peak memory 212512 kb
Host smart-cfc17192-5dd0-4385-a595-0fc9b8d7642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512098144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2512098144
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2785606364
Short name T382
Test name
Test status
Simulation time 6629919384 ps
CPU time 74.23 seconds
Started Mar 26 01:18:43 PM PDT 24
Finished Mar 26 01:19:57 PM PDT 24
Peak memory 375344 kb
Host smart-ec1468bb-ce1e-43f3-b789-b512a28c5fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785606364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2785606364
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3224929486
Short name T881
Test name
Test status
Simulation time 9670333438 ps
CPU time 4.89 seconds
Started Mar 26 01:18:34 PM PDT 24
Finished Mar 26 01:18:39 PM PDT 24
Peak memory 204260 kb
Host smart-a23141aa-8522-4f7d-bc9a-5eda30dd630a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224929486 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3224929486
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.527360962
Short name T741
Test name
Test status
Simulation time 10092320874 ps
CPU time 74.73 seconds
Started Mar 26 01:18:39 PM PDT 24
Finished Mar 26 01:19:54 PM PDT 24
Peak memory 593944 kb
Host smart-46743669-5b15-41f8-9bf1-be0a5498b6b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527360962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.527360962
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1153624955
Short name T737
Test name
Test status
Simulation time 10064373241 ps
CPU time 35.4 seconds
Started Mar 26 01:18:34 PM PDT 24
Finished Mar 26 01:19:10 PM PDT 24
Peak memory 431820 kb
Host smart-612bbfb9-df32-473c-9c38-8b48ac02084e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153624955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1153624955
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1697459968
Short name T103
Test name
Test status
Simulation time 317679978 ps
CPU time 2.16 seconds
Started Mar 26 01:18:36 PM PDT 24
Finished Mar 26 01:18:38 PM PDT 24
Peak memory 204172 kb
Host smart-cd5fec9a-c38b-4527-b7d1-d5f93b0dd704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697459968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1697459968
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1973165724
Short name T749
Test name
Test status
Simulation time 872751851 ps
CPU time 4.56 seconds
Started Mar 26 01:18:44 PM PDT 24
Finished Mar 26 01:18:49 PM PDT 24
Peak memory 207088 kb
Host smart-b635f3a7-149a-4123-b87a-c075b808ad28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973165724 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1973165724
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.655224666
Short name T896
Test name
Test status
Simulation time 975448247 ps
CPU time 37.16 seconds
Started Mar 26 01:18:38 PM PDT 24
Finished Mar 26 01:19:16 PM PDT 24
Peak memory 204384 kb
Host smart-3cb4841b-e6ee-4c52-a02c-5ab389f789c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655224666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.655224666
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.1905218982
Short name T432
Test name
Test status
Simulation time 1751648863 ps
CPU time 26.89 seconds
Started Mar 26 01:18:38 PM PDT 24
Finished Mar 26 01:19:06 PM PDT 24
Peak memory 238188 kb
Host smart-56b37ccc-dd5a-4ab7-90e7-13e7820e2bfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905218982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.1905218982
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1067993004
Short name T408
Test name
Test status
Simulation time 27223195657 ps
CPU time 245.35 seconds
Started Mar 26 01:18:37 PM PDT 24
Finished Mar 26 01:22:42 PM PDT 24
Peak memory 937576 kb
Host smart-7c29930a-43fb-48a2-9922-9cda0f2a6f47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067993004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1067993004
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1472957820
Short name T301
Test name
Test status
Simulation time 5344931603 ps
CPU time 7.29 seconds
Started Mar 26 01:18:34 PM PDT 24
Finished Mar 26 01:18:42 PM PDT 24
Peak memory 220368 kb
Host smart-89bad4fa-969e-4b3f-b95b-b4fc79845357
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472957820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1472957820
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3607356609
Short name T629
Test name
Test status
Simulation time 34083784 ps
CPU time 0.66 seconds
Started Mar 26 01:18:52 PM PDT 24
Finished Mar 26 01:18:55 PM PDT 24
Peak memory 203816 kb
Host smart-a6b15bce-34a0-44d0-93d5-7b6c5c5e8b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607356609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3607356609
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.301230958
Short name T719
Test name
Test status
Simulation time 43504176 ps
CPU time 1.26 seconds
Started Mar 26 01:18:45 PM PDT 24
Finished Mar 26 01:18:46 PM PDT 24
Peak memory 215756 kb
Host smart-343a588f-4a8b-4812-a76b-eadb77c03e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301230958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.301230958
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1154928902
Short name T355
Test name
Test status
Simulation time 779404303 ps
CPU time 27.08 seconds
Started Mar 26 01:18:44 PM PDT 24
Finished Mar 26 01:19:11 PM PDT 24
Peak memory 320260 kb
Host smart-3bbaef12-bbc9-4a52-bc8d-5b1b4d689fef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154928902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1154928902
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3580197335
Short name T729
Test name
Test status
Simulation time 2459775416 ps
CPU time 72.91 seconds
Started Mar 26 01:18:45 PM PDT 24
Finished Mar 26 01:19:58 PM PDT 24
Peak memory 709428 kb
Host smart-bb166b2f-8594-44bd-8a2d-340c5da1036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580197335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3580197335
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2397970049
Short name T921
Test name
Test status
Simulation time 4511222331 ps
CPU time 76.36 seconds
Started Mar 26 01:18:34 PM PDT 24
Finished Mar 26 01:19:50 PM PDT 24
Peak memory 703156 kb
Host smart-7f28e71a-8260-4630-b3b4-8d87f2ecd70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397970049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2397970049
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2587152150
Short name T802
Test name
Test status
Simulation time 551119408 ps
CPU time 1.23 seconds
Started Mar 26 01:18:43 PM PDT 24
Finished Mar 26 01:18:45 PM PDT 24
Peak memory 204096 kb
Host smart-cde41214-4165-4d33-b058-ad0ed7fa2620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587152150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2587152150
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2198540594
Short name T642
Test name
Test status
Simulation time 115351659 ps
CPU time 2.93 seconds
Started Mar 26 01:18:44 PM PDT 24
Finished Mar 26 01:18:47 PM PDT 24
Peak memory 204060 kb
Host smart-ffe51537-0ec3-4f41-aea7-94cac2e6ac18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198540594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2198540594
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1161580150
Short name T612
Test name
Test status
Simulation time 3884698611 ps
CPU time 267.32 seconds
Started Mar 26 01:18:42 PM PDT 24
Finished Mar 26 01:23:10 PM PDT 24
Peak memory 1057576 kb
Host smart-2252e433-3c74-41ba-9849-7b6dac80513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161580150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1161580150
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_override.1056330259
Short name T732
Test name
Test status
Simulation time 16962710 ps
CPU time 0.65 seconds
Started Mar 26 01:18:35 PM PDT 24
Finished Mar 26 01:18:36 PM PDT 24
Peak memory 203816 kb
Host smart-794d81c7-4fe9-4e00-b451-3a3c6eabc7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056330259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1056330259
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1202829488
Short name T2
Test name
Test status
Simulation time 1589880231 ps
CPU time 20.55 seconds
Started Mar 26 01:18:45 PM PDT 24
Finished Mar 26 01:19:06 PM PDT 24
Peak memory 204000 kb
Host smart-f51aab96-579e-4bd3-b98e-a5622fe77351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202829488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1202829488
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2575678374
Short name T898
Test name
Test status
Simulation time 1265566972 ps
CPU time 55.28 seconds
Started Mar 26 01:18:35 PM PDT 24
Finished Mar 26 01:19:30 PM PDT 24
Peak memory 248908 kb
Host smart-f8a7cd47-e7d9-4023-b614-3d3cc519f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575678374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2575678374
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3471551200
Short name T1035
Test name
Test status
Simulation time 2713327583 ps
CPU time 2.73 seconds
Started Mar 26 01:18:53 PM PDT 24
Finished Mar 26 01:18:57 PM PDT 24
Peak memory 204280 kb
Host smart-6054826a-336b-4b3c-a61a-4bcca5fee26f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471551200 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3471551200
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2911699095
Short name T350
Test name
Test status
Simulation time 10162517401 ps
CPU time 8.1 seconds
Started Mar 26 01:18:50 PM PDT 24
Finished Mar 26 01:18:58 PM PDT 24
Peak memory 255648 kb
Host smart-437905b5-0f0b-4619-ae14-89025c7a14ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911699095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2911699095
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.980897273
Short name T634
Test name
Test status
Simulation time 10522517893 ps
CPU time 18.31 seconds
Started Mar 26 01:18:52 PM PDT 24
Finished Mar 26 01:19:10 PM PDT 24
Peak memory 350864 kb
Host smart-ea976b6b-0e85-4681-a776-96b91ab8f459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980897273 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.980897273
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.865652733
Short name T270
Test name
Test status
Simulation time 289272460 ps
CPU time 2 seconds
Started Mar 26 01:18:51 PM PDT 24
Finished Mar 26 01:18:53 PM PDT 24
Peak memory 204076 kb
Host smart-a5cac4f5-ddf3-4414-ada7-bb848d1ba51a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865652733 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.i2c_target_hrst.865652733
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1850577515
Short name T276
Test name
Test status
Simulation time 3253642361 ps
CPU time 3.61 seconds
Started Mar 26 01:18:54 PM PDT 24
Finished Mar 26 01:18:59 PM PDT 24
Peak memory 204228 kb
Host smart-4fb3354f-96b3-4851-8c00-9e4dc2fc88b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850577515 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1850577515
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3963320976
Short name T910
Test name
Test status
Simulation time 5050610393 ps
CPU time 16.1 seconds
Started Mar 26 01:18:33 PM PDT 24
Finished Mar 26 01:18:50 PM PDT 24
Peak memory 204244 kb
Host smart-eeb0dc81-f6c2-4e43-adf0-159196a8aa80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963320976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3963320976
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3366256076
Short name T319
Test name
Test status
Simulation time 4383090980 ps
CPU time 37.88 seconds
Started Mar 26 01:18:51 PM PDT 24
Finished Mar 26 01:19:29 PM PDT 24
Peak memory 205616 kb
Host smart-e547c8f9-69e1-4834-87f6-3c0c537012d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366256076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3366256076
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.3386220561
Short name T1040
Test name
Test status
Simulation time 21846196866 ps
CPU time 138.2 seconds
Started Mar 26 01:18:51 PM PDT 24
Finished Mar 26 01:21:09 PM PDT 24
Peak memory 1301760 kb
Host smart-f3838a36-89f7-44e5-83d7-9924f3060873
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386220561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.3386220561
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2785167970
Short name T92
Test name
Test status
Simulation time 1211446216 ps
CPU time 6.66 seconds
Started Mar 26 01:18:57 PM PDT 24
Finished Mar 26 01:19:04 PM PDT 24
Peak memory 217732 kb
Host smart-74bc3248-d3f2-456c-9abc-24030dcff04b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785167970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2785167970
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3534723223
Short name T369
Test name
Test status
Simulation time 19907771 ps
CPU time 0.61 seconds
Started Mar 26 01:19:04 PM PDT 24
Finished Mar 26 01:19:05 PM PDT 24
Peak memory 203724 kb
Host smart-fdd30057-8fff-4342-8406-56f566d67d51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534723223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3534723223
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2201262892
Short name T49
Test name
Test status
Simulation time 133364244 ps
CPU time 1.43 seconds
Started Mar 26 01:18:53 PM PDT 24
Finished Mar 26 01:18:55 PM PDT 24
Peak memory 212320 kb
Host smart-c473a884-7045-4348-b46c-11dd2ecced2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201262892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2201262892
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3470471058
Short name T655
Test name
Test status
Simulation time 408222916 ps
CPU time 7.65 seconds
Started Mar 26 01:18:50 PM PDT 24
Finished Mar 26 01:18:58 PM PDT 24
Peak memory 277724 kb
Host smart-67d066ee-6422-4654-917c-2954c2cbc67e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470471058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3470471058
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1286302139
Short name T852
Test name
Test status
Simulation time 7633667482 ps
CPU time 58.69 seconds
Started Mar 26 01:18:52 PM PDT 24
Finished Mar 26 01:19:50 PM PDT 24
Peak memory 681196 kb
Host smart-ad290e06-c3a1-4990-9ba6-9a630d231521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286302139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1286302139
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.1707319343
Short name T691
Test name
Test status
Simulation time 1681755585 ps
CPU time 120.46 seconds
Started Mar 26 01:18:52 PM PDT 24
Finished Mar 26 01:20:52 PM PDT 24
Peak memory 613324 kb
Host smart-897a4ae1-1437-4134-83b6-ee131fb9dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707319343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1707319343
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.181650945
Short name T219
Test name
Test status
Simulation time 130889086 ps
CPU time 0.94 seconds
Started Mar 26 01:18:53 PM PDT 24
Finished Mar 26 01:18:56 PM PDT 24
Peak memory 204076 kb
Host smart-33eb8e60-a993-4037-8377-f55dcb5673c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181650945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fm
t.181650945
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1782337361
Short name T120
Test name
Test status
Simulation time 355409748 ps
CPU time 9.99 seconds
Started Mar 26 01:18:54 PM PDT 24
Finished Mar 26 01:19:05 PM PDT 24
Peak memory 237812 kb
Host smart-951f13c0-f301-445f-9067-0fb1f74d71ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782337361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1782337361
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2291832999
Short name T177
Test name
Test status
Simulation time 16886064578 ps
CPU time 100.62 seconds
Started Mar 26 01:18:50 PM PDT 24
Finished Mar 26 01:20:31 PM PDT 24
Peak memory 1188312 kb
Host smart-5cab1034-d444-4f7a-9ce9-87b0b4ce336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291832999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2291832999
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_override.1638493537
Short name T1083
Test name
Test status
Simulation time 19901736 ps
CPU time 0.65 seconds
Started Mar 26 01:18:54 PM PDT 24
Finished Mar 26 01:18:56 PM PDT 24
Peak memory 203796 kb
Host smart-9815e4c3-1c66-462a-83d9-6db940adc693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638493537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1638493537
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.488140068
Short name T942
Test name
Test status
Simulation time 9065454844 ps
CPU time 863.69 seconds
Started Mar 26 01:18:50 PM PDT 24
Finished Mar 26 01:33:14 PM PDT 24
Peak memory 509068 kb
Host smart-8088cf8c-e4fe-4526-97fc-f664ec3b2ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488140068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.488140068
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1736987116
Short name T497
Test name
Test status
Simulation time 3250390629 ps
CPU time 75.21 seconds
Started Mar 26 01:18:54 PM PDT 24
Finished Mar 26 01:20:10 PM PDT 24
Peak memory 345296 kb
Host smart-56363015-57a8-4fb0-8e78-29a42d29ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736987116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1736987116
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.50613095
Short name T772
Test name
Test status
Simulation time 444719816 ps
CPU time 2.36 seconds
Started Mar 26 01:18:57 PM PDT 24
Finished Mar 26 01:19:01 PM PDT 24
Peak memory 204196 kb
Host smart-d5690e9c-b973-4487-a219-29866894b1db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50613095 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_bad_addr.50613095
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3101193778
Short name T989
Test name
Test status
Simulation time 10246346068 ps
CPU time 14.61 seconds
Started Mar 26 01:18:52 PM PDT 24
Finished Mar 26 01:19:09 PM PDT 24
Peak memory 299680 kb
Host smart-a46ccb3a-0798-43fe-b2d4-865842f0b417
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101193778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3101193778
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.4242130199
Short name T914
Test name
Test status
Simulation time 10103599268 ps
CPU time 14.74 seconds
Started Mar 26 01:18:53 PM PDT 24
Finished Mar 26 01:19:10 PM PDT 24
Peak memory 336496 kb
Host smart-b2ee9377-100a-4bb4-b3e5-4a2d49bc8fd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242130199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.4242130199
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2118602966
Short name T725
Test name
Test status
Simulation time 327270951 ps
CPU time 2.22 seconds
Started Mar 26 01:18:56 PM PDT 24
Finished Mar 26 01:18:59 PM PDT 24
Peak memory 204196 kb
Host smart-a2f8c6f0-dc6e-49dd-a565-44398e550030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118602966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2118602966
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2109314756
Short name T452
Test name
Test status
Simulation time 3924206350 ps
CPU time 3.22 seconds
Started Mar 26 01:18:51 PM PDT 24
Finished Mar 26 01:18:55 PM PDT 24
Peak memory 204288 kb
Host smart-14ecac75-c1b1-4578-bff9-1eb1f8e038bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109314756 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2109314756
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.888510043
Short name T313
Test name
Test status
Simulation time 4340386479 ps
CPU time 49 seconds
Started Mar 26 01:18:53 PM PDT 24
Finished Mar 26 01:19:44 PM PDT 24
Peak memory 204288 kb
Host smart-452d65e9-1522-4129-8e6e-fd4730f20853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888510043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_tar
get_smoke.888510043
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1788811906
Short name T611
Test name
Test status
Simulation time 854327929 ps
CPU time 36 seconds
Started Mar 26 01:18:50 PM PDT 24
Finished Mar 26 01:19:26 PM PDT 24
Peak memory 204076 kb
Host smart-8fd2398e-05f3-4122-b426-05d47de5ebb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788811906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1788811906
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3931701550
Short name T931
Test name
Test status
Simulation time 12773678695 ps
CPU time 26.1 seconds
Started Mar 26 01:18:53 PM PDT 24
Finished Mar 26 01:19:21 PM PDT 24
Peak memory 204192 kb
Host smart-562ef8b9-89b6-45e0-82df-4ab95f6c2538
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931701550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3931701550
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.211578198
Short name T996
Test name
Test status
Simulation time 29360877120 ps
CPU time 441.68 seconds
Started Mar 26 01:18:51 PM PDT 24
Finished Mar 26 01:26:13 PM PDT 24
Peak memory 1389164 kb
Host smart-f62275d0-8234-441e-91dd-27a25c122507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211578198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.211578198
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1158150395
Short name T889
Test name
Test status
Simulation time 3033755314 ps
CPU time 6.62 seconds
Started Mar 26 01:18:52 PM PDT 24
Finished Mar 26 01:19:01 PM PDT 24
Peak memory 212548 kb
Host smart-baa62f01-95b6-4be5-9a58-f1cd593d6f6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158150395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1158150395
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2765390127
Short name T500
Test name
Test status
Simulation time 15466307 ps
CPU time 0.6 seconds
Started Mar 26 01:18:58 PM PDT 24
Finished Mar 26 01:19:00 PM PDT 24
Peak memory 203728 kb
Host smart-35e68187-280b-4514-8033-3666b0c3e689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765390127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2765390127
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2327331973
Short name T752
Test name
Test status
Simulation time 373880022 ps
CPU time 1.43 seconds
Started Mar 26 01:18:57 PM PDT 24
Finished Mar 26 01:18:59 PM PDT 24
Peak memory 212404 kb
Host smart-e94e8402-20f4-4261-9318-32b8e4f4c370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327331973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2327331973
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3477119120
Short name T807
Test name
Test status
Simulation time 1089587099 ps
CPU time 14.24 seconds
Started Mar 26 01:18:57 PM PDT 24
Finished Mar 26 01:19:13 PM PDT 24
Peak memory 260896 kb
Host smart-a873cb73-de24-4f7b-b2a6-c8e12992e6d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477119120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3477119120
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2270088079
Short name T357
Test name
Test status
Simulation time 3251063496 ps
CPU time 37.51 seconds
Started Mar 26 01:18:59 PM PDT 24
Finished Mar 26 01:19:37 PM PDT 24
Peak memory 324920 kb
Host smart-8255a4bc-5374-433e-b6bb-863c25ce4eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270088079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2270088079
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.781994241
Short name T779
Test name
Test status
Simulation time 1410579133 ps
CPU time 39.49 seconds
Started Mar 26 01:18:59 PM PDT 24
Finished Mar 26 01:19:39 PM PDT 24
Peak memory 547120 kb
Host smart-dd861e54-2863-44a0-9ce1-95f2c615760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781994241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.781994241
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2144879040
Short name T286
Test name
Test status
Simulation time 692357475 ps
CPU time 0.86 seconds
Started Mar 26 01:18:56 PM PDT 24
Finished Mar 26 01:18:58 PM PDT 24
Peak memory 203840 kb
Host smart-6e74b6d9-6111-41da-a347-ab6842a4af79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144879040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2144879040
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1081417682
Short name T586
Test name
Test status
Simulation time 1070082509 ps
CPU time 8.16 seconds
Started Mar 26 01:18:57 PM PDT 24
Finished Mar 26 01:19:06 PM PDT 24
Peak memory 204028 kb
Host smart-5e1962b9-8331-4b41-97d6-3032b6403a47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081417682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1081417682
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2428429437
Short name T854
Test name
Test status
Simulation time 15049110954 ps
CPU time 58.85 seconds
Started Mar 26 01:18:58 PM PDT 24
Finished Mar 26 01:19:58 PM PDT 24
Peak memory 853672 kb
Host smart-dbd6dfaf-f120-4c07-bc6e-18161ef237e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428429437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2428429437
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_override.2807299970
Short name T207
Test name
Test status
Simulation time 22793448 ps
CPU time 0.65 seconds
Started Mar 26 01:19:01 PM PDT 24
Finished Mar 26 01:19:03 PM PDT 24
Peak memory 203784 kb
Host smart-2ed79b74-e164-49f0-9b6a-ddb8e74b7075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807299970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2807299970
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.4041548627
Short name T789
Test name
Test status
Simulation time 12633138706 ps
CPU time 343.85 seconds
Started Mar 26 01:18:59 PM PDT 24
Finished Mar 26 01:24:43 PM PDT 24
Peak memory 588336 kb
Host smart-c9f30605-622a-42d7-853c-260ede10f204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041548627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.4041548627
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3784673643
Short name T608
Test name
Test status
Simulation time 3631138563 ps
CPU time 63.17 seconds
Started Mar 26 01:19:03 PM PDT 24
Finished Mar 26 01:20:07 PM PDT 24
Peak memory 321308 kb
Host smart-93b53fc6-c07a-40a3-bf9b-de9ae9be2fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784673643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3784673643
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1849981708
Short name T649
Test name
Test status
Simulation time 4031797172 ps
CPU time 4.8 seconds
Started Mar 26 01:18:58 PM PDT 24
Finished Mar 26 01:19:04 PM PDT 24
Peak memory 212456 kb
Host smart-729fc165-663e-4072-bb30-42bf359483cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849981708 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1849981708
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3629967780
Short name T253
Test name
Test status
Simulation time 10434910534 ps
CPU time 7.16 seconds
Started Mar 26 01:18:59 PM PDT 24
Finished Mar 26 01:19:06 PM PDT 24
Peak memory 249428 kb
Host smart-ee27d3c3-083e-40d0-b833-ac1526ec53bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629967780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3629967780
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1615007038
Short name T72
Test name
Test status
Simulation time 10261525581 ps
CPU time 9.91 seconds
Started Mar 26 01:19:01 PM PDT 24
Finished Mar 26 01:19:12 PM PDT 24
Peak memory 304556 kb
Host smart-2b882bcb-866b-40c2-add5-0c9894d2e4a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615007038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1615007038
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.4050995447
Short name T605
Test name
Test status
Simulation time 430125906 ps
CPU time 2.37 seconds
Started Mar 26 01:18:56 PM PDT 24
Finished Mar 26 01:18:59 PM PDT 24
Peak memory 204196 kb
Host smart-3e4d8563-26a9-466b-9467-fea5e206f22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050995447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.4050995447
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3557635158
Short name T339
Test name
Test status
Simulation time 1812110198 ps
CPU time 5.04 seconds
Started Mar 26 01:18:59 PM PDT 24
Finished Mar 26 01:19:05 PM PDT 24
Peak memory 204112 kb
Host smart-56d82eb5-8ea9-4e65-98c2-834be488ba52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557635158 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3557635158
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2001055225
Short name T1010
Test name
Test status
Simulation time 690386562 ps
CPU time 10.96 seconds
Started Mar 26 01:19:00 PM PDT 24
Finished Mar 26 01:19:12 PM PDT 24
Peak memory 204068 kb
Host smart-12cf6bb6-e697-488e-9924-3ce18f4dd07d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001055225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2001055225
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.642735615
Short name T962
Test name
Test status
Simulation time 224849170 ps
CPU time 8.6 seconds
Started Mar 26 01:19:00 PM PDT 24
Finished Mar 26 01:19:09 PM PDT 24
Peak memory 204144 kb
Host smart-af9e28e8-9330-4f4b-9176-04983d19f46e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642735615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.642735615
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3264374837
Short name T690
Test name
Test status
Simulation time 16892946375 ps
CPU time 53.57 seconds
Started Mar 26 01:18:58 PM PDT 24
Finished Mar 26 01:19:53 PM PDT 24
Peak memory 338124 kb
Host smart-30361b88-9547-46f7-b891-46107a7b27fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264374837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3264374837
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1502083422
Short name T1100
Test name
Test status
Simulation time 4248141307 ps
CPU time 6.55 seconds
Started Mar 26 01:19:01 PM PDT 24
Finished Mar 26 01:19:09 PM PDT 24
Peak memory 212556 kb
Host smart-a18b7ee0-7179-4bb6-9243-069adcffef0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502083422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1502083422
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1127440041
Short name T317
Test name
Test status
Simulation time 20086033 ps
CPU time 0.62 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:19:20 PM PDT 24
Peak memory 203724 kb
Host smart-0c9bb321-b101-48c7-96e9-e158c4fe8ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127440041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1127440041
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3177844260
Short name T524
Test name
Test status
Simulation time 35941478 ps
CPU time 1.26 seconds
Started Mar 26 01:19:00 PM PDT 24
Finished Mar 26 01:19:02 PM PDT 24
Peak memory 212272 kb
Host smart-72c2d6d7-293c-480e-91c0-3a4c38f3938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177844260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3177844260
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3190087494
Short name T552
Test name
Test status
Simulation time 229015391 ps
CPU time 11.64 seconds
Started Mar 26 01:19:02 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 250552 kb
Host smart-dcc24b2c-965d-4e99-81e4-90e99d514477
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190087494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3190087494
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.508027648
Short name T1038
Test name
Test status
Simulation time 2244260325 ps
CPU time 69.24 seconds
Started Mar 26 01:19:00 PM PDT 24
Finished Mar 26 01:20:10 PM PDT 24
Peak memory 757252 kb
Host smart-62a833e5-c200-4066-9d05-56d8acca055e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508027648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.508027648
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1403262708
Short name T468
Test name
Test status
Simulation time 13304462966 ps
CPU time 131.01 seconds
Started Mar 26 01:18:57 PM PDT 24
Finished Mar 26 01:21:09 PM PDT 24
Peak memory 589748 kb
Host smart-e7381ca5-9d55-4be7-98dd-f2a0cb1de6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403262708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1403262708
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1965628348
Short name T895
Test name
Test status
Simulation time 380797861 ps
CPU time 0.9 seconds
Started Mar 26 01:19:02 PM PDT 24
Finished Mar 26 01:19:03 PM PDT 24
Peak memory 203928 kb
Host smart-07b78e63-454a-4267-9c0f-fc3789d68e21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965628348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1965628348
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2356041473
Short name T385
Test name
Test status
Simulation time 339450754 ps
CPU time 4.74 seconds
Started Mar 26 01:19:01 PM PDT 24
Finished Mar 26 01:19:07 PM PDT 24
Peak memory 233536 kb
Host smart-42704684-1f33-4fea-b29b-7f53def40824
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356041473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2356041473
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1090255207
Short name T591
Test name
Test status
Simulation time 4226491756 ps
CPU time 309.8 seconds
Started Mar 26 01:18:57 PM PDT 24
Finished Mar 26 01:24:09 PM PDT 24
Peak memory 1185160 kb
Host smart-ac07bd51-e7d9-44cb-ba2d-1fd856fd20fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090255207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1090255207
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_override.149225532
Short name T200
Test name
Test status
Simulation time 18989092 ps
CPU time 0.62 seconds
Started Mar 26 01:18:58 PM PDT 24
Finished Mar 26 01:18:59 PM PDT 24
Peak memory 203884 kb
Host smart-7ee4ada4-6484-4c20-8bac-fe4984abba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149225532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.149225532
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2663714470
Short name T482
Test name
Test status
Simulation time 12241502934 ps
CPU time 2227.43 seconds
Started Mar 26 01:18:59 PM PDT 24
Finished Mar 26 01:56:07 PM PDT 24
Peak memory 1357660 kb
Host smart-0fc40359-614b-463a-847d-07ada5a28c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663714470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2663714470
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.352220067
Short name T751
Test name
Test status
Simulation time 1595844308 ps
CPU time 67.85 seconds
Started Mar 26 01:19:01 PM PDT 24
Finished Mar 26 01:20:10 PM PDT 24
Peak memory 342292 kb
Host smart-27556f54-396c-4157-9030-3b35b2ac3d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352220067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.352220067
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3286688199
Short name T1050
Test name
Test status
Simulation time 692608426 ps
CPU time 3.54 seconds
Started Mar 26 01:19:11 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 204204 kb
Host smart-ade0685c-0c0b-4dcf-8f5e-64f2180827e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286688199 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3286688199
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2382659895
Short name T1075
Test name
Test status
Simulation time 10069054505 ps
CPU time 103.4 seconds
Started Mar 26 01:19:11 PM PDT 24
Finished Mar 26 01:20:54 PM PDT 24
Peak memory 620220 kb
Host smart-3a2df984-211f-4ec4-8c32-d89d9a7a1c0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382659895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2382659895
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.757041672
Short name T1104
Test name
Test status
Simulation time 10292137455 ps
CPU time 15.81 seconds
Started Mar 26 01:19:07 PM PDT 24
Finished Mar 26 01:19:24 PM PDT 24
Peak memory 310472 kb
Host smart-a077e8b7-7943-4538-82f2-aaf6f9abae6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757041672 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.757041672
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.123727780
Short name T880
Test name
Test status
Simulation time 476256814 ps
CPU time 2.91 seconds
Started Mar 26 01:19:11 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 204112 kb
Host smart-a10d70be-202a-4d58-815e-b94c8113ec83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123727780 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.123727780
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3365188132
Short name T376
Test name
Test status
Simulation time 804241827 ps
CPU time 4.39 seconds
Started Mar 26 01:19:08 PM PDT 24
Finished Mar 26 01:19:13 PM PDT 24
Peak memory 204624 kb
Host smart-77468dea-f9c3-4cae-a1f3-8de2567631f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365188132 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3365188132
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2305383973
Short name T1072
Test name
Test status
Simulation time 1171092332 ps
CPU time 19.2 seconds
Started Mar 26 01:19:07 PM PDT 24
Finished Mar 26 01:19:27 PM PDT 24
Peak memory 204052 kb
Host smart-ee1f5717-1271-498d-a50b-fbc37a487e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305383973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2305383973
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1457376390
Short name T815
Test name
Test status
Simulation time 3129949786 ps
CPU time 3.97 seconds
Started Mar 26 01:19:10 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 204144 kb
Host smart-04104641-2847-4d5b-9ad2-39beb317271d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457376390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1457376390
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.114161726
Short name T551
Test name
Test status
Simulation time 27618862478 ps
CPU time 187.17 seconds
Started Mar 26 01:19:06 PM PDT 24
Finished Mar 26 01:22:14 PM PDT 24
Peak memory 1448660 kb
Host smart-aa9d2a0e-2c4c-465d-8c58-68db4fedee4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114161726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_t
arget_stretch.114161726
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2888811731
Short name T693
Test name
Test status
Simulation time 5059716483 ps
CPU time 6.19 seconds
Started Mar 26 01:19:09 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 204276 kb
Host smart-a9134a2e-7a64-4497-9910-28e7078d36ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888811731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2888811731
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1441543989
Short name T621
Test name
Test status
Simulation time 35945498 ps
CPU time 0.59 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:19:19 PM PDT 24
Peak memory 203852 kb
Host smart-7a793e1f-842a-4b02-8f6d-624f8e609659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441543989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1441543989
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3397386632
Short name T835
Test name
Test status
Simulation time 48915926 ps
CPU time 1.33 seconds
Started Mar 26 01:19:10 PM PDT 24
Finished Mar 26 01:19:11 PM PDT 24
Peak memory 212368 kb
Host smart-96d9aba3-b841-4635-a4dc-a1e63f657400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397386632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3397386632
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3205350967
Short name T846
Test name
Test status
Simulation time 1429163835 ps
CPU time 3.97 seconds
Started Mar 26 01:19:07 PM PDT 24
Finished Mar 26 01:19:12 PM PDT 24
Peak memory 204168 kb
Host smart-4166c616-280c-4189-807f-ff53ee676d0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205350967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3205350967
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.2090195282
Short name T768
Test name
Test status
Simulation time 17004958617 ps
CPU time 33.97 seconds
Started Mar 26 01:19:06 PM PDT 24
Finished Mar 26 01:19:41 PM PDT 24
Peak memory 501792 kb
Host smart-faca39d0-efac-4f8d-9cf9-b62f51669d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090195282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2090195282
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.944199037
Short name T613
Test name
Test status
Simulation time 6434470982 ps
CPU time 49.47 seconds
Started Mar 26 01:19:08 PM PDT 24
Finished Mar 26 01:19:58 PM PDT 24
Peak memory 563468 kb
Host smart-947d2f9b-0ac1-446f-a138-8863f846ac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944199037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.944199037
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1786313314
Short name T444
Test name
Test status
Simulation time 418944311 ps
CPU time 0.95 seconds
Started Mar 26 01:19:13 PM PDT 24
Finished Mar 26 01:19:14 PM PDT 24
Peak memory 203920 kb
Host smart-16d09266-b080-44f2-8a5d-d2a333c7be70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786313314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1786313314
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.781275904
Short name T87
Test name
Test status
Simulation time 578701468 ps
CPU time 4.33 seconds
Started Mar 26 01:19:10 PM PDT 24
Finished Mar 26 01:19:15 PM PDT 24
Peak memory 230216 kb
Host smart-3c8458f0-9e99-4747-a28c-ab476027f6fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781275904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
781275904
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.853505665
Short name T182
Test name
Test status
Simulation time 42346641091 ps
CPU time 91.82 seconds
Started Mar 26 01:19:16 PM PDT 24
Finished Mar 26 01:20:48 PM PDT 24
Peak memory 1154180 kb
Host smart-871f6d85-4a71-4a80-bdab-f9cfb6a91474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853505665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.853505665
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_override.275440373
Short name T793
Test name
Test status
Simulation time 78624183 ps
CPU time 0.66 seconds
Started Mar 26 01:19:17 PM PDT 24
Finished Mar 26 01:19:18 PM PDT 24
Peak memory 203728 kb
Host smart-580d3624-3271-43e1-a338-26ecd724028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275440373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.275440373
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1732342031
Short name T903
Test name
Test status
Simulation time 6397180771 ps
CPU time 335.94 seconds
Started Mar 26 01:19:07 PM PDT 24
Finished Mar 26 01:24:43 PM PDT 24
Peak memory 652712 kb
Host smart-6a0955f0-6d75-4ed8-a340-f593cfb67229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732342031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1732342031
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3376470303
Short name T196
Test name
Test status
Simulation time 5477680912 ps
CPU time 68.25 seconds
Started Mar 26 01:19:08 PM PDT 24
Finished Mar 26 01:20:16 PM PDT 24
Peak memory 351164 kb
Host smart-548ca9c3-48e9-4cdb-9856-ce4ace52962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376470303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3376470303
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.2508516113
Short name T63
Test name
Test status
Simulation time 34570462102 ps
CPU time 990.72 seconds
Started Mar 26 01:19:08 PM PDT 24
Finished Mar 26 01:35:39 PM PDT 24
Peak memory 1981248 kb
Host smart-524d0bc5-35e3-4c6a-8855-284c9d7aba15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508516113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.2508516113
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1882142346
Short name T843
Test name
Test status
Simulation time 893316752 ps
CPU time 4.32 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:19:24 PM PDT 24
Peak memory 204192 kb
Host smart-2686d10b-65d9-413f-abef-b3788f26f15d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882142346 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1882142346
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.152024078
Short name T467
Test name
Test status
Simulation time 10305243351 ps
CPU time 14.53 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:19:34 PM PDT 24
Peak memory 306200 kb
Host smart-8145abf7-5928-41cc-8c13-8a7e90c9c9e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152024078 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.152024078
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.782153302
Short name T69
Test name
Test status
Simulation time 10121131655 ps
CPU time 105.52 seconds
Started Mar 26 01:19:20 PM PDT 24
Finished Mar 26 01:21:05 PM PDT 24
Peak memory 736816 kb
Host smart-31744b08-325a-4509-8e75-38ae16a2b7ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782153302 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.782153302
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1678239671
Short name T269
Test name
Test status
Simulation time 534494100 ps
CPU time 3.08 seconds
Started Mar 26 01:19:30 PM PDT 24
Finished Mar 26 01:19:33 PM PDT 24
Peak memory 204716 kb
Host smart-bacb33c4-1bf7-420b-8e98-be5816d055c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678239671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1678239671
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2694489812
Short name T307
Test name
Test status
Simulation time 3212745740 ps
CPU time 4.34 seconds
Started Mar 26 01:19:21 PM PDT 24
Finished Mar 26 01:19:26 PM PDT 24
Peak memory 204244 kb
Host smart-e3d44002-f731-41e5-aca6-d1a0bb0841ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694489812 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2694489812
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2197772264
Short name T848
Test name
Test status
Simulation time 4341260389 ps
CPU time 53.22 seconds
Started Mar 26 01:19:08 PM PDT 24
Finished Mar 26 01:20:01 PM PDT 24
Peak memory 204312 kb
Host smart-04636108-1da9-4495-be90-0720d8af2c75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197772264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2197772264
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1550018606
Short name T755
Test name
Test status
Simulation time 6059003758 ps
CPU time 23.11 seconds
Started Mar 26 01:19:07 PM PDT 24
Finished Mar 26 01:19:30 PM PDT 24
Peak memory 218884 kb
Host smart-db9d6f55-4e34-4c95-8d08-6b80ef1fa693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550018606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1550018606
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2779528518
Short name T822
Test name
Test status
Simulation time 2446705829 ps
CPU time 6.96 seconds
Started Mar 26 01:19:20 PM PDT 24
Finished Mar 26 01:19:27 PM PDT 24
Peak memory 215976 kb
Host smart-a8e14984-2a59-4403-b20b-038875ad9b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779528518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2779528518
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1303366794
Short name T268
Test name
Test status
Simulation time 26399779 ps
CPU time 0.62 seconds
Started Mar 26 01:19:32 PM PDT 24
Finished Mar 26 01:19:33 PM PDT 24
Peak memory 203824 kb
Host smart-770107ce-8e17-4337-b5d4-7ddc79ad2aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303366794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1303366794
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2172405876
Short name T644
Test name
Test status
Simulation time 116294069 ps
CPU time 1.7 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:19:21 PM PDT 24
Peak memory 212384 kb
Host smart-21f897e2-6e25-4d1b-8089-c6f1bf3a6370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172405876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2172405876
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3404103281
Short name T405
Test name
Test status
Simulation time 418968357 ps
CPU time 22.91 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:19:42 PM PDT 24
Peak memory 297188 kb
Host smart-e311500e-7c9f-433f-8b56-d7840851142a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404103281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3404103281
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.744405480
Short name T984
Test name
Test status
Simulation time 11509876544 ps
CPU time 130.22 seconds
Started Mar 26 01:19:20 PM PDT 24
Finished Mar 26 01:21:30 PM PDT 24
Peak memory 625224 kb
Host smart-0e0927af-d4c0-47ee-8814-db316ea3c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744405480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.744405480
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2553656670
Short name T123
Test name
Test status
Simulation time 1975726926 ps
CPU time 64.22 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:20:24 PM PDT 24
Peak memory 685276 kb
Host smart-356e6fe8-8f5f-4c80-9a77-c9cf525b83c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553656670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2553656670
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2595122536
Short name T38
Test name
Test status
Simulation time 683997409 ps
CPU time 1.09 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:19:20 PM PDT 24
Peak memory 203868 kb
Host smart-d7e1351b-bb7c-4acc-8b4b-ae3d2777372c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595122536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2595122536
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.4158807522
Short name T520
Test name
Test status
Simulation time 318560120 ps
CPU time 4.19 seconds
Started Mar 26 01:19:20 PM PDT 24
Finished Mar 26 01:19:24 PM PDT 24
Peak memory 233104 kb
Host smart-da126fa8-b08a-4081-8117-a1637ca79f32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158807522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.4158807522
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.951009126
Short name T727
Test name
Test status
Simulation time 48460949624 ps
CPU time 54.96 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:20:14 PM PDT 24
Peak memory 808808 kb
Host smart-57d70194-53ea-4926-a2cd-6bf077421fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951009126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.951009126
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_override.3058018124
Short name T833
Test name
Test status
Simulation time 30500468 ps
CPU time 0.63 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:19:19 PM PDT 24
Peak memory 203892 kb
Host smart-79afcc54-05e1-4c66-82f0-01bbf266f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058018124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3058018124
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.649183263
Short name T1032
Test name
Test status
Simulation time 7156066863 ps
CPU time 55 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:20:14 PM PDT 24
Peak memory 226028 kb
Host smart-a8efd29e-0825-47f3-8d46-f6f73235349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649183263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.649183263
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3636335955
Short name T362
Test name
Test status
Simulation time 1277056293 ps
CPU time 50.12 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:20:08 PM PDT 24
Peak memory 336688 kb
Host smart-508f78c3-f0d9-4f70-88db-e370f2524636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636335955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3636335955
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.838794732
Short name T399
Test name
Test status
Simulation time 904386364 ps
CPU time 2.66 seconds
Started Mar 26 01:19:36 PM PDT 24
Finished Mar 26 01:19:39 PM PDT 24
Peak memory 204044 kb
Host smart-5e9301f6-c2d9-4766-837d-a58933d33e5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838794732 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.838794732
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2470813443
Short name T96
Test name
Test status
Simulation time 10079496864 ps
CPU time 28.54 seconds
Started Mar 26 01:19:32 PM PDT 24
Finished Mar 26 01:20:01 PM PDT 24
Peak memory 376128 kb
Host smart-eb187ebf-ea66-4a6e-8d20-fff4e99e837c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470813443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2470813443
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3135596608
Short name T594
Test name
Test status
Simulation time 10139447615 ps
CPU time 60.77 seconds
Started Mar 26 01:19:33 PM PDT 24
Finished Mar 26 01:20:36 PM PDT 24
Peak memory 608436 kb
Host smart-c3bea09a-5873-4cfc-9224-7d876cef1e1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135596608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3135596608
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3954404272
Short name T1102
Test name
Test status
Simulation time 979799938 ps
CPU time 3.01 seconds
Started Mar 26 01:19:32 PM PDT 24
Finished Mar 26 01:19:35 PM PDT 24
Peak memory 204112 kb
Host smart-3c2ba989-2517-45ce-ac5e-9cee1ff28418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954404272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3954404272
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1395756296
Short name T448
Test name
Test status
Simulation time 6592030748 ps
CPU time 4.52 seconds
Started Mar 26 01:19:31 PM PDT 24
Finished Mar 26 01:19:37 PM PDT 24
Peak memory 204304 kb
Host smart-4c73e03c-3fa9-41a2-bef3-831c60a8952c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395756296 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1395756296
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2113716879
Short name T344
Test name
Test status
Simulation time 2986289927 ps
CPU time 2.75 seconds
Started Mar 26 01:19:30 PM PDT 24
Finished Mar 26 01:19:33 PM PDT 24
Peak memory 204188 kb
Host smart-eac6a54a-fc06-4b83-9246-81909764089c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113716879 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2113716879
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1818697251
Short name T873
Test name
Test status
Simulation time 2621191924 ps
CPU time 18.08 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:19:38 PM PDT 24
Peak memory 204312 kb
Host smart-47bd9129-a4e2-4f4a-9b7e-c3d479b4b175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818697251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1818697251
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2139082995
Short name T775
Test name
Test status
Simulation time 1542477849 ps
CPU time 12.83 seconds
Started Mar 26 01:19:18 PM PDT 24
Finished Mar 26 01:19:32 PM PDT 24
Peak memory 213364 kb
Host smart-273eeb60-9cc8-4803-9fe6-bee9faa6d731
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139082995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2139082995
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3582985335
Short name T353
Test name
Test status
Simulation time 12457234653 ps
CPU time 7.45 seconds
Started Mar 26 01:19:19 PM PDT 24
Finished Mar 26 01:19:27 PM PDT 24
Peak memory 204140 kb
Host smart-72faafc6-fdf1-4ecf-a497-1fb4a06b556a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582985335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3582985335
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1261780843
Short name T653
Test name
Test status
Simulation time 5343008202 ps
CPU time 20.61 seconds
Started Mar 26 01:19:35 PM PDT 24
Finished Mar 26 01:19:57 PM PDT 24
Peak memory 454168 kb
Host smart-6c0feab2-722b-478c-9df8-71784bc1b5c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261780843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1261780843
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1815062112
Short name T713
Test name
Test status
Simulation time 4749791839 ps
CPU time 6.28 seconds
Started Mar 26 01:19:33 PM PDT 24
Finished Mar 26 01:19:39 PM PDT 24
Peak memory 204236 kb
Host smart-b4d4d7d9-8b45-4143-aedb-272ecf91e042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815062112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1815062112
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3591334283
Short name T866
Test name
Test status
Simulation time 17814491 ps
CPU time 0.61 seconds
Started Mar 26 01:19:52 PM PDT 24
Finished Mar 26 01:19:53 PM PDT 24
Peak memory 203688 kb
Host smart-58c59d26-cd5b-4408-996e-6a61c164d923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591334283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3591334283
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2170901557
Short name T502
Test name
Test status
Simulation time 327774495 ps
CPU time 1.26 seconds
Started Mar 26 01:19:36 PM PDT 24
Finished Mar 26 01:19:38 PM PDT 24
Peak memory 212300 kb
Host smart-09f3943a-9ab7-47df-8f87-8a2557f269d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170901557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2170901557
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3682017691
Short name T560
Test name
Test status
Simulation time 630757183 ps
CPU time 16.18 seconds
Started Mar 26 01:19:29 PM PDT 24
Finished Mar 26 01:19:46 PM PDT 24
Peak memory 268308 kb
Host smart-63156b35-e863-44b6-ac25-76f60c6a2454
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682017691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3682017691
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2141303447
Short name T99
Test name
Test status
Simulation time 2961894840 ps
CPU time 31.4 seconds
Started Mar 26 01:19:32 PM PDT 24
Finished Mar 26 01:20:04 PM PDT 24
Peak memory 415516 kb
Host smart-79c79bb3-d7fe-4e12-ad10-763c58fb531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141303447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2141303447
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2931889315
Short name T954
Test name
Test status
Simulation time 21178914011 ps
CPU time 75.88 seconds
Started Mar 26 01:19:29 PM PDT 24
Finished Mar 26 01:20:46 PM PDT 24
Peak memory 786888 kb
Host smart-eef35eef-8435-4d89-82b7-d735d7a55591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931889315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2931889315
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3196783705
Short name T782
Test name
Test status
Simulation time 232367317 ps
CPU time 0.84 seconds
Started Mar 26 01:19:30 PM PDT 24
Finished Mar 26 01:19:31 PM PDT 24
Peak memory 203832 kb
Host smart-da58dc5a-8fae-4660-9f4d-9c79c9176982
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196783705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3196783705
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2628668234
Short name T714
Test name
Test status
Simulation time 171010983 ps
CPU time 3.73 seconds
Started Mar 26 01:19:33 PM PDT 24
Finished Mar 26 01:19:38 PM PDT 24
Peak memory 204112 kb
Host smart-c897da75-95a7-4e02-b0b9-f910037b6ce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628668234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2628668234
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2131144769
Short name T897
Test name
Test status
Simulation time 4602581397 ps
CPU time 54.55 seconds
Started Mar 26 01:19:32 PM PDT 24
Finished Mar 26 01:20:27 PM PDT 24
Peak memory 696796 kb
Host smart-85316a75-12cb-448f-8454-36b8755002f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131144769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2131144769
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_override.1916825297
Short name T577
Test name
Test status
Simulation time 26541922 ps
CPU time 0.65 seconds
Started Mar 26 01:19:31 PM PDT 24
Finished Mar 26 01:19:33 PM PDT 24
Peak memory 203768 kb
Host smart-d1ec0c2f-6b98-4eb0-874d-501aab58acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916825297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1916825297
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3581327222
Short name T41
Test name
Test status
Simulation time 28895843233 ps
CPU time 96.46 seconds
Started Mar 26 01:19:30 PM PDT 24
Finished Mar 26 01:21:07 PM PDT 24
Peak memory 275380 kb
Host smart-d64e0e13-17c4-4853-8c13-9e8e4dd68e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581327222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3581327222
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2091495356
Short name T450
Test name
Test status
Simulation time 4938518680 ps
CPU time 124.02 seconds
Started Mar 26 01:19:36 PM PDT 24
Finished Mar 26 01:21:40 PM PDT 24
Peak memory 307360 kb
Host smart-377ef890-f87a-4ffe-a693-1ce4bbf4ed9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091495356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2091495356
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.276725860
Short name T274
Test name
Test status
Simulation time 811480528 ps
CPU time 4.02 seconds
Started Mar 26 01:19:49 PM PDT 24
Finished Mar 26 01:19:53 PM PDT 24
Peak memory 204088 kb
Host smart-1fa5ebf2-9d11-403b-b59e-26358618edc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276725860 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.276725860
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3439808774
Short name T797
Test name
Test status
Simulation time 10042382008 ps
CPU time 80.39 seconds
Started Mar 26 01:19:50 PM PDT 24
Finished Mar 26 01:21:10 PM PDT 24
Peak memory 530660 kb
Host smart-4f440e86-890b-4f98-8a36-504ce8e35440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439808774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3439808774
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3705451461
Short name T282
Test name
Test status
Simulation time 10126264199 ps
CPU time 102.62 seconds
Started Mar 26 01:19:49 PM PDT 24
Finished Mar 26 01:21:32 PM PDT 24
Peak memory 731112 kb
Host smart-d7daf5e1-8771-4a65-a229-88225ed6dccd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705451461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3705451461
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.282249036
Short name T823
Test name
Test status
Simulation time 468587628 ps
CPU time 2.86 seconds
Started Mar 26 01:19:50 PM PDT 24
Finished Mar 26 01:19:53 PM PDT 24
Peak memory 204120 kb
Host smart-f7534c63-6d26-4892-95d7-e3218e5c6c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282249036 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.282249036
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.263681947
Short name T595
Test name
Test status
Simulation time 1227193325 ps
CPU time 6.24 seconds
Started Mar 26 01:19:32 PM PDT 24
Finished Mar 26 01:19:38 PM PDT 24
Peak memory 211192 kb
Host smart-9c6bd528-6395-4c11-8835-27c49312d76f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263681947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.263681947
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.4036834225
Short name T721
Test name
Test status
Simulation time 2405805369 ps
CPU time 7.42 seconds
Started Mar 26 01:19:30 PM PDT 24
Finished Mar 26 01:19:38 PM PDT 24
Peak memory 204424 kb
Host smart-e7049f2f-0b2f-47ee-8423-17102f5c7d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036834225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.4036834225
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1169907645
Short name T832
Test name
Test status
Simulation time 6135564893 ps
CPU time 67.97 seconds
Started Mar 26 01:19:36 PM PDT 24
Finished Mar 26 01:20:44 PM PDT 24
Peak memory 205924 kb
Host smart-7169c257-9539-4875-b935-c881c632ec88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169907645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1169907645
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2736393546
Short name T260
Test name
Test status
Simulation time 6514945744 ps
CPU time 12.79 seconds
Started Mar 26 01:19:37 PM PDT 24
Finished Mar 26 01:19:52 PM PDT 24
Peak memory 322308 kb
Host smart-4f322baf-36a5-4135-8fab-68b7a7e49338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736393546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2736393546
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2115278241
Short name T410
Test name
Test status
Simulation time 5361363188 ps
CPU time 6.78 seconds
Started Mar 26 01:19:28 PM PDT 24
Finished Mar 26 01:19:35 PM PDT 24
Peak memory 204272 kb
Host smart-e4fbdba5-2bf7-46c9-a429-722ef35ca1f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115278241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2115278241
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.307721018
Short name T486
Test name
Test status
Simulation time 17615477 ps
CPU time 0.64 seconds
Started Mar 26 01:13:04 PM PDT 24
Finished Mar 26 01:13:04 PM PDT 24
Peak memory 203704 kb
Host smart-3b43c4fa-c63f-49a0-90ef-cfb1f9f88d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307721018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.307721018
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.4085559340
Short name T318
Test name
Test status
Simulation time 84481464 ps
CPU time 1.31 seconds
Started Mar 26 01:12:47 PM PDT 24
Finished Mar 26 01:12:48 PM PDT 24
Peak memory 212424 kb
Host smart-6d0ab90c-ebb5-4b08-a048-608eac6363f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085559340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.4085559340
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.615332852
Short name T934
Test name
Test status
Simulation time 726472358 ps
CPU time 19.4 seconds
Started Mar 26 01:12:47 PM PDT 24
Finished Mar 26 01:13:07 PM PDT 24
Peak memory 277756 kb
Host smart-6df46d2a-f5d6-469e-bac6-60a27697d335
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615332852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.615332852
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2298063915
Short name T358
Test name
Test status
Simulation time 2453079898 ps
CPU time 175.07 seconds
Started Mar 26 01:12:49 PM PDT 24
Finished Mar 26 01:15:44 PM PDT 24
Peak memory 790016 kb
Host smart-915ba0b2-6c32-4efe-ac4f-d6de0d671cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298063915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2298063915
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.884626005
Short name T628
Test name
Test status
Simulation time 5665906737 ps
CPU time 99.9 seconds
Started Mar 26 01:12:48 PM PDT 24
Finished Mar 26 01:14:28 PM PDT 24
Peak memory 558068 kb
Host smart-def24629-f6eb-4bc6-8fcc-6be17a7b13ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884626005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.884626005
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2165556002
Short name T1086
Test name
Test status
Simulation time 196793621 ps
CPU time 0.91 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:12:55 PM PDT 24
Peak memory 203864 kb
Host smart-7270f90c-b83f-4adc-9863-10d61fb178a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165556002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2165556002
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3103462519
Short name T821
Test name
Test status
Simulation time 399972250 ps
CPU time 3.01 seconds
Started Mar 26 01:12:43 PM PDT 24
Finished Mar 26 01:12:47 PM PDT 24
Peak memory 204016 kb
Host smart-ae96456f-ddc0-40ee-b1f5-661dc663f6f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103462519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3103462519
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2058234148
Short name T911
Test name
Test status
Simulation time 2265601047 ps
CPU time 138.81 seconds
Started Mar 26 01:12:44 PM PDT 24
Finished Mar 26 01:15:04 PM PDT 24
Peak memory 749764 kb
Host smart-3f4fa7ec-5241-4e3a-8a4d-20d128b50f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058234148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2058234148
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_override.649888207
Short name T683
Test name
Test status
Simulation time 16291072 ps
CPU time 0.62 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:12:55 PM PDT 24
Peak memory 203780 kb
Host smart-73195c09-e2dc-492e-87e4-4569543bbf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649888207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.649888207
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.662926398
Short name T998
Test name
Test status
Simulation time 25894112004 ps
CPU time 65.04 seconds
Started Mar 26 01:12:49 PM PDT 24
Finished Mar 26 01:13:54 PM PDT 24
Peak memory 231392 kb
Host smart-bbfc087f-8261-4cb3-a345-616fd1d77561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662926398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.662926398
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1095053301
Short name T851
Test name
Test status
Simulation time 2594391505 ps
CPU time 80.46 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:14:15 PM PDT 24
Peak memory 283820 kb
Host smart-11f10cd2-a8b7-45fe-b908-a4e669707b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095053301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1095053301
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.741239242
Short name T803
Test name
Test status
Simulation time 2565452492 ps
CPU time 3.07 seconds
Started Mar 26 01:12:56 PM PDT 24
Finished Mar 26 01:12:59 PM PDT 24
Peak memory 204224 kb
Host smart-aebb6c6b-c979-41a7-942d-737e8eb9df2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741239242 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.741239242
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2034860871
Short name T801
Test name
Test status
Simulation time 10385615521 ps
CPU time 3.59 seconds
Started Mar 26 01:13:01 PM PDT 24
Finished Mar 26 01:13:05 PM PDT 24
Peak memory 219200 kb
Host smart-ec17ea2e-89ee-4a0d-b094-e3c3e94f38b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034860871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2034860871
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3854396503
Short name T565
Test name
Test status
Simulation time 10154063786 ps
CPU time 82.77 seconds
Started Mar 26 01:12:55 PM PDT 24
Finished Mar 26 01:14:18 PM PDT 24
Peak memory 659504 kb
Host smart-06e7e1f7-abd3-49e5-a41f-ec8ca0a914ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854396503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3854396503
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.2410754881
Short name T1074
Test name
Test status
Simulation time 786792764 ps
CPU time 2.45 seconds
Started Mar 26 01:12:52 PM PDT 24
Finished Mar 26 01:12:55 PM PDT 24
Peak memory 204084 kb
Host smart-08b6bdcc-8d69-4029-a6a0-2d1e84622af5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410754881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.2410754881
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1735488906
Short name T255
Test name
Test status
Simulation time 1073950566 ps
CPU time 5.66 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:13:00 PM PDT 24
Peak memory 208720 kb
Host smart-2e6271f5-8254-49c3-9d26-641af2a1f106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735488906 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1735488906
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2009494270
Short name T441
Test name
Test status
Simulation time 6279368957 ps
CPU time 4.51 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:12:59 PM PDT 24
Peak memory 204208 kb
Host smart-62cfc5c5-7e32-422a-b885-8ce945789311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009494270 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2009494270
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.877336001
Short name T254
Test name
Test status
Simulation time 1567140154 ps
CPU time 10.83 seconds
Started Mar 26 01:12:47 PM PDT 24
Finished Mar 26 01:12:58 PM PDT 24
Peak memory 204132 kb
Host smart-0b784395-acf8-46cc-8ab0-86af73b349bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877336001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.877336001
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.870662848
Short name T1069
Test name
Test status
Simulation time 1375197063 ps
CPU time 6.55 seconds
Started Mar 26 01:12:49 PM PDT 24
Finished Mar 26 01:12:56 PM PDT 24
Peak memory 204028 kb
Host smart-ae2746b0-3904-47bb-8a67-785bb4d33a62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870662848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.870662848
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1031790115
Short name T557
Test name
Test status
Simulation time 3068382553 ps
CPU time 6.5 seconds
Started Mar 26 01:12:58 PM PDT 24
Finished Mar 26 01:13:04 PM PDT 24
Peak memory 212488 kb
Host smart-53fbae35-2d9c-412c-be61-58bf1b33ce39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031790115 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1031790115
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3744796921
Short name T598
Test name
Test status
Simulation time 15394076 ps
CPU time 0.61 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:13:21 PM PDT 24
Peak memory 203724 kb
Host smart-0ee892c6-4f63-4863-95df-9c91beb010d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744796921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3744796921
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.4207546222
Short name T6
Test name
Test status
Simulation time 341341035 ps
CPU time 1.08 seconds
Started Mar 26 01:12:56 PM PDT 24
Finished Mar 26 01:12:58 PM PDT 24
Peak memory 212344 kb
Host smart-5b839dce-2112-44dd-b519-cf60fa7d4652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207546222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.4207546222
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.4173151925
Short name T435
Test name
Test status
Simulation time 1886398179 ps
CPU time 7.04 seconds
Started Mar 26 01:12:53 PM PDT 24
Finished Mar 26 01:13:01 PM PDT 24
Peak memory 265628 kb
Host smart-3606f69f-f450-41c8-a1ac-c7e0e04325b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173151925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.4173151925
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2893448607
Short name T1005
Test name
Test status
Simulation time 2159038982 ps
CPU time 53.88 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:13:49 PM PDT 24
Peak memory 575124 kb
Host smart-9143ed06-dfdd-43d7-a6cb-b5babeed065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893448607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2893448607
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1128036455
Short name T917
Test name
Test status
Simulation time 838557705 ps
CPU time 0.86 seconds
Started Mar 26 01:12:55 PM PDT 24
Finished Mar 26 01:12:56 PM PDT 24
Peak memory 203912 kb
Host smart-84a63a6f-c9c4-4ab1-a1d4-b8f450ada690
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128036455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1128036455
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1438594661
Short name T941
Test name
Test status
Simulation time 606734124 ps
CPU time 7.12 seconds
Started Mar 26 01:12:55 PM PDT 24
Finished Mar 26 01:13:02 PM PDT 24
Peak memory 204164 kb
Host smart-63c4ecc9-8314-41b9-994b-81d21a43798b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438594661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1438594661
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1091853110
Short name T728
Test name
Test status
Simulation time 21280820247 ps
CPU time 106.61 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:14:41 PM PDT 24
Peak memory 1052900 kb
Host smart-ee60d68c-b60e-4df9-a558-681cbb8ae810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091853110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1091853110
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_override.1405381300
Short name T976
Test name
Test status
Simulation time 20184075 ps
CPU time 0.7 seconds
Started Mar 26 01:12:56 PM PDT 24
Finished Mar 26 01:12:56 PM PDT 24
Peak memory 203768 kb
Host smart-514473b8-ea79-489e-a450-02e2f9c65117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405381300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1405381300
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1138059492
Short name T871
Test name
Test status
Simulation time 5971201946 ps
CPU time 95.55 seconds
Started Mar 26 01:12:57 PM PDT 24
Finished Mar 26 01:14:33 PM PDT 24
Peak memory 293660 kb
Host smart-d6a97db0-5c54-4e96-bdf8-8aa44fcd8292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138059492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1138059492
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.2958053196
Short name T646
Test name
Test status
Simulation time 836883962 ps
CPU time 4.71 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:13:11 PM PDT 24
Peak memory 212344 kb
Host smart-9748195e-42a2-4564-a132-72b46ade140c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958053196 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2958053196
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.443286378
Short name T754
Test name
Test status
Simulation time 10040899467 ps
CPU time 91.46 seconds
Started Mar 26 01:12:55 PM PDT 24
Finished Mar 26 01:14:27 PM PDT 24
Peak memory 611992 kb
Host smart-8b9fd0f3-0f3e-43e4-ae3b-d5b0e033c09f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443286378 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.443286378
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.650172376
Short name T953
Test name
Test status
Simulation time 10176564664 ps
CPU time 14.77 seconds
Started Mar 26 01:13:12 PM PDT 24
Finished Mar 26 01:13:27 PM PDT 24
Peak memory 309712 kb
Host smart-996b3baa-42cf-48ce-8831-41107307fa2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650172376 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.650172376
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3093858314
Short name T636
Test name
Test status
Simulation time 375477370 ps
CPU time 2.67 seconds
Started Mar 26 01:13:11 PM PDT 24
Finished Mar 26 01:13:14 PM PDT 24
Peak memory 204420 kb
Host smart-c6324746-1124-4b7d-b448-470e53ecd5f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093858314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3093858314
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.48109001
Short name T1082
Test name
Test status
Simulation time 7748951763 ps
CPU time 4.26 seconds
Started Mar 26 01:12:56 PM PDT 24
Finished Mar 26 01:13:01 PM PDT 24
Peak memory 210560 kb
Host smart-d62248a7-5529-406b-84e0-9d47b5324d36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48109001 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.48109001
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3019614064
Short name T105
Test name
Test status
Simulation time 5311320048 ps
CPU time 7.12 seconds
Started Mar 26 01:12:54 PM PDT 24
Finished Mar 26 01:13:01 PM PDT 24
Peak memory 204188 kb
Host smart-846be376-e081-428d-9a90-73907159247a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019614064 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3019614064
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.288909963
Short name T59
Test name
Test status
Simulation time 9363018520 ps
CPU time 25.44 seconds
Started Mar 26 01:12:57 PM PDT 24
Finished Mar 26 01:13:23 PM PDT 24
Peak memory 204200 kb
Host smart-c4e825a5-4983-415d-834c-7afeb8a54b2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288909963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.288909963
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1316532391
Short name T288
Test name
Test status
Simulation time 1422860272 ps
CPU time 5.54 seconds
Started Mar 26 01:12:55 PM PDT 24
Finished Mar 26 01:13:01 PM PDT 24
Peak memory 204096 kb
Host smart-99ea6403-033a-4469-99e9-6fe3217a88ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316532391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1316532391
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1176833642
Short name T842
Test name
Test status
Simulation time 33658858500 ps
CPU time 2033.51 seconds
Started Mar 26 01:12:57 PM PDT 24
Finished Mar 26 01:46:51 PM PDT 24
Peak memory 7065400 kb
Host smart-c47e848d-9daa-422c-ac2a-de010796deba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176833642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1176833642
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2687279865
Short name T1098
Test name
Test status
Simulation time 1443262135 ps
CPU time 6.98 seconds
Started Mar 26 01:12:58 PM PDT 24
Finished Mar 26 01:13:06 PM PDT 24
Peak memory 219632 kb
Host smart-75723ed6-af48-42a3-b626-9902288dc4ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687279865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2687279865
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2967501271
Short name T104
Test name
Test status
Simulation time 131468601 ps
CPU time 0.62 seconds
Started Mar 26 01:13:07 PM PDT 24
Finished Mar 26 01:13:08 PM PDT 24
Peak memory 203772 kb
Host smart-b9eb6e92-cb9c-4e55-bc02-b508d40fe06b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967501271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2967501271
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.4238405240
Short name T673
Test name
Test status
Simulation time 88629994 ps
CPU time 1.25 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:13:07 PM PDT 24
Peak memory 220496 kb
Host smart-0e68dfb1-d970-4d17-8bb4-2ee638c4044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238405240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4238405240
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3631001995
Short name T489
Test name
Test status
Simulation time 297835706 ps
CPU time 5.31 seconds
Started Mar 26 01:13:07 PM PDT 24
Finished Mar 26 01:13:13 PM PDT 24
Peak memory 263396 kb
Host smart-071901bf-1f22-4e71-bdc6-0798cebd0bc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631001995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3631001995
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1475553944
Short name T453
Test name
Test status
Simulation time 2075915920 ps
CPU time 60.92 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:14:07 PM PDT 24
Peak memory 564944 kb
Host smart-158161dd-156d-4701-8369-c25155df9820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475553944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1475553944
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2094467749
Short name T429
Test name
Test status
Simulation time 2216949129 ps
CPU time 75.62 seconds
Started Mar 26 01:13:11 PM PDT 24
Finished Mar 26 01:14:27 PM PDT 24
Peak memory 702124 kb
Host smart-48de0882-f4a3-4309-a790-175625afce5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094467749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2094467749
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1366616435
Short name T550
Test name
Test status
Simulation time 86076756 ps
CPU time 0.84 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:13:07 PM PDT 24
Peak memory 203920 kb
Host smart-495444c6-4cf9-401d-a5c1-e3b0886c0752
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366616435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1366616435
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.429081236
Short name T447
Test name
Test status
Simulation time 119261105 ps
CPU time 3.55 seconds
Started Mar 26 01:13:11 PM PDT 24
Finished Mar 26 01:13:15 PM PDT 24
Peak memory 222268 kb
Host smart-3811c091-1b0d-4e3b-adac-cf1d102bdbe6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429081236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.429081236
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1063466956
Short name T1058
Test name
Test status
Simulation time 4832288790 ps
CPU time 151.37 seconds
Started Mar 26 01:13:05 PM PDT 24
Finished Mar 26 01:15:36 PM PDT 24
Peak memory 794020 kb
Host smart-d52e3b33-e761-40df-8f2a-6902f2583320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063466956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1063466956
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_override.3546726630
Short name T380
Test name
Test status
Simulation time 14935034 ps
CPU time 0.64 seconds
Started Mar 26 01:13:08 PM PDT 24
Finished Mar 26 01:13:08 PM PDT 24
Peak memory 203788 kb
Host smart-f5528df4-b1a1-490f-9410-cbb4365b4f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546726630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.3546726630
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.966383861
Short name T1094
Test name
Test status
Simulation time 5038168707 ps
CPU time 634.97 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:23:42 PM PDT 24
Peak memory 804860 kb
Host smart-6eef42ca-7442-4e99-9148-74aa182c56c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966383861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.966383861
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2604907593
Short name T82
Test name
Test status
Simulation time 1907459088 ps
CPU time 66.84 seconds
Started Mar 26 01:13:08 PM PDT 24
Finished Mar 26 01:14:15 PM PDT 24
Peak memory 247020 kb
Host smart-98f7ced3-79f0-45d0-aa71-7dfadbf7afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604907593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2604907593
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2220001450
Short name T945
Test name
Test status
Simulation time 765091236 ps
CPU time 3.55 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:13:24 PM PDT 24
Peak memory 212316 kb
Host smart-3f857335-c02c-44ed-811a-8be62faa5249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220001450 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2220001450
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2629341379
Short name T94
Test name
Test status
Simulation time 10324677896 ps
CPU time 10.5 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:13:17 PM PDT 24
Peak memory 269768 kb
Host smart-2a53d38c-9027-4123-aeb2-0b4b7efd52df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629341379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2629341379
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.499454650
Short name T699
Test name
Test status
Simulation time 10367639406 ps
CPU time 13.12 seconds
Started Mar 26 01:13:08 PM PDT 24
Finished Mar 26 01:13:21 PM PDT 24
Peak memory 316632 kb
Host smart-615c173b-0715-4da6-bc3d-27d7240ad935
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499454650 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_tx.499454650
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2900598462
Short name T126
Test name
Test status
Simulation time 2536581134 ps
CPU time 2.82 seconds
Started Mar 26 01:13:09 PM PDT 24
Finished Mar 26 01:13:11 PM PDT 24
Peak memory 204236 kb
Host smart-cdf7108e-0a8b-467a-a39f-41ec63f7249d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900598462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2900598462
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.677880280
Short name T978
Test name
Test status
Simulation time 4696954905 ps
CPU time 5.48 seconds
Started Mar 26 01:13:12 PM PDT 24
Finished Mar 26 01:13:17 PM PDT 24
Peak memory 204220 kb
Host smart-560d1411-c20c-44ed-b4d4-f34611564f89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677880280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.677880280
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2420796563
Short name T420
Test name
Test status
Simulation time 3439282245 ps
CPU time 14.75 seconds
Started Mar 26 01:13:12 PM PDT 24
Finished Mar 26 01:13:27 PM PDT 24
Peak memory 204236 kb
Host smart-f267d89f-c2a8-4d96-b014-6f81ad92d3f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420796563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2420796563
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2540587127
Short name T738
Test name
Test status
Simulation time 3586257949 ps
CPU time 18.9 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:13:25 PM PDT 24
Peak memory 214572 kb
Host smart-d5a391fe-77f1-4629-84e7-8562a4d886dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540587127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2540587127
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3894549781
Short name T664
Test name
Test status
Simulation time 37920032839 ps
CPU time 276.32 seconds
Started Mar 26 01:13:07 PM PDT 24
Finished Mar 26 01:17:44 PM PDT 24
Peak memory 2182804 kb
Host smart-9b44411a-6722-44ac-b887-b796d9d1cafc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894549781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3894549781
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3525457716
Short name T758
Test name
Test status
Simulation time 1445485957 ps
CPU time 7.02 seconds
Started Mar 26 01:13:05 PM PDT 24
Finished Mar 26 01:13:13 PM PDT 24
Peak memory 212292 kb
Host smart-8db65586-a82b-4821-86d3-224d8b7b76f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525457716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3525457716
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3727384597
Short name T631
Test name
Test status
Simulation time 31689179 ps
CPU time 0.61 seconds
Started Mar 26 01:13:26 PM PDT 24
Finished Mar 26 01:13:27 PM PDT 24
Peak memory 203700 kb
Host smart-2b41fe58-809a-45aa-83bf-7585a5092654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727384597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3727384597
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1869894351
Short name T493
Test name
Test status
Simulation time 76723014 ps
CPU time 1.17 seconds
Started Mar 26 01:13:23 PM PDT 24
Finished Mar 26 01:13:24 PM PDT 24
Peak memory 214700 kb
Host smart-c7249758-bdd6-4b29-9c59-ae1c523406a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869894351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1869894351
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1169059243
Short name T294
Test name
Test status
Simulation time 570514088 ps
CPU time 14.3 seconds
Started Mar 26 01:13:11 PM PDT 24
Finished Mar 26 01:13:25 PM PDT 24
Peak memory 252796 kb
Host smart-b20676c2-5b3f-4232-9f2b-5231f289fc0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169059243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1169059243
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.634048134
Short name T89
Test name
Test status
Simulation time 1428230963 ps
CPU time 95.03 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:14:56 PM PDT 24
Peak memory 544844 kb
Host smart-424a0d11-07e3-4a54-bb6e-b8dd2f311587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634048134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.634048134
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.3976854517
Short name T589
Test name
Test status
Simulation time 1787252965 ps
CPU time 48.27 seconds
Started Mar 26 01:13:11 PM PDT 24
Finished Mar 26 01:13:59 PM PDT 24
Peak memory 630240 kb
Host smart-ff83e97a-cd05-4440-999c-e7463b4e903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976854517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3976854517
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1728279058
Short name T218
Test name
Test status
Simulation time 195932230 ps
CPU time 1.01 seconds
Started Mar 26 01:13:09 PM PDT 24
Finished Mar 26 01:13:10 PM PDT 24
Peak memory 204060 kb
Host smart-9df4957f-a673-4fd8-b0a9-13c6e4763fa7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728279058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1728279058
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.151987405
Short name T614
Test name
Test status
Simulation time 524019110 ps
CPU time 7.49 seconds
Started Mar 26 01:13:09 PM PDT 24
Finished Mar 26 01:13:16 PM PDT 24
Peak memory 204160 kb
Host smart-b0bb8e9d-744d-47d1-8b2a-689a688c1893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151987405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.151987405
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1895509815
Short name T36
Test name
Test status
Simulation time 3087478087 ps
CPU time 80.92 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:14:42 PM PDT 24
Peak memory 941064 kb
Host smart-53b40d72-88b7-47fd-a113-822a79487bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895509815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1895509815
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_override.1610579511
Short name T698
Test name
Test status
Simulation time 33063443 ps
CPU time 0.65 seconds
Started Mar 26 01:13:06 PM PDT 24
Finished Mar 26 01:13:07 PM PDT 24
Peak memory 203760 kb
Host smart-ad98d385-004e-44a6-922e-d32bd304a7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610579511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1610579511
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.154481721
Short name T715
Test name
Test status
Simulation time 48021255691 ps
CPU time 724.37 seconds
Started Mar 26 01:13:21 PM PDT 24
Finished Mar 26 01:25:26 PM PDT 24
Peak memory 264108 kb
Host smart-548d4998-2cdc-42c2-983d-069979e2add3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154481721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.154481721
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2155056662
Short name T795
Test name
Test status
Simulation time 1125573366 ps
CPU time 81.5 seconds
Started Mar 26 01:13:07 PM PDT 24
Finished Mar 26 01:14:29 PM PDT 24
Peak memory 270380 kb
Host smart-b617eb84-b644-40d4-9953-8c285df25923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155056662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2155056662
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.876295565
Short name T483
Test name
Test status
Simulation time 10198126686 ps
CPU time 13.51 seconds
Started Mar 26 01:13:22 PM PDT 24
Finished Mar 26 01:13:36 PM PDT 24
Peak memory 273032 kb
Host smart-42c028b6-7709-463f-b8b2-e364bcfed558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876295565 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.876295565
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.585040553
Short name T449
Test name
Test status
Simulation time 10379606629 ps
CPU time 14.78 seconds
Started Mar 26 01:13:21 PM PDT 24
Finished Mar 26 01:13:36 PM PDT 24
Peak memory 330752 kb
Host smart-0282af17-7639-41d5-9605-390ea252cdb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585040553 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.585040553
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.4108879776
Short name T310
Test name
Test status
Simulation time 403364180 ps
CPU time 2.26 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:13:23 PM PDT 24
Peak memory 204124 kb
Host smart-dd58410f-d6c0-4370-b7d4-eaeebc9cc5bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108879776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.4108879776
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.1598302500
Short name T648
Test name
Test status
Simulation time 672040152 ps
CPU time 3.6 seconds
Started Mar 26 01:13:18 PM PDT 24
Finished Mar 26 01:13:22 PM PDT 24
Peak memory 204032 kb
Host smart-04494fa7-357f-4c88-943b-309485ce2643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598302500 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.1598302500
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3625979223
Short name T295
Test name
Test status
Simulation time 3817905582 ps
CPU time 34.51 seconds
Started Mar 26 01:13:21 PM PDT 24
Finished Mar 26 01:13:56 PM PDT 24
Peak memory 204164 kb
Host smart-f4906a43-b28d-464d-ac77-ff754d0d60a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625979223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3625979223
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2594163764
Short name T531
Test name
Test status
Simulation time 2510951906 ps
CPU time 10.18 seconds
Started Mar 26 01:13:19 PM PDT 24
Finished Mar 26 01:13:31 PM PDT 24
Peak memory 209396 kb
Host smart-6c849ffc-8e0b-4f60-bf0a-c33be5705f3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594163764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2594163764
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.4023232620
Short name T985
Test name
Test status
Simulation time 38063766278 ps
CPU time 267.54 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:17:48 PM PDT 24
Peak memory 2188220 kb
Host smart-9db28e82-f03f-463e-a826-6b288dbb170a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023232620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.4023232620
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1358985455
Short name T397
Test name
Test status
Simulation time 1197582769 ps
CPU time 6.75 seconds
Started Mar 26 01:13:19 PM PDT 24
Finished Mar 26 01:13:26 PM PDT 24
Peak memory 217188 kb
Host smart-72ad1e25-40fe-402f-95ac-3149b78e3d81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358985455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1358985455
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.282421588
Short name T806
Test name
Test status
Simulation time 15998998 ps
CPU time 0.63 seconds
Started Mar 26 01:13:34 PM PDT 24
Finished Mar 26 01:13:35 PM PDT 24
Peak memory 203788 kb
Host smart-527dcdee-d586-4ba9-8b97-3882103d120c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282421588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.282421588
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3900136120
Short name T479
Test name
Test status
Simulation time 36803168 ps
CPU time 1.18 seconds
Started Mar 26 01:13:18 PM PDT 24
Finished Mar 26 01:13:19 PM PDT 24
Peak memory 212308 kb
Host smart-777c4941-5008-464a-b246-82f2e1a02d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900136120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3900136120
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2454418759
Short name T902
Test name
Test status
Simulation time 363601025 ps
CPU time 6.73 seconds
Started Mar 26 01:13:19 PM PDT 24
Finished Mar 26 01:13:26 PM PDT 24
Peak memory 284288 kb
Host smart-4f68f7b3-c11f-461a-89ee-43d3283ebb63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454418759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2454418759
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1630722443
Short name T841
Test name
Test status
Simulation time 21523553842 ps
CPU time 80.36 seconds
Started Mar 26 01:13:21 PM PDT 24
Finished Mar 26 01:14:41 PM PDT 24
Peak memory 796572 kb
Host smart-4abe35f3-603d-4e0e-84a6-598840b23429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630722443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1630722443
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.828893657
Short name T573
Test name
Test status
Simulation time 1937025620 ps
CPU time 137.27 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:15:38 PM PDT 24
Peak memory 638124 kb
Host smart-5f5113f1-a85e-4a0e-9889-94413abcc037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828893657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.828893657
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3776156828
Short name T1021
Test name
Test status
Simulation time 1168937245 ps
CPU time 0.86 seconds
Started Mar 26 01:13:27 PM PDT 24
Finished Mar 26 01:13:28 PM PDT 24
Peak memory 203812 kb
Host smart-29d546f4-fc3a-4c13-a84d-bb676f81e807
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776156828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3776156828
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1732538217
Short name T503
Test name
Test status
Simulation time 157223640 ps
CPU time 3.95 seconds
Started Mar 26 01:13:20 PM PDT 24
Finished Mar 26 01:13:25 PM PDT 24
Peak memory 204116 kb
Host smart-b4a67dc2-22cc-4d31-b704-f18cc5b98616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732538217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1732538217
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_override.2923562262
Short name T204
Test name
Test status
Simulation time 17483216 ps
CPU time 0.65 seconds
Started Mar 26 01:13:18 PM PDT 24
Finished Mar 26 01:13:19 PM PDT 24
Peak memory 203896 kb
Host smart-8cd97fa4-409e-4143-a9a6-5471e23b5152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923562262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2923562262
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1116594773
Short name T192
Test name
Test status
Simulation time 7442342894 ps
CPU time 412.76 seconds
Started Mar 26 01:13:19 PM PDT 24
Finished Mar 26 01:20:12 PM PDT 24
Peak memory 698092 kb
Host smart-94b453e4-8c54-4615-b322-1b15b528af4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116594773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1116594773
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2709143313
Short name T688
Test name
Test status
Simulation time 4694261769 ps
CPU time 43.41 seconds
Started Mar 26 01:13:52 PM PDT 24
Finished Mar 26 01:14:36 PM PDT 24
Peak memory 328292 kb
Host smart-1871a41e-743d-451f-b841-de030019c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709143313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2709143313
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1201278393
Short name T244
Test name
Test status
Simulation time 7038100189 ps
CPU time 308.26 seconds
Started Mar 26 01:13:22 PM PDT 24
Finished Mar 26 01:18:31 PM PDT 24
Peak memory 752264 kb
Host smart-edb33336-6ae4-465a-af28-042873b7e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201278393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1201278393
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.446646164
Short name T800
Test name
Test status
Simulation time 9778106198 ps
CPU time 4.32 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:13:37 PM PDT 24
Peak memory 212508 kb
Host smart-e28b7d92-77f2-48c4-ae39-ac4570110b03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446646164 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.446646164
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.4205739644
Short name T78
Test name
Test status
Simulation time 10050483735 ps
CPU time 32.26 seconds
Started Mar 26 01:13:31 PM PDT 24
Finished Mar 26 01:14:03 PM PDT 24
Peak memory 411288 kb
Host smart-73014fb7-71e2-4e66-bc3e-71fe26f4668c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205739644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.4205739644
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2022384455
Short name T422
Test name
Test status
Simulation time 10091019951 ps
CPU time 16.73 seconds
Started Mar 26 01:13:35 PM PDT 24
Finished Mar 26 01:13:52 PM PDT 24
Peak memory 328308 kb
Host smart-837ee5d7-a10c-4013-bac1-30a4f42f8f8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022384455 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2022384455
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2925253915
Short name T544
Test name
Test status
Simulation time 5684038895 ps
CPU time 2.43 seconds
Started Mar 26 01:13:31 PM PDT 24
Finished Mar 26 01:13:34 PM PDT 24
Peak memory 204280 kb
Host smart-aa6f706f-a96b-4a32-9aa3-ad5c59f8ad36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925253915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2925253915
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1091896216
Short name T337
Test name
Test status
Simulation time 4418996887 ps
CPU time 6.39 seconds
Started Mar 26 01:13:34 PM PDT 24
Finished Mar 26 01:13:40 PM PDT 24
Peak memory 217472 kb
Host smart-061f500d-5521-4bed-9547-0818042a6133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091896216 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1091896216
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.506685545
Short name T970
Test name
Test status
Simulation time 7273299651 ps
CPU time 16.66 seconds
Started Mar 26 01:13:35 PM PDT 24
Finished Mar 26 01:13:52 PM PDT 24
Peak memory 204324 kb
Host smart-30aef534-57ad-4601-8dd6-3a42a6b6fafe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506685545 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.506685545
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2812931295
Short name T563
Test name
Test status
Simulation time 1953104598 ps
CPU time 32.23 seconds
Started Mar 26 01:13:32 PM PDT 24
Finished Mar 26 01:14:05 PM PDT 24
Peak memory 204072 kb
Host smart-01d4422e-e56c-42f8-be02-8817cd991823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812931295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2812931295
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.594980747
Short name T326
Test name
Test status
Simulation time 297347624 ps
CPU time 5.15 seconds
Started Mar 26 01:13:32 PM PDT 24
Finished Mar 26 01:13:37 PM PDT 24
Peak memory 204132 kb
Host smart-37383a64-c49c-4adc-9c22-f2521e478707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594980747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.594980747
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.719946907
Short name T977
Test name
Test status
Simulation time 35701364407 ps
CPU time 6.14 seconds
Started Mar 26 01:13:35 PM PDT 24
Finished Mar 26 01:13:41 PM PDT 24
Peak memory 204128 kb
Host smart-cf70f3d6-570f-47d5-86b1-a83aaf25929e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719946907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.719946907
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2645823815
Short name T517
Test name
Test status
Simulation time 10044734766 ps
CPU time 67.33 seconds
Started Mar 26 01:13:34 PM PDT 24
Finished Mar 26 01:14:42 PM PDT 24
Peak memory 1090784 kb
Host smart-70687fb0-3514-42b5-9441-b944b8f9565d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645823815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2645823815
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.353050400
Short name T314
Test name
Test status
Simulation time 3059056717 ps
CPU time 7.52 seconds
Started Mar 26 01:13:35 PM PDT 24
Finished Mar 26 01:13:43 PM PDT 24
Peak memory 212392 kb
Host smart-24e67b48-e198-49f8-a564-f72fe5d50ec2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353050400 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.353050400
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.1716004581
Short name T1000
Test name
Test status
Simulation time 2269361226 ps
CPU time 4.47 seconds
Started Mar 26 01:13:33 PM PDT 24
Finished Mar 26 01:13:37 PM PDT 24
Peak memory 205640 kb
Host smart-0dfbe0f0-49e1-4c0d-a70a-6fe7706ebde7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716004581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.1716004581
Directory /workspace/9.i2c_target_unexp_stop/latest
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