Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	104122	1			T1	2		T2	3		T3	3
all_values[1]	104122	1			T1	2		T2	3		T3	3
all_values[2]	104122	1			T1	2		T2	3		T3	3
all_values[3]	104122	1			T1	2		T2	3		T3	3
all_values[4]	104122	1			T1	2		T2	3		T3	3
all_values[5]	104122	1			T1	2		T2	3		T3	3
all_values[6]	104122	1			T1	2		T2	3		T3	3
all_values[7]	104122	1			T1	2		T2	3		T3	3
all_values[8]	104122	1			T1	2		T2	3		T3	3
all_values[9]	104122	1			T1	2		T2	3		T3	3
all_values[10]	104122	1			T1	2		T2	3		T3	3
all_values[11]	104122	1			T1	2		T2	3		T3	3
all_values[12]	104122	1			T1	2		T2	3		T3	3
all_values[13]	104122	1			T1	2		T2	3		T3	3
all_values[14]	104122	1			T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1334195

1

T1

26

T2

37

T3

44

auto[1]

227635

1

T1

4

T2

8

T3

1

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1457292

1

T1

30

T2

45

T3

45

auto[1]

104538

1

T6

4999

T28

12565

T29

14830

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	16707	1			T2	1		T3	3		T4	1
all_values[0]	auto[0]	auto[1]	1608	1			T6	300		T28	277		T29	17
all_values[0]	auto[1]	auto[0]	80613	1			T1	2		T2	2		T4	2
all_values[0]	auto[1]	auto[1]	5194	1			T6	34		T28	556		T29	972
all_values[1]	auto[0]	auto[0]	96908	1			T1	2		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	7018	1			T6	329		T28	832		T29	987
all_values[1]	auto[1]	auto[0]	37	1			T51	2		T31	1		T221	4
all_values[1]	auto[1]	auto[1]	159	1			T6	5		T28	5		T29	3
all_values[2]	auto[0]	auto[0]	96978	1			T1	2		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	6992	1			T6	331		T28	831		T29	984
all_values[2]	auto[1]	auto[1]	152	1			T6	3		T28	8		T29	2
all_values[3]	auto[0]	auto[0]	97502	1			T1	2		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	6442	1			T6	329		T28	829		T29	987
all_values[3]	auto[1]	auto[1]	178	1			T6	5		T28	10		T29	2
all_values[4]	auto[0]	auto[0]	96945	1			T1	2		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	7001	1			T6	327		T28	825		T29	983
all_values[4]	auto[1]	auto[0]	6	1			T23	1		T24	1		T222	1
all_values[4]	auto[1]	auto[1]	170	1			T6	5		T28	9		T29	6
all_values[5]	auto[0]	auto[0]	96938	1			T1	2		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	7021	1			T6	330		T28	830		T29	985
all_values[5]	auto[1]	auto[1]	163	1			T6	4		T28	9		T29	3
all_values[6]	auto[0]	auto[0]	94768	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	6829	1			T6	266		T28	818		T29	981
all_values[6]	auto[1]	auto[0]	2169	1			T2	1		T3	1		T4	1
all_values[6]	auto[1]	auto[1]	356	1			T6	68		T28	21		T29	9
all_values[7]	auto[0]	auto[0]	73959	1			T1	2		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	5172	1			T6	327		T28	788		T29	719
all_values[7]	auto[1]	auto[0]	22981	1			T2	1		T9	1		T10	1
all_values[7]	auto[1]	auto[1]	2010	1			T6	7		T28	50		T29	270
all_values[8]	auto[0]	auto[0]	89902	1			T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	6361	1			T6	278		T28	737		T29	937
all_values[8]	auto[1]	auto[0]	7037	1			T2	1		T4	1		T9	1
all_values[8]	auto[1]	auto[1]	822	1			T6	56		T28	100		T29	53
all_values[9]	auto[0]	auto[0]	94257	1			T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	6832	1			T6	325		T28	815		T29	967
all_values[9]	auto[1]	auto[0]	2688	1			T2	1		T4	1		T5	1
all_values[9]	auto[1]	auto[1]	345	1			T6	8		T28	22		T29	20
all_values[10]	auto[0]	auto[0]	96945	1			T1	2		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	7020	1			T6	331		T28	831		T29	985
all_values[10]	auto[1]	auto[1]	157	1			T6	3		T28	6		T29	1
all_values[11]	auto[0]	auto[0]	1926	1			T2	1		T3	3		T4	1
all_values[11]	auto[0]	auto[1]	316	1			T6	26		T28	23		T29	9
all_values[11]	auto[1]	auto[0]	95570	1			T1	2		T2	2		T4	2
all_values[11]	auto[1]	auto[1]	6310	1			T6	305		T28	816		T29	981
all_values[12]	auto[0]	auto[0]	97328	1			T1	2		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	6641	1			T6	331		T28	831		T29	985
all_values[12]	auto[1]	auto[1]	153	1			T6	3		T28	8		T29	5
all_values[13]	auto[0]	auto[0]	98178	1			T1	2		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	5760	1			T6	331		T28	827		T29	985
all_values[13]	auto[1]	auto[0]	5	1			T35	1		T223	1		T224	1
all_values[13]	auto[1]	auto[1]	179	1			T6	3		T28	12		T29	5
all_values[14]	auto[0]	auto[0]	96945	1			T1	2		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	6996	1			T6	327		T28	831		T29	985
all_values[14]	auto[1]	auto[1]	181	1			T6	2		T28	8		T29	2