Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	104122	1			T1	2		T2	3		T3	3
all_pins[1]	104122	1			T1	2		T2	3		T3	3
all_pins[2]	104122	1			T1	2		T2	3		T3	3
all_pins[3]	104122	1			T1	2		T2	3		T3	3
all_pins[4]	104122	1			T1	2		T2	3		T3	3
all_pins[5]	104122	1			T1	2		T2	3		T3	3
all_pins[6]	104122	1			T1	2		T2	3		T3	3
all_pins[7]	104122	1			T1	2		T2	3		T3	3
all_pins[8]	104122	1			T1	2		T2	3		T3	3
all_pins[9]	104122	1			T1	2		T2	3		T3	3
all_pins[10]	104122	1			T1	2		T2	3		T3	3
all_pins[11]	104122	1			T1	2		T2	3		T3	3
all_pins[12]	104122	1			T1	2		T2	3		T3	3
all_pins[13]	104122	1			T1	2		T2	3		T3	3
all_pins[14]	104122	1			T1	2		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1342027	1			T1	26		T2	37		T3	44
values[0x1]	219803	1			T1	4		T2	8		T3	1
transitions[0x0=>0x1]	214872	1			T1	4		T2	5		T3	1
transitions[0x1=>0x0]	213993	1			T1	3		T2	4		T3	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	21329	1			T2	1		T3	3		T4	1
all_pins[0]	values[0x1]	82793	1			T1	2		T2	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	82725	1			T1	2		T2	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	51	1			T28	3		T29	1		T26	1
all_pins[1]	values[0x0]	104003	1			T1	2		T2	3		T3	3
all_pins[1]	values[0x1]	119	1			T6	1		T51	3		T28	3
all_pins[1]	transitions[0x0=>0x1]	104	1			T6	1		T51	3		T28	3
all_pins[1]	transitions[0x1=>0x0]	65	1			T6	2		T28	3		T26	2
all_pins[2]	values[0x0]	104042	1			T1	2		T2	3		T3	3
all_pins[2]	values[0x1]	80	1			T6	2		T28	3		T26	2
all_pins[2]	transitions[0x0=>0x1]	59	1			T6	2		T28	3		T232	2
all_pins[2]	transitions[0x1=>0x0]	66	1			T6	3		T28	5		T29	1
all_pins[3]	values[0x0]	104035	1			T1	2		T2	3		T3	3
all_pins[3]	values[0x1]	87	1			T6	3		T28	5		T29	1
all_pins[3]	transitions[0x0=>0x1]	65	1			T6	3		T28	3		T29	1
all_pins[3]	transitions[0x1=>0x0]	70	1			T6	2		T23	1		T24	1
all_pins[4]	values[0x0]	104030	1			T1	2		T2	3		T3	3
all_pins[4]	values[0x1]	92	1			T6	2		T23	1		T24	1
all_pins[4]	transitions[0x0=>0x1]	74	1			T6	2		T23	1		T24	1
all_pins[4]	transitions[0x1=>0x0]	60	1			T6	3		T28	3		T29	1
all_pins[5]	values[0x0]	104044	1			T1	2		T2	3		T3	3
all_pins[5]	values[0x1]	78	1			T6	3		T28	3		T29	1
all_pins[5]	transitions[0x0=>0x1]	54	1			T6	3		T28	3		T29	1
all_pins[5]	transitions[0x1=>0x0]	2224	1			T2	1		T3	1		T4	1
all_pins[6]	values[0x0]	101874	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	2248	1			T2	1		T3	1		T4	1
all_pins[6]	transitions[0x0=>0x1]	1367	1			T3	1		T4	1		T6	62
all_pins[6]	transitions[0x1=>0x0]	24027	1			T6	3		T51	52		T15	73
all_pins[7]	values[0x0]	79214	1			T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	24908	1			T2	1		T6	7		T9	1
all_pins[7]	transitions[0x0=>0x1]	22202	1			T6	4		T51	33		T15	71
all_pins[7]	transitions[0x1=>0x0]	4886	1			T4	1		T6	53		T51	18
all_pins[8]	values[0x0]	96530	1			T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	7592	1			T2	1		T4	1		T6	56
all_pins[8]	transitions[0x0=>0x1]	6546	1			T6	52		T51	36		T15	24
all_pins[8]	transitions[0x1=>0x0]	1926	1			T5	1		T6	3		T16	1
all_pins[9]	values[0x0]	101150	1			T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	2972	1			T2	1		T4	1		T5	1
all_pins[9]	transitions[0x0=>0x1]	2950	1			T2	1		T4	1		T5	1
all_pins[9]	transitions[0x1=>0x0]	58	1			T6	2		T28	3		T29	1
all_pins[10]	values[0x0]	104042	1			T1	2		T2	3		T3	3
all_pins[10]	values[0x1]	80	1			T6	2		T28	4		T29	1
all_pins[10]	transitions[0x0=>0x1]	55	1			T6	2		T28	2		T29	1
all_pins[10]	transitions[0x1=>0x0]	98471	1			T1	2		T2	2		T4	2
all_pins[11]	values[0x0]	5626	1			T2	1		T3	3		T4	1
all_pins[11]	values[0x1]	98496	1			T1	2		T2	2		T4	2
all_pins[11]	transitions[0x0=>0x1]	98482	1			T1	2		T2	2		T4	2
all_pins[11]	transitions[0x1=>0x0]	67	1			T6	2		T28	4		T29	3
all_pins[12]	values[0x0]	104041	1			T1	2		T2	3		T3	3
all_pins[12]	values[0x1]	81	1			T6	2		T28	5		T29	3
all_pins[12]	transitions[0x0=>0x1]	63	1			T6	1		T28	5		T29	1
all_pins[12]	transitions[0x1=>0x0]	74	1			T6	2		T28	6		T29	3
all_pins[13]	values[0x0]	104030	1			T1	2		T2	3		T3	3
all_pins[13]	values[0x1]	92	1			T6	3		T28	6		T29	5
all_pins[13]	transitions[0x0=>0x1]	71	1			T6	3		T28	6		T29	5
all_pins[13]	transitions[0x1=>0x0]	64	1			T28	4		T29	1		T97	2
all_pins[14]	values[0x0]	104037	1			T1	2		T2	3		T3	3
all_pins[14]	values[0x1]	85	1			T28	4		T29	1		T97	5
all_pins[14]	transitions[0x0=>0x1]	55	1			T28	3		T29	1		T97	1
all_pins[14]	transitions[0x1=>0x0]	81884	1			T1	1		T2	1		T4	1