Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	377	1			T6	7		T28	19		T29	7
all_values[1]	377	1			T6	7		T28	19		T29	7
all_values[2]	377	1			T6	7		T28	19		T29	7
all_values[3]	377	1			T6	7		T28	19		T29	7
all_values[4]	377	1			T6	7		T28	19		T29	7
all_values[5]	377	1			T6	7		T28	19		T29	7
all_values[6]	377	1			T6	7		T28	19		T29	7
all_values[7]	377	1			T6	7		T28	19		T29	7
all_values[8]	377	1			T6	7		T28	19		T29	7
all_values[9]	377	1			T6	7		T28	19		T29	7
all_values[10]	377	1			T6	7		T28	19		T29	7
all_values[11]	377	1			T6	7		T28	19		T29	7
all_values[12]	377	1			T6	7		T28	19		T29	7
all_values[13]	377	1			T6	7		T28	19		T29	7
all_values[14]	377	1			T6	7		T28	19		T29	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3167

1

T6

42

T28

177

T29

60

auto[1]

2488

1

T6

63

T28

108

T29

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

911

1

T6

11

T28

18

T29

20

auto[1]

4744

1

T6

94

T28

267

T29

85

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3285

1

T6

59

T28

175

T29

59

auto[1]

2370

1

T6

46

T28

110

T29

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1			T28	2		T29	1		T97	1
all_values[0]	auto[0]	auto[0]	auto[1]	79	1			T28	8		T97	1		T26	3
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T28	3		T97	1		T26	1
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T6	2		T29	2		T43	2
all_values[0]	auto[1]	auto[0]	auto[1]	90	1			T6	2		T28	5		T97	2
all_values[0]	auto[1]	auto[1]	auto[1]	65	1			T6	3		T28	1		T29	4
all_values[1]	auto[0]	auto[0]	auto[0]	36	1			T28	1		T97	1		T232	1
all_values[1]	auto[0]	auto[0]	auto[1]	86	1			T6	1		T28	6		T29	2
all_values[1]	auto[0]	auto[1]	auto[0]	20	1			T28	1		T97	2		T165	1
all_values[1]	auto[0]	auto[1]	auto[1]	77	1			T6	1		T28	6		T29	2
all_values[1]	auto[1]	auto[0]	auto[1]	95	1			T6	3		T28	3		T29	3
all_values[1]	auto[1]	auto[1]	auto[1]	63	1			T6	2		T28	2		T97	1
all_values[2]	auto[0]	auto[0]	auto[0]	46	1			T29	3		T97	4		T43	2
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T6	2		T28	6		T29	1
all_values[2]	auto[0]	auto[1]	auto[0]	26	1			T29	1		T97	3		T26	1
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T6	2		T28	5		T26	2
all_values[2]	auto[1]	auto[0]	auto[1]	92	1			T28	5		T29	2		T43	1
all_values[2]	auto[1]	auto[1]	auto[1]	60	1			T6	3		T28	3		T26	1
all_values[3]	auto[0]	auto[0]	auto[0]	43	1			T29	1		T97	5		T43	1
all_values[3]	auto[0]	auto[0]	auto[1]	82	1			T6	1		T28	6		T29	2
all_values[3]	auto[0]	auto[1]	auto[0]	17	1			T97	2		T43	1		T232	1
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T6	2		T28	3		T29	2
all_values[3]	auto[1]	auto[0]	auto[1]	104	1			T6	1		T28	8		T29	1
all_values[3]	auto[1]	auto[1]	auto[1]	54	1			T6	3		T28	2		T29	1
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T6	1		T28	1		T29	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T6	2		T28	5		T97	2
all_values[4]	auto[0]	auto[1]	auto[0]	22	1			T6	1		T28	3		T164	1
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T28	5		T29	1		T97	2
all_values[4]	auto[1]	auto[0]	auto[1]	87	1			T6	1		T28	3		T29	4
all_values[4]	auto[1]	auto[1]	auto[1]	83	1			T6	2		T28	2		T29	1
all_values[5]	auto[0]	auto[0]	auto[0]	33	1			T29	1		T97	1		T232	1
all_values[5]	auto[0]	auto[0]	auto[1]	89	1			T6	2		T28	8		T29	1
all_values[5]	auto[0]	auto[1]	auto[0]	18	1			T29	1		T233	3		T234	1
all_values[5]	auto[0]	auto[1]	auto[1]	75	1			T6	1		T28	3		T29	1
all_values[5]	auto[1]	auto[0]	auto[1]	96	1			T6	1		T28	6		T29	2
all_values[5]	auto[1]	auto[1]	auto[1]	66	1			T6	3		T28	2		T29	1
all_values[6]	auto[0]	auto[0]	auto[0]	22	1			T26	1		T27	1		T162	1
all_values[6]	auto[0]	auto[0]	auto[1]	86	1			T6	2		T28	9		T29	3
all_values[6]	auto[0]	auto[1]	auto[0]	26	1			T26	1		T162	1		T165	2
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T6	1		T28	3		T29	2
all_values[6]	auto[1]	auto[0]	auto[1]	95	1			T6	3		T28	6		T29	2
all_values[6]	auto[1]	auto[1]	auto[1]	72	1			T6	1		T28	1		T97	1
all_values[7]	auto[0]	auto[0]	auto[0]	39	1			T28	1		T29	1		T43	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T28	3		T97	1		T43	1
all_values[7]	auto[0]	auto[1]	auto[0]	11	1			T207	2		T233	1		T235	2
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T6	3		T28	7		T29	2
all_values[7]	auto[1]	auto[0]	auto[1]	100	1			T28	6		T29	2		T97	4
all_values[7]	auto[1]	auto[1]	auto[1]	63	1			T6	4		T28	2		T29	2
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T43	1		T232	1		T207	1
all_values[8]	auto[0]	auto[0]	auto[1]	78	1			T6	3		T28	10		T29	1
all_values[8]	auto[0]	auto[1]	auto[0]	14	1			T28	2		T26	1		T27	1
all_values[8]	auto[0]	auto[1]	auto[1]	97	1			T6	3		T28	1		T29	2
all_values[8]	auto[1]	auto[0]	auto[1]	73	1			T28	1		T29	1		T97	2
all_values[8]	auto[1]	auto[1]	auto[1]	79	1			T6	1		T28	5		T29	3
all_values[9]	auto[0]	auto[0]	auto[0]	43	1			T28	2		T29	2		T97	2
all_values[9]	auto[0]	auto[0]	auto[1]	94	1			T6	3		T28	6		T29	3
all_values[9]	auto[0]	auto[1]	auto[0]	16	1			T6	1		T29	1		T26	1
all_values[9]	auto[0]	auto[1]	auto[1]	77	1			T6	1		T28	5		T97	1
all_values[9]	auto[1]	auto[0]	auto[1]	89	1			T6	1		T28	5		T29	1
all_values[9]	auto[1]	auto[1]	auto[1]	58	1			T6	1		T28	1		T97	1
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T28	1		T29	2		T43	2
all_values[10]	auto[0]	auto[0]	auto[1]	88	1			T6	3		T28	9		T29	1
all_values[10]	auto[0]	auto[1]	auto[0]	22	1			T28	1		T29	2		T164	1
all_values[10]	auto[0]	auto[1]	auto[1]	77	1			T6	1		T28	2		T29	1
all_values[10]	auto[1]	auto[0]	auto[1]	91	1			T6	1		T28	4		T97	3
all_values[10]	auto[1]	auto[1]	auto[1]	66	1			T6	2		T28	2		T29	1
all_values[11]	auto[0]	auto[0]	auto[0]	37	1			T6	1		T97	1		T43	1
all_values[11]	auto[0]	auto[0]	auto[1]	82	1			T6	1		T28	7		T29	2
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T6	2		T232	1		T27	2
all_values[11]	auto[0]	auto[1]	auto[1]	78	1			T6	2		T28	5		T29	2
all_values[11]	auto[1]	auto[0]	auto[1]	89	1			T28	3		T29	2		T97	2
all_values[11]	auto[1]	auto[1]	auto[1]	66	1			T6	1		T28	4		T29	1
all_values[12]	auto[0]	auto[0]	auto[0]	45	1			T97	1		T43	1		T26	3
all_values[12]	auto[0]	auto[0]	auto[1]	75	1			T6	2		T28	6		T29	1
all_values[12]	auto[0]	auto[1]	auto[0]	32	1			T97	1		T43	1		T26	1
all_values[12]	auto[0]	auto[1]	auto[1]	72	1			T6	2		T28	5		T29	1
all_values[12]	auto[1]	auto[0]	auto[1]	79	1			T6	1		T28	4		T29	3
all_values[12]	auto[1]	auto[1]	auto[1]	74	1			T6	2		T28	4		T29	2
all_values[13]	auto[0]	auto[0]	auto[0]	40	1			T97	1		T43	3		T26	1
all_values[13]	auto[0]	auto[0]	auto[1]	84	1			T28	6		T29	1		T97	1
all_values[13]	auto[0]	auto[1]	auto[0]	42	1			T43	1		T26	1		T233	1
all_values[13]	auto[0]	auto[1]	auto[1]	62	1			T6	4		T28	3		T29	2
all_values[13]	auto[1]	auto[0]	auto[1]	85	1			T28	7		T29	2		T26	1
all_values[13]	auto[1]	auto[1]	auto[1]	64	1			T6	3		T28	3		T29	2
all_values[14]	auto[0]	auto[0]	auto[0]	36	1			T6	2		T29	3		T26	1
all_values[14]	auto[0]	auto[0]	auto[1]	75	1			T6	1		T28	2		T43	2
all_values[14]	auto[0]	auto[1]	auto[0]	22	1			T6	3		T26	2		T27	1
all_values[14]	auto[0]	auto[1]	auto[1]	72	1			T28	7		T29	1		T97	2
all_values[14]	auto[1]	auto[0]	auto[1]	105	1			T6	1		T28	6		T29	2
all_values[14]	auto[1]	auto[1]	auto[1]	67	1			T28	4		T29	1		T97	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal