Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	92175	1			T1	2		T2	3		T4	3
all_values[1]	92175	1			T1	2		T2	3		T4	3
all_values[2]	92175	1			T1	2		T2	3		T4	3
all_values[3]	92175	1			T1	2		T2	3		T4	3
all_values[4]	92175	1			T1	2		T2	3		T4	3
all_values[5]	92175	1			T1	2		T2	3		T4	3
all_values[6]	92175	1			T1	2		T2	3		T4	3
all_values[7]	92175	1			T1	2		T2	3		T4	3
all_values[8]	92175	1			T1	2		T2	3		T4	3
all_values[9]	92175	1			T1	2		T2	3		T4	3
all_values[10]	92175	1			T1	2		T2	3		T4	3
all_values[11]	92175	1			T1	2		T2	3		T4	3
all_values[12]	92175	1			T1	2		T2	3		T4	3
all_values[13]	92175	1			T1	2		T2	3		T4	3
all_values[14]	92175	1			T1	2		T2	3		T4	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184952

1

T1

26

T2

40

T4

37

auto[1]

197673

1

T1

4

T2

5

T4

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1243586

1

T1

30

T2

45

T4

45

auto[1]

139039

1

T29

308

T14

9245

T25

15945

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	19584	1			T4	1		T9	17		T10	1
all_values[0]	auto[0]	auto[1]	3498	1			T29	18		T14	32		T25	1
all_values[0]	auto[1]	auto[0]	63287	1			T1	2		T2	3		T4	2
all_values[0]	auto[1]	auto[1]	5806	1			T29	3		T14	586		T25	1226
all_values[1]	auto[0]	auto[0]	82647	1			T1	2		T2	3		T4	3
all_values[1]	auto[0]	auto[1]	9296	1			T29	16		T14	611		T25	1224
all_values[1]	auto[1]	auto[0]	55	1			T208	1		T209	2		T210	3
all_values[1]	auto[1]	auto[1]	177	1			T29	5		T14	7		T25	2
all_values[2]	auto[0]	auto[0]	82728	1			T1	2		T2	3		T4	3
all_values[2]	auto[0]	auto[1]	9285	1			T29	18		T14	604		T25	1225
all_values[2]	auto[1]	auto[1]	162	1			T29	3		T14	3		T25	2
all_values[3]	auto[0]	auto[0]	82863	1			T1	2		T2	3		T4	3
all_values[3]	auto[0]	auto[1]	9138	1			T29	16		T14	612		T25	1223
all_values[3]	auto[1]	auto[1]	174	1			T29	5		T14	6		T25	4
all_values[4]	auto[0]	auto[0]	82698	1			T1	2		T2	3		T4	3
all_values[4]	auto[0]	auto[1]	9293	1			T29	16		T14	610		T25	1226
all_values[4]	auto[1]	auto[0]	10	1			T211	1		T212	1		T213	1
all_values[4]	auto[1]	auto[1]	174	1			T29	5		T14	7		T26	8
all_values[5]	auto[0]	auto[0]	83929	1			T1	2		T2	3		T4	3
all_values[5]	auto[0]	auto[1]	8087	1			T29	13		T14	611		T26	24
all_values[5]	auto[1]	auto[1]	159	1			T29	6		T14	6		T26	6
all_values[6]	auto[0]	auto[0]	80646	1			T1	2		T2	3		T4	2
all_values[6]	auto[0]	auto[1]	9198	1			T29	13		T14	576		T25	1224
all_values[6]	auto[1]	auto[0]	2050	1			T4	1		T9	9		T10	1
all_values[6]	auto[1]	auto[1]	281	1			T29	7		T14	41		T25	3
all_values[7]	auto[0]	auto[0]	61904	1			T1	2		T2	3		T4	2
all_values[7]	auto[0]	auto[1]	6281	1			T29	11		T14	363		T25	579
all_values[7]	auto[1]	auto[0]	20973	1			T4	1		T9	92		T10	1
all_values[7]	auto[1]	auto[1]	3017	1			T29	10		T14	255		T25	647
all_values[8]	auto[0]	auto[0]	75632	1			T1	2		T2	3		T4	2
all_values[8]	auto[0]	auto[1]	8717	1			T29	15		T14	497		T25	1221
all_values[8]	auto[1]	auto[0]	7084	1			T4	1		T9	37		T10	1
all_values[8]	auto[1]	auto[1]	742	1			T29	5		T14	120		T25	6
all_values[9]	auto[0]	auto[0]	80027	1			T1	2		T2	2		T4	2
all_values[9]	auto[0]	auto[1]	9146	1			T29	18		T14	559		T25	1219
all_values[9]	auto[1]	auto[0]	2672	1			T2	1		T4	1		T7	1
all_values[9]	auto[1]	auto[1]	330	1			T29	3		T14	58		T25	8
all_values[10]	auto[0]	auto[0]	82717	1			T1	2		T2	3		T4	3
all_values[10]	auto[0]	auto[1]	9294	1			T29	13		T14	610		T25	1224
all_values[10]	auto[1]	auto[1]	164	1			T29	7		T14	8		T25	1
all_values[11]	auto[0]	auto[0]	2045	1			T2	2		T4	1		T9	3
all_values[11]	auto[0]	auto[1]	321	1			T29	16		T14	23		T25	1
all_values[11]	auto[1]	auto[0]	80656	1			T1	2		T2	1		T4	2
all_values[11]	auto[1]	auto[1]	9153	1			T29	5		T14	594		T25	1225
all_values[12]	auto[0]	auto[0]	82710	1			T1	2		T2	3		T4	3
all_values[12]	auto[0]	auto[1]	9297	1			T29	16		T14	608		T25	1224
all_values[12]	auto[1]	auto[1]	168	1			T29	4		T14	4		T25	3
all_values[13]	auto[0]	auto[0]	82717	1			T1	2		T2	3		T4	3
all_values[13]	auto[0]	auto[1]	9275	1			T29	17		T14	613		T25	1227
all_values[13]	auto[1]	auto[0]	5	1			T214	1		T215	1		T216	1
all_values[13]	auto[1]	auto[1]	178	1			T29	4		T14	5		T26	3
all_values[14]	auto[0]	auto[0]	83947	1			T1	2		T2	3		T4	3
all_values[14]	auto[0]	auto[1]	8032	1			T29	17		T14	608		T26	24
all_values[14]	auto[1]	auto[1]	196	1			T29	3		T14	8		T26	7