Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_stretch_cg

Group : i2c_env_pkg::i2c_scl_stretch_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	1	3	75.00

Variables for Group i2c_env_pkg::i2c_scl_stretch_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_fifo_size	2	0	2	100.00	100	1	1	0
cp_host_mode_stretch	1	0	1	100.00	100	1	1	0
cp_target_scl_stretch_addr_write	1	0	1	100.00	100	1	1	0
cp_tx_fifo_size	2	0	2	100.00	100	1	1	0

Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_target_scl_stretch_read	4	1	3	75.00	100	1	1	0

Summary for Variable cp_acq_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_acq_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

52974593

1

T1

1344

T2

153728

T5

2740

empty

67227565

1

T1

240

T2

1512

T4

97140

---

Summary for Variable cp_host_mode_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins

NAME	COUNT	STATUS
unused	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

stretch

44297829

1

T4

42753

T9

53834

T10

8756

---

Summary for Variable cp_target_scl_stretch_addr_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_target_scl_stretch_addr_write

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
addr_write_byte_stretch	8388	1			T39	7599		T40	789

---

Summary for Variable cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_tx_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

52566467

1

T1

571

T2

153581

T5

2629

empty

67635691

1

T1

1013

T2

1659

T4

97140

---

Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	1	3	75.00	1
Automatically Generated Cross Bins	2	1	1	50.00	1
User Defined Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for cp_target_scl_stretch_read

Uncovered bins

cp_acq_fifo_size	cp_tx_fifo_size	COUNT	AT LEAST	NUMBER	STATUS
[empty]	[not_empty]	0	1	1

Covered bins

cp_acq_fifo_size

cp_tx_fifo_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

empty

empty

636147

1

T1

240

T2

1512

T5

119

User Defined Cross Bins for cp_target_scl_stretch_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_byte_stretch

324882

1

T1

773

T2

147

T5

111

scl_stretch_read_request

52891246

1

T1

1344

T2

153728

T5

2740