Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	92175	1			T1	2		T2	3		T4	3
all_pins[1]	92175	1			T1	2		T2	3		T4	3
all_pins[2]	92175	1			T1	2		T2	3		T4	3
all_pins[3]	92175	1			T1	2		T2	3		T4	3
all_pins[4]	92175	1			T1	2		T2	3		T4	3
all_pins[5]	92175	1			T1	2		T2	3		T4	3
all_pins[6]	92175	1			T1	2		T2	3		T4	3
all_pins[7]	92175	1			T1	2		T2	3		T4	3
all_pins[8]	92175	1			T1	2		T2	3		T4	3
all_pins[9]	92175	1			T1	2		T2	3		T4	3
all_pins[10]	92175	1			T1	2		T2	3		T4	3
all_pins[11]	92175	1			T1	2		T2	3		T4	3
all_pins[12]	92175	1			T1	2		T2	3		T4	3
all_pins[13]	92175	1			T1	2		T2	3		T4	3
all_pins[14]	92175	1			T1	2		T2	3		T4	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1192681	1			T1	26		T2	40		T4	37
values[0x1]	189944	1			T1	4		T2	5		T4	8
transitions[0x0=>0x1]	184734	1			T1	4		T2	5		T4	5
transitions[0x1=>0x0]	183852	1			T1	3		T2	4		T4	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	25964	1			T4	1		T9	17		T10	1
all_pins[0]	values[0x1]	66211	1			T1	2		T2	3		T4	2
all_pins[0]	transitions[0x0=>0x1]	66118	1			T1	2		T2	3		T4	2
all_pins[0]	transitions[0x1=>0x0]	75	1			T29	2		T14	1		T228	1
all_pins[1]	values[0x0]	92007	1			T1	2		T2	3		T4	3
all_pins[1]	values[0x1]	168	1			T29	2		T14	4		T208	3
all_pins[1]	transitions[0x0=>0x1]	148	1			T29	2		T14	3		T208	3
all_pins[1]	transitions[0x1=>0x0]	57	1			T29	2		T14	1		T25	1
all_pins[2]	values[0x0]	92098	1			T1	2		T2	3		T4	3
all_pins[2]	values[0x1]	77	1			T29	2		T14	2		T25	1
all_pins[2]	transitions[0x0=>0x1]	64	1			T29	2		T14	2		T25	1
all_pins[2]	transitions[0x1=>0x0]	68	1			T14	3		T25	3		T26	2
all_pins[3]	values[0x0]	92094	1			T1	2		T2	3		T4	3
all_pins[3]	values[0x1]	81	1			T14	3		T25	3		T26	2
all_pins[3]	transitions[0x0=>0x1]	59	1			T14	2		T25	3		T26	2
all_pins[3]	transitions[0x1=>0x0]	86	1			T29	1		T14	1		T229	1
all_pins[4]	values[0x0]	92067	1			T1	2		T2	3		T4	3
all_pins[4]	values[0x1]	108	1			T29	1		T14	2		T229	1
all_pins[4]	transitions[0x0=>0x1]	80	1			T14	2		T229	1		T26	2
all_pins[4]	transitions[0x1=>0x0]	65	1			T29	4		T14	3		T26	4
all_pins[5]	values[0x0]	92082	1			T1	2		T2	3		T4	3
all_pins[5]	values[0x1]	93	1			T29	5		T14	3		T26	5
all_pins[5]	transitions[0x0=>0x1]	63	1			T29	2		T14	3		T26	4
all_pins[5]	transitions[0x1=>0x0]	1964	1			T4	1		T9	9		T10	1
all_pins[6]	values[0x0]	90181	1			T1	2		T2	3		T4	2
all_pins[6]	values[0x1]	1994	1			T4	1		T9	9		T10	1
all_pins[6]	transitions[0x0=>0x1]	1173	1			T9	6		T35	13		T36	1
all_pins[6]	transitions[0x1=>0x0]	22975	1			T9	92		T35	130		T17	96
all_pins[7]	values[0x0]	68379	1			T1	2		T2	3		T4	2
all_pins[7]	values[0x1]	23796	1			T4	1		T9	95		T10	1
all_pins[7]	transitions[0x0=>0x1]	20836	1			T9	74		T35	121		T29	2
all_pins[7]	transitions[0x1=>0x0]	4595	1			T9	17		T35	45		T29	1
all_pins[8]	values[0x0]	84620	1			T1	2		T2	3		T4	2
all_pins[8]	values[0x1]	7555	1			T4	1		T9	38		T10	1
all_pins[8]	transitions[0x0=>0x1]	6464	1			T9	33		T35	49		T29	4
all_pins[8]	transitions[0x1=>0x0]	1827	1			T2	1		T7	1		T9	5
all_pins[9]	values[0x0]	89257	1			T1	2		T2	2		T4	2
all_pins[9]	values[0x1]	2918	1			T2	1		T4	1		T7	1
all_pins[9]	transitions[0x0=>0x1]	2901	1			T2	1		T4	1		T7	1
all_pins[9]	transitions[0x1=>0x0]	75	1			T29	4		T14	6		T26	2
all_pins[10]	values[0x0]	92083	1			T1	2		T2	3		T4	3
all_pins[10]	values[0x1]	92	1			T29	4		T14	7		T26	4
all_pins[10]	transitions[0x0=>0x1]	73	1			T29	3		T14	6		T26	3
all_pins[10]	transitions[0x1=>0x0]	86559	1			T1	2		T2	1		T4	2
all_pins[11]	values[0x0]	5597	1			T2	2		T4	1		T9	3
all_pins[11]	values[0x1]	86578	1			T1	2		T2	1		T4	2
all_pins[11]	transitions[0x0=>0x1]	86561	1			T1	2		T2	1		T4	2
all_pins[11]	transitions[0x1=>0x0]	63	1			T29	1		T14	1		T25	1
all_pins[12]	values[0x0]	92095	1			T1	2		T2	3		T4	3
all_pins[12]	values[0x1]	80	1			T29	1		T14	1		T25	2
all_pins[12]	transitions[0x0=>0x1]	61	1			T29	1		T14	1		T25	2
all_pins[12]	transitions[0x1=>0x0]	80	1			T29	3		T14	1		T214	1
all_pins[13]	values[0x0]	92076	1			T1	2		T2	3		T4	3
all_pins[13]	values[0x1]	99	1			T29	3		T14	1		T214	1
all_pins[13]	transitions[0x0=>0x1]	72	1			T29	1		T14	1		T214	1
all_pins[13]	transitions[0x1=>0x0]	67	1			T29	1		T14	4		T26	2
all_pins[14]	values[0x0]	92081	1			T1	2		T2	3		T4	3
all_pins[14]	values[0x1]	94	1			T29	3		T14	4		T26	2
all_pins[14]	transitions[0x0=>0x1]	61	1			T29	3		T14	3		T26	2
all_pins[14]	transitions[0x1=>0x0]	65296	1			T1	1		T2	2		T4	1