Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	392	1			T29	11		T14	15		T25	4
all_values[1]	392	1			T29	11		T14	15		T25	4
all_values[2]	392	1			T29	11		T14	15		T25	4
all_values[3]	392	1			T29	11		T14	15		T25	4
all_values[4]	392	1			T29	11		T14	15		T25	4
all_values[5]	392	1			T29	11		T14	15		T25	4
all_values[6]	392	1			T29	11		T14	15		T25	4
all_values[7]	392	1			T29	11		T14	15		T25	4
all_values[8]	392	1			T29	11		T14	15		T25	4
all_values[9]	392	1			T29	11		T14	15		T25	4
all_values[10]	392	1			T29	11		T14	15		T25	4
all_values[11]	392	1			T29	11		T14	15		T25	4
all_values[12]	392	1			T29	11		T14	15		T25	4
all_values[13]	392	1			T29	11		T14	15		T25	4
all_values[14]	392	1			T29	11		T14	15		T25	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3070

1

T29

72

T14

112

T25

26

auto[1]

2810

1

T29

93

T14

113

T25

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

921

1

T29

7

T14

22

T25

14

auto[1]

4959

1

T29

158

T14

203

T25

46

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3416

1

T29

92

T14

133

T25

36

auto[1]

2464

1

T29

73

T14

92

T25

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	34	1			T230	1		T231	1		T232	2
all_values[0]	auto[0]	auto[0]	auto[1]	82	1			T29	4		T14	3		T25	3
all_values[0]	auto[0]	auto[1]	auto[0]	32	1			T26	1		T222	2		T230	3
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T29	4		T14	5		T26	6
all_values[0]	auto[1]	auto[0]	auto[1]	91	1			T29	2		T14	4		T26	3
all_values[0]	auto[1]	auto[1]	auto[1]	71	1			T29	1		T14	3		T25	1
all_values[1]	auto[0]	auto[0]	auto[0]	30	1			T233	1		T222	1		T160	2
all_values[1]	auto[0]	auto[0]	auto[1]	88	1			T29	4		T14	5		T25	1
all_values[1]	auto[0]	auto[1]	auto[0]	20	1			T25	1		T233	1		T222	1
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T29	2		T14	5		T26	4
all_values[1]	auto[1]	auto[0]	auto[1]	78	1			T29	3		T14	2		T25	2
all_values[1]	auto[1]	auto[1]	auto[1]	97	1			T29	2		T14	3		T26	5
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T14	4		T234	1		T235	2
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T25	1		T26	5		T233	4
all_values[2]	auto[0]	auto[1]	auto[0]	37	1			T14	5		T233	1		T222	2
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T29	8		T14	3		T25	1
all_values[2]	auto[1]	auto[0]	auto[1]	92	1			T29	1		T14	1		T25	1
all_values[2]	auto[1]	auto[1]	auto[1]	70	1			T29	2		T14	2		T25	1
all_values[3]	auto[0]	auto[0]	auto[0]	33	1			T222	1		T231	1		T236	1
all_values[3]	auto[0]	auto[0]	auto[1]	97	1			T29	4		T14	8		T25	1
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T233	1		T222	1		T230	4
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T29	1		T14	2		T25	1
all_values[3]	auto[1]	auto[0]	auto[1]	88	1			T29	6		T14	1		T26	1
all_values[3]	auto[1]	auto[1]	auto[1]	68	1			T14	4		T25	2		T26	5
all_values[4]	auto[0]	auto[0]	auto[0]	31	1			T233	1		T237	1		T162	2
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T29	2		T14	4		T26	6
all_values[4]	auto[0]	auto[1]	auto[0]	27	1			T14	1		T25	1		T26	1
all_values[4]	auto[0]	auto[1]	auto[1]	87	1			T29	5		T14	2		T25	2
all_values[4]	auto[1]	auto[0]	auto[1]	75	1			T29	3		T14	4		T26	1
all_values[4]	auto[1]	auto[1]	auto[1]	85	1			T29	1		T14	4		T25	1
all_values[5]	auto[0]	auto[0]	auto[0]	30	1			T25	1		T238	1		T239	1
all_values[5]	auto[0]	auto[0]	auto[1]	80	1			T29	3		T14	4		T26	2
all_values[5]	auto[0]	auto[1]	auto[0]	27	1			T29	2		T14	1		T25	3
all_values[5]	auto[0]	auto[1]	auto[1]	100	1			T29	1		T14	3		T26	4
all_values[5]	auto[1]	auto[0]	auto[1]	73	1			T29	1		T14	4		T26	3
all_values[5]	auto[1]	auto[1]	auto[1]	82	1			T29	4		T14	3		T26	3
all_values[6]	auto[0]	auto[0]	auto[0]	25	1			T26	1		T234	1		T240	1
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T29	2		T14	3		T25	1
all_values[6]	auto[0]	auto[1]	auto[0]	23	1			T29	1		T14	1		T26	1
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T29	1		T14	2		T25	1
all_values[6]	auto[1]	auto[0]	auto[1]	91	1			T29	2		T14	6		T25	1
all_values[6]	auto[1]	auto[1]	auto[1]	84	1			T29	5		T14	3		T25	1
all_values[7]	auto[0]	auto[0]	auto[0]	38	1			T238	2		T230	1		T162	1
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T29	2		T14	6		T25	1
all_values[7]	auto[0]	auto[1]	auto[0]	32	1			T25	1		T222	1		T238	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T29	3		T14	2		T26	3
all_values[7]	auto[1]	auto[0]	auto[1]	95	1			T29	3		T14	2		T25	1
all_values[7]	auto[1]	auto[1]	auto[1]	73	1			T29	3		T14	5		T25	1
all_values[8]	auto[0]	auto[0]	auto[0]	37	1			T230	1		T160	2		T234	3
all_values[8]	auto[0]	auto[0]	auto[1]	85	1			T14	3		T25	1		T26	3
all_values[8]	auto[0]	auto[1]	auto[0]	22	1			T29	1		T14	1		T233	4
all_values[8]	auto[0]	auto[1]	auto[1]	76	1			T29	5		T14	3		T25	2
all_values[8]	auto[1]	auto[0]	auto[1]	95	1			T29	1		T14	4		T26	4
all_values[8]	auto[1]	auto[1]	auto[1]	77	1			T29	4		T14	4		T25	1
all_values[9]	auto[0]	auto[0]	auto[0]	27	1			T238	1		T239	1		T241	1
all_values[9]	auto[0]	auto[0]	auto[1]	93	1			T29	6		T14	6		T25	1
all_values[9]	auto[0]	auto[1]	auto[0]	23	1			T14	1		T222	2		T238	1
all_values[9]	auto[0]	auto[1]	auto[1]	79	1			T29	1		T14	2		T26	3
all_values[9]	auto[1]	auto[0]	auto[1]	98	1			T29	2		T14	1		T25	1
all_values[9]	auto[1]	auto[1]	auto[1]	72	1			T29	2		T14	5		T25	2
all_values[10]	auto[0]	auto[0]	auto[0]	39	1			T25	1		T26	1		T161	2
all_values[10]	auto[0]	auto[0]	auto[1]	71	1			T29	1		T14	2		T25	1
all_values[10]	auto[0]	auto[1]	auto[0]	29	1			T29	1		T25	1		T26	1
all_values[10]	auto[0]	auto[1]	auto[1]	89	1			T29	2		T14	5		T26	4
all_values[10]	auto[1]	auto[0]	auto[1]	76	1			T29	2		T14	2		T25	1
all_values[10]	auto[1]	auto[1]	auto[1]	88	1			T29	5		T14	6		T26	1
all_values[11]	auto[0]	auto[0]	auto[0]	29	1			T160	1		T161	2		T163	2
all_values[11]	auto[0]	auto[0]	auto[1]	96	1			T29	1		T14	6		T26	5
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T14	1		T25	1		T26	1
all_values[11]	auto[0]	auto[1]	auto[1]	82	1			T29	5		T14	4		T25	1
all_values[11]	auto[1]	auto[0]	auto[1]	97	1			T29	3		T25	1		T26	2
all_values[11]	auto[1]	auto[1]	auto[1]	64	1			T29	2		T14	4		T25	1
all_values[12]	auto[0]	auto[0]	auto[0]	35	1			T14	3		T233	1		T232	2
all_values[12]	auto[0]	auto[0]	auto[1]	75	1			T29	3		T14	5		T25	1
all_values[12]	auto[0]	auto[1]	auto[0]	24	1			T29	1		T14	2		T238	1
all_values[12]	auto[0]	auto[1]	auto[1]	90	1			T29	3		T14	1		T26	1
all_values[12]	auto[1]	auto[0]	auto[1]	96	1			T29	2		T14	4		T26	4
all_values[12]	auto[1]	auto[1]	auto[1]	72	1			T29	2		T25	3		T26	4
all_values[13]	auto[0]	auto[0]	auto[0]	46	1			T26	2		T160	2		T161	1
all_values[13]	auto[0]	auto[0]	auto[1]	75	1			T29	1		T14	8		T25	1
all_values[13]	auto[0]	auto[1]	auto[0]	28	1			T26	1		T222	1		T238	1
all_values[13]	auto[0]	auto[1]	auto[1]	86	1			T29	4		T14	2		T25	1
all_values[13]	auto[1]	auto[0]	auto[1]	79	1			T29	3		T14	2		T25	1
all_values[13]	auto[1]	auto[1]	auto[1]	78	1			T29	3		T14	3		T25	1
all_values[14]	auto[0]	auto[0]	auto[0]	36	1			T25	2		T233	2		T222	1
all_values[14]	auto[0]	auto[0]	auto[1]	83	1			T29	4		T14	2		T26	5
all_values[14]	auto[0]	auto[1]	auto[0]	38	1			T29	1		T14	2		T25	2
all_values[14]	auto[0]	auto[1]	auto[1]	76	1			T29	3		T14	5		T26	3
all_values[14]	auto[1]	auto[0]	auto[1]	90	1			T29	1		T14	3		T26	4
all_values[14]	auto[1]	auto[1]	auto[1]	69	1			T29	2		T14	3		T26	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal