Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.32 97.79 91.54 97.65 46.79 95.29 98.23 90.97


Total test records in report: 1318
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T1256 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2505166422 Apr 04 01:27:08 PM PDT 24 Apr 04 01:27:09 PM PDT 24 58965349 ps
T1257 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3004042405 Apr 04 01:25:36 PM PDT 24 Apr 04 01:25:38 PM PDT 24 117001779 ps
T1258 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3783957253 Apr 04 01:27:00 PM PDT 24 Apr 04 01:27:03 PM PDT 24 350551369 ps
T119 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2625833166 Apr 04 01:26:12 PM PDT 24 Apr 04 01:26:14 PM PDT 24 154070528 ps
T1259 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1142196366 Apr 04 01:26:55 PM PDT 24 Apr 04 01:26:56 PM PDT 24 29775280 ps
T113 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2438676743 Apr 04 01:27:00 PM PDT 24 Apr 04 01:27:02 PM PDT 24 84124006 ps
T1260 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1802118917 Apr 04 01:26:11 PM PDT 24 Apr 04 01:26:12 PM PDT 24 140298743 ps
T1261 /workspace/coverage/cover_reg_top/34.i2c_intr_test.999175666 Apr 04 01:27:17 PM PDT 24 Apr 04 01:27:18 PM PDT 24 20323091 ps
T1262 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1620976563 Apr 04 01:26:10 PM PDT 24 Apr 04 01:26:11 PM PDT 24 27019548 ps
T200 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2893703112 Apr 04 01:26:57 PM PDT 24 Apr 04 01:26:58 PM PDT 24 353238933 ps
T139 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3956100591 Apr 04 01:25:58 PM PDT 24 Apr 04 01:26:00 PM PDT 24 166426457 ps
T1263 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.306721747 Apr 04 01:26:59 PM PDT 24 Apr 04 01:27:01 PM PDT 24 268519423 ps
T1264 /workspace/coverage/cover_reg_top/17.i2c_intr_test.3856734136 Apr 04 01:26:54 PM PDT 24 Apr 04 01:26:55 PM PDT 24 76022140 ps
T1265 /workspace/coverage/cover_reg_top/27.i2c_intr_test.1933144319 Apr 04 01:27:07 PM PDT 24 Apr 04 01:27:08 PM PDT 24 55644330 ps
T1266 /workspace/coverage/cover_reg_top/3.i2c_intr_test.3601793050 Apr 04 01:25:57 PM PDT 24 Apr 04 01:25:58 PM PDT 24 15426299 ps
T1267 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3740502889 Apr 04 01:27:07 PM PDT 24 Apr 04 01:27:08 PM PDT 24 70079756 ps
T1268 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1452634220 Apr 04 01:26:23 PM PDT 24 Apr 04 01:26:24 PM PDT 24 76766730 ps
T1269 /workspace/coverage/cover_reg_top/35.i2c_intr_test.2667096595 Apr 04 01:27:11 PM PDT 24 Apr 04 01:27:12 PM PDT 24 63394245 ps
T1270 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4036897640 Apr 04 01:27:07 PM PDT 24 Apr 04 01:27:07 PM PDT 24 81750195 ps
T1271 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3788227832 Apr 04 01:26:47 PM PDT 24 Apr 04 01:26:48 PM PDT 24 80323721 ps
T1272 /workspace/coverage/cover_reg_top/19.i2c_intr_test.296990371 Apr 04 01:27:07 PM PDT 24 Apr 04 01:27:08 PM PDT 24 23659954 ps
T1273 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3097964208 Apr 04 01:26:09 PM PDT 24 Apr 04 01:26:11 PM PDT 24 40080319 ps
T1274 /workspace/coverage/cover_reg_top/28.i2c_intr_test.1768415740 Apr 04 01:27:07 PM PDT 24 Apr 04 01:27:08 PM PDT 24 47164170 ps
T1275 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2900454625 Apr 04 01:26:55 PM PDT 24 Apr 04 01:26:56 PM PDT 24 32376377 ps
T1276 /workspace/coverage/cover_reg_top/30.i2c_intr_test.390893931 Apr 04 01:27:15 PM PDT 24 Apr 04 01:27:16 PM PDT 24 17055723 ps
T1277 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3425860435 Apr 04 01:26:24 PM PDT 24 Apr 04 01:26:25 PM PDT 24 98081413 ps
T1278 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2638864100 Apr 04 01:25:50 PM PDT 24 Apr 04 01:25:52 PM PDT 24 26869647 ps
T1279 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1080157683 Apr 04 01:26:59 PM PDT 24 Apr 04 01:26:59 PM PDT 24 16416071 ps
T1280 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.102396788 Apr 04 01:26:35 PM PDT 24 Apr 04 01:26:36 PM PDT 24 19605540 ps
T1281 /workspace/coverage/cover_reg_top/9.i2c_intr_test.755935290 Apr 04 01:26:34 PM PDT 24 Apr 04 01:26:35 PM PDT 24 149891961 ps
T1282 /workspace/coverage/cover_reg_top/1.i2c_intr_test.536624300 Apr 04 01:25:47 PM PDT 24 Apr 04 01:25:48 PM PDT 24 19174712 ps
T1283 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1633296143 Apr 04 01:26:58 PM PDT 24 Apr 04 01:27:01 PM PDT 24 491081552 ps
T1284 /workspace/coverage/cover_reg_top/46.i2c_intr_test.512134849 Apr 04 01:27:08 PM PDT 24 Apr 04 01:27:09 PM PDT 24 16256344 ps
T1285 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3043161655 Apr 04 01:26:46 PM PDT 24 Apr 04 01:26:48 PM PDT 24 414096014 ps
T1286 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2769280344 Apr 04 01:26:37 PM PDT 24 Apr 04 01:26:37 PM PDT 24 53960824 ps
T1287 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3106303521 Apr 04 01:27:11 PM PDT 24 Apr 04 01:27:11 PM PDT 24 18699167 ps
T1288 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3314147834 Apr 04 01:27:10 PM PDT 24 Apr 04 01:27:11 PM PDT 24 60415443 ps
T1289 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1529577887 Apr 04 01:27:08 PM PDT 24 Apr 04 01:27:08 PM PDT 24 17730268 ps
T1290 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1019101307 Apr 04 01:26:34 PM PDT 24 Apr 04 01:26:35 PM PDT 24 55833263 ps
T1291 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4030350264 Apr 04 01:27:11 PM PDT 24 Apr 04 01:27:12 PM PDT 24 15951049 ps
T1292 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.665852291 Apr 04 01:26:34 PM PDT 24 Apr 04 01:26:35 PM PDT 24 18998180 ps
T1293 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3630492263 Apr 04 01:26:34 PM PDT 24 Apr 04 01:26:36 PM PDT 24 29343994 ps
T1294 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1256785674 Apr 04 01:26:48 PM PDT 24 Apr 04 01:26:49 PM PDT 24 103550360 ps
T1295 /workspace/coverage/cover_reg_top/16.i2c_intr_test.472117202 Apr 04 01:27:00 PM PDT 24 Apr 04 01:27:01 PM PDT 24 51408104 ps
T1296 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.490046097 Apr 04 01:27:10 PM PDT 24 Apr 04 01:27:11 PM PDT 24 35733358 ps
T1297 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1326684730 Apr 04 01:26:27 PM PDT 24 Apr 04 01:26:28 PM PDT 24 89553086 ps
T1298 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1943684165 Apr 04 01:27:10 PM PDT 24 Apr 04 01:27:11 PM PDT 24 40271855 ps
T1299 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1032769351 Apr 04 01:26:09 PM PDT 24 Apr 04 01:26:10 PM PDT 24 122342153 ps
T1300 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.930391010 Apr 04 01:26:01 PM PDT 24 Apr 04 01:26:01 PM PDT 24 48267587 ps
T1301 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1099667623 Apr 04 01:26:12 PM PDT 24 Apr 04 01:26:13 PM PDT 24 259420582 ps
T1302 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1069735392 Apr 04 01:26:49 PM PDT 24 Apr 04 01:26:50 PM PDT 24 27782853 ps
T1303 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2567602448 Apr 04 01:27:11 PM PDT 24 Apr 04 01:27:12 PM PDT 24 20428926 ps
T1304 /workspace/coverage/cover_reg_top/21.i2c_intr_test.167171618 Apr 04 01:27:08 PM PDT 24 Apr 04 01:27:09 PM PDT 24 16209259 ps
T1305 /workspace/coverage/cover_reg_top/42.i2c_intr_test.205522204 Apr 04 01:27:13 PM PDT 24 Apr 04 01:27:14 PM PDT 24 18644704 ps
T1306 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.916331687 Apr 04 01:25:49 PM PDT 24 Apr 04 01:25:50 PM PDT 24 212128432 ps
T1307 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1548578282 Apr 04 01:26:24 PM PDT 24 Apr 04 01:26:25 PM PDT 24 25734305 ps
T1308 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.299836675 Apr 04 01:25:59 PM PDT 24 Apr 04 01:26:00 PM PDT 24 25101868 ps
T1309 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2809620244 Apr 04 01:26:12 PM PDT 24 Apr 04 01:26:12 PM PDT 24 18069656 ps
T1310 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1996967419 Apr 04 01:27:08 PM PDT 24 Apr 04 01:27:09 PM PDT 24 50549190 ps
T1311 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1107778639 Apr 04 01:26:58 PM PDT 24 Apr 04 01:27:01 PM PDT 24 138001070 ps
T140 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2593668412 Apr 04 01:26:10 PM PDT 24 Apr 04 01:26:12 PM PDT 24 57464756 ps
T1312 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1237998547 Apr 04 01:25:59 PM PDT 24 Apr 04 01:26:03 PM PDT 24 204564318 ps
T1313 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.929688113 Apr 04 01:25:59 PM PDT 24 Apr 04 01:26:00 PM PDT 24 20009057 ps
T1314 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3104749206 Apr 04 01:26:00 PM PDT 24 Apr 04 01:26:01 PM PDT 24 26797297 ps
T1315 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4191119004 Apr 04 01:26:57 PM PDT 24 Apr 04 01:26:58 PM PDT 24 26044090 ps
T1316 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1769452775 Apr 04 01:25:59 PM PDT 24 Apr 04 01:26:00 PM PDT 24 62626418 ps
T1317 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1058616000 Apr 04 01:26:57 PM PDT 24 Apr 04 01:26:58 PM PDT 24 67404915 ps
T1318 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.756811393 Apr 04 01:26:12 PM PDT 24 Apr 04 01:26:13 PM PDT 24 71579456 ps

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1095052663
Short name T9
Test name
Test status
Simulation time 12277302870 ps
CPU time 20.84 seconds
Started Apr 04 03:06:03 PM PDT 24
Finished Apr 04 03:06:24 PM PDT 24
Peak memory 344056 kb
Host smart-63c0c4f3-6742-4808-8755-3b2892cf8bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095052663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1095052663
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2134467075
Short name T2
Test name
Test status
Simulation time 10105538761 ps
CPU time 81.48 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:04:00 PM PDT 24
Peak memory 594008 kb
Host smart-cf5f49d2-f039-4f35-b2cc-2b6201aadd19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134467075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2134467075
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3788832833
Short name T29
Test name
Test status
Simulation time 2530073561 ps
CPU time 84.8 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:08:46 PM PDT 24
Peak memory 807456 kb
Host smart-07a22ca4-2e80-4aa8-a7c0-93c869cf47ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788832833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3788832833
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.420837651
Short name T71
Test name
Test status
Simulation time 149235542 ps
CPU time 2.15 seconds
Started Apr 04 01:26:56 PM PDT 24
Finished Apr 04 01:26:58 PM PDT 24
Peak memory 203668 kb
Host smart-8895404c-34eb-436d-89c9-c3248287ddf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420837651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.420837651
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3858705234
Short name T40
Test name
Test status
Simulation time 10741233642 ps
CPU time 7.85 seconds
Started Apr 04 03:04:05 PM PDT 24
Finished Apr 04 03:04:13 PM PDT 24
Peak memory 225648 kb
Host smart-6f7e3074-736a-4949-a327-82c127ee7bbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858705234 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3858705234
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_host_override.1025910232
Short name T250
Test name
Test status
Simulation time 27111011 ps
CPU time 0.68 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:17 PM PDT 24
Peak memory 203508 kb
Host smart-215f6cbc-d3d0-4034-bfd4-36925881f320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025910232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1025910232
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3861981806
Short name T229
Test name
Test status
Simulation time 502122083 ps
CPU time 10.34 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:05:21 PM PDT 24
Peak memory 203732 kb
Host smart-05ce9f35-c5f6-4057-91d1-17a7dca666f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861981806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3861981806
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.3387166370
Short name T54
Test name
Test status
Simulation time 10297029525 ps
CPU time 3.48 seconds
Started Apr 04 03:04:03 PM PDT 24
Finished Apr 04 03:04:06 PM PDT 24
Peak memory 204120 kb
Host smart-88d4a70b-6fdb-4c16-83d3-68d9a79eeab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387166370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.3387166370
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.3315216284
Short name T14
Test name
Test status
Simulation time 31733899371 ps
CPU time 329.3 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:12:51 PM PDT 24
Peak memory 1515268 kb
Host smart-24b4c468-8425-4f70-9eab-3b95506485ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315216284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3315216284
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.955434861
Short name T91
Test name
Test status
Simulation time 80664473 ps
CPU time 0.89 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:02:39 PM PDT 24
Peak memory 221264 kb
Host smart-f89f0061-4134-45e9-af04-3f5254e1820f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955434861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.955434861
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.808302800
Short name T110
Test name
Test status
Simulation time 107965993 ps
CPU time 2.12 seconds
Started Apr 04 01:26:58 PM PDT 24
Finished Apr 04 01:27:00 PM PDT 24
Peak memory 203688 kb
Host smart-fe1fe9e2-8360-4583-be7e-d98aaab4802a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808302800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.808302800
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3908849183
Short name T180
Test name
Test status
Simulation time 50908343454 ps
CPU time 1919.48 seconds
Started Apr 04 03:02:45 PM PDT 24
Finished Apr 04 03:34:45 PM PDT 24
Peak memory 3419128 kb
Host smart-215fea3b-aacb-4e7f-bb4a-60e2d6eb7b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908849183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3908849183
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.354028197
Short name T125
Test name
Test status
Simulation time 66046319 ps
CPU time 0.72 seconds
Started Apr 04 01:26:35 PM PDT 24
Finished Apr 04 01:26:36 PM PDT 24
Peak memory 203388 kb
Host smart-8a07ea00-a6ed-47a4-8112-1ba9550c07f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354028197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.354028197
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1072645082
Short name T31
Test name
Test status
Simulation time 1102378278 ps
CPU time 5.46 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:22 PM PDT 24
Peak memory 212344 kb
Host smart-19f171f2-6501-4ca6-841f-3dfb8aedd925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072645082 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1072645082
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3521498274
Short name T222
Test name
Test status
Simulation time 35284603852 ps
CPU time 1980.46 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:37:49 PM PDT 24
Peak memory 2559764 kb
Host smart-6f0ee972-58ed-4717-b14b-500322e77295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521498274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3521498274
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1709197516
Short name T206
Test name
Test status
Simulation time 1036965159 ps
CPU time 1.81 seconds
Started Apr 04 03:07:01 PM PDT 24
Finished Apr 04 03:07:03 PM PDT 24
Peak memory 203752 kb
Host smart-ac497295-4c30-4676-86b4-d3c5e373b630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709197516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1709197516
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1745411236
Short name T190
Test name
Test status
Simulation time 72750519 ps
CPU time 0.82 seconds
Started Apr 04 03:04:02 PM PDT 24
Finished Apr 04 03:04:02 PM PDT 24
Peak memory 203604 kb
Host smart-e3563017-83f2-4876-ab89-09c1e20635f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745411236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1745411236
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.309456612
Short name T1251
Test name
Test status
Simulation time 48478418 ps
CPU time 0.67 seconds
Started Apr 04 01:27:14 PM PDT 24
Finished Apr 04 01:27:15 PM PDT 24
Peak memory 203324 kb
Host smart-cfda1231-cd8b-4c0f-83fc-d774db62ea3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309456612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.309456612
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3868745746
Short name T57
Test name
Test status
Simulation time 18168670418 ps
CPU time 666.02 seconds
Started Apr 04 03:03:59 PM PDT 24
Finished Apr 04 03:15:05 PM PDT 24
Peak memory 1444784 kb
Host smart-652e34cb-a00d-4bd6-9818-1ebe2f16cba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868745746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3868745746
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2929540286
Short name T262
Test name
Test status
Simulation time 89784623 ps
CPU time 2.52 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:18 PM PDT 24
Peak memory 214416 kb
Host smart-326b6d80-a71c-47cc-ba9a-49534de080b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929540286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2929540286
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3647809143
Short name T258
Test name
Test status
Simulation time 14977088 ps
CPU time 0.58 seconds
Started Apr 04 03:02:45 PM PDT 24
Finished Apr 04 03:02:46 PM PDT 24
Peak memory 203640 kb
Host smart-639d4446-f7c9-4c13-9399-40e1cad544f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647809143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3647809143
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.828361648
Short name T15
Test name
Test status
Simulation time 44463740834 ps
CPU time 574.24 seconds
Started Apr 04 03:05:12 PM PDT 24
Finished Apr 04 03:14:46 PM PDT 24
Peak memory 2276648 kb
Host smart-df0596d1-7c26-45ed-9952-02d96bb4ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828361648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.828361648
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1377531869
Short name T247
Test name
Test status
Simulation time 1499987320 ps
CPU time 7.14 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:29 PM PDT 24
Peak memory 218852 kb
Host smart-af4e1195-6936-4707-b385-eda5eb8622c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377531869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1377531869
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.739530507
Short name T25
Test name
Test status
Simulation time 14355606758 ps
CPU time 2244.97 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:43:45 PM PDT 24
Peak memory 2784188 kb
Host smart-740c7143-4c4c-4937-b2b8-71b360dae230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739530507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.739530507
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1348674994
Short name T78
Test name
Test status
Simulation time 2466802433 ps
CPU time 61.71 seconds
Started Apr 04 03:06:44 PM PDT 24
Finished Apr 04 03:07:46 PM PDT 24
Peak memory 785772 kb
Host smart-7875b20f-b815-4150-bb09-aa05f17c8d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348674994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1348674994
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.731386587
Short name T116
Test name
Test status
Simulation time 119456160 ps
CPU time 2.15 seconds
Started Apr 04 01:25:37 PM PDT 24
Finished Apr 04 01:25:39 PM PDT 24
Peak memory 203628 kb
Host smart-457658dc-62f4-423d-ad49-43a520fa31b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731386587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.731386587
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1742861956
Short name T95
Test name
Test status
Simulation time 60924441 ps
CPU time 0.92 seconds
Started Apr 04 03:02:45 PM PDT 24
Finished Apr 04 03:02:46 PM PDT 24
Peak memory 221276 kb
Host smart-22cdde82-9fc9-42cf-ba94-13b4886e26b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742861956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1742861956
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_host_override.2953374092
Short name T103
Test name
Test status
Simulation time 54410283 ps
CPU time 0.65 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:02:39 PM PDT 24
Peak memory 203544 kb
Host smart-8dfd633e-b333-47cb-b711-5dafe436ce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953374092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2953374092
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2893703112
Short name T200
Test name
Test status
Simulation time 353238933 ps
CPU time 1.05 seconds
Started Apr 04 01:26:57 PM PDT 24
Finished Apr 04 01:26:58 PM PDT 24
Peak memory 203692 kb
Host smart-0dbc1565-9ce6-4c3e-b5dd-2310e90497da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893703112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2893703112
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1213925969
Short name T216
Test name
Test status
Simulation time 1795697870 ps
CPU time 2.64 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:08 PM PDT 24
Peak memory 203668 kb
Host smart-c3472194-c7dc-4c2f-8b78-6b126d3c43de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213925969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1213925969
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1487164803
Short name T187
Test name
Test status
Simulation time 10442268548 ps
CPU time 17.23 seconds
Started Apr 04 03:04:17 PM PDT 24
Finished Apr 04 03:04:35 PM PDT 24
Peak memory 327900 kb
Host smart-a7f5a4e2-59a5-440c-992f-019d0cc5c785
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487164803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1487164803
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2798186514
Short name T157
Test name
Test status
Simulation time 23662334532 ps
CPU time 1691.35 seconds
Started Apr 04 03:05:14 PM PDT 24
Finished Apr 04 03:33:25 PM PDT 24
Peak memory 5494176 kb
Host smart-f1c842f0-85ab-4559-8c47-0996444fa08f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798186514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2798186514
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1825483620
Short name T193
Test name
Test status
Simulation time 154607221 ps
CPU time 1.06 seconds
Started Apr 04 03:05:48 PM PDT 24
Finished Apr 04 03:05:50 PM PDT 24
Peak memory 203616 kb
Host smart-8c3a3f8b-c20f-4c26-a549-26f72019dbc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825483620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1825483620
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.382030326
Short name T241
Test name
Test status
Simulation time 21031311 ps
CPU time 0.63 seconds
Started Apr 04 01:26:46 PM PDT 24
Finished Apr 04 01:26:47 PM PDT 24
Peak memory 203344 kb
Host smart-7fa3533c-d892-43c1-afb8-454607ea0182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382030326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.382030326
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2845939506
Short name T223
Test name
Test status
Simulation time 15913540272 ps
CPU time 97.67 seconds
Started Apr 04 03:02:36 PM PDT 24
Finished Apr 04 03:04:14 PM PDT 24
Peak memory 838368 kb
Host smart-9dbf0e48-f7d1-47c6-a5ee-e5b36bbc21e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845939506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2845939506
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1703373528
Short name T227
Test name
Test status
Simulation time 2513542730 ps
CPU time 166.22 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:07:01 PM PDT 24
Peak memory 803380 kb
Host smart-9752493f-c2a7-4249-8f35-3dbb82b95796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703373528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1703373528
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.540079725
Short name T244
Test name
Test status
Simulation time 10104517093 ps
CPU time 72.34 seconds
Started Apr 04 03:04:31 PM PDT 24
Finished Apr 04 03:05:44 PM PDT 24
Peak memory 574388 kb
Host smart-f751dd69-5455-467a-8528-b1b6918815b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540079725 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.540079725
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.364601807
Short name T221
Test name
Test status
Simulation time 14684509190 ps
CPU time 86.8 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:05:57 PM PDT 24
Peak memory 1055668 kb
Host smart-600c227c-cd0f-4e34-827a-35c6233990da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364601807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.364601807
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_perf.4017651464
Short name T184
Test name
Test status
Simulation time 5860494046 ps
CPU time 35.75 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:05:24 PM PDT 24
Peak memory 228084 kb
Host smart-c56cd96d-2af3-414e-a2ec-8b5f655dd37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017651464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.4017651464
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.422395781
Short name T1201
Test name
Test status
Simulation time 620380205 ps
CPU time 3.75 seconds
Started Apr 04 03:02:44 PM PDT 24
Finished Apr 04 03:02:47 PM PDT 24
Peak memory 203688 kb
Host smart-1784253b-cc3c-4c36-adce-6fb3e22f0f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422395781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.422395781
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1001311712
Short name T243
Test name
Test status
Simulation time 10270456267 ps
CPU time 30.48 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:06:05 PM PDT 24
Peak memory 354472 kb
Host smart-7b479286-9e15-4439-b827-876bcbbfdf9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001311712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1001311712
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1448086437
Short name T219
Test name
Test status
Simulation time 3049439957 ps
CPU time 236.08 seconds
Started Apr 04 03:02:50 PM PDT 24
Finished Apr 04 03:06:47 PM PDT 24
Peak memory 962224 kb
Host smart-e5144f23-f24e-4bb1-9319-5ebc7be3378a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448086437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1448086437
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1069281089
Short name T1216
Test name
Test status
Simulation time 95634464 ps
CPU time 1.77 seconds
Started Apr 04 01:25:51 PM PDT 24
Finished Apr 04 01:25:53 PM PDT 24
Peak memory 203632 kb
Host smart-8932c7cd-7987-4ef9-8510-29176a976912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069281089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1069281089
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.375298147
Short name T62
Test name
Test status
Simulation time 10082290814 ps
CPU time 39.78 seconds
Started Apr 04 03:05:25 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 460404 kb
Host smart-edce4a79-ab52-4e7e-af5a-3dd47ef3ded0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375298147 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.i2c_target_fifo_reset_tx.375298147
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.948772527
Short name T112
Test name
Test status
Simulation time 66942176 ps
CPU time 1.35 seconds
Started Apr 04 01:25:50 PM PDT 24
Finished Apr 04 01:25:51 PM PDT 24
Peak memory 203688 kb
Host smart-3f69a372-970d-44a5-8700-1efcc4edac1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948772527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.948772527
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1617663435
Short name T123
Test name
Test status
Simulation time 90614020 ps
CPU time 2.19 seconds
Started Apr 04 01:26:34 PM PDT 24
Finished Apr 04 01:26:36 PM PDT 24
Peak memory 203624 kb
Host smart-e6de3cc5-095e-42d0-a84a-9afe1cad0b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617663435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1617663435
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3582163111
Short name T117
Test name
Test status
Simulation time 132494355 ps
CPU time 1.39 seconds
Started Apr 04 01:26:57 PM PDT 24
Finished Apr 04 01:26:58 PM PDT 24
Peak memory 203620 kb
Host smart-e43e6ebd-a1ad-4b4b-9557-61d80b951cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582163111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3582163111
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2195355446
Short name T962
Test name
Test status
Simulation time 10229371309 ps
CPU time 37.86 seconds
Started Apr 04 03:02:36 PM PDT 24
Finished Apr 04 03:03:14 PM PDT 24
Peak memory 417960 kb
Host smart-6ce20f3d-8944-4034-a392-fc2d159c69df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195355446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2195355446
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2709693656
Short name T138
Test name
Test status
Simulation time 42345367 ps
CPU time 1.63 seconds
Started Apr 04 01:25:49 PM PDT 24
Finished Apr 04 01:25:51 PM PDT 24
Peak memory 203544 kb
Host smart-f6855e08-ca19-4de6-83a3-2cae898514a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709693656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2709693656
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.515178038
Short name T135
Test name
Test status
Simulation time 133601157 ps
CPU time 2.59 seconds
Started Apr 04 01:25:50 PM PDT 24
Finished Apr 04 01:25:52 PM PDT 24
Peak memory 203544 kb
Host smart-f74997ae-f61a-4472-9922-9eccb005085a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515178038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.515178038
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.3899264593
Short name T128
Test name
Test status
Simulation time 21336324 ps
CPU time 0.63 seconds
Started Apr 04 01:25:51 PM PDT 24
Finished Apr 04 01:25:51 PM PDT 24
Peak memory 203184 kb
Host smart-a074d448-b288-4773-b094-9b7f235fc657
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899264593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.3899264593
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2436571904
Short name T124
Test name
Test status
Simulation time 77783884 ps
CPU time 0.75 seconds
Started Apr 04 01:25:49 PM PDT 24
Finished Apr 04 01:25:49 PM PDT 24
Peak memory 203452 kb
Host smart-6968b2fe-798f-4408-8366-db8be9230c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436571904 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2436571904
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1422117196
Short name T129
Test name
Test status
Simulation time 51451766 ps
CPU time 0.68 seconds
Started Apr 04 01:25:51 PM PDT 24
Finished Apr 04 01:25:51 PM PDT 24
Peak memory 203324 kb
Host smart-47d7754f-997b-44ea-bf3c-2057a57d26b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422117196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1422117196
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3100863516
Short name T1231
Test name
Test status
Simulation time 19942582 ps
CPU time 0.66 seconds
Started Apr 04 01:25:49 PM PDT 24
Finished Apr 04 01:25:50 PM PDT 24
Peak memory 203312 kb
Host smart-5c328abe-1de1-4531-b78c-998a4e4cd7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100863516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3100863516
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.3004042405
Short name T1257
Test name
Test status
Simulation time 117001779 ps
CPU time 1.57 seconds
Started Apr 04 01:25:36 PM PDT 24
Finished Apr 04 01:25:38 PM PDT 24
Peak memory 203704 kb
Host smart-2876f570-4759-42f1-8f43-0a396905765c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004042405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3004042405
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2638864100
Short name T1278
Test name
Test status
Simulation time 26869647 ps
CPU time 1.13 seconds
Started Apr 04 01:25:50 PM PDT 24
Finished Apr 04 01:25:52 PM PDT 24
Peak memory 203688 kb
Host smart-e85fb7bf-7313-43c3-98cc-e09350d58526
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638864100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2638864100
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1041857457
Short name T136
Test name
Test status
Simulation time 519923092 ps
CPU time 2.51 seconds
Started Apr 04 01:25:50 PM PDT 24
Finished Apr 04 01:25:53 PM PDT 24
Peak memory 203544 kb
Host smart-392d5e8c-aaf4-49ec-8a68-f5dffef99a0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041857457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1041857457
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2775861469
Short name T1220
Test name
Test status
Simulation time 54109236 ps
CPU time 0.65 seconds
Started Apr 04 01:25:48 PM PDT 24
Finished Apr 04 01:25:48 PM PDT 24
Peak memory 203336 kb
Host smart-72ad39d4-25a0-4645-8dc6-813247f0d35b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775861469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2775861469
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.299836675
Short name T1308
Test name
Test status
Simulation time 25101868 ps
CPU time 1.11 seconds
Started Apr 04 01:25:59 PM PDT 24
Finished Apr 04 01:26:00 PM PDT 24
Peak memory 203684 kb
Host smart-540c6551-d7a7-4bdd-a0de-029482a6f3ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299836675 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.299836675
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1202961505
Short name T134
Test name
Test status
Simulation time 134646850 ps
CPU time 0.72 seconds
Started Apr 04 01:25:49 PM PDT 24
Finished Apr 04 01:25:49 PM PDT 24
Peak memory 203332 kb
Host smart-90ba894a-f62a-4e04-86f6-aae755eeaaf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202961505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1202961505
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.536624300
Short name T1282
Test name
Test status
Simulation time 19174712 ps
CPU time 0.67 seconds
Started Apr 04 01:25:47 PM PDT 24
Finished Apr 04 01:25:48 PM PDT 24
Peak memory 203348 kb
Host smart-cf85139e-22b0-45f5-b4ba-07de2d303143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536624300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.536624300
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.916331687
Short name T1306
Test name
Test status
Simulation time 212128432 ps
CPU time 1.1 seconds
Started Apr 04 01:25:49 PM PDT 24
Finished Apr 04 01:25:50 PM PDT 24
Peak memory 203512 kb
Host smart-2b8de9d4-6b37-4cde-95df-2eaf0f0f7925
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916331687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.916331687
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.805310928
Short name T1232
Test name
Test status
Simulation time 37135193 ps
CPU time 0.9 seconds
Started Apr 04 01:26:33 PM PDT 24
Finished Apr 04 01:26:34 PM PDT 24
Peak memory 203484 kb
Host smart-429193c9-c745-4b49-a10f-411ea0bd7a2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805310928 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.805310928
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.102396788
Short name T1280
Test name
Test status
Simulation time 19605540 ps
CPU time 0.66 seconds
Started Apr 04 01:26:35 PM PDT 24
Finished Apr 04 01:26:36 PM PDT 24
Peak memory 203372 kb
Host smart-2a98ea33-c9d3-40a4-9117-e7af0e127369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102396788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.102396788
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2769280344
Short name T1286
Test name
Test status
Simulation time 53960824 ps
CPU time 0.63 seconds
Started Apr 04 01:26:37 PM PDT 24
Finished Apr 04 01:26:37 PM PDT 24
Peak memory 203220 kb
Host smart-08499d58-cbec-4515-a3b5-0141d51ed1a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769280344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2769280344
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3009118434
Short name T141
Test name
Test status
Simulation time 52832769 ps
CPU time 1.15 seconds
Started Apr 04 01:26:34 PM PDT 24
Finished Apr 04 01:26:36 PM PDT 24
Peak memory 203584 kb
Host smart-7b1ef2cf-ea22-4cd7-8f3f-9a50f9167bb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009118434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3009118434
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1602396302
Short name T120
Test name
Test status
Simulation time 55369244 ps
CPU time 1.23 seconds
Started Apr 04 01:26:35 PM PDT 24
Finished Apr 04 01:26:37 PM PDT 24
Peak memory 203692 kb
Host smart-0bac9275-ee9b-438e-b009-fc8238b8c095
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602396302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1602396302
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1374401453
Short name T218
Test name
Test status
Simulation time 67492443 ps
CPU time 1.29 seconds
Started Apr 04 01:26:35 PM PDT 24
Finished Apr 04 01:26:37 PM PDT 24
Peak memory 203636 kb
Host smart-b25bc966-d61b-4f45-b56e-921cb41d1d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374401453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1374401453
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3630492263
Short name T1293
Test name
Test status
Simulation time 29343994 ps
CPU time 1.29 seconds
Started Apr 04 01:26:34 PM PDT 24
Finished Apr 04 01:26:36 PM PDT 24
Peak memory 203652 kb
Host smart-6ab3eac2-e1d4-4bf0-a01e-53ff2722c682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630492263 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3630492263
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1019101307
Short name T1290
Test name
Test status
Simulation time 55833263 ps
CPU time 0.67 seconds
Started Apr 04 01:26:34 PM PDT 24
Finished Apr 04 01:26:35 PM PDT 24
Peak memory 203348 kb
Host smart-0d942620-8654-46a1-a81b-407b1c7e614a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019101307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1019101307
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3207782202
Short name T1239
Test name
Test status
Simulation time 65614858 ps
CPU time 0.8 seconds
Started Apr 04 01:26:34 PM PDT 24
Finished Apr 04 01:26:35 PM PDT 24
Peak memory 203412 kb
Host smart-2ad6fabb-fbd2-4e31-887b-8db0d8dd6322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207782202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.3207782202
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.4093921903
Short name T111
Test name
Test status
Simulation time 55272977 ps
CPU time 1.35 seconds
Started Apr 04 01:26:35 PM PDT 24
Finished Apr 04 01:26:37 PM PDT 24
Peak memory 203680 kb
Host smart-94ae93ce-ee35-4a6e-9011-cdf4800f54c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093921903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.4093921903
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3821082279
Short name T1219
Test name
Test status
Simulation time 107271001 ps
CPU time 0.94 seconds
Started Apr 04 01:26:46 PM PDT 24
Finished Apr 04 01:26:47 PM PDT 24
Peak memory 203432 kb
Host smart-b862d5e7-cd62-44db-97d3-3e232c3fe654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821082279 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3821082279
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.4104421009
Short name T130
Test name
Test status
Simulation time 45759409 ps
CPU time 0.64 seconds
Started Apr 04 01:26:44 PM PDT 24
Finished Apr 04 01:26:45 PM PDT 24
Peak memory 203264 kb
Host smart-df3ecd3b-100a-44ad-8889-aee3a45ab11c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104421009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.4104421009
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.465662
Short name T142
Test name
Test status
Simulation time 37485389 ps
CPU time 0.9 seconds
Started Apr 04 01:26:46 PM PDT 24
Finished Apr 04 01:26:47 PM PDT 24
Peak memory 203392 kb
Host smart-22ff72b6-1a03-4988-983c-2dcb34c463cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outst
anding.465662
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3575612233
Short name T1244
Test name
Test status
Simulation time 171027409 ps
CPU time 2.22 seconds
Started Apr 04 01:26:46 PM PDT 24
Finished Apr 04 01:26:48 PM PDT 24
Peak memory 203532 kb
Host smart-1f47a776-9a0c-4106-be00-1376c58817ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575612233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3575612233
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.4117056195
Short name T114
Test name
Test status
Simulation time 94010011 ps
CPU time 1.33 seconds
Started Apr 04 01:26:44 PM PDT 24
Finished Apr 04 01:26:46 PM PDT 24
Peak memory 203592 kb
Host smart-0fbc1215-3f3d-458e-beee-024e992657fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117056195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4117056195
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3367436833
Short name T1248
Test name
Test status
Simulation time 350493482 ps
CPU time 0.96 seconds
Started Apr 04 01:26:47 PM PDT 24
Finished Apr 04 01:26:48 PM PDT 24
Peak memory 203424 kb
Host smart-1cd4fe42-9122-4601-a0b2-812cbd328203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367436833 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3367436833
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1256785674
Short name T1294
Test name
Test status
Simulation time 103550360 ps
CPU time 0.69 seconds
Started Apr 04 01:26:48 PM PDT 24
Finished Apr 04 01:26:49 PM PDT 24
Peak memory 203288 kb
Host smart-05e71caf-d073-4847-b4d3-9f838f0f6975
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256785674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1256785674
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1069735392
Short name T1302
Test name
Test status
Simulation time 27782853 ps
CPU time 0.67 seconds
Started Apr 04 01:26:49 PM PDT 24
Finished Apr 04 01:26:50 PM PDT 24
Peak memory 203248 kb
Host smart-e341b8c8-3c6f-432f-8989-5e15775a8122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069735392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1069735392
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3788227832
Short name T1271
Test name
Test status
Simulation time 80323721 ps
CPU time 0.74 seconds
Started Apr 04 01:26:47 PM PDT 24
Finished Apr 04 01:26:48 PM PDT 24
Peak memory 203404 kb
Host smart-4a1c778e-6023-41f6-b9d0-4950de3c777c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788227832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3788227832
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3043161655
Short name T1285
Test name
Test status
Simulation time 414096014 ps
CPU time 2.34 seconds
Started Apr 04 01:26:46 PM PDT 24
Finished Apr 04 01:26:48 PM PDT 24
Peak memory 203696 kb
Host smart-e7f0457b-9614-45be-a751-3a4d04b124f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043161655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3043161655
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1726150668
Short name T122
Test name
Test status
Simulation time 186943665 ps
CPU time 1.39 seconds
Started Apr 04 01:26:49 PM PDT 24
Finished Apr 04 01:26:50 PM PDT 24
Peak memory 203616 kb
Host smart-2c62282f-c35a-4769-8b25-4b18fb9430ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726150668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1726150668
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.701644008
Short name T1217
Test name
Test status
Simulation time 28112890 ps
CPU time 0.85 seconds
Started Apr 04 01:27:00 PM PDT 24
Finished Apr 04 01:27:01 PM PDT 24
Peak memory 203444 kb
Host smart-9ce70b51-8e43-4da0-9f9d-71dd2b82b10c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701644008 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.701644008
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1142196366
Short name T1259
Test name
Test status
Simulation time 29775280 ps
CPU time 0.76 seconds
Started Apr 04 01:26:55 PM PDT 24
Finished Apr 04 01:26:56 PM PDT 24
Peak memory 203384 kb
Host smart-8f94943d-dcee-448c-9ecd-2081b5c3c1b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142196366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1142196366
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1080157683
Short name T1279
Test name
Test status
Simulation time 16416071 ps
CPU time 0.65 seconds
Started Apr 04 01:26:59 PM PDT 24
Finished Apr 04 01:26:59 PM PDT 24
Peak memory 203316 kb
Host smart-1879e538-028f-460b-9570-f6e2e592a033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080157683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1080157683
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1332299167
Short name T1218
Test name
Test status
Simulation time 66464145 ps
CPU time 1.15 seconds
Started Apr 04 01:26:56 PM PDT 24
Finished Apr 04 01:26:57 PM PDT 24
Peak memory 203556 kb
Host smart-32cac285-01c1-40f7-94d6-c6145b6bba52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332299167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1332299167
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3276416649
Short name T1222
Test name
Test status
Simulation time 65872870 ps
CPU time 0.88 seconds
Started Apr 04 01:26:58 PM PDT 24
Finished Apr 04 01:26:59 PM PDT 24
Peak memory 203448 kb
Host smart-8c8ded8d-177a-4351-a468-ac8f89433fc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276416649 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3276416649
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.943302407
Short name T1253
Test name
Test status
Simulation time 115242246 ps
CPU time 0.64 seconds
Started Apr 04 01:26:56 PM PDT 24
Finished Apr 04 01:26:57 PM PDT 24
Peak memory 203304 kb
Host smart-f5d740e5-c79b-4176-94bf-b62902f0251c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943302407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.943302407
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.666896083
Short name T163
Test name
Test status
Simulation time 32893046 ps
CPU time 0.68 seconds
Started Apr 04 01:26:57 PM PDT 24
Finished Apr 04 01:26:57 PM PDT 24
Peak memory 203328 kb
Host smart-9b2e0955-827c-46f7-9c7a-f024bd62518f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666896083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.666896083
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1107778639
Short name T1311
Test name
Test status
Simulation time 138001070 ps
CPU time 2.59 seconds
Started Apr 04 01:26:58 PM PDT 24
Finished Apr 04 01:27:01 PM PDT 24
Peak memory 203584 kb
Host smart-00942c40-2521-4e86-82b6-89a37b262ec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107778639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1107778639
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.306721747
Short name T1263
Test name
Test status
Simulation time 268519423 ps
CPU time 1.85 seconds
Started Apr 04 01:26:59 PM PDT 24
Finished Apr 04 01:27:01 PM PDT 24
Peak memory 203560 kb
Host smart-1c6c835b-cb02-4ea5-b3ea-db8c61fbb82b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306721747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.306721747
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4191119004
Short name T1315
Test name
Test status
Simulation time 26044090 ps
CPU time 0.81 seconds
Started Apr 04 01:26:57 PM PDT 24
Finished Apr 04 01:26:58 PM PDT 24
Peak memory 203540 kb
Host smart-9046eed2-0c8b-449a-be73-9614bbdd907c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191119004 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.4191119004
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.79237585
Short name T127
Test name
Test status
Simulation time 20618448 ps
CPU time 0.74 seconds
Started Apr 04 01:26:56 PM PDT 24
Finished Apr 04 01:26:57 PM PDT 24
Peak memory 203372 kb
Host smart-96523154-8a13-4951-9a89-9de4610abc9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79237585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.79237585
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.472117202
Short name T1295
Test name
Test status
Simulation time 51408104 ps
CPU time 0.67 seconds
Started Apr 04 01:27:00 PM PDT 24
Finished Apr 04 01:27:01 PM PDT 24
Peak memory 203328 kb
Host smart-c4fc3b7b-be72-4146-b1c7-560f760e37df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472117202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.472117202
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3933761628
Short name T1240
Test name
Test status
Simulation time 112631084 ps
CPU time 0.82 seconds
Started Apr 04 01:26:59 PM PDT 24
Finished Apr 04 01:27:00 PM PDT 24
Peak memory 203320 kb
Host smart-4de99df8-41f5-44f1-9cdb-db54b5d50f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933761628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3933761628
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3845192468
Short name T1250
Test name
Test status
Simulation time 204746179 ps
CPU time 2.24 seconds
Started Apr 04 01:26:56 PM PDT 24
Finished Apr 04 01:26:58 PM PDT 24
Peak memory 203712 kb
Host smart-12194e25-4b61-4394-9459-4880e927afde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845192468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3845192468
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2438676743
Short name T113
Test name
Test status
Simulation time 84124006 ps
CPU time 1.88 seconds
Started Apr 04 01:27:00 PM PDT 24
Finished Apr 04 01:27:02 PM PDT 24
Peak memory 203656 kb
Host smart-0536f099-1192-4f7b-98a5-8b4b8ff06296
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438676743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2438676743
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.188635719
Short name T1246
Test name
Test status
Simulation time 68848036 ps
CPU time 1.04 seconds
Started Apr 04 01:26:58 PM PDT 24
Finished Apr 04 01:26:59 PM PDT 24
Peak memory 203540 kb
Host smart-a63df893-4886-4c26-9acd-0531c3af2526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188635719 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.188635719
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1058616000
Short name T1317
Test name
Test status
Simulation time 67404915 ps
CPU time 0.72 seconds
Started Apr 04 01:26:57 PM PDT 24
Finished Apr 04 01:26:58 PM PDT 24
Peak memory 203324 kb
Host smart-dd4edfe0-9cb1-4f98-9f8d-cebcc6dd8ddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058616000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1058616000
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.3856734136
Short name T1264
Test name
Test status
Simulation time 76022140 ps
CPU time 0.62 seconds
Started Apr 04 01:26:54 PM PDT 24
Finished Apr 04 01:26:55 PM PDT 24
Peak memory 203280 kb
Host smart-37e863fb-1f04-4bac-966f-0c72b1569228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856734136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3856734136
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.492119896
Short name T1215
Test name
Test status
Simulation time 23929029 ps
CPU time 0.85 seconds
Started Apr 04 01:26:59 PM PDT 24
Finished Apr 04 01:27:00 PM PDT 24
Peak memory 203372 kb
Host smart-13e568af-e1b3-456a-9561-047bdb56fead
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492119896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.492119896
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3783957253
Short name T1258
Test name
Test status
Simulation time 350551369 ps
CPU time 2.5 seconds
Started Apr 04 01:27:00 PM PDT 24
Finished Apr 04 01:27:03 PM PDT 24
Peak memory 203708 kb
Host smart-091c109a-3fda-4c19-a479-5c697713821f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783957253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3783957253
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2985090677
Short name T1238
Test name
Test status
Simulation time 36027749 ps
CPU time 0.92 seconds
Started Apr 04 01:26:59 PM PDT 24
Finished Apr 04 01:27:00 PM PDT 24
Peak memory 203464 kb
Host smart-47f11233-40c2-4b48-b85a-a7c07a03c023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985090677 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2985090677
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3910770759
Short name T1229
Test name
Test status
Simulation time 18172956 ps
CPU time 0.76 seconds
Started Apr 04 01:26:57 PM PDT 24
Finished Apr 04 01:26:57 PM PDT 24
Peak memory 203364 kb
Host smart-b98f6fd2-cd1a-449f-acd2-4c355e53d237
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910770759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3910770759
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.976348548
Short name T1243
Test name
Test status
Simulation time 41404938 ps
CPU time 0.62 seconds
Started Apr 04 01:26:56 PM PDT 24
Finished Apr 04 01:26:57 PM PDT 24
Peak memory 203284 kb
Host smart-68c425d1-e131-41e4-b647-50c1b4775cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976348548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.976348548
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2900454625
Short name T1275
Test name
Test status
Simulation time 32376377 ps
CPU time 0.82 seconds
Started Apr 04 01:26:55 PM PDT 24
Finished Apr 04 01:26:56 PM PDT 24
Peak memory 203320 kb
Host smart-b0061f7c-1cb6-4894-8b4b-96c390ab276e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900454625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2900454625
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1633296143
Short name T1283
Test name
Test status
Simulation time 491081552 ps
CPU time 2.96 seconds
Started Apr 04 01:26:58 PM PDT 24
Finished Apr 04 01:27:01 PM PDT 24
Peak memory 203580 kb
Host smart-6ae1a179-e7ac-4037-8f68-7548fd1fd536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633296143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1633296143
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2531361196
Short name T118
Test name
Test status
Simulation time 157229253 ps
CPU time 1.89 seconds
Started Apr 04 01:26:59 PM PDT 24
Finished Apr 04 01:27:01 PM PDT 24
Peak memory 203656 kb
Host smart-cf95b87a-72ae-48d2-a05f-876abe79342d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531361196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2531361196
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.490046097
Short name T1296
Test name
Test status
Simulation time 35733358 ps
CPU time 0.89 seconds
Started Apr 04 01:27:10 PM PDT 24
Finished Apr 04 01:27:11 PM PDT 24
Peak memory 203460 kb
Host smart-e6ee99e1-bddb-4a8d-b7a5-ec0c266eaf03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490046097 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.490046097
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3314147834
Short name T1288
Test name
Test status
Simulation time 60415443 ps
CPU time 0.71 seconds
Started Apr 04 01:27:10 PM PDT 24
Finished Apr 04 01:27:11 PM PDT 24
Peak memory 203288 kb
Host smart-76336de5-9774-4c4a-b0f2-2bfe1d89e94a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314147834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3314147834
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.296990371
Short name T1272
Test name
Test status
Simulation time 23659954 ps
CPU time 0.63 seconds
Started Apr 04 01:27:07 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203276 kb
Host smart-1ca87b28-6fbd-46bf-9a06-eae4cf4a0250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296990371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.296990371
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3966113584
Short name T70
Test name
Test status
Simulation time 93493698 ps
CPU time 1 seconds
Started Apr 04 01:27:10 PM PDT 24
Finished Apr 04 01:27:12 PM PDT 24
Peak memory 203648 kb
Host smart-617a67ec-9c4c-4e6f-aa5e-7fdf6980682e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966113584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3966113584
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.313603684
Short name T1230
Test name
Test status
Simulation time 87755654 ps
CPU time 1.85 seconds
Started Apr 04 01:26:59 PM PDT 24
Finished Apr 04 01:27:01 PM PDT 24
Peak memory 203704 kb
Host smart-a9763d8e-2999-4a02-a0a8-ad790af88b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313603684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.313603684
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1339839300
Short name T1242
Test name
Test status
Simulation time 86564523 ps
CPU time 2.01 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:10 PM PDT 24
Peak memory 203600 kb
Host smart-e80c2ee4-f686-4ac2-8011-7b1ba28f07be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339839300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1339839300
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3956100591
Short name T139
Test name
Test status
Simulation time 166426457 ps
CPU time 1.8 seconds
Started Apr 04 01:25:58 PM PDT 24
Finished Apr 04 01:26:00 PM PDT 24
Peak memory 203608 kb
Host smart-37d89b85-1e3b-40e2-9aa7-b86f0ce550af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956100591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3956100591
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2563372423
Short name T72
Test name
Test status
Simulation time 1887768207 ps
CPU time 5.48 seconds
Started Apr 04 01:26:02 PM PDT 24
Finished Apr 04 01:26:08 PM PDT 24
Peak memory 203644 kb
Host smart-39ece920-70c4-4d3f-95c1-d4bcc862515b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563372423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2563372423
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.929688113
Short name T1313
Test name
Test status
Simulation time 20009057 ps
CPU time 0.68 seconds
Started Apr 04 01:25:59 PM PDT 24
Finished Apr 04 01:26:00 PM PDT 24
Peak memory 203396 kb
Host smart-1f3fc27f-e2e7-4ef4-9623-885bda8a5f24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929688113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.929688113
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1389628019
Short name T106
Test name
Test status
Simulation time 26460644 ps
CPU time 1.13 seconds
Started Apr 04 01:25:57 PM PDT 24
Finished Apr 04 01:25:59 PM PDT 24
Peak memory 203596 kb
Host smart-e3d4b994-00a3-47ba-8940-b054d46a9e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389628019 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1389628019
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3769817565
Short name T143
Test name
Test status
Simulation time 21001673 ps
CPU time 0.63 seconds
Started Apr 04 01:25:59 PM PDT 24
Finished Apr 04 01:26:00 PM PDT 24
Peak memory 203296 kb
Host smart-3ed24714-3ae8-4fdc-8f7c-9239fb70fc8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769817565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3769817565
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3104749206
Short name T1314
Test name
Test status
Simulation time 26797297 ps
CPU time 0.64 seconds
Started Apr 04 01:26:00 PM PDT 24
Finished Apr 04 01:26:01 PM PDT 24
Peak memory 203348 kb
Host smart-d844902c-a6c7-4c00-baff-ad2d8bd8754f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104749206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3104749206
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1769452775
Short name T1316
Test name
Test status
Simulation time 62626418 ps
CPU time 1.04 seconds
Started Apr 04 01:25:59 PM PDT 24
Finished Apr 04 01:26:00 PM PDT 24
Peak memory 203564 kb
Host smart-9a22c2d4-cf7f-4d5e-ad46-55d088a0a22a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769452775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1769452775
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3873216720
Short name T1247
Test name
Test status
Simulation time 398014151 ps
CPU time 1.34 seconds
Started Apr 04 01:26:00 PM PDT 24
Finished Apr 04 01:26:01 PM PDT 24
Peak memory 203524 kb
Host smart-f5be9347-cccf-472d-ad4d-b3b8873c413b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873216720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3873216720
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1439959406
Short name T90
Test name
Test status
Simulation time 307635591 ps
CPU time 1.33 seconds
Started Apr 04 01:25:59 PM PDT 24
Finished Apr 04 01:26:00 PM PDT 24
Peak memory 203596 kb
Host smart-7ea91a66-47ea-43d0-912c-6fcf16f87d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439959406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1439959406
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1269800826
Short name T1252
Test name
Test status
Simulation time 47346073 ps
CPU time 0.59 seconds
Started Apr 04 01:27:06 PM PDT 24
Finished Apr 04 01:27:07 PM PDT 24
Peak memory 203204 kb
Host smart-21cb32f4-7187-4f00-865b-8b770473298b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269800826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1269800826
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.167171618
Short name T1304
Test name
Test status
Simulation time 16209259 ps
CPU time 0.68 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:09 PM PDT 24
Peak memory 203312 kb
Host smart-048805a3-83b9-4e62-8096-f7e59006406d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167171618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.167171618
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4030350264
Short name T1291
Test name
Test status
Simulation time 15951049 ps
CPU time 0.63 seconds
Started Apr 04 01:27:11 PM PDT 24
Finished Apr 04 01:27:12 PM PDT 24
Peak memory 203328 kb
Host smart-04385719-d587-410f-8fe5-b09522c25c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030350264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4030350264
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3230963423
Short name T1249
Test name
Test status
Simulation time 16109204 ps
CPU time 0.67 seconds
Started Apr 04 01:27:10 PM PDT 24
Finished Apr 04 01:27:11 PM PDT 24
Peak memory 203344 kb
Host smart-646a1ba7-22a9-4d7e-9c44-40fdec136cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230963423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3230963423
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2461250409
Short name T236
Test name
Test status
Simulation time 60642178 ps
CPU time 0.65 seconds
Started Apr 04 01:27:10 PM PDT 24
Finished Apr 04 01:27:11 PM PDT 24
Peak memory 203308 kb
Host smart-51f23034-d4c9-499d-9aa9-a377d7633caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461250409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2461250409
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3740502889
Short name T1267
Test name
Test status
Simulation time 70079756 ps
CPU time 0.64 seconds
Started Apr 04 01:27:07 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203284 kb
Host smart-459b7c40-60db-4eda-986b-0bea87a7df2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740502889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3740502889
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.386478718
Short name T240
Test name
Test status
Simulation time 18090374 ps
CPU time 0.67 seconds
Started Apr 04 01:27:07 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203348 kb
Host smart-6c1711ce-f0e1-411f-85a6-4049a1ca0ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386478718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.386478718
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1933144319
Short name T1265
Test name
Test status
Simulation time 55644330 ps
CPU time 0.66 seconds
Started Apr 04 01:27:07 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203328 kb
Host smart-3bdefcf7-8f4c-4965-b156-6cf06532dd17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933144319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1933144319
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1768415740
Short name T1274
Test name
Test status
Simulation time 47164170 ps
CPU time 0.66 seconds
Started Apr 04 01:27:07 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203364 kb
Host smart-897a2694-6153-4227-9960-194cc373e083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768415740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1768415740
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1943684165
Short name T1298
Test name
Test status
Simulation time 40271855 ps
CPU time 0.64 seconds
Started Apr 04 01:27:10 PM PDT 24
Finished Apr 04 01:27:11 PM PDT 24
Peak memory 203248 kb
Host smart-ea410a95-b590-4b72-83a6-8d89ab5d1087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943684165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1943684165
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1616919885
Short name T133
Test name
Test status
Simulation time 85532424 ps
CPU time 1.09 seconds
Started Apr 04 01:26:11 PM PDT 24
Finished Apr 04 01:26:12 PM PDT 24
Peak memory 203708 kb
Host smart-6a6c3de3-9da0-4b49-a09d-008b0ab4d512
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616919885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1616919885
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1237998547
Short name T1312
Test name
Test status
Simulation time 204564318 ps
CPU time 2.91 seconds
Started Apr 04 01:25:59 PM PDT 24
Finished Apr 04 01:26:03 PM PDT 24
Peak memory 203480 kb
Host smart-3ea6944f-9acd-464d-b75d-ae280ff65d01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237998547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1237998547
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1271694259
Short name T126
Test name
Test status
Simulation time 28226026 ps
CPU time 0.72 seconds
Started Apr 04 01:25:59 PM PDT 24
Finished Apr 04 01:26:00 PM PDT 24
Peak memory 203396 kb
Host smart-2ac6cf60-adb0-4db2-a1bd-775e72dd6dfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271694259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1271694259
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.756811393
Short name T1318
Test name
Test status
Simulation time 71579456 ps
CPU time 1.09 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 203544 kb
Host smart-4b05438b-997b-4635-a829-c8e116281729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756811393 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.756811393
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.930391010
Short name T1300
Test name
Test status
Simulation time 48267587 ps
CPU time 0.76 seconds
Started Apr 04 01:26:01 PM PDT 24
Finished Apr 04 01:26:01 PM PDT 24
Peak memory 203340 kb
Host smart-ad3b5844-f9a6-4fae-9fd3-115977eedda2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930391010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.930391010
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3601793050
Short name T1266
Test name
Test status
Simulation time 15426299 ps
CPU time 0.62 seconds
Started Apr 04 01:25:57 PM PDT 24
Finished Apr 04 01:25:58 PM PDT 24
Peak memory 203368 kb
Host smart-e547ae3c-5048-43bb-96e8-a300cc853b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601793050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3601793050
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3036789021
Short name T1245
Test name
Test status
Simulation time 200950493 ps
CPU time 0.77 seconds
Started Apr 04 01:26:10 PM PDT 24
Finished Apr 04 01:26:11 PM PDT 24
Peak memory 203388 kb
Host smart-32a2857d-f818-4752-990d-1a4d77e1739e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036789021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3036789021
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.4259397799
Short name T1225
Test name
Test status
Simulation time 55530261 ps
CPU time 1.26 seconds
Started Apr 04 01:26:00 PM PDT 24
Finished Apr 04 01:26:02 PM PDT 24
Peak memory 203664 kb
Host smart-928a6a0c-aea4-4981-9566-7bd30beb6326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259397799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.4259397799
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3471907235
Short name T121
Test name
Test status
Simulation time 1134623353 ps
CPU time 2.19 seconds
Started Apr 04 01:25:57 PM PDT 24
Finished Apr 04 01:25:59 PM PDT 24
Peak memory 203664 kb
Host smart-04b8e143-e4ca-421c-a7a5-f94cf73a369f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471907235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3471907235
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.390893931
Short name T1276
Test name
Test status
Simulation time 17055723 ps
CPU time 0.68 seconds
Started Apr 04 01:27:15 PM PDT 24
Finished Apr 04 01:27:16 PM PDT 24
Peak memory 203328 kb
Host smart-e0c55608-fd2a-464d-ad1a-07a04db651c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390893931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.390893931
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.1950202144
Short name T235
Test name
Test status
Simulation time 47571860 ps
CPU time 0.65 seconds
Started Apr 04 01:27:10 PM PDT 24
Finished Apr 04 01:27:11 PM PDT 24
Peak memory 203248 kb
Host smart-49470aac-f05c-4964-b00f-5149b483b531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950202144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1950202144
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1996967419
Short name T1310
Test name
Test status
Simulation time 50549190 ps
CPU time 0.64 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:09 PM PDT 24
Peak memory 203244 kb
Host smart-e511105d-7c66-449c-aa3b-341c5e466532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996967419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1996967419
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3625937255
Short name T232
Test name
Test status
Simulation time 14640230 ps
CPU time 0.62 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203336 kb
Host smart-d5d807a7-a34d-4cd8-85cf-fa4452b9591c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625937255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3625937255
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.999175666
Short name T1261
Test name
Test status
Simulation time 20323091 ps
CPU time 0.67 seconds
Started Apr 04 01:27:17 PM PDT 24
Finished Apr 04 01:27:18 PM PDT 24
Peak memory 203328 kb
Host smart-6a73113b-63c9-404e-9b3c-5db33460b660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999175666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.999175666
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2667096595
Short name T1269
Test name
Test status
Simulation time 63394245 ps
CPU time 0.62 seconds
Started Apr 04 01:27:11 PM PDT 24
Finished Apr 04 01:27:12 PM PDT 24
Peak memory 203328 kb
Host smart-a0f298de-c352-4713-9de1-35721fe5d52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667096595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2667096595
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3241072437
Short name T1255
Test name
Test status
Simulation time 39749933 ps
CPU time 0.65 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203264 kb
Host smart-88a99891-d7a9-4ea5-8caa-0160e73e280d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241072437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3241072437
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.517951316
Short name T1233
Test name
Test status
Simulation time 26649911 ps
CPU time 0.63 seconds
Started Apr 04 01:27:07 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203300 kb
Host smart-22cd67df-92f3-4706-839f-fb6188373c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517951316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.517951316
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1660559183
Short name T1254
Test name
Test status
Simulation time 180459010 ps
CPU time 0.63 seconds
Started Apr 04 01:27:11 PM PDT 24
Finished Apr 04 01:27:12 PM PDT 24
Peak memory 203328 kb
Host smart-7f1d2d6a-a482-477e-9844-203f674ef420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660559183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1660559183
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.47839627
Short name T162
Test name
Test status
Simulation time 18189486 ps
CPU time 0.66 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:09 PM PDT 24
Peak memory 203480 kb
Host smart-289441eb-6a01-495e-af45-c56cb77d6d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47839627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.47839627
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2593668412
Short name T140
Test name
Test status
Simulation time 57464756 ps
CPU time 1.18 seconds
Started Apr 04 01:26:10 PM PDT 24
Finished Apr 04 01:26:12 PM PDT 24
Peak memory 203616 kb
Host smart-ced13797-9ace-4346-abf1-2088bd8ce087
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593668412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2593668412
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.3543596246
Short name T137
Test name
Test status
Simulation time 565051148 ps
CPU time 3.07 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:15 PM PDT 24
Peak memory 203616 kb
Host smart-f95288f5-1f33-44c6-9575-b121cdb75f79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543596246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3543596246
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.663150886
Short name T1213
Test name
Test status
Simulation time 100946314 ps
CPU time 0.65 seconds
Started Apr 04 01:26:13 PM PDT 24
Finished Apr 04 01:26:14 PM PDT 24
Peak memory 203152 kb
Host smart-7c595e7c-aa7d-404a-9d94-856467809623
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663150886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.663150886
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1443956598
Short name T115
Test name
Test status
Simulation time 106777671 ps
CPU time 1.38 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 203708 kb
Host smart-ea8fcdfa-cf8a-4db9-ba1e-b3ddc0eb5e8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443956598 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1443956598
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1620976563
Short name T1262
Test name
Test status
Simulation time 27019548 ps
CPU time 0.77 seconds
Started Apr 04 01:26:10 PM PDT 24
Finished Apr 04 01:26:11 PM PDT 24
Peak memory 203356 kb
Host smart-209cfc04-802b-4bc7-9991-9e748d0ef153
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620976563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1620976563
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.14637340
Short name T1214
Test name
Test status
Simulation time 52375234 ps
CPU time 0.63 seconds
Started Apr 04 01:26:10 PM PDT 24
Finished Apr 04 01:26:11 PM PDT 24
Peak memory 203352 kb
Host smart-f8b962d9-3ceb-420c-9615-9eee7942003e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14637340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.14637340
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2216416801
Short name T1236
Test name
Test status
Simulation time 27467323 ps
CPU time 0.95 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 203628 kb
Host smart-b49db49f-1fbf-407c-b785-ece8a9940ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216416801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2216416801
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2323495785
Short name T1223
Test name
Test status
Simulation time 128148607 ps
CPU time 1.63 seconds
Started Apr 04 01:26:15 PM PDT 24
Finished Apr 04 01:26:16 PM PDT 24
Peak memory 203700 kb
Host smart-061942f0-e54f-478b-9465-ddc43a848173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323495785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2323495785
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2703233115
Short name T217
Test name
Test status
Simulation time 264095679 ps
CPU time 1.38 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 203564 kb
Host smart-16c73289-6831-4a88-b690-982d1c41f542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703233115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2703233115
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4036897640
Short name T1270
Test name
Test status
Simulation time 81750195 ps
CPU time 0.63 seconds
Started Apr 04 01:27:07 PM PDT 24
Finished Apr 04 01:27:07 PM PDT 24
Peak memory 203352 kb
Host smart-79ad024e-2c82-490e-abed-979788c6480d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036897640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4036897640
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1529577887
Short name T1289
Test name
Test status
Simulation time 17730268 ps
CPU time 0.64 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:08 PM PDT 24
Peak memory 203212 kb
Host smart-d73ca356-6cd1-41f5-b9c0-f2603ba14563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529577887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1529577887
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.205522204
Short name T1305
Test name
Test status
Simulation time 18644704 ps
CPU time 0.65 seconds
Started Apr 04 01:27:13 PM PDT 24
Finished Apr 04 01:27:14 PM PDT 24
Peak memory 203328 kb
Host smart-a8971948-8d50-4ec9-b5cf-c5b0654e3e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205522204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.205522204
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.213109960
Short name T231
Test name
Test status
Simulation time 17437488 ps
CPU time 0.63 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:09 PM PDT 24
Peak memory 203480 kb
Host smart-be84259c-a1dc-45fc-b63e-b143127258eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213109960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.213109960
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2505166422
Short name T1256
Test name
Test status
Simulation time 58965349 ps
CPU time 0.69 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:09 PM PDT 24
Peak memory 203212 kb
Host smart-b86ba696-3273-4652-9171-db1c1fc3c778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505166422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2505166422
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.512134849
Short name T1284
Test name
Test status
Simulation time 16256344 ps
CPU time 0.64 seconds
Started Apr 04 01:27:08 PM PDT 24
Finished Apr 04 01:27:09 PM PDT 24
Peak memory 203340 kb
Host smart-43036b71-9982-4bd3-8f7c-35de0830ed3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512134849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.512134849
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3106303521
Short name T1287
Test name
Test status
Simulation time 18699167 ps
CPU time 0.66 seconds
Started Apr 04 01:27:11 PM PDT 24
Finished Apr 04 01:27:11 PM PDT 24
Peak memory 203340 kb
Host smart-3ff613d8-63c1-461c-9925-7b5b97fd90ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106303521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3106303521
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2567602448
Short name T1303
Test name
Test status
Simulation time 20428926 ps
CPU time 0.69 seconds
Started Apr 04 01:27:11 PM PDT 24
Finished Apr 04 01:27:12 PM PDT 24
Peak memory 203340 kb
Host smart-63342419-f1b4-4893-803e-a8d6194cf86a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567602448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2567602448
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1294011443
Short name T1234
Test name
Test status
Simulation time 15741499 ps
CPU time 0.66 seconds
Started Apr 04 01:27:14 PM PDT 24
Finished Apr 04 01:27:15 PM PDT 24
Peak memory 203328 kb
Host smart-bc07cd9a-f50e-47e0-96ed-4b752177fa0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294011443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1294011443
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1014318430
Short name T1227
Test name
Test status
Simulation time 26855085 ps
CPU time 0.74 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 203444 kb
Host smart-e5db2375-ea77-4c10-ab1b-bcf755ed31f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014318430 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1014318430
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.2621311333
Short name T131
Test name
Test status
Simulation time 61724088 ps
CPU time 0.65 seconds
Started Apr 04 01:26:10 PM PDT 24
Finished Apr 04 01:26:11 PM PDT 24
Peak memory 203384 kb
Host smart-04a80bbc-c7a5-429c-9c18-d62c2d2bf8b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621311333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2621311333
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2809620244
Short name T1309
Test name
Test status
Simulation time 18069656 ps
CPU time 0.67 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:12 PM PDT 24
Peak memory 203328 kb
Host smart-df778d75-ba23-4c51-ac5d-75aa9799a7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809620244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2809620244
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1099667623
Short name T1301
Test name
Test status
Simulation time 259420582 ps
CPU time 1.12 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 203508 kb
Host smart-98fdcbbf-9e33-400d-9cbc-5c802a89f853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099667623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1099667623
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3097964208
Short name T1273
Test name
Test status
Simulation time 40080319 ps
CPU time 1.97 seconds
Started Apr 04 01:26:09 PM PDT 24
Finished Apr 04 01:26:11 PM PDT 24
Peak memory 203676 kb
Host smart-c255b0a0-0eb5-4524-bedf-6f6efc4e5c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097964208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3097964208
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1032769351
Short name T1299
Test name
Test status
Simulation time 122342153 ps
CPU time 1.37 seconds
Started Apr 04 01:26:09 PM PDT 24
Finished Apr 04 01:26:10 PM PDT 24
Peak memory 203564 kb
Host smart-9e9c4cfa-fedd-497e-bfcf-4d85fd100b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032769351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1032769351
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1452634220
Short name T1268
Test name
Test status
Simulation time 76766730 ps
CPU time 1.07 seconds
Started Apr 04 01:26:23 PM PDT 24
Finished Apr 04 01:26:24 PM PDT 24
Peak memory 203740 kb
Host smart-187525bf-ba88-47ad-b23b-0f34a5311640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452634220 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1452634220
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1802118917
Short name T1260
Test name
Test status
Simulation time 140298743 ps
CPU time 0.75 seconds
Started Apr 04 01:26:11 PM PDT 24
Finished Apr 04 01:26:12 PM PDT 24
Peak memory 203388 kb
Host smart-dd61534c-297f-4470-b8af-5c8895369e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802118917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1802118917
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1659390528
Short name T1235
Test name
Test status
Simulation time 17441479 ps
CPU time 0.67 seconds
Started Apr 04 01:26:15 PM PDT 24
Finished Apr 04 01:26:16 PM PDT 24
Peak memory 203336 kb
Host smart-3f5fdc26-ca89-408e-b2bf-459dc2eea40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659390528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1659390528
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1347362160
Short name T144
Test name
Test status
Simulation time 218763328 ps
CPU time 1.07 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 203516 kb
Host smart-461f3b62-1aa6-4247-bb81-12f22f1251fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347362160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1347362160
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3982695012
Short name T1237
Test name
Test status
Simulation time 77877771 ps
CPU time 1.65 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:14 PM PDT 24
Peak memory 203612 kb
Host smart-0e6aa256-5c58-4de5-8f83-e3a994f62dee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982695012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3982695012
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2625833166
Short name T119
Test name
Test status
Simulation time 154070528 ps
CPU time 2.18 seconds
Started Apr 04 01:26:12 PM PDT 24
Finished Apr 04 01:26:14 PM PDT 24
Peak memory 203580 kb
Host smart-ff70a371-b4a5-4def-a1c5-5a48e3da64d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625833166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2625833166
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1326684730
Short name T1297
Test name
Test status
Simulation time 89553086 ps
CPU time 0.77 seconds
Started Apr 04 01:26:27 PM PDT 24
Finished Apr 04 01:26:28 PM PDT 24
Peak memory 203392 kb
Host smart-74749433-a1f9-47f2-b192-9bf4211a6e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326684730 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1326684730
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1432162870
Short name T132
Test name
Test status
Simulation time 17364870 ps
CPU time 0.72 seconds
Started Apr 04 01:26:22 PM PDT 24
Finished Apr 04 01:26:23 PM PDT 24
Peak memory 203380 kb
Host smart-9c1103bd-4aeb-482e-9663-024e06811d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432162870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1432162870
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2603142858
Short name T1224
Test name
Test status
Simulation time 17979346 ps
CPU time 0.66 seconds
Started Apr 04 01:26:27 PM PDT 24
Finished Apr 04 01:26:28 PM PDT 24
Peak memory 203340 kb
Host smart-7e218b2a-914c-4888-b88d-b7f648ba02bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603142858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2603142858
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.425961639
Short name T145
Test name
Test status
Simulation time 67413850 ps
CPU time 1.1 seconds
Started Apr 04 01:26:22 PM PDT 24
Finished Apr 04 01:26:23 PM PDT 24
Peak memory 203480 kb
Host smart-a9ba296d-7de6-477c-b421-8905eb38f56f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425961639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.425961639
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2900862524
Short name T105
Test name
Test status
Simulation time 112358750 ps
CPU time 1.48 seconds
Started Apr 04 01:26:27 PM PDT 24
Finished Apr 04 01:26:29 PM PDT 24
Peak memory 203596 kb
Host smart-63efdd9e-1360-4bfd-b759-5e8213f3a5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900862524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2900862524
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4101676486
Short name T109
Test name
Test status
Simulation time 67542570 ps
CPU time 1.07 seconds
Started Apr 04 01:26:22 PM PDT 24
Finished Apr 04 01:26:23 PM PDT 24
Peak memory 203700 kb
Host smart-13e5d8d3-ca7b-4aa9-b124-e11c9f575372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101676486 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.4101676486
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2984388147
Short name T1221
Test name
Test status
Simulation time 18926631 ps
CPU time 0.66 seconds
Started Apr 04 01:26:23 PM PDT 24
Finished Apr 04 01:26:25 PM PDT 24
Peak memory 203352 kb
Host smart-99f9f794-27ce-4010-aa7b-c576cc0f4d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984388147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2984388147
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1548578282
Short name T1307
Test name
Test status
Simulation time 25734305 ps
CPU time 0.67 seconds
Started Apr 04 01:26:24 PM PDT 24
Finished Apr 04 01:26:25 PM PDT 24
Peak memory 203264 kb
Host smart-185945ee-0788-4e20-8a89-7c17873a813e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548578282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1548578282
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3425860435
Short name T1277
Test name
Test status
Simulation time 98081413 ps
CPU time 1.06 seconds
Started Apr 04 01:26:24 PM PDT 24
Finished Apr 04 01:26:25 PM PDT 24
Peak memory 203596 kb
Host smart-9387711a-452c-4e8c-b897-86bdcbebd79a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425860435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3425860435
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2389339037
Short name T89
Test name
Test status
Simulation time 71150820 ps
CPU time 1.65 seconds
Started Apr 04 01:26:22 PM PDT 24
Finished Apr 04 01:26:24 PM PDT 24
Peak memory 203712 kb
Host smart-587c4a4f-deb6-4b4a-a0c9-589052afbb35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389339037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2389339037
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.1911470325
Short name T108
Test name
Test status
Simulation time 299995200 ps
CPU time 1.37 seconds
Started Apr 04 01:26:28 PM PDT 24
Finished Apr 04 01:26:30 PM PDT 24
Peak memory 203700 kb
Host smart-a09fdb4f-32d1-49a5-afe9-3fac88292b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911470325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1911470325
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1752815610
Short name T1228
Test name
Test status
Simulation time 20767473 ps
CPU time 0.73 seconds
Started Apr 04 01:26:35 PM PDT 24
Finished Apr 04 01:26:37 PM PDT 24
Peak memory 203456 kb
Host smart-08328b4d-b338-419d-a561-5fa099f7529c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752815610 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1752815610
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.665852291
Short name T1292
Test name
Test status
Simulation time 18998180 ps
CPU time 0.67 seconds
Started Apr 04 01:26:34 PM PDT 24
Finished Apr 04 01:26:35 PM PDT 24
Peak memory 203452 kb
Host smart-d6aae749-5514-4274-8248-9ff5c9176224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665852291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.665852291
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.755935290
Short name T1281
Test name
Test status
Simulation time 149891961 ps
CPU time 0.64 seconds
Started Apr 04 01:26:34 PM PDT 24
Finished Apr 04 01:26:35 PM PDT 24
Peak memory 203168 kb
Host smart-2797daf0-e5ec-401b-b0f9-9ba822d5e64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755935290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.755935290
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2160192168
Short name T1241
Test name
Test status
Simulation time 121198312 ps
CPU time 0.8 seconds
Started Apr 04 01:26:40 PM PDT 24
Finished Apr 04 01:26:42 PM PDT 24
Peak memory 203452 kb
Host smart-a2c400da-2b2b-4f62-93c8-b3d73bba3800
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160192168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2160192168
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.629897804
Short name T1226
Test name
Test status
Simulation time 580987575 ps
CPU time 2.69 seconds
Started Apr 04 01:26:23 PM PDT 24
Finished Apr 04 01:26:26 PM PDT 24
Peak memory 203684 kb
Host smart-2b58147d-8559-4dae-963e-785f5335746c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629897804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.629897804
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2245961519
Short name T107
Test name
Test status
Simulation time 282692076 ps
CPU time 1.92 seconds
Started Apr 04 01:26:35 PM PDT 24
Finished Apr 04 01:26:37 PM PDT 24
Peak memory 203556 kb
Host smart-f50479e1-f163-4b32-9dd1-c70abdc093b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245961519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2245961519
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2196708054
Short name T708
Test name
Test status
Simulation time 110523019 ps
CPU time 0.64 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:02:39 PM PDT 24
Peak memory 203492 kb
Host smart-1e5a6f17-7c5e-4a2e-b82c-332b9bde0574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196708054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2196708054
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.625922895
Short name T706
Test name
Test status
Simulation time 72971522 ps
CPU time 1.36 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:02:45 PM PDT 24
Peak memory 211984 kb
Host smart-0cbc79c1-f8f1-47ec-801b-6f4fb30ecc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625922895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.625922895
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2589236558
Short name T416
Test name
Test status
Simulation time 322505124 ps
CPU time 5.47 seconds
Started Apr 04 03:02:37 PM PDT 24
Finished Apr 04 03:02:42 PM PDT 24
Peak memory 251488 kb
Host smart-ac85ba42-3a0b-40ae-8568-873e5f924f20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589236558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2589236558
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.4145079782
Short name T922
Test name
Test status
Simulation time 1706799890 ps
CPU time 114.72 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:04:38 PM PDT 24
Peak memory 602968 kb
Host smart-15cf35ea-f05a-49ee-9467-8ce8b5e54bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145079782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.4145079782
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.268111759
Short name T661
Test name
Test status
Simulation time 1539929911 ps
CPU time 99.48 seconds
Started Apr 04 03:02:21 PM PDT 24
Finished Apr 04 03:04:01 PM PDT 24
Peak memory 524648 kb
Host smart-8f5bef13-2a07-4b53-ad09-7dfc0cf26eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268111759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.268111759
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.516313482
Short name T189
Test name
Test status
Simulation time 99177880 ps
CPU time 0.99 seconds
Started Apr 04 03:02:20 PM PDT 24
Finished Apr 04 03:02:21 PM PDT 24
Peak memory 203588 kb
Host smart-90210202-63fa-4f34-ab59-42a138d5ab39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516313482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.516313482
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1244545811
Short name T295
Test name
Test status
Simulation time 181776948 ps
CPU time 5.01 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:02:48 PM PDT 24
Peak memory 235632 kb
Host smart-b2665b95-59ba-4045-a6f4-f6cb875130f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244545811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1244545811
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3693974532
Short name T1171
Test name
Test status
Simulation time 4214962052 ps
CPU time 129.68 seconds
Started Apr 04 03:02:21 PM PDT 24
Finished Apr 04 03:04:31 PM PDT 24
Peak memory 1190884 kb
Host smart-ed16314e-a4ee-4d28-8be7-9f8ff328c09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693974532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3693974532
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1303476944
Short name T554
Test name
Test status
Simulation time 1970772206 ps
CPU time 21.88 seconds
Started Apr 04 03:02:37 PM PDT 24
Finished Apr 04 03:02:59 PM PDT 24
Peak memory 203740 kb
Host smart-eac44d73-3486-4646-9063-e2a75204e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303476944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1303476944
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1817599914
Short name T680
Test name
Test status
Simulation time 4802152629 ps
CPU time 21.68 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:03:00 PM PDT 24
Peak memory 313108 kb
Host smart-574493bf-28f6-4a53-a3da-35d34efd2b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817599914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1817599914
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.453368966
Short name T1124
Test name
Test status
Simulation time 45100578 ps
CPU time 0.64 seconds
Started Apr 04 03:02:19 PM PDT 24
Finished Apr 04 03:02:20 PM PDT 24
Peak memory 203424 kb
Host smart-d056745a-e1b1-40f4-87cf-9d0897fb4093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453368966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.453368966
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3962983177
Short name T943
Test name
Test status
Simulation time 3347701118 ps
CPU time 86.38 seconds
Started Apr 04 03:02:22 PM PDT 24
Finished Apr 04 03:03:48 PM PDT 24
Peak memory 405764 kb
Host smart-0be371d7-927e-49c1-8003-31c61bab424e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962983177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3962983177
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.72909827
Short name T450
Test name
Test status
Simulation time 2799917345 ps
CPU time 2.54 seconds
Started Apr 04 03:02:40 PM PDT 24
Finished Apr 04 03:02:42 PM PDT 24
Peak memory 203844 kb
Host smart-22415fc7-2056-4d1d-8993-16ba14860f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72909827 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_bad_addr.72909827
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2901750505
Short name T300
Test name
Test status
Simulation time 10103024938 ps
CPU time 95.84 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:04:15 PM PDT 24
Peak memory 740404 kb
Host smart-b978e989-cc13-499a-9024-22c48decceda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901750505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2901750505
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1715768831
Short name T646
Test name
Test status
Simulation time 1557086413 ps
CPU time 2.24 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:02:46 PM PDT 24
Peak memory 203744 kb
Host smart-b30e85c1-e01c-4477-873b-86b39ef811e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715768831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1715768831
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.4197018716
Short name T483
Test name
Test status
Simulation time 1181993437 ps
CPU time 3.72 seconds
Started Apr 04 03:02:37 PM PDT 24
Finished Apr 04 03:02:41 PM PDT 24
Peak memory 204476 kb
Host smart-25c5b650-a356-4445-9b3c-6b34bbd6444f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197018716 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.4197018716
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3966603564
Short name T486
Test name
Test status
Simulation time 1173079412 ps
CPU time 43.45 seconds
Started Apr 04 03:02:37 PM PDT 24
Finished Apr 04 03:03:21 PM PDT 24
Peak memory 203736 kb
Host smart-27eb7e62-53e9-46a9-94a8-8e6c2b3b6c96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966603564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3966603564
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.595782953
Short name T439
Test name
Test status
Simulation time 1018843504 ps
CPU time 9.04 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:02:47 PM PDT 24
Peak memory 203696 kb
Host smart-02ee4f91-117c-444b-b169-36ee7f3b8c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595782953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.595782953
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.394007669
Short name T158
Test name
Test status
Simulation time 15591755401 ps
CPU time 9.13 seconds
Started Apr 04 03:02:36 PM PDT 24
Finished Apr 04 03:02:45 PM PDT 24
Peak memory 203752 kb
Host smart-89b7a724-b588-4227-85d2-7f7451282f0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394007669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_wr.394007669
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3479170246
Short name T290
Test name
Test status
Simulation time 31720289901 ps
CPU time 290.22 seconds
Started Apr 04 03:02:36 PM PDT 24
Finished Apr 04 03:07:27 PM PDT 24
Peak memory 1940864 kb
Host smart-3b4d732f-cb1d-4bca-9260-8a1ac1324f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479170246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3479170246
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.692801022
Short name T826
Test name
Test status
Simulation time 1188958743 ps
CPU time 6.25 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:02:45 PM PDT 24
Peak memory 211968 kb
Host smart-f4fba74d-c64e-4f94-a8cd-1b5d8c953c1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692801022 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.692801022
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3258943947
Short name T828
Test name
Test status
Simulation time 70534902 ps
CPU time 1.18 seconds
Started Apr 04 03:02:41 PM PDT 24
Finished Apr 04 03:02:42 PM PDT 24
Peak memory 215708 kb
Host smart-f8ce829e-c59a-402d-92cc-bba7424f674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258943947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3258943947
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3346926942
Short name T866
Test name
Test status
Simulation time 515348231 ps
CPU time 8.96 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:02:47 PM PDT 24
Peak memory 287052 kb
Host smart-1cb8ec4d-7970-4984-a220-7297e6d9e075
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346926942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3346926942
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3173638508
Short name T4
Test name
Test status
Simulation time 1483558366 ps
CPU time 87.42 seconds
Started Apr 04 03:02:36 PM PDT 24
Finished Apr 04 03:04:04 PM PDT 24
Peak memory 446200 kb
Host smart-b47780de-e16d-46ed-8200-7bb53ad23f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173638508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3173638508
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1312986553
Short name T1120
Test name
Test status
Simulation time 523419117 ps
CPU time 1.21 seconds
Started Apr 04 03:02:37 PM PDT 24
Finished Apr 04 03:02:39 PM PDT 24
Peak memory 203664 kb
Host smart-9c839e63-9fdb-4d76-bff4-607a53921cf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312986553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1312986553
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.428497317
Short name T378
Test name
Test status
Simulation time 130855774 ps
CPU time 6.74 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:02:46 PM PDT 24
Peak memory 222060 kb
Host smart-a469026f-d573-44b2-8298-a8ebecbef8d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428497317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.428497317
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3247153801
Short name T1192
Test name
Test status
Simulation time 2500975506 ps
CPU time 52.39 seconds
Started Apr 04 03:02:40 PM PDT 24
Finished Apr 04 03:03:32 PM PDT 24
Peak memory 765384 kb
Host smart-9f58ebaa-52f4-4c2f-8fda-36b5d328dc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247153801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3247153801
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.4288366661
Short name T284
Test name
Test status
Simulation time 219145153 ps
CPU time 8.71 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:02:46 PM PDT 24
Peak memory 203716 kb
Host smart-2c3ef92c-f54e-4851-a950-cf2ba532e890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288366661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4288366661
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3267266433
Short name T305
Test name
Test status
Simulation time 1437539180 ps
CPU time 54.5 seconds
Started Apr 04 03:02:46 PM PDT 24
Finished Apr 04 03:03:40 PM PDT 24
Peak memory 297128 kb
Host smart-61ee4b15-423d-4fdf-9270-6f27b62e4da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267266433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3267266433
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2435703368
Short name T535
Test name
Test status
Simulation time 2575072755 ps
CPU time 174.14 seconds
Started Apr 04 03:02:40 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 790112 kb
Host smart-8afb1440-4d4a-4580-ab8d-5f04862b1337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435703368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2435703368
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2499372376
Short name T494
Test name
Test status
Simulation time 1550718096 ps
CPU time 36.09 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:03:14 PM PDT 24
Peak memory 462612 kb
Host smart-c2bd28bb-5bde-438a-adb6-7c9583d0c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499372376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2499372376
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3545595956
Short name T960
Test name
Test status
Simulation time 2154095510 ps
CPU time 2.96 seconds
Started Apr 04 03:02:37 PM PDT 24
Finished Apr 04 03:02:40 PM PDT 24
Peak memory 203692 kb
Host smart-c28f1b8c-1b6b-440a-aa58-5e9d2cc9e6aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545595956 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3545595956
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2166276372
Short name T1108
Test name
Test status
Simulation time 10038689139 ps
CPU time 80.47 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:04:04 PM PDT 24
Peak memory 685352 kb
Host smart-cf841a01-ecfa-450b-9975-449e9f663ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166276372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2166276372
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3458906856
Short name T799
Test name
Test status
Simulation time 599200501 ps
CPU time 3.32 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:02:42 PM PDT 24
Peak memory 203708 kb
Host smart-7ac2e814-123b-46ef-803f-d71191149078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458906856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3458906856
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2237158980
Short name T99
Test name
Test status
Simulation time 905314726 ps
CPU time 5.45 seconds
Started Apr 04 03:02:36 PM PDT 24
Finished Apr 04 03:02:42 PM PDT 24
Peak memory 203656 kb
Host smart-cabeb1b6-ac8b-4b51-99a3-0712b21a0693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237158980 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2237158980
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.607127753
Short name T309
Test name
Test status
Simulation time 8411319922 ps
CPU time 3.36 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:02:47 PM PDT 24
Peak memory 203748 kb
Host smart-51fd32b9-5538-4cd5-a7f1-d75b6b4b3e12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607127753 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.607127753
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3140820700
Short name T336
Test name
Test status
Simulation time 1553609895 ps
CPU time 16.01 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:02:56 PM PDT 24
Peak memory 203760 kb
Host smart-b172bd56-a287-4e31-9278-4213c96a02a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140820700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3140820700
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1347145998
Short name T251
Test name
Test status
Simulation time 935805519 ps
CPU time 39.75 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:03:18 PM PDT 24
Peak memory 203736 kb
Host smart-30a63c45-777f-4790-ba21-56e9dfd25d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347145998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1347145998
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.4066268926
Short name T980
Test name
Test status
Simulation time 31176618050 ps
CPU time 2469.32 seconds
Started Apr 04 03:02:40 PM PDT 24
Finished Apr 04 03:43:50 PM PDT 24
Peak memory 7352648 kb
Host smart-92b3581d-1e88-4f4c-9631-3a21710501ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066268926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.4066268926
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.434099674
Short name T512
Test name
Test status
Simulation time 2284952166 ps
CPU time 5.92 seconds
Started Apr 04 03:02:38 PM PDT 24
Finished Apr 04 03:02:44 PM PDT 24
Peak memory 219844 kb
Host smart-a90e1cae-0b13-49db-a1c1-d6354ad28fd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434099674 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.434099674
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1098911947
Short name T988
Test name
Test status
Simulation time 47552037 ps
CPU time 0.61 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:07 PM PDT 24
Peak memory 203572 kb
Host smart-251dc1f1-1d2d-4589-8717-3e8b146145cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098911947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1098911947
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1134041688
Short name T1185
Test name
Test status
Simulation time 270311269 ps
CPU time 1.22 seconds
Started Apr 04 03:03:59 PM PDT 24
Finished Apr 04 03:04:01 PM PDT 24
Peak memory 211976 kb
Host smart-20483f42-e39e-4b8b-a45d-554f62a457c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134041688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1134041688
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1064371585
Short name T1071
Test name
Test status
Simulation time 562797060 ps
CPU time 3.6 seconds
Started Apr 04 03:03:53 PM PDT 24
Finished Apr 04 03:03:57 PM PDT 24
Peak memory 230256 kb
Host smart-98591a20-f1c0-4758-9903-c7fa9dac785a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064371585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1064371585
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.174170095
Short name T60
Test name
Test status
Simulation time 5899719353 ps
CPU time 87.22 seconds
Started Apr 04 03:03:59 PM PDT 24
Finished Apr 04 03:05:27 PM PDT 24
Peak memory 506180 kb
Host smart-efbbd381-3ee3-4e12-bd02-63dcd4951b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174170095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.174170095
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1901602655
Short name T515
Test name
Test status
Simulation time 1169340826 ps
CPU time 32.68 seconds
Started Apr 04 03:03:56 PM PDT 24
Finished Apr 04 03:04:29 PM PDT 24
Peak memory 481820 kb
Host smart-20bedf58-c05c-4088-9fc5-5e60a2417817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901602655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1901602655
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3911249475
Short name T192
Test name
Test status
Simulation time 197145506 ps
CPU time 0.91 seconds
Started Apr 04 03:03:56 PM PDT 24
Finished Apr 04 03:03:57 PM PDT 24
Peak memory 203604 kb
Host smart-2159b7d0-47a6-4cfc-b8d9-3ed3d15ece46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911249475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3911249475
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1557003224
Short name T1032
Test name
Test status
Simulation time 529014292 ps
CPU time 7.77 seconds
Started Apr 04 03:04:09 PM PDT 24
Finished Apr 04 03:04:18 PM PDT 24
Peak memory 203776 kb
Host smart-a7c20cd8-fff0-44ee-8dd7-235d75a0d27e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557003224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1557003224
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3981351578
Short name T484
Test name
Test status
Simulation time 10744089706 ps
CPU time 245.08 seconds
Started Apr 04 03:03:50 PM PDT 24
Finished Apr 04 03:07:56 PM PDT 24
Peak memory 1031108 kb
Host smart-c717d814-9d49-4b17-bc02-6503afb01968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981351578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3981351578
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2710971249
Short name T702
Test name
Test status
Simulation time 305444748 ps
CPU time 3.68 seconds
Started Apr 04 03:04:07 PM PDT 24
Finished Apr 04 03:04:11 PM PDT 24
Peak memory 203716 kb
Host smart-11874020-6639-4f99-9049-f656e93cbd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710971249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2710971249
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1707077509
Short name T761
Test name
Test status
Simulation time 1453763228 ps
CPU time 29.07 seconds
Started Apr 04 03:04:02 PM PDT 24
Finished Apr 04 03:04:31 PM PDT 24
Peak memory 350204 kb
Host smart-6c5ce434-3b78-4891-995b-052119532ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707077509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1707077509
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2033348633
Short name T462
Test name
Test status
Simulation time 193712210 ps
CPU time 0.65 seconds
Started Apr 04 03:03:56 PM PDT 24
Finished Apr 04 03:03:57 PM PDT 24
Peak memory 203504 kb
Host smart-33e22710-62af-44cf-90cc-99c9d1cb0a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033348633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2033348633
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.820361305
Short name T1160
Test name
Test status
Simulation time 3047993176 ps
CPU time 12.5 seconds
Started Apr 04 03:04:00 PM PDT 24
Finished Apr 04 03:04:12 PM PDT 24
Peak memory 219764 kb
Host smart-2a15f449-cbde-44d9-ae7b-a50d50f7e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820361305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.820361305
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3110951439
Short name T394
Test name
Test status
Simulation time 3012059166 ps
CPU time 29.09 seconds
Started Apr 04 03:03:56 PM PDT 24
Finished Apr 04 03:04:26 PM PDT 24
Peak memory 354536 kb
Host smart-5ba2c07f-ce84-40fe-ba9b-d6e0fac7fc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110951439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3110951439
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1951642332
Short name T811
Test name
Test status
Simulation time 860634914 ps
CPU time 3.5 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:10 PM PDT 24
Peak memory 203664 kb
Host smart-f11f2b88-c315-40dc-879d-5eb90a60d762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951642332 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1951642332
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1229922180
Short name T926
Test name
Test status
Simulation time 10241092213 ps
CPU time 14.24 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:04:25 PM PDT 24
Peak memory 311364 kb
Host smart-ddd5a5d9-5d82-4b47-b29e-a00e359b8f8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229922180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1229922180
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.325232960
Short name T784
Test name
Test status
Simulation time 10122865758 ps
CPU time 16.76 seconds
Started Apr 04 03:04:02 PM PDT 24
Finished Apr 04 03:04:19 PM PDT 24
Peak memory 342056 kb
Host smart-60cf6344-412f-4148-a986-640f8f63677c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325232960 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.325232960
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.3518186295
Short name T857
Test name
Test status
Simulation time 1349562424 ps
CPU time 6.81 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:04:17 PM PDT 24
Peak memory 218544 kb
Host smart-fa8f4803-ef49-4c8d-ae8f-ae8340146c08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518186295 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.3518186295
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.947785950
Short name T746
Test name
Test status
Simulation time 496104621 ps
CPU time 7.86 seconds
Started Apr 04 03:04:02 PM PDT 24
Finished Apr 04 03:04:10 PM PDT 24
Peak memory 203752 kb
Host smart-a2750439-d192-4489-9387-9545878794c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947785950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.947785950
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.607473899
Short name T488
Test name
Test status
Simulation time 20699690609 ps
CPU time 72.7 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 209460 kb
Host smart-18cf1247-9756-4225-81f8-8cf7c8352e7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607473899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.607473899
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2349566252
Short name T924
Test name
Test status
Simulation time 23606456143 ps
CPU time 142.04 seconds
Started Apr 04 03:04:03 PM PDT 24
Finished Apr 04 03:06:25 PM PDT 24
Peak memory 1318148 kb
Host smart-41dcd9a4-9447-4ad1-b512-77fc54b1d650
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349566252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2349566252
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1977627525
Short name T707
Test name
Test status
Simulation time 2654705580 ps
CPU time 6.39 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:04:17 PM PDT 24
Peak memory 211596 kb
Host smart-1209ee44-5098-44db-a8dd-ef36c9210de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977627525 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1977627525
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2969786449
Short name T322
Test name
Test status
Simulation time 37647388 ps
CPU time 0.62 seconds
Started Apr 04 03:03:59 PM PDT 24
Finished Apr 04 03:04:00 PM PDT 24
Peak memory 203452 kb
Host smart-1e75b656-5fe5-4d74-b320-d5af5c4ef29a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969786449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2969786449
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2303063109
Short name T1010
Test name
Test status
Simulation time 326480859 ps
CPU time 1.66 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:04:12 PM PDT 24
Peak memory 212020 kb
Host smart-362dc61e-f7a9-493a-b833-7096b7efcc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303063109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2303063109
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.702437772
Short name T526
Test name
Test status
Simulation time 810348409 ps
CPU time 7.34 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:13 PM PDT 24
Peak memory 278408 kb
Host smart-789d4c51-de7c-4367-b36e-e84d3f1455d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702437772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.702437772
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3765526790
Short name T285
Test name
Test status
Simulation time 1978299238 ps
CPU time 56.43 seconds
Started Apr 04 03:04:00 PM PDT 24
Finished Apr 04 03:04:57 PM PDT 24
Peak memory 589776 kb
Host smart-c0a775dd-13d8-46c8-88bf-37d22e5479c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765526790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3765526790
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.623173753
Short name T593
Test name
Test status
Simulation time 8148261721 ps
CPU time 162.45 seconds
Started Apr 04 03:04:01 PM PDT 24
Finished Apr 04 03:06:43 PM PDT 24
Peak memory 730416 kb
Host smart-589285e0-98cd-41d1-96e0-c15d977fadb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623173753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.623173753
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3392863439
Short name T301
Test name
Test status
Simulation time 193846053 ps
CPU time 4.55 seconds
Started Apr 04 03:04:07 PM PDT 24
Finished Apr 04 03:04:12 PM PDT 24
Peak memory 237716 kb
Host smart-01c5e418-524d-4c21-8689-dd5f3db0f1b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392863439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3392863439
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.827668919
Short name T856
Test name
Test status
Simulation time 8655256376 ps
CPU time 114.22 seconds
Started Apr 04 03:04:01 PM PDT 24
Finished Apr 04 03:05:56 PM PDT 24
Peak memory 1279492 kb
Host smart-9d770773-a7ea-40b1-954c-17d472c21018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827668919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.827668919
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.238277782
Short name T528
Test name
Test status
Simulation time 414939296 ps
CPU time 17.3 seconds
Started Apr 04 03:03:59 PM PDT 24
Finished Apr 04 03:04:16 PM PDT 24
Peak memory 203688 kb
Host smart-bb49217a-55cf-4734-87e1-a688adfd7d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238277782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.238277782
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3811677039
Short name T579
Test name
Test status
Simulation time 7923234589 ps
CPU time 27.24 seconds
Started Apr 04 03:04:05 PM PDT 24
Finished Apr 04 03:04:32 PM PDT 24
Peak memory 373520 kb
Host smart-10e8500c-78bb-4a7b-a491-79759e3ff7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811677039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3811677039
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.3454456975
Short name T166
Test name
Test status
Simulation time 54302576 ps
CPU time 0.63 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:04:11 PM PDT 24
Peak memory 203520 kb
Host smart-9b9c4788-f881-4801-b703-aa769448cdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454456975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3454456975
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2896396962
Short name T45
Test name
Test status
Simulation time 12805917694 ps
CPU time 45.57 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:04:56 PM PDT 24
Peak memory 203904 kb
Host smart-15a4611d-b139-483f-a668-b3c215017b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896396962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2896396962
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1709928403
Short name T1159
Test name
Test status
Simulation time 2073112993 ps
CPU time 23.39 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 360048 kb
Host smart-ed517c8d-51f0-42af-97c4-962ea497ed7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709928403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1709928403
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1563823950
Short name T1021
Test name
Test status
Simulation time 1131363814 ps
CPU time 3.8 seconds
Started Apr 04 03:04:00 PM PDT 24
Finished Apr 04 03:04:03 PM PDT 24
Peak memory 203696 kb
Host smart-26c7da16-51aa-4e59-b3a1-c07117693a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563823950 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1563823950
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1866042667
Short name T1129
Test name
Test status
Simulation time 10635964781 ps
CPU time 9.22 seconds
Started Apr 04 03:04:09 PM PDT 24
Finished Apr 04 03:04:19 PM PDT 24
Peak memory 269496 kb
Host smart-f04318d1-4f6b-4f01-a861-4fdfe7d94819
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866042667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1866042667
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4066763744
Short name T602
Test name
Test status
Simulation time 10774015742 ps
CPU time 15.33 seconds
Started Apr 04 03:04:05 PM PDT 24
Finished Apr 04 03:04:21 PM PDT 24
Peak memory 328504 kb
Host smart-29eea5b8-283c-426b-a25c-a0b89dc9e797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066763744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.4066763744
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3865399358
Short name T1164
Test name
Test status
Simulation time 1858646419 ps
CPU time 2.88 seconds
Started Apr 04 03:04:00 PM PDT 24
Finished Apr 04 03:04:03 PM PDT 24
Peak memory 203752 kb
Host smart-9d3dc096-5830-43d2-acd9-28bc10445ec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865399358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3865399358
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3527667012
Short name T277
Test name
Test status
Simulation time 1186159873 ps
CPU time 6 seconds
Started Apr 04 03:04:00 PM PDT 24
Finished Apr 04 03:04:07 PM PDT 24
Peak memory 208876 kb
Host smart-42f2bd8f-79a1-484a-a826-f76abf05a54c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527667012 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3527667012
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.4186294652
Short name T765
Test name
Test status
Simulation time 1059317435 ps
CPU time 33.11 seconds
Started Apr 04 03:04:00 PM PDT 24
Finished Apr 04 03:04:33 PM PDT 24
Peak memory 203760 kb
Host smart-7065e644-5ed6-4c77-b036-a2d71ac0167f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186294652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.4186294652
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.621066263
Short name T472
Test name
Test status
Simulation time 1689690366 ps
CPU time 12.92 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:19 PM PDT 24
Peak memory 214552 kb
Host smart-c05dbe3f-d376-497e-b0de-c6e95394b84c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621066263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.621066263
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.928526960
Short name T319
Test name
Test status
Simulation time 46207152652 ps
CPU time 101.38 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:05:52 PM PDT 24
Peak memory 453892 kb
Host smart-9e2f2e36-812a-4437-a31f-3190816bf795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928526960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.928526960
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1765431884
Short name T929
Test name
Test status
Simulation time 1874343069 ps
CPU time 6.7 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:13 PM PDT 24
Peak memory 211932 kb
Host smart-23b78f7d-6807-45e7-8f97-6a6930c0f48e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765431884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1765431884
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2769939244
Short name T917
Test name
Test status
Simulation time 22803870 ps
CPU time 0.68 seconds
Started Apr 04 03:04:03 PM PDT 24
Finished Apr 04 03:04:04 PM PDT 24
Peak memory 203580 kb
Host smart-954a08ed-0626-4d07-bee0-fab8042b2fda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769939244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2769939244
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2949596360
Short name T573
Test name
Test status
Simulation time 93105283 ps
CPU time 1.63 seconds
Started Apr 04 03:04:02 PM PDT 24
Finished Apr 04 03:04:04 PM PDT 24
Peak memory 211912 kb
Host smart-e747a5a3-028c-4cb2-a19c-cebecf1ce66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949596360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2949596360
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3478725079
Short name T878
Test name
Test status
Simulation time 609886275 ps
CPU time 5.42 seconds
Started Apr 04 03:04:07 PM PDT 24
Finished Apr 04 03:04:13 PM PDT 24
Peak memory 262320 kb
Host smart-f51dd72d-2f12-43c2-9732-17f03bb8d302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478725079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3478725079
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1114779425
Short name T983
Test name
Test status
Simulation time 3717299705 ps
CPU time 88.04 seconds
Started Apr 04 03:04:01 PM PDT 24
Finished Apr 04 03:05:29 PM PDT 24
Peak memory 526272 kb
Host smart-fd864070-a89c-4580-83aa-5cf9baee0679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114779425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1114779425
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2187464710
Short name T259
Test name
Test status
Simulation time 1423916316 ps
CPU time 100 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:05:44 PM PDT 24
Peak memory 553664 kb
Host smart-d7bc0e64-5b09-4fa3-bfbd-ce61beea5373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187464710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2187464710
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2985230497
Short name T1065
Test name
Test status
Simulation time 2267941394 ps
CPU time 1.21 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:04:06 PM PDT 24
Peak memory 203692 kb
Host smart-37d7f8ca-ffae-4dd7-9146-7536f2f23593
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985230497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2985230497
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3647695084
Short name T272
Test name
Test status
Simulation time 225225544 ps
CPU time 6.64 seconds
Started Apr 04 03:04:07 PM PDT 24
Finished Apr 04 03:04:14 PM PDT 24
Peak memory 222320 kb
Host smart-fc958375-eef5-4a8e-879c-8792343cbfb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647695084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3647695084
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.673821573
Short name T625
Test name
Test status
Simulation time 2998409807 ps
CPU time 195.49 seconds
Started Apr 04 03:04:07 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 904808 kb
Host smart-339cd96e-f658-4e35-9a0f-d915970b443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673821573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.673821573
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.892526584
Short name T228
Test name
Test status
Simulation time 1180309623 ps
CPU time 11.21 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:04:15 PM PDT 24
Peak memory 203640 kb
Host smart-534e1d71-8dc8-4ba6-8fc8-ab7202e4b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892526584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.892526584
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3766142615
Short name T18
Test name
Test status
Simulation time 16358667758 ps
CPU time 57.15 seconds
Started Apr 04 03:04:02 PM PDT 24
Finished Apr 04 03:04:59 PM PDT 24
Peak memory 326364 kb
Host smart-7acc37d6-1e91-4379-9fe7-135ffe02a3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766142615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3766142615
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3184982483
Short name T337
Test name
Test status
Simulation time 24778553 ps
CPU time 0.64 seconds
Started Apr 04 03:04:07 PM PDT 24
Finished Apr 04 03:04:08 PM PDT 24
Peak memory 203524 kb
Host smart-b71956ef-6dfc-4b5c-b5d4-18875d99b440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184982483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3184982483
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3493563789
Short name T1190
Test name
Test status
Simulation time 556797194 ps
CPU time 11.1 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:17 PM PDT 24
Peak memory 228196 kb
Host smart-ff139953-eec9-4565-b94a-5fca64c22037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493563789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3493563789
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.576396264
Short name T629
Test name
Test status
Simulation time 5097228829 ps
CPU time 66.59 seconds
Started Apr 04 03:04:10 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 405288 kb
Host smart-68ac362d-4bf5-4fcd-a1ca-15f1e5ef2282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576396264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.576396264
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.451550560
Short name T721
Test name
Test status
Simulation time 853704591 ps
CPU time 4.11 seconds
Started Apr 04 03:04:07 PM PDT 24
Finished Apr 04 03:04:11 PM PDT 24
Peak memory 203764 kb
Host smart-d7fcd32b-d787-442b-b9b5-f57ddcff0c05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451550560 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.451550560
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3864905066
Short name T787
Test name
Test status
Simulation time 10079353365 ps
CPU time 88.54 seconds
Started Apr 04 03:04:09 PM PDT 24
Finished Apr 04 03:05:38 PM PDT 24
Peak memory 565764 kb
Host smart-0b12f71f-cac3-4e0c-869d-fce35a0da160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864905066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3864905066
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2890903221
Short name T7
Test name
Test status
Simulation time 10298145940 ps
CPU time 41.66 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:04:45 PM PDT 24
Peak memory 527444 kb
Host smart-8cf4595e-0aa7-40ac-8546-b1408b6d77f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890903221 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2890903221
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.2820487798
Short name T344
Test name
Test status
Simulation time 1693890313 ps
CPU time 2.55 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:09 PM PDT 24
Peak memory 203676 kb
Host smart-ca432cd8-e470-4de5-9e3a-666bab428f35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820487798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.2820487798
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.598123570
Short name T803
Test name
Test status
Simulation time 1296020872 ps
CPU time 7.82 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:04:13 PM PDT 24
Peak memory 218196 kb
Host smart-deb0bf56-4cb6-49cf-9eca-68f627771389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598123570 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.598123570
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.539213966
Short name T1157
Test name
Test status
Simulation time 1330986091 ps
CPU time 25.31 seconds
Started Apr 04 03:04:03 PM PDT 24
Finished Apr 04 03:04:29 PM PDT 24
Peak memory 203760 kb
Host smart-877bf730-af79-48aa-82af-cad9bfe1a5b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539213966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_tar
get_smoke.539213966
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.801334750
Short name T204
Test name
Test status
Simulation time 24405926894 ps
CPU time 25.11 seconds
Started Apr 04 03:04:00 PM PDT 24
Finished Apr 04 03:04:25 PM PDT 24
Peak memory 228336 kb
Host smart-97f4bfd5-f594-4821-8f6a-b3edb16cefb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801334750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.801334750
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1563909332
Short name T1121
Test name
Test status
Simulation time 11083228763 ps
CPU time 114.44 seconds
Started Apr 04 03:04:05 PM PDT 24
Finished Apr 04 03:06:00 PM PDT 24
Peak memory 623512 kb
Host smart-89de7a82-82d9-4dd8-9aa7-f827204e3006
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563909332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1563909332
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3489523801
Short name T376
Test name
Test status
Simulation time 1120174993 ps
CPU time 6.41 seconds
Started Apr 04 03:04:02 PM PDT 24
Finished Apr 04 03:04:08 PM PDT 24
Peak memory 203748 kb
Host smart-b6b36314-34c4-4f5d-ba7d-3a229e489a40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489523801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3489523801
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2614234497
Short name T501
Test name
Test status
Simulation time 18235879 ps
CPU time 0.61 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:04:15 PM PDT 24
Peak memory 203412 kb
Host smart-45235f87-72a4-4979-8926-5f55a36f3638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614234497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2614234497
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.695518426
Short name T50
Test name
Test status
Simulation time 156299946 ps
CPU time 1.14 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:04:15 PM PDT 24
Peak memory 214388 kb
Host smart-4f49afa1-d469-436a-8f5f-96fb5f614dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695518426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.695518426
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2448270925
Short name T553
Test name
Test status
Simulation time 821509129 ps
CPU time 5.49 seconds
Started Apr 04 03:04:16 PM PDT 24
Finished Apr 04 03:04:23 PM PDT 24
Peak memory 247900 kb
Host smart-c74d1a55-bb81-4af3-b044-b80932cea910
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448270925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2448270925
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1335259750
Short name T651
Test name
Test status
Simulation time 1696924607 ps
CPU time 44.8 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:05:00 PM PDT 24
Peak memory 417232 kb
Host smart-de305054-591f-48e1-b54c-e6979fc347cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335259750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1335259750
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3339927363
Short name T276
Test name
Test status
Simulation time 4799278623 ps
CPU time 83.46 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:05:30 PM PDT 24
Peak memory 503420 kb
Host smart-fda7e899-ffdc-481a-af84-c5b25c9842e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339927363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3339927363
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.4086620811
Short name T191
Test name
Test status
Simulation time 91069808 ps
CPU time 0.98 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:04:06 PM PDT 24
Peak memory 203576 kb
Host smart-8f5acfdf-35d8-4ffc-8d29-4bd690896f84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086620811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.4086620811
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2460098854
Short name T524
Test name
Test status
Simulation time 110021638 ps
CPU time 3.47 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:04:17 PM PDT 24
Peak memory 219920 kb
Host smart-e345cb21-248a-4e63-8b17-7d066d26fe6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460098854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2460098854
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.196916682
Short name T825
Test name
Test status
Simulation time 4769459748 ps
CPU time 143.92 seconds
Started Apr 04 03:04:04 PM PDT 24
Finished Apr 04 03:06:28 PM PDT 24
Peak memory 753644 kb
Host smart-5c5698b8-448c-4632-be5c-50b227dc916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196916682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.196916682
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.158970201
Short name T368
Test name
Test status
Simulation time 555538379 ps
CPU time 4.68 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:04:18 PM PDT 24
Peak memory 203716 kb
Host smart-ad58055a-cd9d-4e0f-82b2-60b9d70a2786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158970201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.158970201
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1555423550
Short name T17
Test name
Test status
Simulation time 3793418277 ps
CPU time 21.69 seconds
Started Apr 04 03:04:12 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 379712 kb
Host smart-f63ca15d-82f6-4379-b9bb-067aa33f06cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555423550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1555423550
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1248971492
Short name T1194
Test name
Test status
Simulation time 28577961 ps
CPU time 0.67 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:07 PM PDT 24
Peak memory 203532 kb
Host smart-0a823575-7552-4146-ba8f-d47a4bc05433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248971492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1248971492
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1468742558
Short name T182
Test name
Test status
Simulation time 5694936489 ps
CPU time 98.84 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:05:52 PM PDT 24
Peak memory 444784 kb
Host smart-ff0a498e-5ab1-44b9-b59a-201079bef3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468742558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1468742558
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3532667171
Short name T1135
Test name
Test status
Simulation time 2560396623 ps
CPU time 30.15 seconds
Started Apr 04 03:04:06 PM PDT 24
Finished Apr 04 03:04:36 PM PDT 24
Peak memory 405320 kb
Host smart-c45ced86-df88-4398-984e-59e2a786d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532667171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3532667171
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3628296386
Short name T612
Test name
Test status
Simulation time 10207764155 ps
CPU time 3.46 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:19 PM PDT 24
Peak memory 212032 kb
Host smart-7975b0b3-89f7-41c6-8c36-f1fd606a50a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628296386 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3628296386
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.4107464742
Short name T441
Test name
Test status
Simulation time 10141930459 ps
CPU time 22.81 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:04:36 PM PDT 24
Peak memory 323440 kb
Host smart-83185ab3-a89b-4bb1-af46-23b1bd1d03ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107464742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.4107464742
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.234976796
Short name T435
Test name
Test status
Simulation time 10080898392 ps
CPU time 111.07 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 721484 kb
Host smart-e9d32cc8-270c-4b18-8129-4e9c2174234b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234976796 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.234976796
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2008907007
Short name T492
Test name
Test status
Simulation time 1342696892 ps
CPU time 2.27 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:04:16 PM PDT 24
Peak memory 203696 kb
Host smart-6ef9170b-d15c-40ff-a5ef-7536ff0ea58f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008907007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2008907007
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.145939908
Short name T503
Test name
Test status
Simulation time 1289168631 ps
CPU time 6.09 seconds
Started Apr 04 03:04:21 PM PDT 24
Finished Apr 04 03:04:28 PM PDT 24
Peak memory 219876 kb
Host smart-0746a4a9-c48c-431a-99f7-bbc9cc987c5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145939908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.145939908
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.857192529
Short name T352
Test name
Test status
Simulation time 986024572 ps
CPU time 15.48 seconds
Started Apr 04 03:04:12 PM PDT 24
Finished Apr 04 03:04:28 PM PDT 24
Peak memory 203728 kb
Host smart-d50db435-4293-4050-981c-4175da96f541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857192529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.857192529
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1064878209
Short name T370
Test name
Test status
Simulation time 4367964904 ps
CPU time 18.07 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:33 PM PDT 24
Peak memory 220372 kb
Host smart-1efff832-b1ea-47a7-a6d8-887225ea1014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064878209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1064878209
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.182225182
Short name T865
Test name
Test status
Simulation time 49210503499 ps
CPU time 272.37 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:08:46 PM PDT 24
Peak memory 863304 kb
Host smart-14f37b30-2728-4947-9edb-637bfa9cb957
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182225182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.182225182
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1220075873
Short name T478
Test name
Test status
Simulation time 1385944932 ps
CPU time 7.19 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:04:21 PM PDT 24
Peak memory 219960 kb
Host smart-c77b8cdb-2926-49f4-a7e1-6c9e7936da18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220075873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1220075873
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2988196272
Short name T872
Test name
Test status
Simulation time 26950791 ps
CPU time 0.67 seconds
Started Apr 04 03:04:22 PM PDT 24
Finished Apr 04 03:04:22 PM PDT 24
Peak memory 203636 kb
Host smart-7ba577ec-4662-44af-9e40-a6c5b673015a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988196272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2988196272
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.103774017
Short name T677
Test name
Test status
Simulation time 184554468 ps
CPU time 1.48 seconds
Started Apr 04 03:04:16 PM PDT 24
Finished Apr 04 03:04:18 PM PDT 24
Peak memory 212004 kb
Host smart-7b329922-3bca-4378-a291-bf073319692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103774017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.103774017
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1702283621
Short name T466
Test name
Test status
Simulation time 1314774409 ps
CPU time 7.2 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:04:21 PM PDT 24
Peak memory 286196 kb
Host smart-aac91fd8-5f63-4783-9180-b4f90252e0b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702283621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1702283621
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.3802917427
Short name T405
Test name
Test status
Simulation time 9833405631 ps
CPU time 189.77 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:07:25 PM PDT 24
Peak memory 793040 kb
Host smart-b1b37536-df7f-4921-9378-cef5ccb15006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802917427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3802917427
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1543841697
Short name T1125
Test name
Test status
Simulation time 2722471730 ps
CPU time 44.03 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:59 PM PDT 24
Peak memory 523548 kb
Host smart-dc8ee67e-97c1-48aa-942a-49aa804d24f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543841697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1543841697
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2975505372
Short name T745
Test name
Test status
Simulation time 106295515 ps
CPU time 0.91 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:17 PM PDT 24
Peak memory 203608 kb
Host smart-3fe5da36-cd83-49fb-b2c4-1c8faa24f57d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975505372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2975505372
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1444278961
Short name T83
Test name
Test status
Simulation time 839742518 ps
CPU time 4.68 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:04:18 PM PDT 24
Peak memory 203736 kb
Host smart-3bf74ed5-ef7a-4166-88bc-9d848bbc29a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444278961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1444278961
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3358078969
Short name T767
Test name
Test status
Simulation time 16769847440 ps
CPU time 134.92 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:06:29 PM PDT 24
Peak memory 1207044 kb
Host smart-4f262cb8-f6da-4964-8926-c2272231e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358078969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3358078969
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2412205265
Short name T979
Test name
Test status
Simulation time 1889878266 ps
CPU time 6.16 seconds
Started Apr 04 03:04:18 PM PDT 24
Finished Apr 04 03:04:25 PM PDT 24
Peak memory 203732 kb
Host smart-f3087f7e-5d95-41f0-a535-179dce97db2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412205265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2412205265
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2751461467
Short name T589
Test name
Test status
Simulation time 7766015419 ps
CPU time 70.87 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:05:26 PM PDT 24
Peak memory 397928 kb
Host smart-fe060419-8963-4352-9c54-4677436798d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751461467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2751461467
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3791880603
Short name T1144
Test name
Test status
Simulation time 82571805 ps
CPU time 0.67 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:16 PM PDT 24
Peak memory 203516 kb
Host smart-2b5ccf57-7b7a-4337-b514-a64987a09f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791880603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3791880603
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1503012914
Short name T832
Test name
Test status
Simulation time 27410425940 ps
CPU time 1093.67 seconds
Started Apr 04 03:04:21 PM PDT 24
Finished Apr 04 03:22:35 PM PDT 24
Peak memory 203832 kb
Host smart-8a254af2-5fbb-4575-93c8-a4cf41d1509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503012914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1503012914
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2051773170
Short name T862
Test name
Test status
Simulation time 6507641258 ps
CPU time 27.57 seconds
Started Apr 04 03:04:22 PM PDT 24
Finished Apr 04 03:04:49 PM PDT 24
Peak memory 349796 kb
Host smart-5bdb8136-214b-4311-8467-9d57d64cb9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051773170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2051773170
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.290978490
Short name T890
Test name
Test status
Simulation time 3314199229 ps
CPU time 3.92 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:19 PM PDT 24
Peak memory 204528 kb
Host smart-8debdde4-9e93-4f15-a84c-ed8582718e7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290978490 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.290978490
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.912048584
Short name T574
Test name
Test status
Simulation time 10712454759 ps
CPU time 14.17 seconds
Started Apr 04 03:04:16 PM PDT 24
Finished Apr 04 03:04:31 PM PDT 24
Peak memory 294400 kb
Host smart-65de13e1-4605-4a1e-b5ab-6884ab047abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912048584 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.912048584
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.436050
Short name T1083
Test name
Test status
Simulation time 559875073 ps
CPU time 3.13 seconds
Started Apr 04 03:04:17 PM PDT 24
Finished Apr 04 03:04:21 PM PDT 24
Peak memory 203768 kb
Host smart-f6ad449d-55a2-4e19-be7e-8b5f9dafbaeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436050 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.i2c_target_hrst.436050
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3826398402
Short name T1167
Test name
Test status
Simulation time 13326613036 ps
CPU time 5.89 seconds
Started Apr 04 03:04:14 PM PDT 24
Finished Apr 04 03:04:21 PM PDT 24
Peak memory 219572 kb
Host smart-f610807c-d6a1-4bbd-9502-f4bfcc544db6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826398402 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3826398402
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1122528715
Short name T1024
Test name
Test status
Simulation time 448526337 ps
CPU time 6.67 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:22 PM PDT 24
Peak memory 203712 kb
Host smart-f9d4c833-8cd2-40ee-b0f7-870515aa06b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122528715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1122528715
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.4066832061
Short name T842
Test name
Test status
Simulation time 6477023977 ps
CPU time 30.68 seconds
Started Apr 04 03:04:13 PM PDT 24
Finished Apr 04 03:04:44 PM PDT 24
Peak memory 224016 kb
Host smart-1b43a275-813a-4635-8abc-2ea64a5849ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066832061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.4066832061
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3101103787
Short name T864
Test name
Test status
Simulation time 31252419713 ps
CPU time 426.15 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:11:22 PM PDT 24
Peak memory 1753232 kb
Host smart-c64c63e4-6fe6-4bde-981f-434df6adab0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101103787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3101103787
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1551104033
Short name T1187
Test name
Test status
Simulation time 3164454240 ps
CPU time 7.1 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:23 PM PDT 24
Peak memory 212188 kb
Host smart-4fd0469e-9800-4c11-bead-96b92846ed18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551104033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1551104033
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3380247739
Short name T155
Test name
Test status
Simulation time 45763001 ps
CPU time 0.59 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:28 PM PDT 24
Peak memory 203568 kb
Host smart-54cdf13d-dcc1-4475-9e29-4289732ae8bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380247739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3380247739
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.184098446
Short name T809
Test name
Test status
Simulation time 87402244 ps
CPU time 1.51 seconds
Started Apr 04 03:04:24 PM PDT 24
Finished Apr 04 03:04:26 PM PDT 24
Peak memory 211976 kb
Host smart-7703a568-60d2-4a26-bb92-b1f3f9444681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184098446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.184098446
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.4237586184
Short name T1077
Test name
Test status
Simulation time 1154619977 ps
CPU time 14.11 seconds
Started Apr 04 03:04:22 PM PDT 24
Finished Apr 04 03:04:36 PM PDT 24
Peak memory 256040 kb
Host smart-b31aaa82-5e67-42aa-b7b0-f14724b8fd9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237586184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.4237586184
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1060343463
Short name T637
Test name
Test status
Simulation time 7984723454 ps
CPU time 69.94 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:05:41 PM PDT 24
Peak memory 683008 kb
Host smart-52ceb0d6-3ccb-4ade-a8fd-842d328ace32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060343463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1060343463
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3059047511
Short name T738
Test name
Test status
Simulation time 4417719377 ps
CPU time 80.74 seconds
Started Apr 04 03:04:17 PM PDT 24
Finished Apr 04 03:05:38 PM PDT 24
Peak memory 741576 kb
Host smart-8205bb73-989e-47d8-90aa-367cafa4690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059047511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3059047511
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2799759302
Short name T1059
Test name
Test status
Simulation time 267054851 ps
CPU time 1.22 seconds
Started Apr 04 03:04:21 PM PDT 24
Finished Apr 04 03:04:23 PM PDT 24
Peak memory 203724 kb
Host smart-fca56ba5-9d47-4274-9f26-371e7d9e6037
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799759302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2799759302
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3008406534
Short name T1048
Test name
Test status
Simulation time 137505391 ps
CPU time 7.66 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:04:39 PM PDT 24
Peak memory 224428 kb
Host smart-185e62a9-8c2f-4c85-b9d8-3ca830f8ddb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008406534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3008406534
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1296335528
Short name T1068
Test name
Test status
Simulation time 384637909 ps
CPU time 6.94 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:04:36 PM PDT 24
Peak memory 203656 kb
Host smart-8335069d-15d9-48cd-ba37-e89add5a163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296335528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1296335528
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.51297243
Short name T1057
Test name
Test status
Simulation time 1678702431 ps
CPU time 35.3 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:05:03 PM PDT 24
Peak memory 465380 kb
Host smart-34c99f3b-482e-457c-a437-9ab17786b29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51297243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.51297243
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.3011139685
Short name T171
Test name
Test status
Simulation time 31086817 ps
CPU time 0.66 seconds
Started Apr 04 03:04:15 PM PDT 24
Finished Apr 04 03:04:16 PM PDT 24
Peak memory 203500 kb
Host smart-fb80a45f-b0e5-477e-bd95-aa7b6ff25d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011139685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3011139685
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3859762617
Short name T831
Test name
Test status
Simulation time 7065228569 ps
CPU time 267.37 seconds
Started Apr 04 03:04:25 PM PDT 24
Finished Apr 04 03:08:53 PM PDT 24
Peak memory 1017032 kb
Host smart-6e0e03c5-5d57-449c-84ab-1bc63ba9187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859762617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3859762617
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2558879611
Short name T627
Test name
Test status
Simulation time 5732171912 ps
CPU time 25.12 seconds
Started Apr 04 03:04:17 PM PDT 24
Finished Apr 04 03:04:43 PM PDT 24
Peak memory 364776 kb
Host smart-5af7d0be-529d-4ca2-9f33-c7ce5a172b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558879611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2558879611
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2787829539
Short name T658
Test name
Test status
Simulation time 728810715 ps
CPU time 3.42 seconds
Started Apr 04 03:04:24 PM PDT 24
Finished Apr 04 03:04:28 PM PDT 24
Peak memory 203712 kb
Host smart-76fd41b6-9a4d-4b7a-a8a2-20d1eeb06e7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787829539 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2787829539
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.4191764765
Short name T659
Test name
Test status
Simulation time 10196378268 ps
CPU time 12.26 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:04:44 PM PDT 24
Peak memory 265816 kb
Host smart-99461942-5d90-4ec4-89e3-287fff392ba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191764765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.4191764765
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.774263682
Short name T408
Test name
Test status
Simulation time 10418250449 ps
CPU time 19.35 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:04:49 PM PDT 24
Peak memory 351188 kb
Host smart-e85167b5-977a-4b7a-9ff1-645afbeb3d00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774263682 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.774263682
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.407931081
Short name T600
Test name
Test status
Simulation time 466132963 ps
CPU time 2.89 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:30 PM PDT 24
Peak memory 203608 kb
Host smart-9099b677-3715-42c7-a806-67a1d7764511
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407931081 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_hrst.407931081
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3487975163
Short name T176
Test name
Test status
Simulation time 3298974219 ps
CPU time 4.05 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 205896 kb
Host smart-2f280756-5423-4b27-9b5c-e4aea20a2343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487975163 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3487975163
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1767198023
Short name T976
Test name
Test status
Simulation time 6559016670 ps
CPU time 8.21 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:04:38 PM PDT 24
Peak memory 203860 kb
Host smart-0fd354e8-2fcc-4b34-a578-49dae477db5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767198023 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1767198023
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1986380562
Short name T913
Test name
Test status
Simulation time 7930853838 ps
CPU time 10.95 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:04:42 PM PDT 24
Peak memory 203852 kb
Host smart-c56271a9-fcf6-4428-a7ce-23c4871d8523
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986380562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1986380562
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1344601088
Short name T1015
Test name
Test status
Simulation time 367457864 ps
CPU time 5.5 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 203796 kb
Host smart-d8fb53eb-3055-46da-a70b-d7ebd7c045b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344601088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1344601088
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.1491696289
Short name T1055
Test name
Test status
Simulation time 45438901192 ps
CPU time 1374.52 seconds
Started Apr 04 03:04:25 PM PDT 24
Finished Apr 04 03:27:20 PM PDT 24
Peak memory 5124064 kb
Host smart-8697efeb-a8c3-4db3-aed1-d0768c6499d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491696289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.1491696289
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.4134453316
Short name T288
Test name
Test status
Simulation time 1516396347 ps
CPU time 7.8 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:36 PM PDT 24
Peak memory 219932 kb
Host smart-e08d00ef-2324-47e6-b2dc-4bd3361f5121
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134453316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.4134453316
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.3359588302
Short name T33
Test name
Test status
Simulation time 2997657179 ps
CPU time 4.49 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:33 PM PDT 24
Peak memory 203844 kb
Host smart-fa4931c8-9cd3-4dc2-a517-29f0c74d9242
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359588302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.3359588302
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3350450698
Short name T1080
Test name
Test status
Simulation time 18511237 ps
CPU time 0.61 seconds
Started Apr 04 03:04:31 PM PDT 24
Finished Apr 04 03:04:32 PM PDT 24
Peak memory 203588 kb
Host smart-e6e84ab2-3d2f-4b39-9153-a9066f7b1df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350450698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3350450698
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.397466104
Short name T772
Test name
Test status
Simulation time 676355276 ps
CPU time 1.99 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:30 PM PDT 24
Peak memory 211848 kb
Host smart-134391c2-d9b7-4cf1-8fd6-d9c0731ff10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397466104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.397466104
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.3083444599
Short name T453
Test name
Test status
Simulation time 612390195 ps
CPU time 5.08 seconds
Started Apr 04 03:04:25 PM PDT 24
Finished Apr 04 03:04:31 PM PDT 24
Peak memory 248356 kb
Host smart-9678c7bc-6052-49ec-879c-c6a6f1222c60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083444599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.3083444599
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2794859536
Short name T82
Test name
Test status
Simulation time 10594030664 ps
CPU time 185.12 seconds
Started Apr 04 03:04:25 PM PDT 24
Finished Apr 04 03:07:30 PM PDT 24
Peak memory 809728 kb
Host smart-c4d84a10-c39b-43bc-bf2c-aa67866127ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794859536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2794859536
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.796937170
Short name T683
Test name
Test status
Simulation time 1157969732 ps
CPU time 35.6 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:05:03 PM PDT 24
Peak memory 476572 kb
Host smart-367b7f69-2568-4483-b745-eb54c97d79de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796937170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.796937170
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.685690231
Short name T663
Test name
Test status
Simulation time 391325452 ps
CPU time 0.9 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:29 PM PDT 24
Peak memory 203608 kb
Host smart-e79c870e-b735-44f2-98b4-abc690231f84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685690231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.685690231
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.233790331
Short name T350
Test name
Test status
Simulation time 190497794 ps
CPU time 10.54 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:04:40 PM PDT 24
Peak memory 238724 kb
Host smart-39f6714f-6198-49f2-a1be-02b1defe750e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233790331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
233790331
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3709107977
Short name T581
Test name
Test status
Simulation time 42777722663 ps
CPU time 169.84 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:07:17 PM PDT 24
Peak memory 801512 kb
Host smart-3eebc057-49ea-4f6e-b16f-02ab5453c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709107977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3709107977
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2705854841
Short name T502
Test name
Test status
Simulation time 297155159 ps
CPU time 11.37 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:38 PM PDT 24
Peak memory 203712 kb
Host smart-980502e6-412f-474f-baa1-e902b0d1b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705854841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2705854841
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.942099034
Short name T609
Test name
Test status
Simulation time 1474166868 ps
CPU time 26.23 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:04:55 PM PDT 24
Peak memory 384564 kb
Host smart-c11a8956-82f0-4c5f-9b0a-6cea607c849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942099034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.942099034
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.2757762832
Short name T412
Test name
Test status
Simulation time 30564950 ps
CPU time 0.62 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:29 PM PDT 24
Peak memory 203472 kb
Host smart-4e78511a-817f-4684-a3a1-25b6f2038107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757762832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2757762832
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1151648641
Short name T971
Test name
Test status
Simulation time 3098955203 ps
CPU time 120.74 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:06:30 PM PDT 24
Peak memory 203800 kb
Host smart-eaed4626-5eae-4c05-88a7-7513c712cfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151648641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1151648641
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2340527396
Short name T729
Test name
Test status
Simulation time 1532873946 ps
CPU time 24.91 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:04:56 PM PDT 24
Peak memory 332804 kb
Host smart-8ccb6b4c-1aac-492a-8a8b-bc754c7a1b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340527396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2340527396
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2578668090
Short name T682
Test name
Test status
Simulation time 2374531292 ps
CPU time 3.02 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 203748 kb
Host smart-305a64ce-a16f-4696-aa3c-0c99acf99fa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578668090 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2578668090
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1169076007
Short name T359
Test name
Test status
Simulation time 10053219933 ps
CPU time 91.12 seconds
Started Apr 04 03:04:26 PM PDT 24
Finished Apr 04 03:05:57 PM PDT 24
Peak memory 664076 kb
Host smart-5c6a8419-8bb8-439f-8498-afa8c590959b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169076007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1169076007
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2506294994
Short name T879
Test name
Test status
Simulation time 871046800 ps
CPU time 2.31 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 203728 kb
Host smart-a8e8417e-a463-4d86-a2e6-4ce8b50f3e5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506294994 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2506294994
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2015736947
Short name T812
Test name
Test status
Simulation time 833244352 ps
CPU time 3.82 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:31 PM PDT 24
Peak memory 203732 kb
Host smart-8371290a-0146-46d9-b008-cec35f258fc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015736947 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2015736947
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3193018946
Short name T907
Test name
Test status
Simulation time 3496134596 ps
CPU time 2.66 seconds
Started Apr 04 03:04:33 PM PDT 24
Finished Apr 04 03:04:36 PM PDT 24
Peak memory 203804 kb
Host smart-719fdd56-92e9-46ef-907b-03e46f27e21b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193018946 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3193018946
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.1367348062
Short name T421
Test name
Test status
Simulation time 1473305165 ps
CPU time 27.08 seconds
Started Apr 04 03:04:26 PM PDT 24
Finished Apr 04 03:04:53 PM PDT 24
Peak memory 203704 kb
Host smart-2cd89f94-4d4e-4e9c-8aac-379d80a6c5fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367348062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.1367348062
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.537891417
Short name T616
Test name
Test status
Simulation time 1253448582 ps
CPU time 12.92 seconds
Started Apr 04 03:04:26 PM PDT 24
Finished Apr 04 03:04:39 PM PDT 24
Peak memory 203688 kb
Host smart-623896b2-3626-4b98-a72a-44b9f6587fe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537891417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.537891417
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1218031381
Short name T963
Test name
Test status
Simulation time 18014437762 ps
CPU time 35.11 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:05:05 PM PDT 24
Peak memory 203868 kb
Host smart-0bb16eb8-e936-410c-8df1-1feccfeb7539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218031381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1218031381
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1806146880
Short name T480
Test name
Test status
Simulation time 12497247258 ps
CPU time 486.49 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:12:34 PM PDT 24
Peak memory 1628048 kb
Host smart-da5c079a-9154-4e6c-a795-460803e42fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806146880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1806146880
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.917777254
Short name T1097
Test name
Test status
Simulation time 2407977054 ps
CPU time 6.84 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 219220 kb
Host smart-c60712a6-5c0b-46ed-9c57-a9699ff2d38d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917777254 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.917777254
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.931459427
Short name T692
Test name
Test status
Simulation time 2130393695 ps
CPU time 6.01 seconds
Started Apr 04 03:04:31 PM PDT 24
Finished Apr 04 03:04:37 PM PDT 24
Peak memory 207876 kb
Host smart-3e3d1f3e-84f8-4cb5-a422-3f398adc3494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931459427 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_unexp_stop.931459427
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.4119007454
Short name T1013
Test name
Test status
Simulation time 28843498 ps
CPU time 0.62 seconds
Started Apr 04 03:04:41 PM PDT 24
Finished Apr 04 03:04:43 PM PDT 24
Peak memory 203524 kb
Host smart-ad56fca7-ec1f-403f-a88e-52306555eeb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119007454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.4119007454
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2897132113
Short name T353
Test name
Test status
Simulation time 193385333 ps
CPU time 1.81 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:30 PM PDT 24
Peak memory 211944 kb
Host smart-0ccd70b7-cc7b-4514-867a-eaccbc0ed49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897132113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2897132113
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.144861569
Short name T452
Test name
Test status
Simulation time 2045463253 ps
CPU time 5.85 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:33 PM PDT 24
Peak memory 271316 kb
Host smart-d27321ab-983c-4e54-9d57-daba453bcca7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144861569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.144861569
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.1567392826
Short name T1092
Test name
Test status
Simulation time 1283657813 ps
CPU time 39.13 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:05:06 PM PDT 24
Peak memory 521848 kb
Host smart-9e5935f1-0bd7-43c3-a0e3-93e82849073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567392826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1567392826
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2450422280
Short name T454
Test name
Test status
Simulation time 8176250356 ps
CPU time 75.33 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:05:47 PM PDT 24
Peak memory 469460 kb
Host smart-eb6a72e3-7a95-4db7-984f-b775b716de8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450422280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2450422280
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.773793703
Short name T317
Test name
Test status
Simulation time 506223397 ps
CPU time 0.9 seconds
Started Apr 04 03:04:33 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 203540 kb
Host smart-ecd58460-4d99-48df-9162-41b40af79a55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773793703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.773793703
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1323367101
Short name T916
Test name
Test status
Simulation time 1521982249 ps
CPU time 9.82 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:37 PM PDT 24
Peak memory 234808 kb
Host smart-1d32b695-2eaf-4c59-b935-029034828ad5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323367101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1323367101
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1331530839
Short name T348
Test name
Test status
Simulation time 199581937 ps
CPU time 8.14 seconds
Started Apr 04 03:04:44 PM PDT 24
Finished Apr 04 03:04:55 PM PDT 24
Peak memory 203636 kb
Host smart-17683f22-0e20-4d86-bba6-f699c99df369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331530839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1331530839
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.576413429
Short name T563
Test name
Test status
Simulation time 1052133204 ps
CPU time 17.73 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:05:05 PM PDT 24
Peak memory 299444 kb
Host smart-776d2392-6bcc-42f8-90f6-e2761cb23605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576413429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.576413429
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.4196862345
Short name T821
Test name
Test status
Simulation time 26450279 ps
CPU time 0.65 seconds
Started Apr 04 03:04:27 PM PDT 24
Finished Apr 04 03:04:27 PM PDT 24
Peak memory 203468 kb
Host smart-e96d8616-68bb-4ffb-b79a-ad3efe9252d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196862345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.4196862345
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.708627511
Short name T818
Test name
Test status
Simulation time 466120976 ps
CPU time 3.03 seconds
Started Apr 04 03:04:33 PM PDT 24
Finished Apr 04 03:04:36 PM PDT 24
Peak memory 228188 kb
Host smart-c5c6dc3d-356b-4158-9d16-34cc2e0cbc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708627511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.708627511
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1988536055
Short name T536
Test name
Test status
Simulation time 1168919229 ps
CPU time 28.85 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:05:00 PM PDT 24
Peak memory 385736 kb
Host smart-91d7b64a-5545-4f55-be11-14b908e6765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988536055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1988536055
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2495887117
Short name T286
Test name
Test status
Simulation time 1103027115 ps
CPU time 3.27 seconds
Started Apr 04 03:04:29 PM PDT 24
Finished Apr 04 03:04:33 PM PDT 24
Peak memory 203720 kb
Host smart-acd2205f-d956-4ad2-8ef0-599322a3c098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495887117 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2495887117
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.498254229
Short name T1143
Test name
Test status
Simulation time 10093483679 ps
CPU time 77.02 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:05:45 PM PDT 24
Peak memory 562476 kb
Host smart-1633f4af-135e-432f-9c19-9efc304df31f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498254229 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.498254229
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2636520947
Short name T1181
Test name
Test status
Simulation time 10108029743 ps
CPU time 117.84 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:06:26 PM PDT 24
Peak memory 689760 kb
Host smart-dc3bf577-95cd-4904-94e2-2cbb31d7564e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636520947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2636520947
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1388045107
Short name T366
Test name
Test status
Simulation time 385494718 ps
CPU time 2.54 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:50 PM PDT 24
Peak memory 203664 kb
Host smart-bf1801d7-dfa9-4b45-8bc3-8983f1425c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388045107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1388045107
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.229953532
Short name T804
Test name
Test status
Simulation time 3107300691 ps
CPU time 7.15 seconds
Started Apr 04 03:04:38 PM PDT 24
Finished Apr 04 03:04:45 PM PDT 24
Peak memory 212144 kb
Host smart-a2e98f1f-892e-441b-8070-867682020bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229953532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.229953532
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2907352339
Short name T968
Test name
Test status
Simulation time 4456555395 ps
CPU time 43.6 seconds
Started Apr 04 03:04:30 PM PDT 24
Finished Apr 04 03:05:15 PM PDT 24
Peak memory 203836 kb
Host smart-1d72a817-5af9-4cab-b264-7791c91b5bd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907352339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2907352339
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2160999191
Short name T697
Test name
Test status
Simulation time 16258219611 ps
CPU time 31.32 seconds
Started Apr 04 03:04:38 PM PDT 24
Finished Apr 04 03:05:10 PM PDT 24
Peak memory 225376 kb
Host smart-9a723060-2bee-4c71-a482-9dc2fd30dc4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160999191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2160999191
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.4034612342
Short name T657
Test name
Test status
Simulation time 9511230694 ps
CPU time 29.1 seconds
Started Apr 04 03:04:33 PM PDT 24
Finished Apr 04 03:05:02 PM PDT 24
Peak memory 281060 kb
Host smart-5709d8f5-a699-4bfa-b17d-1faf7868e57d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034612342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.4034612342
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.4213837710
Short name T339
Test name
Test status
Simulation time 2553025363 ps
CPU time 6.77 seconds
Started Apr 04 03:04:38 PM PDT 24
Finished Apr 04 03:04:45 PM PDT 24
Peak memory 211488 kb
Host smart-64ad43e2-419b-47f4-ba1d-17861f884f84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213837710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.4213837710
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_unexp_stop.3977664617
Short name T789
Test name
Test status
Simulation time 3600217445 ps
CPU time 5.51 seconds
Started Apr 04 03:04:28 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 206056 kb
Host smart-729a4631-9ce1-49f5-9137-4813188f2b79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977664617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.i2c_target_unexp_stop.3977664617
Directory /workspace/17.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/18.i2c_alert_test.1755812177
Short name T1103
Test name
Test status
Simulation time 43308502 ps
CPU time 0.65 seconds
Started Apr 04 03:04:44 PM PDT 24
Finished Apr 04 03:04:47 PM PDT 24
Peak memory 203580 kb
Host smart-e5891286-c615-4af1-9866-965d80c17802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755812177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1755812177
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2760703073
Short name T1115
Test name
Test status
Simulation time 95001673 ps
CPU time 1.38 seconds
Started Apr 04 03:04:40 PM PDT 24
Finished Apr 04 03:04:42 PM PDT 24
Peak memory 220116 kb
Host smart-634fc6c6-6d61-414d-9252-2de5074d78c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760703073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2760703073
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2573551724
Short name T1106
Test name
Test status
Simulation time 2374241416 ps
CPU time 8.29 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:56 PM PDT 24
Peak memory 265644 kb
Host smart-4aa82604-4078-4b2d-a0ae-1fe26c301a91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573551724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2573551724
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3619379795
Short name T1130
Test name
Test status
Simulation time 7986699172 ps
CPU time 60.06 seconds
Started Apr 04 03:04:43 PM PDT 24
Finished Apr 04 03:05:46 PM PDT 24
Peak memory 614100 kb
Host smart-317222ac-1e67-4ae2-99e3-1df529c38a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619379795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3619379795
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.255510954
Short name T510
Test name
Test status
Simulation time 1403518827 ps
CPU time 40.12 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:05:28 PM PDT 24
Peak memory 493272 kb
Host smart-f512261b-d9fb-431a-b007-0e2d2e573e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255510954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.255510954
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1069634591
Short name T38
Test name
Test status
Simulation time 149038728 ps
CPU time 1.04 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:49 PM PDT 24
Peak memory 203524 kb
Host smart-c840f039-87ab-4c0d-be40-0daa26a63c54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069634591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1069634591
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3513848565
Short name T620
Test name
Test status
Simulation time 628308159 ps
CPU time 7.67 seconds
Started Apr 04 03:04:43 PM PDT 24
Finished Apr 04 03:04:54 PM PDT 24
Peak memory 225832 kb
Host smart-221e2857-6e74-4fa1-98b9-eab115277bb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513848565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3513848565
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2478254296
Short name T146
Test name
Test status
Simulation time 3753775977 ps
CPU time 96.41 seconds
Started Apr 04 03:04:42 PM PDT 24
Finished Apr 04 03:06:23 PM PDT 24
Peak memory 1081240 kb
Host smart-c799439f-ffc6-4b8e-bd3c-3ed5432eedaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478254296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2478254296
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2430061292
Short name T22
Test name
Test status
Simulation time 1738511130 ps
CPU time 6.95 seconds
Started Apr 04 03:04:43 PM PDT 24
Finished Apr 04 03:04:51 PM PDT 24
Peak memory 203716 kb
Host smart-0533c807-82e9-444c-99f8-e04640902b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430061292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2430061292
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.530702380
Short name T1094
Test name
Test status
Simulation time 3121722833 ps
CPU time 17.15 seconds
Started Apr 04 03:04:44 PM PDT 24
Finished Apr 04 03:05:04 PM PDT 24
Peak memory 334540 kb
Host smart-6bf7b2ee-1717-440a-a557-a4f4b99bb3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530702380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.530702380
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2133984185
Short name T1067
Test name
Test status
Simulation time 26089968 ps
CPU time 0.67 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:04:48 PM PDT 24
Peak memory 203472 kb
Host smart-0ecc3e67-e14e-425c-8be0-aaf9e5252003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133984185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2133984185
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.963002844
Short name T422
Test name
Test status
Simulation time 6811277581 ps
CPU time 22.24 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:05:12 PM PDT 24
Peak memory 203824 kb
Host smart-a6c6e45c-9343-4fcd-9b58-7e95ea72b990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963002844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.963002844
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1406403669
Short name T35
Test name
Test status
Simulation time 2210929932 ps
CPU time 52.81 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:05:40 PM PDT 24
Peak memory 462060 kb
Host smart-915d2554-7fd3-4cbe-bf54-40b21692c8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406403669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1406403669
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.157847170
Short name T997
Test name
Test status
Simulation time 1434769428 ps
CPU time 3.51 seconds
Started Apr 04 03:04:44 PM PDT 24
Finished Apr 04 03:04:50 PM PDT 24
Peak memory 203692 kb
Host smart-e20c6da3-5a52-4556-9431-1aaf8aef12ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157847170 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.157847170
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.815293434
Short name T885
Test name
Test status
Simulation time 10046170841 ps
CPU time 30.29 seconds
Started Apr 04 03:04:43 PM PDT 24
Finished Apr 04 03:05:16 PM PDT 24
Peak memory 372024 kb
Host smart-6908af7b-b692-42ad-a56b-6d40ca230f9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815293434 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.815293434
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.1252805303
Short name T475
Test name
Test status
Simulation time 10061088604 ps
CPU time 96.25 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:06:24 PM PDT 24
Peak memory 749908 kb
Host smart-c4f7004c-ea30-4fa8-8325-0eae43d295a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252805303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.1252805303
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1429262354
Short name T214
Test name
Test status
Simulation time 347612821 ps
CPU time 2.15 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:04:50 PM PDT 24
Peak memory 203596 kb
Host smart-8060ea9b-a14e-42ef-83e9-87f4edf9999a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429262354 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1429262354
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2257141756
Short name T303
Test name
Test status
Simulation time 2319529279 ps
CPU time 5.6 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:04:53 PM PDT 24
Peak memory 211940 kb
Host smart-4de0c15e-87f0-4d6c-91bc-f9ab45772e86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257141756 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2257141756
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2747167275
Short name T716
Test name
Test status
Simulation time 4846645862 ps
CPU time 2.18 seconds
Started Apr 04 03:04:42 PM PDT 24
Finished Apr 04 03:04:44 PM PDT 24
Peak memory 203840 kb
Host smart-7991ac43-ce82-44f7-9d37-0e72e05db500
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747167275 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2747167275
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1887588077
Short name T615
Test name
Test status
Simulation time 1647030242 ps
CPU time 30.34 seconds
Started Apr 04 03:04:44 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 203624 kb
Host smart-057fe1ea-7b22-4350-b5d6-d711c1c77b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887588077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1887588077
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.4112918398
Short name T644
Test name
Test status
Simulation time 7176377458 ps
CPU time 59.94 seconds
Started Apr 04 03:04:42 PM PDT 24
Finished Apr 04 03:05:42 PM PDT 24
Peak memory 204480 kb
Host smart-7c4a3602-84f6-44bb-b20c-5ae84980c4ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112918398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.4112918398
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2163274067
Short name T703
Test name
Test status
Simulation time 33142978534 ps
CPU time 71.69 seconds
Started Apr 04 03:04:43 PM PDT 24
Finished Apr 04 03:05:58 PM PDT 24
Peak memory 304104 kb
Host smart-a8345857-6019-4aa2-8797-a3cd565a9e79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163274067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2163274067
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3911693211
Short name T1052
Test name
Test status
Simulation time 1398959778 ps
CPU time 6.82 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:54 PM PDT 24
Peak memory 203612 kb
Host smart-371cae52-41d1-4458-88e7-11c64dfb060e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911693211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3911693211
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.1123730871
Short name T5
Test name
Test status
Simulation time 827751349 ps
CPU time 5.07 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:53 PM PDT 24
Peak memory 203748 kb
Host smart-ea563824-dbc8-4cc8-921a-ca9550b83704
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123730871 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.i2c_target_unexp_stop.1123730871
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.361177967
Short name T855
Test name
Test status
Simulation time 82953510 ps
CPU time 0.6 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:48 PM PDT 24
Peak memory 203532 kb
Host smart-bd9f8d62-ae93-4637-ad98-b2b0d046f3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361177967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.361177967
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.111677710
Short name T445
Test name
Test status
Simulation time 73106058 ps
CPU time 1.57 seconds
Started Apr 04 03:04:47 PM PDT 24
Finished Apr 04 03:04:49 PM PDT 24
Peak memory 211976 kb
Host smart-cbe6fabd-ca22-451f-a0ba-39b12f8332a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111677710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.111677710
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.948175064
Short name T1038
Test name
Test status
Simulation time 1520809519 ps
CPU time 14.5 seconds
Started Apr 04 03:04:50 PM PDT 24
Finished Apr 04 03:05:06 PM PDT 24
Peak memory 259472 kb
Host smart-2535b80a-eca3-4b30-b4a9-33502a0a9dfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948175064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.948175064
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2826706379
Short name T458
Test name
Test status
Simulation time 4022361440 ps
CPU time 74.05 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:06:03 PM PDT 24
Peak memory 703708 kb
Host smart-fa16309b-0147-433b-bd62-2d880c5e5259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826706379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2826706379
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.566706431
Short name T712
Test name
Test status
Simulation time 7223255063 ps
CPU time 61.08 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:05:48 PM PDT 24
Peak memory 636652 kb
Host smart-8673e8eb-620f-48aa-8db8-1455edac3b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566706431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.566706431
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1270969245
Short name T379
Test name
Test status
Simulation time 194948061 ps
CPU time 0.93 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:04:48 PM PDT 24
Peak memory 203516 kb
Host smart-a6657feb-7441-4129-a5a6-0def78a6d779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270969245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1270969245
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.184946727
Short name T426
Test name
Test status
Simulation time 625318887 ps
CPU time 4.09 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:04:54 PM PDT 24
Peak memory 203720 kb
Host smart-e3f91f8e-618a-497c-8b94-ed968ca6bd87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184946727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
184946727
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.831335713
Short name T1033
Test name
Test status
Simulation time 2259623435 ps
CPU time 145.54 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:07:13 PM PDT 24
Peak memory 735704 kb
Host smart-a5b90cd3-e419-4db4-b5e0-433a684c1694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831335713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.831335713
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.1722543606
Short name T1117
Test name
Test status
Simulation time 392856268 ps
CPU time 15.43 seconds
Started Apr 04 03:04:44 PM PDT 24
Finished Apr 04 03:05:02 PM PDT 24
Peak memory 203736 kb
Host smart-4b0d4267-766c-42ab-ad76-664a620deca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722543606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.1722543606
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.508301175
Short name T839
Test name
Test status
Simulation time 1578111273 ps
CPU time 28.8 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:05:18 PM PDT 24
Peak memory 403904 kb
Host smart-35261c95-300d-4300-9c28-98385211231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508301175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.508301175
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.313012297
Short name T750
Test name
Test status
Simulation time 15453583 ps
CPU time 0.65 seconds
Started Apr 04 03:04:47 PM PDT 24
Finished Apr 04 03:04:48 PM PDT 24
Peak memory 203508 kb
Host smart-879bbcc7-84d4-4aa8-a767-9ca6523cfd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313012297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.313012297
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3655871188
Short name T451
Test name
Test status
Simulation time 2868638293 ps
CPU time 28.19 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:05:16 PM PDT 24
Peak memory 356948 kb
Host smart-dab0fc43-c17c-4213-bb86-e5b3e5a96baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655871188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3655871188
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2414061300
Short name T230
Test name
Test status
Simulation time 11816515205 ps
CPU time 1338.7 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:27:07 PM PDT 24
Peak memory 2164348 kb
Host smart-a822fbfb-8192-4ba8-82d4-5b80f7098b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414061300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2414061300
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.929222311
Short name T986
Test name
Test status
Simulation time 2801105694 ps
CPU time 3.54 seconds
Started Apr 04 03:04:47 PM PDT 24
Finished Apr 04 03:04:51 PM PDT 24
Peak memory 203784 kb
Host smart-4d2fa11b-46cc-4be4-bf7d-732b5a1e6bf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929222311 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.929222311
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1045508025
Short name T808
Test name
Test status
Simulation time 10145924194 ps
CPU time 15.53 seconds
Started Apr 04 03:04:44 PM PDT 24
Finished Apr 04 03:05:03 PM PDT 24
Peak memory 306524 kb
Host smart-8a786e52-4d90-43e1-af98-5b316978a3db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045508025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1045508025
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.439776892
Short name T318
Test name
Test status
Simulation time 10075680187 ps
CPU time 93.19 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:06:21 PM PDT 24
Peak memory 736128 kb
Host smart-2334af6d-400c-4043-90f5-acf223f0fbeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439776892 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.439776892
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1882145453
Short name T539
Test name
Test status
Simulation time 1076132501 ps
CPU time 2.81 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:04:52 PM PDT 24
Peak memory 203636 kb
Host smart-2a49a745-23c8-475a-a54d-eaf4d9ff93a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882145453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1882145453
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.262690966
Short name T909
Test name
Test status
Simulation time 4668511722 ps
CPU time 4.1 seconds
Started Apr 04 03:04:51 PM PDT 24
Finished Apr 04 03:04:56 PM PDT 24
Peak memory 203860 kb
Host smart-82a1e31c-a41a-470b-98cb-502fc86a8df5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262690966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.262690966
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3243155485
Short name T1148
Test name
Test status
Simulation time 1247737916 ps
CPU time 23.64 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:05:11 PM PDT 24
Peak memory 203728 kb
Host smart-d68e9ec2-52a3-4af8-9ea0-96f40ecf9b79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243155485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3243155485
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.4186315233
Short name T260
Test name
Test status
Simulation time 6017108501 ps
CPU time 10.49 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:58 PM PDT 24
Peak memory 207284 kb
Host smart-b5400503-aa48-4427-aa9d-0d9b57093267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186315233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.4186315233
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1276780861
Short name T1208
Test name
Test status
Simulation time 16472829749 ps
CPU time 3.46 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:04:50 PM PDT 24
Peak memory 203840 kb
Host smart-708de3ae-f87d-4c89-b0ca-50655a269da3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276780861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1276780861
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3634983852
Short name T207
Test name
Test status
Simulation time 49708682440 ps
CPU time 475.05 seconds
Started Apr 04 03:04:46 PM PDT 24
Finished Apr 04 03:12:43 PM PDT 24
Peak memory 2683732 kb
Host smart-79ecc44d-2a14-4a2f-95cf-edb38d117138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634983852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3634983852
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2006998162
Short name T920
Test name
Test status
Simulation time 1339314993 ps
CPU time 7.33 seconds
Started Apr 04 03:04:50 PM PDT 24
Finished Apr 04 03:04:59 PM PDT 24
Peak memory 214860 kb
Host smart-43131739-19a6-4209-b819-d50939b27e5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006998162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2006998162
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2038711203
Short name T84
Test name
Test status
Simulation time 16919242 ps
CPU time 0.65 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:02:40 PM PDT 24
Peak memory 203592 kb
Host smart-c802d26c-47de-4e63-bc6e-bd2cf2c66818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038711203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2038711203
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2766174784
Short name T410
Test name
Test status
Simulation time 112006997 ps
CPU time 1.5 seconds
Started Apr 04 03:02:45 PM PDT 24
Finished Apr 04 03:02:47 PM PDT 24
Peak memory 211928 kb
Host smart-59b197ce-c435-40ad-bd40-a67bce339bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766174784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2766174784
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1353578818
Short name T269
Test name
Test status
Simulation time 1018731264 ps
CPU time 8.47 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:02:52 PM PDT 24
Peak memory 301884 kb
Host smart-936394c0-9849-44a7-8815-45b3abcd14b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353578818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1353578818
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.4054016506
Short name T456
Test name
Test status
Simulation time 1770173230 ps
CPU time 57.15 seconds
Started Apr 04 03:02:41 PM PDT 24
Finished Apr 04 03:03:38 PM PDT 24
Peak memory 635136 kb
Host smart-3653fb81-478f-4499-88e6-c4759a667265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054016506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.4054016506
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3068872626
Short name T1210
Test name
Test status
Simulation time 1081891708 ps
CPU time 65.43 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:03:49 PM PDT 24
Peak memory 384288 kb
Host smart-cdee44ad-856d-4ba8-9711-9a058c1d0924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068872626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3068872626
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.553463337
Short name T819
Test name
Test status
Simulation time 148080987 ps
CPU time 1.15 seconds
Started Apr 04 03:02:46 PM PDT 24
Finished Apr 04 03:02:47 PM PDT 24
Peak memory 203408 kb
Host smart-d75c9ce7-7fb1-4839-a518-dfb99c5f2633
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553463337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.553463337
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3065011158
Short name T1025
Test name
Test status
Simulation time 1058338186 ps
CPU time 4.17 seconds
Started Apr 04 03:02:43 PM PDT 24
Finished Apr 04 03:02:48 PM PDT 24
Peak memory 226044 kb
Host smart-f9305ecf-21c6-47d2-9b1a-e0463504c7aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065011158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3065011158
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.275207022
Short name T639
Test name
Test status
Simulation time 2784287820 ps
CPU time 75.77 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:03:59 PM PDT 24
Peak memory 861304 kb
Host smart-eadb7b99-765e-470d-a616-4e9398eaea6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275207022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.275207022
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.4217528317
Short name T46
Test name
Test status
Simulation time 1255099588 ps
CPU time 21.84 seconds
Started Apr 04 03:02:44 PM PDT 24
Finished Apr 04 03:03:06 PM PDT 24
Peak memory 325452 kb
Host smart-ea68140a-e5c4-400b-bbe5-53e2c11c0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217528317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.4217528317
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1532476337
Short name T289
Test name
Test status
Simulation time 76199204 ps
CPU time 0.72 seconds
Started Apr 04 03:02:44 PM PDT 24
Finished Apr 04 03:02:45 PM PDT 24
Peak memory 203520 kb
Host smart-48320154-06b9-45cc-bd51-859dfa7d19c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532476337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1532476337
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4195881483
Short name T496
Test name
Test status
Simulation time 4805337136 ps
CPU time 38.02 seconds
Started Apr 04 03:02:44 PM PDT 24
Finished Apr 04 03:03:22 PM PDT 24
Peak memory 269736 kb
Host smart-4eeff194-b74d-4338-b479-3adb51a00530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195881483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4195881483
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.761436635
Short name T233
Test name
Test status
Simulation time 7073554299 ps
CPU time 221.53 seconds
Started Apr 04 03:02:43 PM PDT 24
Finished Apr 04 03:06:25 PM PDT 24
Peak memory 1228984 kb
Host smart-cd5c1684-a047-4ce8-b8a3-3d4f54ec6e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761436635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.761436635
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2468549386
Short name T93
Test name
Test status
Simulation time 66429666 ps
CPU time 0.91 seconds
Started Apr 04 03:02:41 PM PDT 24
Finished Apr 04 03:02:44 PM PDT 24
Peak memory 222332 kb
Host smart-706cda06-02da-4440-b597-dc59a641b8bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468549386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2468549386
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.352152632
Short name T711
Test name
Test status
Simulation time 5842298316 ps
CPU time 2.99 seconds
Started Apr 04 03:02:44 PM PDT 24
Finished Apr 04 03:02:47 PM PDT 24
Peak memory 203820 kb
Host smart-1507a967-89da-41d6-aa34-8e05b40892a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352152632 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.352152632
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2691227836
Short name T69
Test name
Test status
Simulation time 10126867078 ps
CPU time 80.53 seconds
Started Apr 04 03:02:43 PM PDT 24
Finished Apr 04 03:04:04 PM PDT 24
Peak memory 575720 kb
Host smart-e96624fb-0a20-4b2d-84c7-23e7de35e7d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691227836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2691227836
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3541819225
Short name T599
Test name
Test status
Simulation time 10140185965 ps
CPU time 75.6 seconds
Started Apr 04 03:02:40 PM PDT 24
Finished Apr 04 03:03:56 PM PDT 24
Peak memory 623604 kb
Host smart-085cfdbe-1d78-4369-8867-1b309187aada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541819225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3541819225
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.1880853795
Short name T1140
Test name
Test status
Simulation time 368266731 ps
CPU time 2.44 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:02:42 PM PDT 24
Peak memory 203736 kb
Host smart-50bab432-e52d-45f5-b533-934cee7d981d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880853795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.1880853795
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2359424242
Short name T1113
Test name
Test status
Simulation time 4498446953 ps
CPU time 5.62 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:02:45 PM PDT 24
Peak memory 208952 kb
Host smart-c94ace42-5132-49e8-b0ff-53cedbcf854f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359424242 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2359424242
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2136814640
Short name T265
Test name
Test status
Simulation time 2562013012 ps
CPU time 5.65 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:02:49 PM PDT 24
Peak memory 203828 kb
Host smart-97823389-a73b-4550-ba82-884aa1318bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136814640 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2136814640
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.140370403
Short name T1127
Test name
Test status
Simulation time 2196267823 ps
CPU time 19.17 seconds
Started Apr 04 03:02:40 PM PDT 24
Finished Apr 04 03:02:59 PM PDT 24
Peak memory 203704 kb
Host smart-6a9e0cea-9375-4b3f-a8d6-9e4f168ceb44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140370403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.140370403
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.2667081895
Short name T610
Test name
Test status
Simulation time 5769564207 ps
CPU time 26.98 seconds
Started Apr 04 03:02:42 PM PDT 24
Finished Apr 04 03:03:11 PM PDT 24
Peak memory 219096 kb
Host smart-b35f78c7-555f-498d-b5fa-988b9b57fb49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667081895 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.2667081895
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1946921132
Short name T829
Test name
Test status
Simulation time 5515103383 ps
CPU time 21.55 seconds
Started Apr 04 03:02:39 PM PDT 24
Finished Apr 04 03:03:01 PM PDT 24
Peak memory 223648 kb
Host smart-889fca3f-0cc5-4415-a3a3-ecf2980b2c53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946921132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1946921132
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.802380420
Short name T345
Test name
Test status
Simulation time 17002665802 ps
CPU time 96.43 seconds
Started Apr 04 03:02:46 PM PDT 24
Finished Apr 04 03:04:22 PM PDT 24
Peak memory 1139120 kb
Host smart-418011dd-838c-4485-a253-3ceeab5f6adf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802380420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.802380420
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2487121938
Short name T860
Test name
Test status
Simulation time 1425683464 ps
CPU time 6.69 seconds
Started Apr 04 03:02:43 PM PDT 24
Finished Apr 04 03:02:50 PM PDT 24
Peak memory 203768 kb
Host smart-2d86321f-7cd5-4dd5-8c0b-9d142bd9346c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487121938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2487121938
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1803828247
Short name T673
Test name
Test status
Simulation time 17704401 ps
CPU time 0.63 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:06 PM PDT 24
Peak memory 203564 kb
Host smart-3883d0d7-47ab-4d22-8548-4e483b85ea98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803828247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1803828247
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.593952806
Short name T785
Test name
Test status
Simulation time 97924635 ps
CPU time 1.38 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:04:49 PM PDT 24
Peak memory 211912 kb
Host smart-abef02fe-ab62-4f81-adf2-ef807ee71877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593952806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.593952806
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.565854329
Short name T1116
Test name
Test status
Simulation time 2170123348 ps
CPU time 24.59 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:05:14 PM PDT 24
Peak memory 287152 kb
Host smart-6f9df933-7287-4be9-a584-4dd1169ea8ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565854329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.565854329
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2028558138
Short name T572
Test name
Test status
Simulation time 2062412896 ps
CPU time 58.46 seconds
Started Apr 04 03:04:53 PM PDT 24
Finished Apr 04 03:05:52 PM PDT 24
Peak memory 613824 kb
Host smart-e28e5120-1596-4937-ab0a-588c928668a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028558138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2028558138
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1107116941
Short name T669
Test name
Test status
Simulation time 8507841317 ps
CPU time 64.4 seconds
Started Apr 04 03:04:53 PM PDT 24
Finished Apr 04 03:05:57 PM PDT 24
Peak memory 735288 kb
Host smart-7e7e4e62-0cf8-45e0-b1ca-2843d07c3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107116941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1107116941
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.691895649
Short name T36
Test name
Test status
Simulation time 110815079 ps
CPU time 0.83 seconds
Started Apr 04 03:04:53 PM PDT 24
Finished Apr 04 03:04:54 PM PDT 24
Peak memory 203580 kb
Host smart-a385283c-5386-47f4-afe7-3b7cdf68f2fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691895649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.691895649
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3338021870
Short name T1141
Test name
Test status
Simulation time 141980332 ps
CPU time 7.2 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:04:56 PM PDT 24
Peak memory 203652 kb
Host smart-df5017b5-9b21-46cb-92a8-eb133bccea6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338021870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3338021870
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.3232182240
Short name T151
Test name
Test status
Simulation time 9271692465 ps
CPU time 52.95 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:05:43 PM PDT 24
Peak memory 779160 kb
Host smart-1149484b-da5b-481d-a61c-00f6e4b3967f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232182240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3232182240
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.2049195274
Short name T443
Test name
Test status
Simulation time 255781291 ps
CPU time 3.55 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:05:07 PM PDT 24
Peak memory 203728 kb
Host smart-3794352a-9154-4ace-b939-a3926f21286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049195274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2049195274
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2328243998
Short name T899
Test name
Test status
Simulation time 1470348130 ps
CPU time 70.69 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:06:15 PM PDT 24
Peak memory 352668 kb
Host smart-2d83c167-4def-4ad9-86fa-97432b22e23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328243998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2328243998
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2892568631
Short name T967
Test name
Test status
Simulation time 41089054 ps
CPU time 0.65 seconds
Started Apr 04 03:04:45 PM PDT 24
Finished Apr 04 03:04:48 PM PDT 24
Peak memory 203440 kb
Host smart-463ad4b9-a233-4dcb-a110-5faf21b8ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892568631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2892568631
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2178296037
Short name T474
Test name
Test status
Simulation time 3622371698 ps
CPU time 38.31 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:05:28 PM PDT 24
Peak memory 401120 kb
Host smart-28b50bec-6200-4201-8041-902efc5c9ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178296037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2178296037
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.405931504
Short name T1183
Test name
Test status
Simulation time 8318923723 ps
CPU time 4.23 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:05:07 PM PDT 24
Peak memory 203884 kb
Host smart-599cf27a-eed1-491d-a819-0fc6e8d8a1a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405931504 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.405931504
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2069328550
Short name T915
Test name
Test status
Simulation time 10203460631 ps
CPU time 27.98 seconds
Started Apr 04 03:04:48 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 349740 kb
Host smart-0ca115a7-1d9a-47ef-8a74-7c7af3628eaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069328550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2069328550
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3559334233
Short name T790
Test name
Test status
Simulation time 10071903297 ps
CPU time 88.56 seconds
Started Apr 04 03:04:36 PM PDT 24
Finished Apr 04 03:06:05 PM PDT 24
Peak memory 708488 kb
Host smart-d1d5d600-7ac7-41a9-aa8e-bf066c6d8339
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559334233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3559334233
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1353808522
Short name T1085
Test name
Test status
Simulation time 517676089 ps
CPU time 2.94 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:05:05 PM PDT 24
Peak memory 203740 kb
Host smart-f257a6c6-6ecd-4c9a-b6eb-05c02e104cf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353808522 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1353808522
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3622310037
Short name T292
Test name
Test status
Simulation time 484907171 ps
CPU time 3.11 seconds
Started Apr 04 03:04:50 PM PDT 24
Finished Apr 04 03:04:55 PM PDT 24
Peak memory 203716 kb
Host smart-482863c7-af41-4629-b75b-fbc06369f3e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622310037 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3622310037
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.871456587
Short name T455
Test name
Test status
Simulation time 10258266358 ps
CPU time 3.14 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:04:53 PM PDT 24
Peak memory 203848 kb
Host smart-3f43a3bc-bbc0-4e64-b022-b0e85b9680ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871456587 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.871456587
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.4016604526
Short name T643
Test name
Test status
Simulation time 4009388974 ps
CPU time 18.28 seconds
Started Apr 04 03:04:53 PM PDT 24
Finished Apr 04 03:05:11 PM PDT 24
Peak memory 203788 kb
Host smart-6eb7233b-8332-4d56-8264-f400c8386a53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016604526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.4016604526
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3105381033
Short name T505
Test name
Test status
Simulation time 881428742 ps
CPU time 8.73 seconds
Started Apr 04 03:04:50 PM PDT 24
Finished Apr 04 03:05:00 PM PDT 24
Peak memory 203812 kb
Host smart-c7795125-9156-4c3f-b998-e39877066240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105381033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3105381033
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.1138025312
Short name T1169
Test name
Test status
Simulation time 16097278822 ps
CPU time 9.06 seconds
Started Apr 04 03:04:53 PM PDT 24
Finished Apr 04 03:05:03 PM PDT 24
Peak memory 203620 kb
Host smart-50cb7bc5-c941-42ae-b4fe-d7f896622244
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138025312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.1138025312
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.1496922704
Short name T912
Test name
Test status
Simulation time 9974382273 ps
CPU time 1033.69 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:22:03 PM PDT 24
Peak memory 2540244 kb
Host smart-3b01c4ca-4717-4253-a886-ec2e8db6214d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496922704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.1496922704
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.4153203757
Short name T20
Test name
Test status
Simulation time 4620176870 ps
CPU time 6.54 seconds
Started Apr 04 03:04:52 PM PDT 24
Finished Apr 04 03:04:58 PM PDT 24
Peak memory 203848 kb
Host smart-a0e19d61-75ba-4713-94d3-8f893a4161af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153203757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.4153203757
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.2249129720
Short name T914
Test name
Test status
Simulation time 3233341156 ps
CPU time 5.56 seconds
Started Apr 04 03:04:49 PM PDT 24
Finished Apr 04 03:04:55 PM PDT 24
Peak memory 204948 kb
Host smart-6009ccc1-39a3-41a7-9feb-d3fce407fdcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249129720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.2249129720
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1587466414
Short name T551
Test name
Test status
Simulation time 57563780 ps
CPU time 0.62 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:06 PM PDT 24
Peak memory 203584 kb
Host smart-14190fc7-c49c-4837-8ccf-642022e64c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587466414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1587466414
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2233498900
Short name T314
Test name
Test status
Simulation time 233780076 ps
CPU time 1.7 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:08 PM PDT 24
Peak memory 211896 kb
Host smart-976ce3ae-bcc8-49a4-8086-b2c097d775ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233498900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2233498900
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3898372550
Short name T307
Test name
Test status
Simulation time 686605260 ps
CPU time 6.29 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:05:08 PM PDT 24
Peak memory 275148 kb
Host smart-a7f9dc17-c77b-47ed-91b3-ad42831c2b2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898372550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3898372550
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2156665087
Short name T446
Test name
Test status
Simulation time 2125134498 ps
CPU time 66.55 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:06:10 PM PDT 24
Peak memory 730148 kb
Host smart-d76e9fbc-27c4-498f-a0da-9a5bfb25450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156665087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2156665087
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1588855317
Short name T79
Test name
Test status
Simulation time 7117993646 ps
CPU time 49.46 seconds
Started Apr 04 03:05:07 PM PDT 24
Finished Apr 04 03:05:57 PM PDT 24
Peak memory 599208 kb
Host smart-afdae88c-b891-433b-bd92-5e91836c84b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588855317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1588855317
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1013382539
Short name T542
Test name
Test status
Simulation time 533171874 ps
CPU time 1.06 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:05:04 PM PDT 24
Peak memory 203632 kb
Host smart-906dd3e2-ae1b-42fb-8a27-468cdc90eb20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013382539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1013382539
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2818284203
Short name T684
Test name
Test status
Simulation time 232687192 ps
CPU time 5.14 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:11 PM PDT 24
Peak memory 203708 kb
Host smart-cff06af3-0f4b-43c3-b50c-d4858f92f0e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818284203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2818284203
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.1144155954
Short name T404
Test name
Test status
Simulation time 5895311384 ps
CPU time 129.33 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:07:15 PM PDT 24
Peak memory 1173788 kb
Host smart-f31dffd0-134a-4c43-a36f-c73d78ec6280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144155954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1144155954
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2871032656
Short name T198
Test name
Test status
Simulation time 363810568 ps
CPU time 13.74 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:20 PM PDT 24
Peak memory 203672 kb
Host smart-a4216874-3c86-46c1-b8a9-da3a7857e9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871032656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2871032656
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.657360918
Short name T957
Test name
Test status
Simulation time 1136718126 ps
CPU time 53.72 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:06:05 PM PDT 24
Peak memory 325940 kb
Host smart-986a9d2c-c51a-4fb2-bcc4-2dacf6adff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657360918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.657360918
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1345833743
Short name T898
Test name
Test status
Simulation time 33965790 ps
CPU time 0.65 seconds
Started Apr 04 03:05:07 PM PDT 24
Finished Apr 04 03:05:08 PM PDT 24
Peak memory 203476 kb
Host smart-4f8fe502-b364-4a32-8578-f5e635d47fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345833743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1345833743
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3058616166
Short name T937
Test name
Test status
Simulation time 2910803792 ps
CPU time 14.19 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:19 PM PDT 24
Peak memory 356852 kb
Host smart-d009f028-c8ae-4971-96e1-1e8dd39b319a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058616166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3058616166
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.327829778
Short name T210
Test name
Test status
Simulation time 4290328756 ps
CPU time 22.56 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:05:25 PM PDT 24
Peak memory 288200 kb
Host smart-3965bb4a-2746-40a0-8e95-cd5fc49ace5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327829778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.327829778
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.373272022
Short name T1114
Test name
Test status
Simulation time 12076052945 ps
CPU time 978.61 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:21:25 PM PDT 24
Peak memory 2948948 kb
Host smart-ec6aab9a-6928-49e8-9027-c2335b8a9c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373272022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.373272022
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3831402977
Short name T990
Test name
Test status
Simulation time 5297497057 ps
CPU time 4.59 seconds
Started Apr 04 03:05:01 PM PDT 24
Finished Apr 04 03:05:06 PM PDT 24
Peak memory 212088 kb
Host smart-3b711ea7-80cf-4b12-9800-1721a1c798bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831402977 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3831402977
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.762616878
Short name T1088
Test name
Test status
Simulation time 10042424261 ps
CPU time 35.58 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:05:40 PM PDT 24
Peak memory 420128 kb
Host smart-7a41a4ef-c0b5-4560-a608-8a6f13850a57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762616878 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.762616878
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.2146769447
Short name T68
Test name
Test status
Simulation time 10034611394 ps
CPU time 102.67 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:06:44 PM PDT 24
Peak memory 750408 kb
Host smart-b1ba397c-60b1-412a-b0ad-92554dc63741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146769447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.2146769447
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.4140477586
Short name T175
Test name
Test status
Simulation time 311289326 ps
CPU time 2.01 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:05:06 PM PDT 24
Peak memory 203744 kb
Host smart-a77be649-a178-4a7c-a5ba-db18a0cbcca5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140477586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.4140477586
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2207742122
Short name T569
Test name
Test status
Simulation time 757951155 ps
CPU time 4.71 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:12 PM PDT 24
Peak memory 203804 kb
Host smart-2edd6e9b-ffea-4dbe-82ff-a459a5dcf9ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207742122 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2207742122
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3213798567
Short name T756
Test name
Test status
Simulation time 2763103618 ps
CPU time 22.85 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:05:27 PM PDT 24
Peak memory 203856 kb
Host smart-c7fd2c93-5d1e-40dc-8392-bbd728120ccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213798567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3213798567
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.827258081
Short name T805
Test name
Test status
Simulation time 7233884105 ps
CPU time 30.61 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:36 PM PDT 24
Peak memory 225864 kb
Host smart-e72f4338-6f0d-46b0-9f12-196691a2f300
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827258081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.827258081
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.541053497
Short name T331
Test name
Test status
Simulation time 10437181014 ps
CPU time 20.75 seconds
Started Apr 04 03:05:07 PM PDT 24
Finished Apr 04 03:05:28 PM PDT 24
Peak memory 203824 kb
Host smart-af210b4e-c06b-441c-afcf-e0a91bbc397c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541053497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.541053497
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2236801470
Short name T415
Test name
Test status
Simulation time 12464115276 ps
CPU time 511.59 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:13:38 PM PDT 24
Peak memory 1671244 kb
Host smart-ae73a30b-b77f-4037-b42c-a6cd4e6cdd05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236801470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2236801470
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3932744859
Short name T1191
Test name
Test status
Simulation time 1313577004 ps
CPU time 7.13 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:05:09 PM PDT 24
Peak memory 215028 kb
Host smart-e627bab0-fed7-47bb-9fdb-c2ccae96d22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932744859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3932744859
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2451317892
Short name T678
Test name
Test status
Simulation time 25501527 ps
CPU time 0.63 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:05:05 PM PDT 24
Peak memory 203572 kb
Host smart-4a8ab2f2-bd82-4134-a947-abc78e2e0cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451317892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2451317892
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3412021305
Short name T438
Test name
Test status
Simulation time 223440952 ps
CPU time 1.6 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:05:05 PM PDT 24
Peak memory 214944 kb
Host smart-f6518b07-47d0-4b02-9857-f29c4c7491dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412021305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3412021305
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1818588366
Short name T851
Test name
Test status
Simulation time 1526925064 ps
CPU time 10.27 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:05:13 PM PDT 24
Peak memory 241696 kb
Host smart-89fc7c7b-8b01-48cd-b5f3-dcaf4e2d2b6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818588366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1818588366
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.525055229
Short name T64
Test name
Test status
Simulation time 1223730428 ps
CPU time 31.67 seconds
Started Apr 04 03:05:07 PM PDT 24
Finished Apr 04 03:05:39 PM PDT 24
Peak memory 348704 kb
Host smart-dddf2318-ba8e-4f17-8cd8-d041758c2378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525055229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.525055229
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3786179574
Short name T312
Test name
Test status
Simulation time 4433363647 ps
CPU time 74.27 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:06:20 PM PDT 24
Peak memory 466952 kb
Host smart-6ee825ff-098b-48df-8606-08ae94a7023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786179574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3786179574
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3071585584
Short name T725
Test name
Test status
Simulation time 104869655 ps
CPU time 1.01 seconds
Started Apr 04 03:05:08 PM PDT 24
Finished Apr 04 03:05:10 PM PDT 24
Peak memory 203576 kb
Host smart-2f216b3c-7457-4bb6-83f4-0e1ebc46eb8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071585584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3071585584
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.249346456
Short name T481
Test name
Test status
Simulation time 504568649 ps
CPU time 7.64 seconds
Started Apr 04 03:05:08 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 225436 kb
Host smart-8bc195eb-5557-4d2c-a17e-f949fcccee17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249346456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
249346456
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2073769048
Short name T757
Test name
Test status
Simulation time 2264132305 ps
CPU time 140.91 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:07:25 PM PDT 24
Peak memory 740784 kb
Host smart-4d85a6b8-bf3a-4c3b-bfb6-41032690355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073769048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2073769048
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.17832605
Short name T955
Test name
Test status
Simulation time 1866277957 ps
CPU time 50.17 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:56 PM PDT 24
Peak memory 315188 kb
Host smart-2fdab0de-b607-4266-89d9-438b663ad17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17832605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.17832605
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.1934034631
Short name T585
Test name
Test status
Simulation time 41563908 ps
CPU time 0.67 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:05:04 PM PDT 24
Peak memory 203432 kb
Host smart-6f448c9b-74b6-4282-b339-08575b7ac3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934034631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1934034631
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1192946172
Short name T185
Test name
Test status
Simulation time 5880010660 ps
CPU time 52.38 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:05:57 PM PDT 24
Peak memory 421652 kb
Host smart-53441692-ef4d-4f27-91b4-cfe67985c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192946172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1192946172
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.714620311
Short name T209
Test name
Test status
Simulation time 1562707509 ps
CPU time 79.63 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:06:26 PM PDT 24
Peak memory 443768 kb
Host smart-c4a92b7c-a6b7-49cd-b117-64f398a18055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714620311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.714620311
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.347373882
Short name T1152
Test name
Test status
Simulation time 4195968641 ps
CPU time 4.85 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:11 PM PDT 24
Peak memory 204108 kb
Host smart-ad99b6c6-fb32-4b39-8862-9678d1dc17fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347373882 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.347373882
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2692621776
Short name T245
Test name
Test status
Simulation time 10112860706 ps
CPU time 26.89 seconds
Started Apr 04 03:05:07 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 401532 kb
Host smart-fcfbf9cb-a2b4-42ad-a55b-9a25866d558a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692621776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2692621776
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.560872232
Short name T1153
Test name
Test status
Simulation time 10077233367 ps
CPU time 21.35 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:05:33 PM PDT 24
Peak memory 357668 kb
Host smart-d3a160ec-446f-4fb6-a44b-4ebee6c132e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560872232 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.560872232
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.703155849
Short name T622
Test name
Test status
Simulation time 369145870 ps
CPU time 2.39 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:10 PM PDT 24
Peak memory 203756 kb
Host smart-9d50c252-6123-4563-b218-71ed3c914364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703155849 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.703155849
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3332109963
Short name T713
Test name
Test status
Simulation time 2884604054 ps
CPU time 4.23 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:05:09 PM PDT 24
Peak memory 204892 kb
Host smart-d163bc36-c54e-4723-a9d8-29014b34ea83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332109963 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3332109963
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3958551448
Short name T586
Test name
Test status
Simulation time 4219611002 ps
CPU time 16.96 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:05:21 PM PDT 24
Peak memory 203740 kb
Host smart-3302f3c5-e132-46e2-bdef-608f4fca4130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958551448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3958551448
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.750183023
Short name T360
Test name
Test status
Simulation time 1532676931 ps
CPU time 23.46 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:29 PM PDT 24
Peak memory 231748 kb
Host smart-3d5e8c1b-640b-434e-aa09-bd2872000bb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750183023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.750183023
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3042143316
Short name T39
Test name
Test status
Simulation time 21016303193 ps
CPU time 49.21 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:05:54 PM PDT 24
Peak memory 375272 kb
Host smart-3f2d7ec4-9700-4288-bd46-740a1d6413cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042143316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3042143316
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.4221594663
Short name T392
Test name
Test status
Simulation time 7148386143 ps
CPU time 42.95 seconds
Started Apr 04 03:05:04 PM PDT 24
Finished Apr 04 03:05:47 PM PDT 24
Peak memory 627744 kb
Host smart-696b3f1d-d3cc-4052-9967-46ce1c4c0b75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221594663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.4221594663
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.3487994137
Short name T1177
Test name
Test status
Simulation time 5983647217 ps
CPU time 7.09 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:14 PM PDT 24
Peak memory 203852 kb
Host smart-555119eb-687c-4d8d-aa3c-27bfa7f2d6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487994137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.3487994137
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.837351946
Short name T617
Test name
Test status
Simulation time 41829315 ps
CPU time 0.62 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:08 PM PDT 24
Peak memory 203600 kb
Host smart-e3c90db3-4b25-4405-ae08-dd5b331f465c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837351946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.837351946
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.4032564995
Short name T1195
Test name
Test status
Simulation time 712442527 ps
CPU time 1.06 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:05:13 PM PDT 24
Peak memory 214364 kb
Host smart-2e0ded0e-6065-4563-84ec-1b4e4dc4c90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032564995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.4032564995
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.583267756
Short name T283
Test name
Test status
Simulation time 1734656489 ps
CPU time 3.13 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:09 PM PDT 24
Peak memory 225708 kb
Host smart-28cf50e8-90be-42f3-b7b1-2d43f7ca4e56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583267756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.583267756
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.2329269847
Short name T335
Test name
Test status
Simulation time 4117709964 ps
CPU time 157.21 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:07:43 PM PDT 24
Peak memory 717196 kb
Host smart-bfce50e8-e4f9-4f75-8b50-3c6a2747c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329269847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2329269847
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.42689645
Short name T418
Test name
Test status
Simulation time 18744093593 ps
CPU time 27.85 seconds
Started Apr 04 03:05:10 PM PDT 24
Finished Apr 04 03:05:38 PM PDT 24
Peak memory 434612 kb
Host smart-dc5b2a10-ea52-4870-adf7-8f9573c26c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42689645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.42689645
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2249762142
Short name T1139
Test name
Test status
Simulation time 88904869 ps
CPU time 0.95 seconds
Started Apr 04 03:05:02 PM PDT 24
Finished Apr 04 03:05:04 PM PDT 24
Peak memory 203628 kb
Host smart-18f65547-1d03-4fb4-88e5-e3352698343b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249762142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2249762142
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1121525347
Short name T777
Test name
Test status
Simulation time 456310614 ps
CPU time 3.43 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:10 PM PDT 24
Peak memory 203748 kb
Host smart-e73c1174-4196-4f1c-97a0-4e78d2ad3d30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121525347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1121525347
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.839722681
Short name T884
Test name
Test status
Simulation time 5321591465 ps
CPU time 248.82 seconds
Started Apr 04 03:05:09 PM PDT 24
Finished Apr 04 03:09:19 PM PDT 24
Peak memory 1025412 kb
Host smart-1c23b331-4bba-42c0-8728-7c5cdc83db77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839722681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.839722681
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1194398284
Short name T1091
Test name
Test status
Simulation time 1922768846 ps
CPU time 21.66 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:27 PM PDT 24
Peak memory 203720 kb
Host smart-d4a1c444-b5fd-4ba2-86d5-ae80d0949801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194398284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1194398284
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.174005184
Short name T580
Test name
Test status
Simulation time 15914853 ps
CPU time 0.65 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:07 PM PDT 24
Peak memory 203460 kb
Host smart-4ce4c22b-59cd-44af-8f33-fd01eb15eba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174005184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.174005184
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.128879591
Short name T181
Test name
Test status
Simulation time 2962246646 ps
CPU time 18.55 seconds
Started Apr 04 03:05:07 PM PDT 24
Finished Apr 04 03:05:26 PM PDT 24
Peak memory 401988 kb
Host smart-2a326b0f-cab6-4b8d-8eca-871aa7bfe312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128879591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.128879591
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.4179735269
Short name T598
Test name
Test status
Simulation time 1059170778 ps
CPU time 50.7 seconds
Started Apr 04 03:05:09 PM PDT 24
Finished Apr 04 03:06:01 PM PDT 24
Peak memory 328164 kb
Host smart-25ff9ff4-a549-40f3-a4f4-b54ef1dbb6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179735269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.4179735269
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.311091287
Short name T947
Test name
Test status
Simulation time 8298547129 ps
CPU time 4.02 seconds
Started Apr 04 03:05:16 PM PDT 24
Finished Apr 04 03:05:21 PM PDT 24
Peak memory 203812 kb
Host smart-c5db12a2-02bf-4b26-b97c-12f05121ce28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311091287 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.311091287
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3597141662
Short name T334
Test name
Test status
Simulation time 10090782254 ps
CPU time 15.14 seconds
Started Apr 04 03:05:05 PM PDT 24
Finished Apr 04 03:05:21 PM PDT 24
Peak memory 324984 kb
Host smart-e0dea742-ef20-484e-803c-01ad4f68d2d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597141662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3597141662
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.19640984
Short name T705
Test name
Test status
Simulation time 10269522908 ps
CPU time 15.9 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:22 PM PDT 24
Peak memory 311064 kb
Host smart-1915cf06-34e8-4a3f-93f2-2ee192c46ff4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19640984 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_fifo_reset_tx.19640984
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.502277775
Short name T399
Test name
Test status
Simulation time 7006212292 ps
CPU time 2.86 seconds
Started Apr 04 03:05:08 PM PDT 24
Finished Apr 04 03:05:12 PM PDT 24
Peak memory 203908 kb
Host smart-24a47b63-ced7-4da1-876d-edd2af1df2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502277775 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.i2c_target_hrst.502277775
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.954986156
Short name T256
Test name
Test status
Simulation time 4339446131 ps
CPU time 7.21 seconds
Started Apr 04 03:05:09 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 220052 kb
Host smart-d35bb294-c41f-441e-940c-fcdd864546d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954986156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.954986156
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2504366489
Short name T1043
Test name
Test status
Simulation time 1616140185 ps
CPU time 10.86 seconds
Started Apr 04 03:05:03 PM PDT 24
Finished Apr 04 03:05:14 PM PDT 24
Peak memory 203776 kb
Host smart-d7f83581-ec57-407f-8636-fb6c22a6d453
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504366489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2504366489
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.80602094
Short name T349
Test name
Test status
Simulation time 6632062880 ps
CPU time 30.31 seconds
Started Apr 04 03:05:12 PM PDT 24
Finished Apr 04 03:05:42 PM PDT 24
Peak memory 222444 kb
Host smart-9543acae-30a6-4ea8-a867-02bc85c3a9ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80602094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stress_rd.80602094
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1366561238
Short name T698
Test name
Test status
Simulation time 30553452000 ps
CPU time 575.49 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:14:43 PM PDT 24
Peak memory 1762836 kb
Host smart-3cd6150b-1343-4e4e-9326-18f7e940e59d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366561238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1366561238
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.1257536421
Short name T556
Test name
Test status
Simulation time 1491117914 ps
CPU time 7.37 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:05:18 PM PDT 24
Peak memory 219948 kb
Host smart-85fe19ef-3731-4b58-ba19-8a115cc3715d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257536421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.1257536421
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.676401543
Short name T511
Test name
Test status
Simulation time 18897962 ps
CPU time 0.6 seconds
Started Apr 04 03:05:14 PM PDT 24
Finished Apr 04 03:05:15 PM PDT 24
Peak memory 203560 kb
Host smart-693bcd1d-078f-4a68-a2f9-9d9612aff3ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676401543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.676401543
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.380406298
Short name T882
Test name
Test status
Simulation time 174240955 ps
CPU time 1.5 seconds
Started Apr 04 03:05:09 PM PDT 24
Finished Apr 04 03:05:11 PM PDT 24
Peak memory 212012 kb
Host smart-8e49b9c6-a456-40f3-a1db-97b749722143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380406298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.380406298
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2074150456
Short name T847
Test name
Test status
Simulation time 269290147 ps
CPU time 13.51 seconds
Started Apr 04 03:05:13 PM PDT 24
Finished Apr 04 03:05:26 PM PDT 24
Peak memory 255292 kb
Host smart-f3da9407-46ab-4be9-a90b-05cb2bd03e55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074150456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2074150456
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1599909281
Short name T80
Test name
Test status
Simulation time 5369213761 ps
CPU time 91.64 seconds
Started Apr 04 03:05:14 PM PDT 24
Finished Apr 04 03:06:45 PM PDT 24
Peak memory 539316 kb
Host smart-7ca1688e-11d5-4182-b0a4-2f9a235e1bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599909281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1599909281
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.306448599
Short name T374
Test name
Test status
Simulation time 5825812864 ps
CPU time 47.37 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:06:10 PM PDT 24
Peak memory 536656 kb
Host smart-84ceaeb4-0d9d-4c0c-bfd0-f871162eb82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306448599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.306448599
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3977484454
Short name T954
Test name
Test status
Simulation time 360141073 ps
CPU time 0.9 seconds
Started Apr 04 03:05:17 PM PDT 24
Finished Apr 04 03:05:18 PM PDT 24
Peak memory 203624 kb
Host smart-aca40146-fe17-472b-8c68-329f5a53efbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977484454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3977484454
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3775778824
Short name T150
Test name
Test status
Simulation time 2405711461 ps
CPU time 55.9 seconds
Started Apr 04 03:05:17 PM PDT 24
Finished Apr 04 03:06:13 PM PDT 24
Peak memory 795316 kb
Host smart-38c8f7c2-d257-4346-93d5-1916093b95d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775778824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3775778824
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2830660202
Short name T23
Test name
Test status
Simulation time 564232587 ps
CPU time 8.49 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:05:30 PM PDT 24
Peak memory 203676 kb
Host smart-6012e435-a732-412f-8a51-0279215b5a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830660202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2830660202
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3380630666
Short name T1123
Test name
Test status
Simulation time 2844270679 ps
CPU time 25.94 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:05:38 PM PDT 24
Peak memory 297628 kb
Host smart-023d6c49-e8d3-4e74-aa57-77c3372ac6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380630666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3380630666
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.991212903
Short name T391
Test name
Test status
Simulation time 27590272 ps
CPU time 0.73 seconds
Started Apr 04 03:05:06 PM PDT 24
Finished Apr 04 03:05:08 PM PDT 24
Peak memory 203552 kb
Host smart-eb737ed9-3082-445c-bce7-c81b0f5a40b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991212903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.991212903
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2359013625
Short name T844
Test name
Test status
Simulation time 3024985079 ps
CPU time 32.06 seconds
Started Apr 04 03:05:08 PM PDT 24
Finished Apr 04 03:05:41 PM PDT 24
Peak memory 542836 kb
Host smart-ecead9ac-31bd-4970-a075-281b66f095a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359013625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2359013625
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.503037739
Short name T928
Test name
Test status
Simulation time 920663863 ps
CPU time 39.22 seconds
Started Apr 04 03:05:07 PM PDT 24
Finished Apr 04 03:05:46 PM PDT 24
Peak memory 295384 kb
Host smart-cf83af45-4d4c-413e-a53a-8ba666ead23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503037739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.503037739
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3241898493
Short name T291
Test name
Test status
Simulation time 1055122649 ps
CPU time 4.83 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:20 PM PDT 24
Peak memory 211972 kb
Host smart-7c966205-ae53-400a-a15c-8a1a3bcb757f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241898493 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3241898493
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.537507173
Short name T296
Test name
Test status
Simulation time 10059884048 ps
CPU time 37.39 seconds
Started Apr 04 03:05:10 PM PDT 24
Finished Apr 04 03:05:48 PM PDT 24
Peak memory 422864 kb
Host smart-ae094fad-ecda-440e-aa8b-e7f098926909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537507173 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.537507173
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1514374165
Short name T525
Test name
Test status
Simulation time 10367128822 ps
CPU time 15.77 seconds
Started Apr 04 03:05:25 PM PDT 24
Finished Apr 04 03:05:40 PM PDT 24
Peak memory 311280 kb
Host smart-252a32e5-4258-4fff-896e-56d06f031292
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514374165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1514374165
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2951416674
Short name T48
Test name
Test status
Simulation time 3021929481 ps
CPU time 2.65 seconds
Started Apr 04 03:05:16 PM PDT 24
Finished Apr 04 03:05:19 PM PDT 24
Peak memory 203792 kb
Host smart-2b111d26-14bc-47f0-9037-a03ff276ccba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951416674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2951416674
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2578412463
Short name T306
Test name
Test status
Simulation time 3641963708 ps
CPU time 4.36 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:19 PM PDT 24
Peak memory 203812 kb
Host smart-cdff0453-5650-44ae-918b-1a3734d50568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578412463 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2578412463
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2501154690
Short name T845
Test name
Test status
Simulation time 1198822273 ps
CPU time 19.25 seconds
Started Apr 04 03:05:17 PM PDT 24
Finished Apr 04 03:05:36 PM PDT 24
Peak memory 203648 kb
Host smart-d04a68a8-ad45-4e09-a085-2a65a4595d43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501154690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2501154690
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.1594041534
Short name T975
Test name
Test status
Simulation time 3822363467 ps
CPU time 38.72 seconds
Started Apr 04 03:05:17 PM PDT 24
Finished Apr 04 03:05:56 PM PDT 24
Peak memory 203744 kb
Host smart-e2dc0efd-2bcc-4a4a-9a4e-9bbabb1cd79c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594041534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.1594041534
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2837581247
Short name T944
Test name
Test status
Simulation time 25759283850 ps
CPU time 1710.85 seconds
Started Apr 04 03:05:10 PM PDT 24
Finished Apr 04 03:33:41 PM PDT 24
Peak memory 6067440 kb
Host smart-e7390a84-0113-4f25-bb49-35522d3e54ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837581247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2837581247
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1252811148
Short name T543
Test name
Test status
Simulation time 1559722075 ps
CPU time 7.67 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:05:29 PM PDT 24
Peak memory 219884 kb
Host smart-cd68db4f-f07b-4873-8922-8b65a5dcfda6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252811148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1252811148
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3703237146
Short name T1007
Test name
Test status
Simulation time 27639797 ps
CPU time 0.63 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:16 PM PDT 24
Peak memory 203576 kb
Host smart-2fce24bb-e9e2-4624-87ff-11188cb5df29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703237146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3703237146
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3826993751
Short name T558
Test name
Test status
Simulation time 253164296 ps
CPU time 1.43 seconds
Started Apr 04 03:05:12 PM PDT 24
Finished Apr 04 03:05:14 PM PDT 24
Peak memory 211984 kb
Host smart-171ba2ba-2387-4e56-b2e8-21e09671c0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826993751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3826993751
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3058394214
Short name T467
Test name
Test status
Simulation time 401834336 ps
CPU time 18.46 seconds
Started Apr 04 03:05:14 PM PDT 24
Finished Apr 04 03:05:33 PM PDT 24
Peak memory 285636 kb
Host smart-4734f02d-12bd-4e37-ba64-8d8e1ec84c61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058394214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3058394214
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1009432475
Short name T73
Test name
Test status
Simulation time 6736653798 ps
CPU time 72.98 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:06:28 PM PDT 24
Peak memory 689408 kb
Host smart-686e4bfe-d3d6-4dbb-8568-a2205e7bd76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009432475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1009432475
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.4288662079
Short name T1203
Test name
Test status
Simulation time 1185294844 ps
CPU time 37.35 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:52 PM PDT 24
Peak memory 494432 kb
Host smart-b15b5d49-a8b0-46d3-9a68-a83552d7764f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288662079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.4288662079
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1005679779
Short name T1168
Test name
Test status
Simulation time 118905174 ps
CPU time 1.01 seconds
Started Apr 04 03:05:16 PM PDT 24
Finished Apr 04 03:05:18 PM PDT 24
Peak memory 203628 kb
Host smart-e89f0c55-36df-4e44-a57e-97b4eca53aab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005679779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1005679779
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2706348304
Short name T760
Test name
Test status
Simulation time 134939400 ps
CPU time 2.9 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:18 PM PDT 24
Peak memory 203728 kb
Host smart-b6cf7325-e508-462c-a0cb-3642c6b51aec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706348304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2706348304
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3910217604
Short name T1030
Test name
Test status
Simulation time 2322605130 ps
CPU time 53.77 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:06:05 PM PDT 24
Peak memory 778256 kb
Host smart-8b24360d-51c7-4056-a9a3-b958c8eb88ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910217604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3910217604
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3702020569
Short name T294
Test name
Test status
Simulation time 271625980 ps
CPU time 10.86 seconds
Started Apr 04 03:05:14 PM PDT 24
Finished Apr 04 03:05:25 PM PDT 24
Peak memory 203708 kb
Host smart-65fc85c0-b5a8-4d5d-ba3c-3dc2659c3cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702020569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3702020569
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3255144502
Short name T778
Test name
Test status
Simulation time 5174342247 ps
CPU time 64.48 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:06:27 PM PDT 24
Peak memory 389104 kb
Host smart-f28626cf-3ad3-4d82-8b87-53a462fb7e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255144502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3255144502
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.423910991
Short name T1163
Test name
Test status
Simulation time 18879959 ps
CPU time 0.66 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:05:12 PM PDT 24
Peak memory 203520 kb
Host smart-6d174347-456c-4bf0-884f-010492c7e4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423910991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.423910991
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.554925932
Short name T739
Test name
Test status
Simulation time 6652861568 ps
CPU time 42.67 seconds
Started Apr 04 03:05:19 PM PDT 24
Finished Apr 04 03:06:02 PM PDT 24
Peak memory 378712 kb
Host smart-1d3addc2-2df9-4da4-a29b-5bb3ba70efe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554925932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.554925932
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2395848494
Short name T1037
Test name
Test status
Simulation time 2820936283 ps
CPU time 80.47 seconds
Started Apr 04 03:05:14 PM PDT 24
Finished Apr 04 03:06:35 PM PDT 24
Peak memory 483528 kb
Host smart-2ccad978-df1e-47f3-9de3-0e8d75b32519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395848494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2395848494
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.2207266212
Short name T156
Test name
Test status
Simulation time 763396837 ps
CPU time 3.4 seconds
Started Apr 04 03:05:13 PM PDT 24
Finished Apr 04 03:05:16 PM PDT 24
Peak memory 203768 kb
Host smart-328b53e3-aa48-4bda-980e-595014bde729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207266212 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.2207266212
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2591485892
Short name T1193
Test name
Test status
Simulation time 10364562129 ps
CPU time 13.18 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:05:35 PM PDT 24
Peak memory 306004 kb
Host smart-282bb4a2-9cf2-45b5-a4b1-96621aa96543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591485892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2591485892
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2777436502
Short name T1041
Test name
Test status
Simulation time 2177166043 ps
CPU time 2.78 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:18 PM PDT 24
Peak memory 203720 kb
Host smart-02adaa62-9b9a-43df-8130-045c4835b2b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777436502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2777436502
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1500198005
Short name T364
Test name
Test status
Simulation time 24248565170 ps
CPU time 5.97 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:21 PM PDT 24
Peak memory 208120 kb
Host smart-5f787a0e-14d0-4a54-bb43-e2f07cdf5e88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500198005 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1500198005
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.4260715855
Short name T367
Test name
Test status
Simulation time 416524379 ps
CPU time 5.95 seconds
Started Apr 04 03:05:11 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 203704 kb
Host smart-89ce81a1-922e-4396-9904-4bfa2609b559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260715855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.4260715855
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3217964175
Short name T1202
Test name
Test status
Simulation time 1417126758 ps
CPU time 22.47 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:37 PM PDT 24
Peak memory 224580 kb
Host smart-ab80ea04-078a-41fe-96aa-04cce8d92a9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217964175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3217964175
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.288688147
Short name T1122
Test name
Test status
Simulation time 4089734716 ps
CPU time 7.02 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:22 PM PDT 24
Peak memory 203856 kb
Host smart-a0ec6398-ee7d-4045-a1de-4d3def2c4c1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288688147 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.288688147
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_unexp_stop.2255992546
Short name T822
Test name
Test status
Simulation time 1006657834 ps
CPU time 6.92 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:22 PM PDT 24
Peak memory 203752 kb
Host smart-8611ec13-fe6f-495b-b12a-6f888838049b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255992546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.i2c_target_unexp_stop.2255992546
Directory /workspace/25.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/26.i2c_alert_test.724183262
Short name T993
Test name
Test status
Simulation time 20267468 ps
CPU time 0.65 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 203632 kb
Host smart-b8dceef0-2596-49be-9ad4-5fb36987ca57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724183262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.724183262
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.1872771696
Short name T51
Test name
Test status
Simulation time 114563556 ps
CPU time 1.55 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:35 PM PDT 24
Peak memory 212004 kb
Host smart-893d3487-bd1d-4086-a1da-87d72a55f20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872771696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.1872771696
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2442523257
Short name T764
Test name
Test status
Simulation time 4227762456 ps
CPU time 6.32 seconds
Started Apr 04 03:05:14 PM PDT 24
Finished Apr 04 03:05:20 PM PDT 24
Peak memory 277896 kb
Host smart-7c5d2be1-1c67-48cc-bc81-3e581d7221ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442523257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2442523257
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.259974723
Short name T448
Test name
Test status
Simulation time 7341665647 ps
CPU time 144.04 seconds
Started Apr 04 03:05:24 PM PDT 24
Finished Apr 04 03:07:48 PM PDT 24
Peak memory 678004 kb
Host smart-fd35f6b5-f1fb-4a0d-bfa3-4896058ec010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259974723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.259974723
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1532482681
Short name T1100
Test name
Test status
Simulation time 8379163180 ps
CPU time 54.23 seconds
Started Apr 04 03:05:13 PM PDT 24
Finished Apr 04 03:06:07 PM PDT 24
Peak memory 625444 kb
Host smart-ccfe9921-9905-49fe-ae73-294f9a2fe328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532482681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1532482681
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3895063548
Short name T774
Test name
Test status
Simulation time 379479587 ps
CPU time 0.94 seconds
Started Apr 04 03:05:16 PM PDT 24
Finished Apr 04 03:05:17 PM PDT 24
Peak memory 203612 kb
Host smart-ea0fcc02-6e14-45b9-8cba-2c2864c6c70a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895063548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3895063548
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.4216419257
Short name T766
Test name
Test status
Simulation time 618332133 ps
CPU time 3.13 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:05:19 PM PDT 24
Peak memory 222492 kb
Host smart-08ce0e2a-f745-4864-bf64-0735821d9eca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216419257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.4216419257
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2998756242
Short name T881
Test name
Test status
Simulation time 5898437225 ps
CPU time 185.14 seconds
Started Apr 04 03:05:15 PM PDT 24
Finished Apr 04 03:08:20 PM PDT 24
Peak memory 840360 kb
Host smart-c66fda31-447e-465d-acfb-f727ccfe226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998756242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2998756242
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.516421201
Short name T1174
Test name
Test status
Simulation time 361156813 ps
CPU time 14.9 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:05:47 PM PDT 24
Peak memory 203748 kb
Host smart-828bb6ed-be5e-4b16-b383-82e178477e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516421201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.516421201
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.441341384
Short name T666
Test name
Test status
Simulation time 2042282625 ps
CPU time 44.28 seconds
Started Apr 04 03:05:25 PM PDT 24
Finished Apr 04 03:06:10 PM PDT 24
Peak memory 329940 kb
Host smart-f07a7288-d2ae-44ed-832a-12cf6c41a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441341384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.441341384
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3959105736
Short name T754
Test name
Test status
Simulation time 37007198 ps
CPU time 0.65 seconds
Started Apr 04 03:05:25 PM PDT 24
Finished Apr 04 03:05:26 PM PDT 24
Peak memory 203396 kb
Host smart-ff8036fc-3c94-4fef-b3e9-13fe34695422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959105736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3959105736
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.27182615
Short name T1049
Test name
Test status
Simulation time 29358953869 ps
CPU time 343.91 seconds
Started Apr 04 03:05:17 PM PDT 24
Finished Apr 04 03:11:02 PM PDT 24
Peak memory 1787828 kb
Host smart-20a59cec-52e7-4a67-874c-ff0c48ae05cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27182615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.27182615
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.542009205
Short name T1137
Test name
Test status
Simulation time 1354634967 ps
CPU time 68.98 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:06:31 PM PDT 24
Peak memory 379312 kb
Host smart-be3366a6-7bd3-4df3-9c31-615c3803f492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542009205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.542009205
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2107851872
Short name T238
Test name
Test status
Simulation time 5775433133 ps
CPU time 217.38 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 1133836 kb
Host smart-5bd04946-7227-470c-829a-0d16f5f19457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107851872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2107851872
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2190894863
Short name T723
Test name
Test status
Simulation time 727424439 ps
CPU time 3.78 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:05:36 PM PDT 24
Peak memory 203684 kb
Host smart-565c3ee2-5c20-46ad-90f9-4ac1b8817f16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190894863 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2190894863
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3191870658
Short name T773
Test name
Test status
Simulation time 10392230097 ps
CPU time 16.5 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:05:38 PM PDT 24
Peak memory 326672 kb
Host smart-0f7837fd-b300-4ec3-9ea9-f6936fd4f1c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191870658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3191870658
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4148074705
Short name T434
Test name
Test status
Simulation time 10123248114 ps
CPU time 138.66 seconds
Started Apr 04 03:05:35 PM PDT 24
Finished Apr 04 03:07:54 PM PDT 24
Peak memory 768140 kb
Host smart-c88c0345-0492-45f1-9099-1c3a1b1895ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148074705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4148074705
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.92944943
Short name T953
Test name
Test status
Simulation time 4697213168 ps
CPU time 3.1 seconds
Started Apr 04 03:05:30 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 203820 kb
Host smart-906522b9-f571-4b2e-b2ca-01dadad83272
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92944943 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.i2c_target_hrst.92944943
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.2962739171
Short name T792
Test name
Test status
Simulation time 788227514 ps
CPU time 4.57 seconds
Started Apr 04 03:05:20 PM PDT 24
Finished Apr 04 03:05:24 PM PDT 24
Peak memory 205388 kb
Host smart-6977fa24-e16b-4ada-809e-06ce20a9852b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962739171 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.2962739171
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1310995944
Short name T709
Test name
Test status
Simulation time 11636496808 ps
CPU time 3.88 seconds
Started Apr 04 03:05:19 PM PDT 24
Finished Apr 04 03:05:23 PM PDT 24
Peak memory 203792 kb
Host smart-a926c8a6-5ef1-4820-9cdc-2d9661eb9ad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310995944 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1310995944
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2383655102
Short name T810
Test name
Test status
Simulation time 3226290743 ps
CPU time 25.58 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:05:55 PM PDT 24
Peak memory 203836 kb
Host smart-db4fb79e-5984-4efb-b93c-faddb0c6920c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383655102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2383655102
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.4027639752
Short name T329
Test name
Test status
Simulation time 3521957776 ps
CPU time 30.62 seconds
Started Apr 04 03:05:30 PM PDT 24
Finished Apr 04 03:06:01 PM PDT 24
Peak memory 228948 kb
Host smart-adb8603b-bdd5-4cfe-930f-47b9554c084a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027639752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.4027639752
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3479359923
Short name T1029
Test name
Test status
Simulation time 17178748969 ps
CPU time 7.46 seconds
Started Apr 04 03:05:22 PM PDT 24
Finished Apr 04 03:05:30 PM PDT 24
Peak memory 203872 kb
Host smart-81b46f9b-e16e-471e-a3c0-ceb02882e2a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479359923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3479359923
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1527243559
Short name T827
Test name
Test status
Simulation time 15568759880 ps
CPU time 78.99 seconds
Started Apr 04 03:05:19 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 1004256 kb
Host smart-82a4f72a-aa98-4c0b-b3a5-6ae9ac515f8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527243559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1527243559
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3717449500
Short name T395
Test name
Test status
Simulation time 2327063193 ps
CPU time 6.79 seconds
Started Apr 04 03:05:25 PM PDT 24
Finished Apr 04 03:05:32 PM PDT 24
Peak memory 220004 kb
Host smart-640bdcf2-5173-4bdd-8527-b1374a6ffc2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717449500 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3717449500
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.441060671
Short name T736
Test name
Test status
Simulation time 95068393 ps
CPU time 0.59 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:33 PM PDT 24
Peak memory 203592 kb
Host smart-19f13f86-8ebc-40cd-8282-c6803e1eeb77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441060671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.441060671
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1454910491
Short name T1028
Test name
Test status
Simulation time 76119490 ps
CPU time 1.14 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:05:23 PM PDT 24
Peak memory 211856 kb
Host smart-81ee45b5-f7a0-45f6-b1b3-90704f3fb90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454910491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1454910491
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2496356866
Short name T1031
Test name
Test status
Simulation time 1322885682 ps
CPU time 6.61 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:05:36 PM PDT 24
Peak memory 274748 kb
Host smart-028e2df6-8372-4e2f-a122-d3b4f801be50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496356866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2496356866
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1618817027
Short name T1142
Test name
Test status
Simulation time 1975068751 ps
CPU time 67.86 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:06:40 PM PDT 24
Peak memory 668420 kb
Host smart-1e43bc4a-4aea-492e-aef0-3af77a2041d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618817027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1618817027
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3015733511
Short name T833
Test name
Test status
Simulation time 3692167889 ps
CPU time 114.1 seconds
Started Apr 04 03:05:19 PM PDT 24
Finished Apr 04 03:07:13 PM PDT 24
Peak memory 522480 kb
Host smart-410192dd-2de8-4ba4-b7a7-f44a369ed55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015733511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3015733511
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1419467745
Short name T903
Test name
Test status
Simulation time 273969588 ps
CPU time 0.97 seconds
Started Apr 04 03:05:20 PM PDT 24
Finished Apr 04 03:05:21 PM PDT 24
Peak memory 203612 kb
Host smart-0d96fa97-6a16-4f11-ba57-b4d66f16b6e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419467745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1419467745
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1627970248
Short name T733
Test name
Test status
Simulation time 426209982 ps
CPU time 3.18 seconds
Started Apr 04 03:05:18 PM PDT 24
Finished Apr 04 03:05:22 PM PDT 24
Peak memory 221456 kb
Host smart-32bca3c5-c7fa-4287-9e53-9d9121be0649
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627970248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1627970248
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.254462934
Short name T1087
Test name
Test status
Simulation time 7746796309 ps
CPU time 116.25 seconds
Started Apr 04 03:05:22 PM PDT 24
Finished Apr 04 03:07:18 PM PDT 24
Peak memory 1149520 kb
Host smart-5e256f1e-088e-4542-bfeb-7cccec9766ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254462934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.254462934
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3602977943
Short name T904
Test name
Test status
Simulation time 1235252534 ps
CPU time 11.88 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 203804 kb
Host smart-dd668a9e-a432-4dcc-b349-2b660ff5f224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602977943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3602977943
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2157985764
Short name T47
Test name
Test status
Simulation time 4697144490 ps
CPU time 20.05 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:05:49 PM PDT 24
Peak memory 346876 kb
Host smart-1be68599-d843-4dae-8be7-f19d868f003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157985764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2157985764
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.2781217983
Short name T695
Test name
Test status
Simulation time 27617433 ps
CPU time 0.69 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:05:30 PM PDT 24
Peak memory 203512 kb
Host smart-9d13b8df-7212-4ccb-8781-c72d554cbe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781217983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2781217983
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1068776376
Short name T984
Test name
Test status
Simulation time 1645710281 ps
CPU time 65.66 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:06:39 PM PDT 24
Peak memory 237576 kb
Host smart-79edc761-bc1b-4df0-a742-c2d6f04e90f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068776376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1068776376
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3338790019
Short name T813
Test name
Test status
Simulation time 4792830200 ps
CPU time 14.67 seconds
Started Apr 04 03:05:24 PM PDT 24
Finished Apr 04 03:05:39 PM PDT 24
Peak memory 292488 kb
Host smart-a62f1e8d-043e-4bc1-ac0d-705498994cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338790019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3338790019
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3379290032
Short name T160
Test name
Test status
Simulation time 14527021319 ps
CPU time 599.3 seconds
Started Apr 04 03:05:28 PM PDT 24
Finished Apr 04 03:15:28 PM PDT 24
Peak memory 2812156 kb
Host smart-706c1993-4495-4235-bfdc-ad9d77ce62da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379290032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3379290032
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2345531426
Short name T1166
Test name
Test status
Simulation time 771130341 ps
CPU time 3.55 seconds
Started Apr 04 03:05:20 PM PDT 24
Finished Apr 04 03:05:23 PM PDT 24
Peak memory 203628 kb
Host smart-99e303a2-61c7-4394-b939-253950f587b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345531426 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2345531426
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2847219030
Short name T594
Test name
Test status
Simulation time 10035309620 ps
CPU time 89.98 seconds
Started Apr 04 03:05:30 PM PDT 24
Finished Apr 04 03:07:01 PM PDT 24
Peak memory 588800 kb
Host smart-74e75ccb-09f0-465e-8ed0-6bdfd5671df3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847219030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2847219030
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2762741447
Short name T498
Test name
Test status
Simulation time 10078068984 ps
CPU time 45.77 seconds
Started Apr 04 03:05:21 PM PDT 24
Finished Apr 04 03:06:08 PM PDT 24
Peak memory 466536 kb
Host smart-62640cc3-71d8-4a58-962f-6a11a9ce2453
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762741447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2762741447
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.464301236
Short name T776
Test name
Test status
Simulation time 324938557 ps
CPU time 2.07 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:35 PM PDT 24
Peak memory 203780 kb
Host smart-310d2a0e-b567-4383-aba9-75c848245e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464301236 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_hrst.464301236
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3167842567
Short name T565
Test name
Test status
Simulation time 11163261958 ps
CPU time 3.72 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:05:33 PM PDT 24
Peak memory 203808 kb
Host smart-e5fc43b5-200e-4a9e-ba96-5dad0c45fba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167842567 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3167842567
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1745060538
Short name T532
Test name
Test status
Simulation time 4971963609 ps
CPU time 3.15 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:36 PM PDT 24
Peak memory 203784 kb
Host smart-882add7a-fc3b-458b-8006-6ddfe2288897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745060538 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1745060538
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3272803163
Short name T1110
Test name
Test status
Simulation time 1316718660 ps
CPU time 18.52 seconds
Started Apr 04 03:05:23 PM PDT 24
Finished Apr 04 03:05:41 PM PDT 24
Peak memory 203784 kb
Host smart-48bd17da-070d-445b-93a1-4109aa007c61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272803163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3272803163
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.974886912
Short name T919
Test name
Test status
Simulation time 22013906459 ps
CPU time 31.47 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:06:01 PM PDT 24
Peak memory 238508 kb
Host smart-d89c87b7-0e31-4453-bcfd-022d29312702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974886912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.974886912
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2910912766
Short name T397
Test name
Test status
Simulation time 15732357546 ps
CPU time 30.92 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:06:00 PM PDT 24
Peak memory 203852 kb
Host smart-ac682fb7-a28f-4f3c-8584-501a0a340de1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910912766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2910912766
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3865070050
Short name T732
Test name
Test status
Simulation time 5366327081 ps
CPU time 7.15 seconds
Started Apr 04 03:05:35 PM PDT 24
Finished Apr 04 03:05:42 PM PDT 24
Peak memory 211764 kb
Host smart-491dd8f9-54da-4fbd-95ca-b8b3c615a9d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865070050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3865070050
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1223201442
Short name T768
Test name
Test status
Simulation time 48049553 ps
CPU time 0.68 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 203588 kb
Host smart-db8e3998-4312-4000-96f9-16b8e7c1b955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223201442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1223201442
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3228201697
Short name T846
Test name
Test status
Simulation time 322988928 ps
CPU time 1.14 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:05:31 PM PDT 24
Peak memory 211956 kb
Host smart-971ecb7e-44c3-46b7-82fa-8edfa913f99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228201697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3228201697
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1000145236
Short name T442
Test name
Test status
Simulation time 475568319 ps
CPU time 4.71 seconds
Started Apr 04 03:05:25 PM PDT 24
Finished Apr 04 03:05:30 PM PDT 24
Peak memory 248684 kb
Host smart-bde40e12-0601-4205-abc1-280f7e8b0aa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000145236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1000145236
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3562807398
Short name T490
Test name
Test status
Simulation time 1790741206 ps
CPU time 45.51 seconds
Started Apr 04 03:05:37 PM PDT 24
Finished Apr 04 03:06:23 PM PDT 24
Peak memory 457308 kb
Host smart-74f818f3-d1df-4178-be3b-a7b1c46972e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562807398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3562807398
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1317979699
Short name T1081
Test name
Test status
Simulation time 1444236364 ps
CPU time 43.59 seconds
Started Apr 04 03:05:29 PM PDT 24
Finished Apr 04 03:06:13 PM PDT 24
Peak memory 538128 kb
Host smart-dbde4034-3f9f-4dbb-bb73-f5ba128fabab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317979699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1317979699
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1670951401
Short name T504
Test name
Test status
Simulation time 582493431 ps
CPU time 1.17 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 203728 kb
Host smart-72ef7a52-f876-4d8a-8f4d-a6c22acf60ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670951401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1670951401
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.2529522242
Short name T718
Test name
Test status
Simulation time 113157965 ps
CPU time 3.18 seconds
Started Apr 04 03:05:36 PM PDT 24
Finished Apr 04 03:05:40 PM PDT 24
Peak memory 219096 kb
Host smart-e05c21c1-ee9f-4f1c-98e9-7d601ca134d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529522242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.2529522242
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.725211862
Short name T1212
Test name
Test status
Simulation time 3642005784 ps
CPU time 269.95 seconds
Started Apr 04 03:05:27 PM PDT 24
Finished Apr 04 03:09:57 PM PDT 24
Peak memory 1072140 kb
Host smart-0a293ba5-bd43-45a4-b213-be9e68b05cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725211862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.725211862
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2579349554
Short name T1112
Test name
Test status
Simulation time 1370246923 ps
CPU time 17.4 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:50 PM PDT 24
Peak memory 203688 kb
Host smart-de25a18d-6943-4cf5-939c-eb549fc5768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579349554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2579349554
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.4281629195
Short name T769
Test name
Test status
Simulation time 1179219216 ps
CPU time 47.16 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:06:21 PM PDT 24
Peak memory 311540 kb
Host smart-457fe3bb-71bf-4c4a-9182-006036fdc725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281629195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.4281629195
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.3825385872
Short name T936
Test name
Test status
Simulation time 23372623 ps
CPU time 0.63 seconds
Started Apr 04 03:05:28 PM PDT 24
Finished Apr 04 03:05:29 PM PDT 24
Peak memory 203496 kb
Host smart-2ce47a92-28a9-4316-8232-4a992b60ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825385872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3825385872
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3836606338
Short name T41
Test name
Test status
Simulation time 30117436827 ps
CPU time 123.82 seconds
Started Apr 04 03:05:37 PM PDT 24
Finished Apr 04 03:07:41 PM PDT 24
Peak memory 1006900 kb
Host smart-24a8b9b4-594e-4ff7-8350-b56027d842ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836606338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3836606338
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1342460749
Short name T340
Test name
Test status
Simulation time 6711321146 ps
CPU time 29.41 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:06:03 PM PDT 24
Peak memory 417616 kb
Host smart-21662f45-0ba0-4483-afe4-100fff84e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342460749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1342460749
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3641420553
Short name T489
Test name
Test status
Simulation time 2219172972 ps
CPU time 2.94 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:05:35 PM PDT 24
Peak memory 203836 kb
Host smart-d02dc9f8-5b0e-46b4-9da6-3f57120e33f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641420553 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3641420553
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3874146052
Short name T791
Test name
Test status
Simulation time 10096647241 ps
CPU time 108.52 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 822940 kb
Host smart-7271de2e-6fb2-4c2b-a81d-7cf4d93282c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874146052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3874146052
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3271794909
Short name T351
Test name
Test status
Simulation time 392498606 ps
CPU time 2.69 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:05:35 PM PDT 24
Peak memory 203640 kb
Host smart-c98503e0-4dd9-4341-be5e-537e9444e7c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271794909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3271794909
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.3626103110
Short name T852
Test name
Test status
Simulation time 2354632912 ps
CPU time 5.82 seconds
Started Apr 04 03:05:37 PM PDT 24
Finished Apr 04 03:05:43 PM PDT 24
Peak memory 203852 kb
Host smart-54553799-2bc3-48ba-9cc2-6be909edc38d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626103110 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.3626103110
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2290976199
Short name T459
Test name
Test status
Simulation time 8069698334 ps
CPU time 34.82 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:06:08 PM PDT 24
Peak memory 203872 kb
Host smart-e79e71d3-45bb-41f2-84b9-95f676b8596f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290976199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2290976199
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1577019400
Short name T254
Test name
Test status
Simulation time 1429367512 ps
CPU time 11.12 seconds
Started Apr 04 03:05:37 PM PDT 24
Finished Apr 04 03:05:48 PM PDT 24
Peak memory 210424 kb
Host smart-3324ecb6-bc8d-4d5c-b4f4-decdcfd11666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577019400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1577019400
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2679217316
Short name T1061
Test name
Test status
Simulation time 39652797177 ps
CPU time 3275.67 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 04:00:09 PM PDT 24
Peak memory 4683384 kb
Host smart-c870f2f7-ee7a-4fc2-8de7-71fb658ac600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679217316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2679217316
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1705943680
Short name T816
Test name
Test status
Simulation time 1533135557 ps
CPU time 7.99 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:41 PM PDT 24
Peak memory 215480 kb
Host smart-0afcdedd-4f97-4215-b132-96b5dd939172
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705943680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1705943680
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1350805319
Short name T972
Test name
Test status
Simulation time 27287340 ps
CPU time 0.6 seconds
Started Apr 04 03:05:31 PM PDT 24
Finished Apr 04 03:05:32 PM PDT 24
Peak memory 203564 kb
Host smart-745432c2-16e6-48ef-b277-ee735fb931e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350805319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1350805319
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2574718109
Short name T838
Test name
Test status
Simulation time 87974465 ps
CPU time 1.24 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:05:35 PM PDT 24
Peak memory 211920 kb
Host smart-e5f7579d-9797-4900-95f3-50ca91a88310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574718109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2574718109
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.233020523
Short name T801
Test name
Test status
Simulation time 846442711 ps
CPU time 7.75 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:05:40 PM PDT 24
Peak memory 293372 kb
Host smart-69c68d70-c7e7-4da4-bd53-ac8719145979
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233020523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.233020523
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3670641888
Short name T759
Test name
Test status
Simulation time 2396804680 ps
CPU time 81.26 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:06:55 PM PDT 24
Peak memory 694780 kb
Host smart-4d9a3bfe-dbb0-49ae-b93f-6ce90da9047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670641888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3670641888
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.350351705
Short name T1128
Test name
Test status
Simulation time 1400704185 ps
CPU time 88.46 seconds
Started Apr 04 03:05:44 PM PDT 24
Finished Apr 04 03:07:14 PM PDT 24
Peak memory 447484 kb
Host smart-85994c04-9b0b-452f-a725-b166f1267c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350351705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.350351705
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1102556431
Short name T1072
Test name
Test status
Simulation time 540347104 ps
CPU time 0.9 seconds
Started Apr 04 03:05:36 PM PDT 24
Finished Apr 04 03:05:37 PM PDT 24
Peak memory 203572 kb
Host smart-5e782d09-956c-45e7-90ab-5730b0d63b1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102556431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1102556431
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.401667537
Short name T1053
Test name
Test status
Simulation time 950096806 ps
CPU time 3 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:36 PM PDT 24
Peak memory 203744 kb
Host smart-0c7af9ae-80a8-4702-8d03-72d63bafe322
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401667537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
401667537
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.378104110
Short name T830
Test name
Test status
Simulation time 4453985432 ps
CPU time 141.64 seconds
Started Apr 04 03:05:36 PM PDT 24
Finished Apr 04 03:07:58 PM PDT 24
Peak memory 1271060 kb
Host smart-3adfaf59-2aed-4092-93f2-7e0c124099b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378104110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.378104110
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.2244666112
Short name T583
Test name
Test status
Simulation time 1652268111 ps
CPU time 6.45 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:05:40 PM PDT 24
Peak memory 203736 kb
Host smart-6e97797a-66fb-4a8c-ab23-b7a35d64086d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244666112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.2244666112
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1722058551
Short name T571
Test name
Test status
Simulation time 2443119211 ps
CPU time 62.14 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:06:36 PM PDT 24
Peak memory 340376 kb
Host smart-d1a1d302-b88b-4bcd-bb7f-849f13ceb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722058551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1722058551
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.4084205544
Short name T167
Test name
Test status
Simulation time 21369508 ps
CPU time 0.67 seconds
Started Apr 04 03:05:33 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 203516 kb
Host smart-97aaaf11-45d8-4fa7-9aeb-fcbc61b83469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084205544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4084205544
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.4205609601
Short name T28
Test name
Test status
Simulation time 2871926098 ps
CPU time 81.62 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:06:53 PM PDT 24
Peak memory 549024 kb
Host smart-0be3e67c-068a-4315-baf3-cfba1cfa1011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205609601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.4205609601
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3561693661
Short name T177
Test name
Test status
Simulation time 916248892 ps
CPU time 43.59 seconds
Started Apr 04 03:05:32 PM PDT 24
Finished Apr 04 03:06:16 PM PDT 24
Peak memory 313068 kb
Host smart-20ed72a3-ad5c-4b20-89fb-18e621941586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561693661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3561693661
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2087691810
Short name T321
Test name
Test status
Simulation time 1975978459 ps
CPU time 4.66 seconds
Started Apr 04 03:05:43 PM PDT 24
Finished Apr 04 03:05:47 PM PDT 24
Peak memory 211928 kb
Host smart-8e26eea4-a38f-4de5-bd3c-54f71df2dc6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087691810 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2087691810
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3735439669
Short name T1211
Test name
Test status
Simulation time 10367054062 ps
CPU time 4.11 seconds
Started Apr 04 03:05:35 PM PDT 24
Finished Apr 04 03:05:40 PM PDT 24
Peak memory 227472 kb
Host smart-15941745-3089-42f8-9f6b-39081dd87089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735439669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3735439669
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3402796267
Short name T424
Test name
Test status
Simulation time 10022945689 ps
CPU time 126.06 seconds
Started Apr 04 03:05:30 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 752528 kb
Host smart-4287a0f5-2fcd-4e72-96a7-6d7e19591540
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402796267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3402796267
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.984843430
Short name T202
Test name
Test status
Simulation time 1604379505 ps
CPU time 2.35 seconds
Started Apr 04 03:05:31 PM PDT 24
Finished Apr 04 03:05:34 PM PDT 24
Peak memory 203636 kb
Host smart-b1e6f08e-7a0e-4271-95e3-da748c4f980a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984843430 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.984843430
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1536655772
Short name T333
Test name
Test status
Simulation time 973178048 ps
CPU time 5.34 seconds
Started Apr 04 03:05:35 PM PDT 24
Finished Apr 04 03:05:41 PM PDT 24
Peak memory 203712 kb
Host smart-583197f8-58d1-427a-b504-60200ce7924a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536655772 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1536655772
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3637655311
Short name T514
Test name
Test status
Simulation time 2591908607 ps
CPU time 43.28 seconds
Started Apr 04 03:05:30 PM PDT 24
Finished Apr 04 03:06:14 PM PDT 24
Peak memory 203824 kb
Host smart-ba7640c0-8aa4-456b-a9f8-ae43771fb508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637655311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3637655311
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.445444472
Short name T248
Test name
Test status
Simulation time 708747803 ps
CPU time 28.77 seconds
Started Apr 04 03:05:36 PM PDT 24
Finished Apr 04 03:06:05 PM PDT 24
Peak memory 203716 kb
Host smart-3774abf0-f1cc-462a-9945-ee1e3b2993d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445444472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.445444472
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.123560189
Short name T858
Test name
Test status
Simulation time 1015575281 ps
CPU time 5.86 seconds
Started Apr 04 03:05:30 PM PDT 24
Finished Apr 04 03:05:37 PM PDT 24
Peak memory 219876 kb
Host smart-bb221cb2-8981-4dc4-bc2b-7fab6f9be197
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123560189 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.123560189
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1260809467
Short name T3
Test name
Test status
Simulation time 26017860 ps
CPU time 0.6 seconds
Started Apr 04 03:02:52 PM PDT 24
Finished Apr 04 03:02:54 PM PDT 24
Peak memory 203600 kb
Host smart-08d416e4-5e43-41a7-9591-49aa2b6fa45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260809467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1260809467
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1512782194
Short name T196
Test name
Test status
Simulation time 285329141 ps
CPU time 1.72 seconds
Started Apr 04 03:02:49 PM PDT 24
Finished Apr 04 03:02:52 PM PDT 24
Peak memory 203632 kb
Host smart-34c6f6f0-b98f-4aa8-9abd-c2ff03e0dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512782194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1512782194
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.3735517623
Short name T402
Test name
Test status
Simulation time 1535150449 ps
CPU time 7.01 seconds
Started Apr 04 03:02:50 PM PDT 24
Finished Apr 04 03:02:58 PM PDT 24
Peak memory 284556 kb
Host smart-94616d11-e8b9-45fe-842d-c64360213bea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735517623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.3735517623
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3291851406
Short name T1079
Test name
Test status
Simulation time 7871640914 ps
CPU time 97.17 seconds
Started Apr 04 03:02:51 PM PDT 24
Finished Apr 04 03:04:31 PM PDT 24
Peak memory 240620 kb
Host smart-b15ca55f-8a53-4f76-ba62-647208aef880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291851406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3291851406
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.779439844
Short name T969
Test name
Test status
Simulation time 17626143123 ps
CPU time 78.49 seconds
Started Apr 04 03:02:53 PM PDT 24
Finished Apr 04 03:04:12 PM PDT 24
Peak memory 729996 kb
Host smart-d6f6c4e5-fc85-48b2-8209-54a23a4b1247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779439844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.779439844
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3585781125
Short name T660
Test name
Test status
Simulation time 198895694 ps
CPU time 0.88 seconds
Started Apr 04 03:02:50 PM PDT 24
Finished Apr 04 03:02:51 PM PDT 24
Peak memory 203516 kb
Host smart-d0e06f8f-1698-43f1-8653-e4314c59de69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585781125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3585781125
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2798992759
Short name T1078
Test name
Test status
Simulation time 863780409 ps
CPU time 3.01 seconds
Started Apr 04 03:02:52 PM PDT 24
Finished Apr 04 03:02:57 PM PDT 24
Peak memory 203748 kb
Host smart-33424b1e-4e7a-4153-83e5-bd5d72c5f6e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798992759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2798992759
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2692679075
Short name T783
Test name
Test status
Simulation time 826479634 ps
CPU time 3.15 seconds
Started Apr 04 03:02:58 PM PDT 24
Finished Apr 04 03:03:02 PM PDT 24
Peak memory 203752 kb
Host smart-edbb32d8-c977-4139-ab1d-f999ce7d9297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692679075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2692679075
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.426066998
Short name T911
Test name
Test status
Simulation time 25084098154 ps
CPU time 27.51 seconds
Started Apr 04 03:02:52 PM PDT 24
Finished Apr 04 03:03:21 PM PDT 24
Peak memory 366024 kb
Host smart-c6bc3f15-5078-40ad-89ca-18dcd532752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426066998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.426066998
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.255540712
Short name T544
Test name
Test status
Simulation time 85597067 ps
CPU time 0.65 seconds
Started Apr 04 03:02:58 PM PDT 24
Finished Apr 04 03:02:59 PM PDT 24
Peak memory 203528 kb
Host smart-e23ac6c8-f254-4026-9992-c0d9fbc076c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255540712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.255540712
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1814934852
Short name T892
Test name
Test status
Simulation time 1285123256 ps
CPU time 26.16 seconds
Started Apr 04 03:02:58 PM PDT 24
Finished Apr 04 03:03:25 PM PDT 24
Peak memory 379444 kb
Host smart-9aa3cff1-1306-4d75-99e4-ec581f192601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814934852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1814934852
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2514468037
Short name T92
Test name
Test status
Simulation time 130908044 ps
CPU time 0.82 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:02:55 PM PDT 24
Peak memory 221296 kb
Host smart-fea29ecc-cda2-49ac-9ef7-ee1aa03431e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514468037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2514468037
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1541030562
Short name T1105
Test name
Test status
Simulation time 3765181726 ps
CPU time 4.34 seconds
Started Apr 04 03:02:50 PM PDT 24
Finished Apr 04 03:02:55 PM PDT 24
Peak memory 203760 kb
Host smart-02f07bef-9929-4582-9b43-514fe8e0dca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541030562 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1541030562
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3135351398
Short name T76
Test name
Test status
Simulation time 10061328480 ps
CPU time 15.1 seconds
Started Apr 04 03:02:50 PM PDT 24
Finished Apr 04 03:03:05 PM PDT 24
Peak memory 294156 kb
Host smart-e607ebed-39f6-4498-a303-fedd56f9bfe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135351398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3135351398
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1106549749
Short name T315
Test name
Test status
Simulation time 10067798038 ps
CPU time 40.19 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:03:34 PM PDT 24
Peak memory 475992 kb
Host smart-ba5bfd4d-1fc4-49c1-add8-32a5066d2851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106549749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1106549749
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.428137256
Short name T848
Test name
Test status
Simulation time 1825003557 ps
CPU time 2.44 seconds
Started Apr 04 03:02:50 PM PDT 24
Finished Apr 04 03:02:53 PM PDT 24
Peak memory 203780 kb
Host smart-566afae7-7f15-4b43-96cb-d9dd0865e447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428137256 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.428137256
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.920981722
Short name T487
Test name
Test status
Simulation time 663616202 ps
CPU time 3.81 seconds
Started Apr 04 03:02:49 PM PDT 24
Finished Apr 04 03:02:54 PM PDT 24
Peak memory 203740 kb
Host smart-a61fa19c-acf3-4a95-b539-c36a5aec4504
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920981722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.920981722
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3281608709
Short name T433
Test name
Test status
Simulation time 826573420 ps
CPU time 13.15 seconds
Started Apr 04 03:02:53 PM PDT 24
Finished Apr 04 03:03:08 PM PDT 24
Peak memory 203696 kb
Host smart-9d50f6ed-7c47-4197-b41a-092d718a7bf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281608709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3281608709
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.692238102
Short name T596
Test name
Test status
Simulation time 718117762 ps
CPU time 30.66 seconds
Started Apr 04 03:02:52 PM PDT 24
Finished Apr 04 03:03:24 PM PDT 24
Peak memory 203756 kb
Host smart-d8dea3ad-51a9-4324-9dba-43c65093e9c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692238102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.692238102
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1613531165
Short name T849
Test name
Test status
Simulation time 2407331810 ps
CPU time 6.72 seconds
Started Apr 04 03:02:56 PM PDT 24
Finished Apr 04 03:03:03 PM PDT 24
Peak memory 208868 kb
Host smart-14836029-c1ea-4029-aa59-9c9b3b198e90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613531165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1613531165
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1581977078
Short name T995
Test name
Test status
Simulation time 39704486 ps
CPU time 0.62 seconds
Started Apr 04 03:05:48 PM PDT 24
Finished Apr 04 03:05:49 PM PDT 24
Peak memory 203488 kb
Host smart-2f075854-dffb-45f2-9b64-46c1e5f89163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581977078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1581977078
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2457677422
Short name T330
Test name
Test status
Simulation time 609666800 ps
CPU time 1.81 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:05:48 PM PDT 24
Peak memory 211820 kb
Host smart-dce88c93-d227-421f-b5bd-3c97933db256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457677422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2457677422
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1744452983
Short name T679
Test name
Test status
Simulation time 289028493 ps
CPU time 13.84 seconds
Started Apr 04 03:05:47 PM PDT 24
Finished Apr 04 03:06:02 PM PDT 24
Peak memory 259180 kb
Host smart-92477c88-969f-46f4-a126-b65cd3adc9cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744452983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1744452983
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.4193566298
Short name T59
Test name
Test status
Simulation time 3966319712 ps
CPU time 149.22 seconds
Started Apr 04 03:05:44 PM PDT 24
Finished Apr 04 03:08:14 PM PDT 24
Peak memory 717732 kb
Host smart-7b339c88-289a-4888-9dc3-7814e25a21c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193566298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.4193566298
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2265057699
Short name T316
Test name
Test status
Simulation time 1685414642 ps
CPU time 44.46 seconds
Started Apr 04 03:05:44 PM PDT 24
Finished Apr 04 03:06:29 PM PDT 24
Peak memory 546372 kb
Host smart-c93a7fcc-093d-4bf2-b784-7d38ec81e362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265057699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2265057699
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1492537719
Short name T1119
Test name
Test status
Simulation time 106802690 ps
CPU time 0.99 seconds
Started Apr 04 03:05:48 PM PDT 24
Finished Apr 04 03:05:50 PM PDT 24
Peak memory 203668 kb
Host smart-79f4ce31-8c0f-4c4b-a295-73369b776584
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492537719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1492537719
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.568876899
Short name T53
Test name
Test status
Simulation time 196608228 ps
CPU time 9.59 seconds
Started Apr 04 03:05:44 PM PDT 24
Finished Apr 04 03:05:54 PM PDT 24
Peak memory 203728 kb
Host smart-e71d6c89-b22e-4523-bf9a-adfe599cb979
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568876899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
568876899
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1435076100
Short name T325
Test name
Test status
Simulation time 12541693045 ps
CPU time 99.71 seconds
Started Apr 04 03:05:49 PM PDT 24
Finished Apr 04 03:07:29 PM PDT 24
Peak memory 1013916 kb
Host smart-a91c8863-a8b6-4a90-8cdf-f9ce138d0ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435076100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1435076100
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3619485717
Short name T213
Test name
Test status
Simulation time 2199574155 ps
CPU time 6.06 seconds
Started Apr 04 03:05:45 PM PDT 24
Finished Apr 04 03:05:51 PM PDT 24
Peak memory 203796 kb
Host smart-b71429f9-036b-446e-a6c7-832c7b44f1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619485717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3619485717
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3918925340
Short name T432
Test name
Test status
Simulation time 5713788301 ps
CPU time 26.81 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:06:13 PM PDT 24
Peak memory 343900 kb
Host smart-d360bd04-4166-4745-bc3b-2f0f92f47951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918925340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3918925340
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3565469979
Short name T930
Test name
Test status
Simulation time 26272759 ps
CPU time 0.72 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:05:35 PM PDT 24
Peak memory 203484 kb
Host smart-14389bb7-71a9-41bf-b01f-4b6ee8ac7edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565469979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3565469979
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1193464529
Short name T27
Test name
Test status
Simulation time 7293337579 ps
CPU time 55.56 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:06:42 PM PDT 24
Peak memory 635284 kb
Host smart-9de508cb-b75a-4f0e-bb23-626e3adcceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193464529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1193464529
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3628900134
Short name T841
Test name
Test status
Simulation time 880014704 ps
CPU time 16.39 seconds
Started Apr 04 03:05:34 PM PDT 24
Finished Apr 04 03:05:50 PM PDT 24
Peak memory 260604 kb
Host smart-c0c9f7df-1589-4df6-a4e8-524d160d8b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628900134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3628900134
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.4223045016
Short name T161
Test name
Test status
Simulation time 76366924507 ps
CPU time 3066.53 seconds
Started Apr 04 03:05:43 PM PDT 24
Finished Apr 04 03:56:50 PM PDT 24
Peak memory 3478824 kb
Host smart-2f8ee462-efbe-4c78-8bb2-86cf9ec381d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223045016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.4223045016
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.4237001603
Short name T989
Test name
Test status
Simulation time 1111116820 ps
CPU time 3.84 seconds
Started Apr 04 03:05:45 PM PDT 24
Finished Apr 04 03:05:50 PM PDT 24
Peak memory 203724 kb
Host smart-673f1696-f5d9-4499-a5b0-bdb5c17638ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237001603 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.4237001603
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2291255846
Short name T55
Test name
Test status
Simulation time 10089914058 ps
CPU time 86.48 seconds
Started Apr 04 03:05:45 PM PDT 24
Finished Apr 04 03:07:12 PM PDT 24
Peak memory 591364 kb
Host smart-79244352-3cca-4d9a-a33e-d2849ca01bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291255846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2291255846
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2104309573
Short name T549
Test name
Test status
Simulation time 10248482751 ps
CPU time 20.28 seconds
Started Apr 04 03:05:50 PM PDT 24
Finished Apr 04 03:06:11 PM PDT 24
Peak memory 396184 kb
Host smart-4f2bfcf0-fffc-4f2d-9814-b98da82d9d09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104309573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2104309573
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.4171584761
Short name T650
Test name
Test status
Simulation time 382198810 ps
CPU time 2.33 seconds
Started Apr 04 03:05:44 PM PDT 24
Finished Apr 04 03:05:46 PM PDT 24
Peak memory 203696 kb
Host smart-672a72b5-a90f-44ec-8c87-fc9211ce4d32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171584761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.4171584761
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.3334203885
Short name T970
Test name
Test status
Simulation time 4129330526 ps
CPU time 4.86 seconds
Started Apr 04 03:05:52 PM PDT 24
Finished Apr 04 03:05:57 PM PDT 24
Peak memory 203820 kb
Host smart-9e004ca8-0cc0-436b-83ca-4b712e54be16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334203885 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.3334203885
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2477431867
Short name T671
Test name
Test status
Simulation time 3167090048 ps
CPU time 8.02 seconds
Started Apr 04 03:05:44 PM PDT 24
Finished Apr 04 03:05:52 PM PDT 24
Peak memory 203864 kb
Host smart-e918acb3-9272-46c8-9d0c-a15132d76789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477431867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2477431867
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2998588860
Short name T537
Test name
Test status
Simulation time 337864173 ps
CPU time 13.58 seconds
Started Apr 04 03:05:45 PM PDT 24
Finished Apr 04 03:05:59 PM PDT 24
Peak memory 203764 kb
Host smart-4ed056cf-d379-4449-b6b0-9c4178b895e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998588860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2998588860
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1584726665
Short name T1058
Test name
Test status
Simulation time 6869665838 ps
CPU time 552.06 seconds
Started Apr 04 03:05:45 PM PDT 24
Finished Apr 04 03:14:57 PM PDT 24
Peak memory 1786620 kb
Host smart-c92d7091-0e04-42f4-8ddb-8965281319fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584726665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1584726665
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1510679987
Short name T807
Test name
Test status
Simulation time 1360961575 ps
CPU time 7.51 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:05:54 PM PDT 24
Peak memory 213652 kb
Host smart-dd766db3-cd46-46d3-8a68-557ebe670719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510679987 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1510679987
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3220715854
Short name T88
Test name
Test status
Simulation time 27930141 ps
CPU time 0.67 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:06:03 PM PDT 24
Peak memory 203572 kb
Host smart-fd7b2df4-206b-4966-a1a7-ba25cd1b40bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220715854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3220715854
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2835657510
Short name T735
Test name
Test status
Simulation time 218493056 ps
CPU time 1.75 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:05:48 PM PDT 24
Peak memory 211972 kb
Host smart-8c6d9ec7-2bd5-43c6-b0e4-dcbb333876d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835657510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2835657510
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2773687528
Short name T664
Test name
Test status
Simulation time 762114605 ps
CPU time 3.52 seconds
Started Apr 04 03:05:47 PM PDT 24
Finished Apr 04 03:05:51 PM PDT 24
Peak memory 238468 kb
Host smart-e70aaece-ef28-4770-a9c9-3028a1efa1b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773687528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2773687528
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2301930700
Short name T991
Test name
Test status
Simulation time 2122281282 ps
CPU time 145.99 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:08:13 PM PDT 24
Peak memory 648564 kb
Host smart-faffbf07-3d81-47a9-9913-8bc518003d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301930700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2301930700
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1203208943
Short name T715
Test name
Test status
Simulation time 1222638782 ps
CPU time 36.3 seconds
Started Apr 04 03:05:47 PM PDT 24
Finished Apr 04 03:06:23 PM PDT 24
Peak memory 491864 kb
Host smart-2757ad01-724f-4a39-aa5b-af497700bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203208943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1203208943
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1341612394
Short name T324
Test name
Test status
Simulation time 247050240 ps
CPU time 3.19 seconds
Started Apr 04 03:05:47 PM PDT 24
Finished Apr 04 03:05:51 PM PDT 24
Peak memory 223572 kb
Host smart-37769460-0c2d-452c-90a3-251b421ca6f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341612394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1341612394
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3047919965
Short name T149
Test name
Test status
Simulation time 66199858138 ps
CPU time 129.32 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:07:56 PM PDT 24
Peak memory 1326132 kb
Host smart-6e48cca3-81af-402c-a019-04643f02b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047919965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3047919965
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3514053700
Short name T212
Test name
Test status
Simulation time 390841086 ps
CPU time 5.09 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:07 PM PDT 24
Peak memory 203724 kb
Host smart-a0d33366-7d8f-4151-85f5-0408721da19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514053700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3514053700
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3600174436
Short name T104
Test name
Test status
Simulation time 1645887721 ps
CPU time 41.48 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:46 PM PDT 24
Peak memory 332004 kb
Host smart-cfb936fd-4a04-4e91-9bac-5580dbd11350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600174436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3600174436
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.3631127255
Short name T752
Test name
Test status
Simulation time 30784002 ps
CPU time 0.69 seconds
Started Apr 04 03:05:48 PM PDT 24
Finished Apr 04 03:05:49 PM PDT 24
Peak memory 203480 kb
Host smart-a3674324-5d71-4c23-8d29-ba371d996677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631127255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3631127255
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.2482852845
Short name T837
Test name
Test status
Simulation time 2869013598 ps
CPU time 67.28 seconds
Started Apr 04 03:05:47 PM PDT 24
Finished Apr 04 03:06:55 PM PDT 24
Peak memory 213912 kb
Host smart-c6323103-7fc9-46dc-960d-cb9add36fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482852845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2482852845
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.477140098
Short name T545
Test name
Test status
Simulation time 1457690452 ps
CPU time 27.6 seconds
Started Apr 04 03:05:50 PM PDT 24
Finished Apr 04 03:06:17 PM PDT 24
Peak memory 380964 kb
Host smart-3ae36d61-63db-4f08-9e75-963cbafa8fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477140098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.477140098
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.834114535
Short name T234
Test name
Test status
Simulation time 48296297941 ps
CPU time 516.21 seconds
Started Apr 04 03:05:46 PM PDT 24
Finished Apr 04 03:14:23 PM PDT 24
Peak memory 2049848 kb
Host smart-dec84b34-d9ee-4caa-8916-6fd62892acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834114535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.834114535
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2350976968
Short name T918
Test name
Test status
Simulation time 885586839 ps
CPU time 4.65 seconds
Started Apr 04 03:05:51 PM PDT 24
Finished Apr 04 03:05:56 PM PDT 24
Peak memory 203804 kb
Host smart-6469553a-86c3-4a76-a50e-8e8b2e5e5398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350976968 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2350976968
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2877441361
Short name T246
Test name
Test status
Simulation time 10104697842 ps
CPU time 17.21 seconds
Started Apr 04 03:05:49 PM PDT 24
Finished Apr 04 03:06:07 PM PDT 24
Peak memory 322172 kb
Host smart-6b487314-e850-43d6-9531-2776303a84b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877441361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2877441361
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1479807182
Short name T696
Test name
Test status
Simulation time 10084466256 ps
CPU time 86.14 seconds
Started Apr 04 03:05:50 PM PDT 24
Finished Apr 04 03:07:16 PM PDT 24
Peak memory 717620 kb
Host smart-0d4688c7-36e6-4c6c-a87b-27135fcce2b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479807182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1479807182
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2763222429
Short name T8
Test name
Test status
Simulation time 1181972701 ps
CPU time 2.45 seconds
Started Apr 04 03:05:48 PM PDT 24
Finished Apr 04 03:05:52 PM PDT 24
Peak memory 203704 kb
Host smart-85697366-2ece-470c-ad17-4d3840e32667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763222429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2763222429
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.273489217
Short name T1102
Test name
Test status
Simulation time 623498105 ps
CPU time 3.16 seconds
Started Apr 04 03:05:52 PM PDT 24
Finished Apr 04 03:05:55 PM PDT 24
Peak memory 203764 kb
Host smart-c1b7d192-f107-4e31-9458-ac41db622af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273489217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_intr_smoke.273489217
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.970892081
Short name T102
Test name
Test status
Simulation time 4279181643 ps
CPU time 31.74 seconds
Started Apr 04 03:05:47 PM PDT 24
Finished Apr 04 03:06:20 PM PDT 24
Peak memory 203840 kb
Host smart-d12e3535-59a1-4a8f-a628-77bccf4e0679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970892081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.970892081
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.1968999877
Short name T628
Test name
Test status
Simulation time 718390040 ps
CPU time 6.45 seconds
Started Apr 04 03:05:47 PM PDT 24
Finished Apr 04 03:05:55 PM PDT 24
Peak memory 203584 kb
Host smart-243ed210-f003-40d7-b002-f798eddad614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968999877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.1968999877
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1110087264
Short name T266
Test name
Test status
Simulation time 11904127970 ps
CPU time 171.34 seconds
Started Apr 04 03:05:50 PM PDT 24
Finished Apr 04 03:08:42 PM PDT 24
Peak memory 798932 kb
Host smart-9702d780-f164-408c-b24a-99ca4a9cc628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110087264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1110087264
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1197062391
Short name T566
Test name
Test status
Simulation time 1481100658 ps
CPU time 6.71 seconds
Started Apr 04 03:05:48 PM PDT 24
Finished Apr 04 03:05:56 PM PDT 24
Peak memory 210012 kb
Host smart-04c33146-c2aa-499c-9218-ed6a9ab3333d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197062391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1197062391
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3197312604
Short name T1046
Test name
Test status
Simulation time 15685435 ps
CPU time 0.61 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:06:03 PM PDT 24
Peak memory 203516 kb
Host smart-2ee6bace-5cef-4cdd-af28-4e269a6e3643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197312604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3197312604
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3359715869
Short name T1096
Test name
Test status
Simulation time 64360104 ps
CPU time 1.34 seconds
Started Apr 04 03:05:58 PM PDT 24
Finished Apr 04 03:06:00 PM PDT 24
Peak memory 211904 kb
Host smart-ce4e5f2c-c5c9-43ce-aa73-1466f5737238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359715869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3359715869
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2488018810
Short name T541
Test name
Test status
Simulation time 828959898 ps
CPU time 5.2 seconds
Started Apr 04 03:05:58 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 259116 kb
Host smart-5e8e850c-b774-4328-899c-28ead26ab0aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488018810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2488018810
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.712056408
Short name T641
Test name
Test status
Simulation time 3132612642 ps
CPU time 102.56 seconds
Started Apr 04 03:06:00 PM PDT 24
Finished Apr 04 03:07:42 PM PDT 24
Peak memory 567920 kb
Host smart-a071f846-4efc-4e59-a7be-566336441ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712056408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.712056408
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1042465258
Short name T634
Test name
Test status
Simulation time 7771530546 ps
CPU time 54.62 seconds
Started Apr 04 03:05:58 PM PDT 24
Finished Apr 04 03:06:52 PM PDT 24
Peak memory 643760 kb
Host smart-2a2b18b3-ef03-4dec-9835-db45404ec2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042465258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1042465258
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.571225172
Short name T37
Test name
Test status
Simulation time 419674915 ps
CPU time 1.02 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:06 PM PDT 24
Peak memory 203772 kb
Host smart-75b8aea3-b2bd-4a87-8140-581a2dbd4180
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571225172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.571225172
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1363219127
Short name T704
Test name
Test status
Simulation time 110319393 ps
CPU time 6.09 seconds
Started Apr 04 03:06:00 PM PDT 24
Finished Apr 04 03:06:07 PM PDT 24
Peak memory 220060 kb
Host smart-a19fad63-a9de-42d7-bd50-8df07ca4d5d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363219127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1363219127
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.357551629
Short name T652
Test name
Test status
Simulation time 11196223150 ps
CPU time 90.05 seconds
Started Apr 04 03:06:00 PM PDT 24
Finished Apr 04 03:07:30 PM PDT 24
Peak memory 982560 kb
Host smart-50cd3ead-425f-4984-8519-51abaa261a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357551629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.357551629
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.4073354657
Short name T876
Test name
Test status
Simulation time 198937485 ps
CPU time 3.27 seconds
Started Apr 04 03:06:07 PM PDT 24
Finished Apr 04 03:06:10 PM PDT 24
Peak memory 203776 kb
Host smart-5c4360f4-1399-4bb6-a7cf-271786496dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073354657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.4073354657
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.4149451559
Short name T362
Test name
Test status
Simulation time 10459151960 ps
CPU time 61.15 seconds
Started Apr 04 03:06:00 PM PDT 24
Finished Apr 04 03:07:02 PM PDT 24
Peak memory 542488 kb
Host smart-fe905277-4c82-4d2d-b161-023edd4cfb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149451559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.4149451559
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3635328550
Short name T347
Test name
Test status
Simulation time 26892501 ps
CPU time 0.68 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:06:03 PM PDT 24
Peak memory 203544 kb
Host smart-823dbad5-107f-4c9e-86c9-bacab30aaa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635328550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3635328550
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2853308146
Short name T1199
Test name
Test status
Simulation time 2807631205 ps
CPU time 199 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:09:23 PM PDT 24
Peak memory 772296 kb
Host smart-a2daaed6-d7a3-43cd-b251-b638aea4f46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853308146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2853308146
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1409472955
Short name T823
Test name
Test status
Simulation time 4098721661 ps
CPU time 62.06 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:07:04 PM PDT 24
Peak memory 361332 kb
Host smart-e2bca4f5-d24d-42eb-9a04-bb04ca4426c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409472955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1409472955
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.4141354379
Short name T471
Test name
Test status
Simulation time 847024025 ps
CPU time 4.09 seconds
Started Apr 04 03:06:00 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 203736 kb
Host smart-29f58258-6e0b-4aee-afca-560fc6eb9349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141354379 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.4141354379
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.53130821
Short name T540
Test name
Test status
Simulation time 10532894019 ps
CPU time 5.75 seconds
Started Apr 04 03:05:58 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 240268 kb
Host smart-7e7cb020-95d9-40b1-89ef-95ca3ae0d628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53130821 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_acq.53130821
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.384108621
Short name T824
Test name
Test status
Simulation time 10553177316 ps
CPU time 19.08 seconds
Started Apr 04 03:06:05 PM PDT 24
Finished Apr 04 03:06:24 PM PDT 24
Peak memory 340856 kb
Host smart-58444768-d670-4c74-95cd-d84d7d6f374b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384108621 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_tx.384108621
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3841871311
Short name T727
Test name
Test status
Simulation time 387152957 ps
CPU time 2.38 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:06 PM PDT 24
Peak memory 203724 kb
Host smart-434e3b23-566d-43a8-afd6-1c65f63bb299
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841871311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3841871311
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2479824213
Short name T268
Test name
Test status
Simulation time 2755343911 ps
CPU time 3.81 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:06 PM PDT 24
Peak memory 203728 kb
Host smart-0f517be9-867b-40b1-abff-28ec4cfeb0c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479824213 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2479824213
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3104843201
Short name T273
Test name
Test status
Simulation time 3944085640 ps
CPU time 32.1 seconds
Started Apr 04 03:06:06 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 203884 kb
Host smart-e94e5ef1-7be3-47fd-82cf-0015a6831f78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104843201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3104843201
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1055470642
Short name T743
Test name
Test status
Simulation time 2369384218 ps
CPU time 12.24 seconds
Started Apr 04 03:06:03 PM PDT 24
Finished Apr 04 03:06:16 PM PDT 24
Peak memory 206132 kb
Host smart-1a5eabb2-f354-44bf-8885-cc8236c39f1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055470642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1055470642
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1314532975
Short name T457
Test name
Test status
Simulation time 1296010719 ps
CPU time 6.55 seconds
Started Apr 04 03:06:05 PM PDT 24
Finished Apr 04 03:06:12 PM PDT 24
Peak memory 203792 kb
Host smart-0d8d4844-8e6b-4ec0-b96e-ef931ef44d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314532975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1314532975
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.2728017451
Short name T956
Test name
Test status
Simulation time 611011169 ps
CPU time 4.21 seconds
Started Apr 04 03:05:58 PM PDT 24
Finished Apr 04 03:06:03 PM PDT 24
Peak memory 203692 kb
Host smart-5ebf3117-1a13-405f-b39b-34a2b80c802c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728017451 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.2728017451
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.4137443193
Short name T645
Test name
Test status
Simulation time 36894577 ps
CPU time 0.61 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 203540 kb
Host smart-76d61ddd-ff77-4255-bce8-14eb6c186874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137443193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.4137443193
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.862595409
Short name T796
Test name
Test status
Simulation time 47451456 ps
CPU time 1.37 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 211952 kb
Host smart-96442204-14c7-4256-a67e-c676d1633d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862595409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.862595409
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2641225470
Short name T668
Test name
Test status
Simulation time 503702838 ps
CPU time 5.68 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:07 PM PDT 24
Peak memory 255440 kb
Host smart-c8c68a2f-6fcf-4dc1-9db7-e9e8069a26e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641225470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2641225470
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1169574695
Short name T1026
Test name
Test status
Simulation time 6841942142 ps
CPU time 115.98 seconds
Started Apr 04 03:06:03 PM PDT 24
Finished Apr 04 03:07:59 PM PDT 24
Peak memory 590432 kb
Host smart-c7396d57-2212-41c5-8ecb-5945a9466c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169574695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1169574695
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3272676448
Short name T1145
Test name
Test status
Simulation time 6559975270 ps
CPU time 48.45 seconds
Started Apr 04 03:06:07 PM PDT 24
Finished Apr 04 03:06:55 PM PDT 24
Peak memory 596736 kb
Host smart-2a11eca8-dd0e-419d-b7fd-9f8f1605aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272676448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3272676448
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.470985698
Short name T619
Test name
Test status
Simulation time 2141549088 ps
CPU time 1.08 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:02 PM PDT 24
Peak memory 203732 kb
Host smart-d4299840-4a70-4843-8772-3388f5a6da32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470985698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.470985698
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1779439760
Short name T74
Test name
Test status
Simulation time 455882731 ps
CPU time 6.85 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:08 PM PDT 24
Peak memory 222488 kb
Host smart-6175d3e4-3d30-4213-a026-11ff9a233c88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779439760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1779439760
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3952089359
Short name T1008
Test name
Test status
Simulation time 4410479586 ps
CPU time 137.56 seconds
Started Apr 04 03:06:07 PM PDT 24
Finished Apr 04 03:08:25 PM PDT 24
Peak memory 720136 kb
Host smart-7137a3c5-ef76-4433-9615-07c3d6068601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952089359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3952089359
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.348432796
Short name T419
Test name
Test status
Simulation time 177366521 ps
CPU time 6.72 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:11 PM PDT 24
Peak memory 203084 kb
Host smart-c07c169c-d954-47af-925c-90f32cada613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348432796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.348432796
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_override.843489258
Short name T170
Test name
Test status
Simulation time 37931302 ps
CPU time 0.63 seconds
Started Apr 04 03:06:06 PM PDT 24
Finished Apr 04 03:06:06 PM PDT 24
Peak memory 203344 kb
Host smart-201ca8b7-8d84-46d5-8943-67d8ce29e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843489258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.843489258
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3022579348
Short name T987
Test name
Test status
Simulation time 9045994503 ps
CPU time 14.48 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:16 PM PDT 24
Peak memory 286796 kb
Host smart-927bb44a-c56a-453e-b7df-705d05b05e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022579348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3022579348
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.1851395731
Short name T1069
Test name
Test status
Simulation time 39701189470 ps
CPU time 490.86 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:14:13 PM PDT 24
Peak memory 2281416 kb
Host smart-01dc05a6-8917-4533-ae76-b2f207f7b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851395731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.1851395731
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2219084759
Short name T638
Test name
Test status
Simulation time 3168392041 ps
CPU time 3.88 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:06 PM PDT 24
Peak memory 203808 kb
Host smart-18e052e4-cfea-4b9f-9210-6464ff630488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219084759 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2219084759
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.852713362
Short name T921
Test name
Test status
Simulation time 10134896085 ps
CPU time 29.93 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:35 PM PDT 24
Peak memory 377416 kb
Host smart-04d02423-0068-4b80-b3eb-e8713072f0a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852713362 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.852713362
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2584296453
Short name T780
Test name
Test status
Simulation time 10052332404 ps
CPU time 107.3 seconds
Started Apr 04 03:06:06 PM PDT 24
Finished Apr 04 03:07:54 PM PDT 24
Peak memory 752108 kb
Host smart-11c446af-0c4a-434f-a5bf-1cda1b12e1bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584296453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2584296453
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.166943745
Short name T215
Test name
Test status
Simulation time 6417241584 ps
CPU time 3.11 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:06:05 PM PDT 24
Peak memory 203716 kb
Host smart-29f83ab6-9270-4541-a532-e6f6362cb0d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166943745 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.i2c_target_hrst.166943745
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.462087551
Short name T665
Test name
Test status
Simulation time 2429959826 ps
CPU time 6.09 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:07 PM PDT 24
Peak memory 218624 kb
Host smart-7391faee-9a04-418a-944a-107bc51475a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462087551 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.462087551
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1412986763
Short name T385
Test name
Test status
Simulation time 682691009 ps
CPU time 24.53 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:06:26 PM PDT 24
Peak memory 203676 kb
Host smart-b0b7d61e-ed64-472b-9087-2f64f2e69972
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412986763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1412986763
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.2177471824
Short name T278
Test name
Test status
Simulation time 1667546417 ps
CPU time 11.4 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:06:14 PM PDT 24
Peak memory 209928 kb
Host smart-9fe9b5a6-f484-442a-9e8f-4c6d02e9d996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177471824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.2177471824
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1010759063
Short name T880
Test name
Test status
Simulation time 36775261203 ps
CPU time 76.33 seconds
Started Apr 04 03:06:00 PM PDT 24
Finished Apr 04 03:07:16 PM PDT 24
Peak memory 746648 kb
Host smart-5fda9e15-8f75-4f13-a615-a82094c406d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010759063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1010759063
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2517831156
Short name T1178
Test name
Test status
Simulation time 4364057334 ps
CPU time 6.33 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:06:09 PM PDT 24
Peak memory 220064 kb
Host smart-8bf60713-30a1-4f8f-82e3-2408aac2668f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517831156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2517831156
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.475275149
Short name T694
Test name
Test status
Simulation time 84728473 ps
CPU time 0.67 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:17 PM PDT 24
Peak memory 203536 kb
Host smart-0c097538-5bd0-495a-b7aa-dc8cda970bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475275149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.475275149
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1502172973
Short name T460
Test name
Test status
Simulation time 144884222 ps
CPU time 1.79 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:06 PM PDT 24
Peak memory 211892 kb
Host smart-b680897f-30f5-4b61-ae49-a045f19e0074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502172973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1502172973
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2459524856
Short name T1134
Test name
Test status
Simulation time 741971195 ps
CPU time 19.46 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:06:24 PM PDT 24
Peak memory 283916 kb
Host smart-7019470d-1652-46ea-9fa5-546763b75e17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459524856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.2459524856
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.4280493803
Short name T648
Test name
Test status
Simulation time 1896523235 ps
CPU time 58 seconds
Started Apr 04 03:06:02 PM PDT 24
Finished Apr 04 03:07:00 PM PDT 24
Peak memory 659064 kb
Host smart-3c5ef3d5-7d18-4166-8da8-a8b8953fbcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280493803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.4280493803
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1443829736
Short name T853
Test name
Test status
Simulation time 1132159997 ps
CPU time 76.29 seconds
Started Apr 04 03:06:06 PM PDT 24
Finished Apr 04 03:07:22 PM PDT 24
Peak memory 479132 kb
Host smart-302dd3da-f926-479a-b7ae-64cd59837ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443829736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1443829736
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2769348844
Short name T1014
Test name
Test status
Simulation time 427331180 ps
CPU time 0.99 seconds
Started Apr 04 03:06:07 PM PDT 24
Finished Apr 04 03:06:08 PM PDT 24
Peak memory 203596 kb
Host smart-fd534e2f-e8bf-4860-ba35-5654cf3d9ee6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769348844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2769348844
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.78940519
Short name T908
Test name
Test status
Simulation time 709068742 ps
CPU time 9.17 seconds
Started Apr 04 03:05:57 PM PDT 24
Finished Apr 04 03:06:06 PM PDT 24
Peak memory 234472 kb
Host smart-d2a89373-95b6-4c8c-8754-46a73e14edd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78940519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.78940519
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2641854658
Short name T100
Test name
Test status
Simulation time 17208951257 ps
CPU time 218.3 seconds
Started Apr 04 03:06:04 PM PDT 24
Finished Apr 04 03:09:43 PM PDT 24
Peak memory 931104 kb
Host smart-7608ea6d-ba4c-4e22-939e-3b442647e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641854658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2641854658
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.795806700
Short name T1155
Test name
Test status
Simulation time 301589775 ps
CPU time 11.99 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:29 PM PDT 24
Peak memory 203596 kb
Host smart-2f234bcb-c74e-4ef4-b9fc-39d9e01bbe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795806700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.795806700
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1950502627
Short name T1009
Test name
Test status
Simulation time 1024998421 ps
CPU time 24.05 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:06:44 PM PDT 24
Peak memory 371696 kb
Host smart-f1e7ae70-bb18-4383-b68e-61f14f1c2d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950502627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1950502627
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.244289409
Short name T199
Test name
Test status
Simulation time 35155030 ps
CPU time 0.65 seconds
Started Apr 04 03:06:03 PM PDT 24
Finished Apr 04 03:06:04 PM PDT 24
Peak memory 203536 kb
Host smart-19489ac8-6aba-4133-951e-8f2967a85ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244289409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.244289409
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3247913530
Short name T43
Test name
Test status
Simulation time 27385703729 ps
CPU time 342.27 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:11:44 PM PDT 24
Peak memory 384340 kb
Host smart-90267c44-29a3-485c-a8cb-43eb75e0858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247913530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3247913530
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3821024785
Short name T945
Test name
Test status
Simulation time 4086571749 ps
CPU time 96.26 seconds
Started Apr 04 03:06:01 PM PDT 24
Finished Apr 04 03:07:37 PM PDT 24
Peak memory 483996 kb
Host smart-2bacc674-e14c-48eb-b45b-c7a78863fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821024785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3821024785
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1085420172
Short name T509
Test name
Test status
Simulation time 1712406486 ps
CPU time 4.27 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:20 PM PDT 24
Peak memory 211876 kb
Host smart-8758f385-c1c5-4205-ba5a-2e2c354039e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085420172 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1085420172
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1062463926
Short name T985
Test name
Test status
Simulation time 10118262452 ps
CPU time 30.41 seconds
Started Apr 04 03:06:13 PM PDT 24
Finished Apr 04 03:06:44 PM PDT 24
Peak memory 369952 kb
Host smart-1c420a25-8dda-4405-877f-a7dbfc6b084b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062463926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1062463926
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1504293534
Short name T749
Test name
Test status
Simulation time 10516496164 ps
CPU time 7.72 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:06:25 PM PDT 24
Peak memory 261344 kb
Host smart-026dd051-ba9b-4607-ad86-a200a68bf497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504293534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1504293534
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1211587277
Short name T444
Test name
Test status
Simulation time 842938790 ps
CPU time 2.66 seconds
Started Apr 04 03:06:18 PM PDT 24
Finished Apr 04 03:06:20 PM PDT 24
Peak memory 203596 kb
Host smart-5b66753a-c1dd-4652-b3dd-08c297343ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211587277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1211587277
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.202529165
Short name T649
Test name
Test status
Simulation time 1378256408 ps
CPU time 6.84 seconds
Started Apr 04 03:06:13 PM PDT 24
Finished Apr 04 03:06:20 PM PDT 24
Peak memory 203756 kb
Host smart-b845c64f-194a-4b07-b083-4f82d42a1809
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202529165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.202529165
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1796341713
Short name T605
Test name
Test status
Simulation time 5839021580 ps
CPU time 2.17 seconds
Started Apr 04 03:06:15 PM PDT 24
Finished Apr 04 03:06:17 PM PDT 24
Peak memory 203724 kb
Host smart-d9d9dce8-49d2-43f8-bd9e-5a251a56029c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796341713 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1796341713
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1529740891
Short name T1182
Test name
Test status
Simulation time 1640735155 ps
CPU time 19.94 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 203736 kb
Host smart-acd7769f-5d3e-4e68-9b76-070296c5df74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529740891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1529740891
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2481758134
Short name T951
Test name
Test status
Simulation time 2737727371 ps
CPU time 23.62 seconds
Started Apr 04 03:06:18 PM PDT 24
Finished Apr 04 03:06:43 PM PDT 24
Peak memory 217900 kb
Host smart-6b609223-e205-4c52-a45d-3d502778f8d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481758134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2481758134
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.372521441
Short name T901
Test name
Test status
Simulation time 25378686186 ps
CPU time 495.04 seconds
Started Apr 04 03:06:14 PM PDT 24
Finished Apr 04 03:14:29 PM PDT 24
Peak memory 1529308 kb
Host smart-78381449-171c-4c66-9067-c48fa6cdce19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372521441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.372521441
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2922321339
Short name T633
Test name
Test status
Simulation time 2394695415 ps
CPU time 7.2 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:06:25 PM PDT 24
Peak memory 219928 kb
Host smart-1998a100-2a3d-46b1-8927-bec1747ad2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922321339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2922321339
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2627689121
Short name T298
Test name
Test status
Simulation time 21686749 ps
CPU time 0.64 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:17 PM PDT 24
Peak memory 203428 kb
Host smart-681de484-83f7-43a2-88fd-92ae784b50c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627689121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2627689121
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1474800456
Short name T1056
Test name
Test status
Simulation time 161696115 ps
CPU time 1.63 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:18 PM PDT 24
Peak memory 211952 kb
Host smart-dc6f45d6-2071-434d-976a-a29e304205c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474800456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1474800456
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3359032175
Short name T482
Test name
Test status
Simulation time 209694312 ps
CPU time 9.71 seconds
Started Apr 04 03:06:18 PM PDT 24
Finished Apr 04 03:06:29 PM PDT 24
Peak memory 209648 kb
Host smart-8b91b83f-c441-4c78-9c0f-187f0baece4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359032175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3359032175
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.966237272
Short name T389
Test name
Test status
Simulation time 1477646160 ps
CPU time 34.47 seconds
Started Apr 04 03:06:15 PM PDT 24
Finished Apr 04 03:06:50 PM PDT 24
Peak memory 270300 kb
Host smart-e33a8542-2e8f-4954-a160-7c00524e50c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966237272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.966237272
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1280053542
Short name T1180
Test name
Test status
Simulation time 7142112686 ps
CPU time 130.52 seconds
Started Apr 04 03:06:14 PM PDT 24
Finished Apr 04 03:08:24 PM PDT 24
Peak memory 647016 kb
Host smart-3a25b3c6-cc56-456c-ae09-66fb1b469184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280053542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1280053542
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3155828057
Short name T999
Test name
Test status
Simulation time 1029761590 ps
CPU time 1.13 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:18 PM PDT 24
Peak memory 203740 kb
Host smart-e26e6068-09df-4f3a-80ca-50c6c786b7e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155828057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3155828057
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2953394037
Short name T933
Test name
Test status
Simulation time 443204092 ps
CPU time 7.38 seconds
Started Apr 04 03:06:24 PM PDT 24
Finished Apr 04 03:06:31 PM PDT 24
Peak memory 225196 kb
Host smart-c417af6a-3c98-493c-a152-8c22df2e1ab5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953394037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2953394037
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1924543991
Short name T152
Test name
Test status
Simulation time 12726757037 ps
CPU time 71.69 seconds
Started Apr 04 03:06:24 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 962540 kb
Host smart-1f1164fa-4b65-418f-950f-c1b43aace877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924543991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1924543991
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1498479175
Short name T1132
Test name
Test status
Simulation time 5062348462 ps
CPU time 17.05 seconds
Started Apr 04 03:06:20 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 203820 kb
Host smart-d1224553-761b-4a80-a5fe-08875612e85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498479175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1498479175
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.3138007289
Short name T164
Test name
Test status
Simulation time 63692474 ps
CPU time 0.67 seconds
Started Apr 04 03:06:18 PM PDT 24
Finished Apr 04 03:06:19 PM PDT 24
Peak memory 203536 kb
Host smart-42228574-c5e2-42ec-b5d8-6794cc85a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138007289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3138007289
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.926037450
Short name T608
Test name
Test status
Simulation time 13609811146 ps
CPU time 59.6 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:07:17 PM PDT 24
Peak memory 520120 kb
Host smart-110e535f-077a-4295-88e5-bfa83e874c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926037450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.926037450
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2590041221
Short name T863
Test name
Test status
Simulation time 6733179962 ps
CPU time 64.22 seconds
Started Apr 04 03:06:15 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 377748 kb
Host smart-2a3e8057-67d8-4184-9877-c73616273671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590041221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2590041221
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.4114306627
Short name T67
Test name
Test status
Simulation time 10073429700 ps
CPU time 67.2 seconds
Started Apr 04 03:06:20 PM PDT 24
Finished Apr 04 03:07:28 PM PDT 24
Peak memory 574776 kb
Host smart-88ac4943-5d58-4cc3-aa1c-870c0a2781a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114306627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.4114306627
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.402540367
Short name T186
Test name
Test status
Simulation time 10505455688 ps
CPU time 8.84 seconds
Started Apr 04 03:06:18 PM PDT 24
Finished Apr 04 03:06:28 PM PDT 24
Peak memory 274852 kb
Host smart-ed82f823-5ade-4d1c-bb79-5a54a3b7541d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402540367 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.402540367
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3874226851
Short name T6
Test name
Test status
Simulation time 1718829177 ps
CPU time 2.5 seconds
Started Apr 04 03:06:18 PM PDT 24
Finished Apr 04 03:06:22 PM PDT 24
Peak memory 203792 kb
Host smart-b848f468-bcd3-4f3a-a356-7e4f2004e506
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874226851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3874226851
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.803000990
Short name T411
Test name
Test status
Simulation time 5342107787 ps
CPU time 5.81 seconds
Started Apr 04 03:06:20 PM PDT 24
Finished Apr 04 03:06:27 PM PDT 24
Peak memory 212128 kb
Host smart-bcbbc0c6-e743-43ff-8a4c-5911985809c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803000990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.803000990
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2881882276
Short name T1060
Test name
Test status
Simulation time 944601609 ps
CPU time 13.27 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:06:33 PM PDT 24
Peak memory 203540 kb
Host smart-f6c790ef-c2af-4ae3-ac6d-c0220aaab3aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881882276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2881882276
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2965699700
Short name T382
Test name
Test status
Simulation time 1416432827 ps
CPU time 60.1 seconds
Started Apr 04 03:06:15 PM PDT 24
Finished Apr 04 03:07:16 PM PDT 24
Peak memory 204512 kb
Host smart-8d7186ef-b8c9-405b-9345-d6a920b73533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965699700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2965699700
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.3825691305
Short name T965
Test name
Test status
Simulation time 33976492100 ps
CPU time 2554.45 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:48:52 PM PDT 24
Peak memory 4052032 kb
Host smart-a48647b4-7ef4-4114-a106-07d015504b91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825691305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.3825691305
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1678048398
Short name T726
Test name
Test status
Simulation time 3654456660 ps
CPU time 6.15 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:06:25 PM PDT 24
Peak memory 212056 kb
Host smart-d8cc5ede-4455-4d2f-a80f-c37f93657cc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678048398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1678048398
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2745149670
Short name T1198
Test name
Test status
Simulation time 21850671 ps
CPU time 0.65 seconds
Started Apr 04 03:06:20 PM PDT 24
Finished Apr 04 03:06:21 PM PDT 24
Peak memory 203564 kb
Host smart-95230da9-e65f-408d-a01a-5183e07abb6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745149670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2745149670
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2213286958
Short name T365
Test name
Test status
Simulation time 51198294 ps
CPU time 1.12 seconds
Started Apr 04 03:06:22 PM PDT 24
Finished Apr 04 03:06:24 PM PDT 24
Peak memory 211924 kb
Host smart-5a118751-f7d4-4ebd-a5d8-25f6921ccc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213286958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2213286958
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.905200608
Short name T850
Test name
Test status
Simulation time 986939638 ps
CPU time 6.1 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:06:22 PM PDT 24
Peak memory 259012 kb
Host smart-746d1af8-7a17-4719-89f9-cdebd7cb1985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905200608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.905200608
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2404750716
Short name T30
Test name
Test status
Simulation time 4351342119 ps
CPU time 134.31 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:08:34 PM PDT 24
Peak memory 566184 kb
Host smart-0ae65a4f-0da9-4d38-8bdb-bf1409df84fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404750716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2404750716
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.707094790
Short name T468
Test name
Test status
Simulation time 8577260954 ps
CPU time 75.23 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 704068 kb
Host smart-8cd58316-6bcb-41cb-9e71-9d5249425670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707094790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.707094790
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.4205878392
Short name T400
Test name
Test status
Simulation time 130583581 ps
CPU time 1.03 seconds
Started Apr 04 03:06:20 PM PDT 24
Finished Apr 04 03:06:22 PM PDT 24
Peak memory 203592 kb
Host smart-1b1b3974-fad6-41d6-970a-4fc2e41d5e36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205878392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.4205878392
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3607786612
Short name T308
Test name
Test status
Simulation time 583694796 ps
CPU time 7.52 seconds
Started Apr 04 03:06:23 PM PDT 24
Finished Apr 04 03:06:31 PM PDT 24
Peak memory 203724 kb
Host smart-a1a20b6d-5853-44b1-bd3f-46be4c0d26a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607786612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3607786612
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.24565512
Short name T147
Test name
Test status
Simulation time 51114210198 ps
CPU time 60.28 seconds
Started Apr 04 03:06:23 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 838740 kb
Host smart-4d825de0-fcd0-486b-a54e-2547149a79f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24565512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.24565512
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3206798243
Short name T588
Test name
Test status
Simulation time 755512908 ps
CPU time 6.06 seconds
Started Apr 04 03:06:20 PM PDT 24
Finished Apr 04 03:06:27 PM PDT 24
Peak memory 203800 kb
Host smart-ff3470a8-95d7-4184-9d4a-95eeb9ced2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206798243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3206798243
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3434960941
Short name T806
Test name
Test status
Simulation time 6447723588 ps
CPU time 66.03 seconds
Started Apr 04 03:06:14 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 368028 kb
Host smart-b9cca555-ff27-4281-8a43-ba5ce11b9062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434960941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3434960941
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.686438772
Short name T377
Test name
Test status
Simulation time 65769732 ps
CPU time 0.65 seconds
Started Apr 04 03:06:22 PM PDT 24
Finished Apr 04 03:06:23 PM PDT 24
Peak memory 203424 kb
Host smart-1f3901ff-d6d6-4299-afa4-01a5604b1950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686438772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.686438772
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.2589025140
Short name T689
Test name
Test status
Simulation time 6230761458 ps
CPU time 82.33 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:07:39 PM PDT 24
Peak memory 203772 kb
Host smart-a6c39c2b-305b-4442-8b65-83ee620f9391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589025140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2589025140
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2388996261
Short name T393
Test name
Test status
Simulation time 8272002832 ps
CPU time 64.69 seconds
Started Apr 04 03:06:22 PM PDT 24
Finished Apr 04 03:07:26 PM PDT 24
Peak memory 359320 kb
Host smart-7e4b27be-8a7a-423c-839c-6a24668c2799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388996261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2388996261
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.743923987
Short name T868
Test name
Test status
Simulation time 3035392538 ps
CPU time 3.46 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:06:21 PM PDT 24
Peak memory 203808 kb
Host smart-20edfae8-d58e-4a25-b3f8-5a072ea6c363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743923987 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.743923987
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3785105937
Short name T560
Test name
Test status
Simulation time 10555737918 ps
CPU time 13.93 seconds
Started Apr 04 03:06:24 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 297668 kb
Host smart-ad8a3f2e-6cb8-4aff-8901-d70568e96426
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785105937 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3785105937
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2517427837
Short name T372
Test name
Test status
Simulation time 10266678745 ps
CPU time 42.04 seconds
Started Apr 04 03:06:18 PM PDT 24
Finished Apr 04 03:07:01 PM PDT 24
Peak memory 479500 kb
Host smart-ba2d4177-ed00-4682-9bf8-5f60c5922e72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517427837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2517427837
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2855802619
Short name T1093
Test name
Test status
Simulation time 9420835619 ps
CPU time 2.58 seconds
Started Apr 04 03:06:23 PM PDT 24
Finished Apr 04 03:06:26 PM PDT 24
Peak memory 203792 kb
Host smart-1baecfdb-e94a-4067-8250-0cb1a8d4766d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855802619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2855802619
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3100445059
Short name T635
Test name
Test status
Simulation time 2829183819 ps
CPU time 6.76 seconds
Started Apr 04 03:06:21 PM PDT 24
Finished Apr 04 03:06:28 PM PDT 24
Peak memory 217036 kb
Host smart-76ed6caf-3d99-495a-b86e-5b0b3ae9a1cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100445059 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3100445059
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3986127365
Short name T640
Test name
Test status
Simulation time 1104036443 ps
CPU time 14.94 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:06:34 PM PDT 24
Peak memory 203768 kb
Host smart-b7e94d2d-70e8-405b-9985-19534dcffd41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986127365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3986127365
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2480676242
Short name T597
Test name
Test status
Simulation time 3728751187 ps
CPU time 44.95 seconds
Started Apr 04 03:06:19 PM PDT 24
Finished Apr 04 03:07:05 PM PDT 24
Peak memory 203840 kb
Host smart-053083b6-3699-4a1e-9da0-ff169682918b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480676242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2480676242
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.809867334
Short name T762
Test name
Test status
Simulation time 28744584253 ps
CPU time 2436.81 seconds
Started Apr 04 03:06:16 PM PDT 24
Finished Apr 04 03:46:54 PM PDT 24
Peak memory 7152548 kb
Host smart-c27b22f6-6b9f-4197-b931-7985c6a17dd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809867334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.809867334
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1367428387
Short name T440
Test name
Test status
Simulation time 2555242400 ps
CPU time 6.7 seconds
Started Apr 04 03:06:17 PM PDT 24
Finished Apr 04 03:06:24 PM PDT 24
Peak memory 203872 kb
Host smart-9b8ae805-6f61-4c12-9092-e2ef66c7b56b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367428387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1367428387
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.1447517122
Short name T948
Test name
Test status
Simulation time 16915136 ps
CPU time 0.62 seconds
Started Apr 04 03:06:34 PM PDT 24
Finished Apr 04 03:06:35 PM PDT 24
Peak memory 203556 kb
Host smart-7ccea6c5-7af2-41c2-94b3-21fba0c50cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447517122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1447517122
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2901446042
Short name T263
Test name
Test status
Simulation time 933010683 ps
CPU time 1.64 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:06:34 PM PDT 24
Peak memory 211940 kb
Host smart-b51554d5-d921-41ed-b059-16de190ac8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901446042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2901446042
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3861066118
Short name T946
Test name
Test status
Simulation time 300943758 ps
CPU time 5.38 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 263640 kb
Host smart-a50f69a3-4c2b-4432-8091-4d478c7b0214
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861066118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3861066118
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1248935717
Short name T81
Test name
Test status
Simulation time 1712317757 ps
CPU time 57.08 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:07:29 PM PDT 24
Peak memory 604108 kb
Host smart-5287130e-3e9c-4ad4-aa00-959f391111ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248935717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1248935717
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2523489954
Short name T530
Test name
Test status
Simulation time 4921998111 ps
CPU time 81.36 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:07:54 PM PDT 24
Peak memory 496072 kb
Host smart-e5eb7ab8-8e65-4b26-acab-12d1ecb879f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523489954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2523489954
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.1479056302
Short name T1204
Test name
Test status
Simulation time 961922601 ps
CPU time 0.88 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:34 PM PDT 24
Peak memory 203620 kb
Host smart-753959c8-e0d2-4620-8d7b-56d1c181296b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479056302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.1479056302
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.76721469
Short name T981
Test name
Test status
Simulation time 125619706 ps
CPU time 3.57 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:36 PM PDT 24
Peak memory 221104 kb
Host smart-f2859ace-77ca-4cd0-aabf-2a963665dd2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76721469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.76721469
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3456824634
Short name T834
Test name
Test status
Simulation time 9605880376 ps
CPU time 136.01 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:08:50 PM PDT 24
Peak memory 1352816 kb
Host smart-6c1c12a1-c057-42b0-a46e-9291f974d683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456824634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3456824634
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2728883117
Short name T97
Test name
Test status
Simulation time 1805600696 ps
CPU time 5.94 seconds
Started Apr 04 03:06:30 PM PDT 24
Finished Apr 04 03:06:36 PM PDT 24
Peak memory 203764 kb
Host smart-b477ba3a-b34c-4517-aba1-c92a59b25754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728883117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2728883117
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.247861499
Short name T893
Test name
Test status
Simulation time 6424871521 ps
CPU time 90.6 seconds
Started Apr 04 03:06:30 PM PDT 24
Finished Apr 04 03:08:01 PM PDT 24
Peak memory 510224 kb
Host smart-d1478434-8871-4e41-9a17-e5b50974b780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247861499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.247861499
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2063586054
Short name T592
Test name
Test status
Simulation time 27061403806 ps
CPU time 354.86 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:12:28 PM PDT 24
Peak memory 203720 kb
Host smart-f202ea8d-f6a2-4304-bb5d-656b8c55347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063586054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2063586054
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.536322633
Short name T670
Test name
Test status
Simulation time 1973479135 ps
CPU time 75.84 seconds
Started Apr 04 03:06:22 PM PDT 24
Finished Apr 04 03:07:38 PM PDT 24
Peak memory 380216 kb
Host smart-fa960d01-0df6-491f-a426-9b1cd68956a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536322633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.536322633
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.793005883
Short name T624
Test name
Test status
Simulation time 575693903 ps
CPU time 2.75 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:06:34 PM PDT 24
Peak memory 203680 kb
Host smart-f7291f9d-87fb-4e9f-9e2d-c293b67ddc97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793005883 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.793005883
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1062808337
Short name T77
Test name
Test status
Simulation time 10123249441 ps
CPU time 38.8 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:07:10 PM PDT 24
Peak memory 398668 kb
Host smart-49808756-7171-4dcf-953e-277f9d2edd75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062808337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1062808337
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.3362315518
Short name T304
Test name
Test status
Simulation time 10130126577 ps
CPU time 13.33 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:47 PM PDT 24
Peak memory 325532 kb
Host smart-97887513-77ee-4b94-be8f-6c2a204c4ddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362315518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.3362315518
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.727829198
Short name T690
Test name
Test status
Simulation time 2962728259 ps
CPU time 2.32 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:36 PM PDT 24
Peak memory 203828 kb
Host smart-5f1244d0-c33b-499a-9ee5-7ee31ca988da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727829198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_hrst.727829198
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.838485404
Short name T491
Test name
Test status
Simulation time 4814331116 ps
CPU time 3.03 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:06:36 PM PDT 24
Peak memory 204932 kb
Host smart-2607da07-2fe6-4d90-946d-f3f2e76613e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838485404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_intr_smoke.838485404
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3322380140
Short name T522
Test name
Test status
Simulation time 6879065182 ps
CPU time 8.82 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:42 PM PDT 24
Peak memory 203804 kb
Host smart-979b9728-9e96-45df-9801-b515d149d5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322380140 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3322380140
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1264787169
Short name T1020
Test name
Test status
Simulation time 15390952860 ps
CPU time 26.66 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:07:00 PM PDT 24
Peak memory 203908 kb
Host smart-a5b3967a-99fa-4fe7-b006-7e5eb2d76eff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264787169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1264787169
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3894993261
Short name T1012
Test name
Test status
Simulation time 11050170306 ps
CPU time 20.92 seconds
Started Apr 04 03:06:30 PM PDT 24
Finished Apr 04 03:06:52 PM PDT 24
Peak memory 226748 kb
Host smart-1b71b94d-6ccd-4814-a5d4-59fa42740ba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894993261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3894993261
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.222467539
Short name T1107
Test name
Test status
Simulation time 30751298661 ps
CPU time 72.25 seconds
Started Apr 04 03:06:30 PM PDT 24
Finished Apr 04 03:07:43 PM PDT 24
Peak memory 368856 kb
Host smart-83ab4ab6-d05b-480d-8b20-8969afa80dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222467539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_t
arget_stretch.222467539
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.464217475
Short name T1197
Test name
Test status
Simulation time 3017051846 ps
CPU time 7.25 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:06:39 PM PDT 24
Peak memory 214748 kb
Host smart-5020adf8-b561-4360-95ea-307025980973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464217475 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.464217475
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3906205608
Short name T357
Test name
Test status
Simulation time 18735138 ps
CPU time 0.63 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:34 PM PDT 24
Peak memory 203584 kb
Host smart-e432ee70-a2ff-43b6-8943-116b5c3dc454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906205608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3906205608
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3451533668
Short name T261
Test name
Test status
Simulation time 447266866 ps
CPU time 1.46 seconds
Started Apr 04 03:06:37 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 212000 kb
Host smart-9a75b93d-cb40-45e4-95fb-46ecced9875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451533668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3451533668
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.4245788804
Short name T870
Test name
Test status
Simulation time 317369201 ps
CPU time 7.16 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 268104 kb
Host smart-3922c15b-e80e-4995-9f4f-ec69c8d48ac1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245788804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.4245788804
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1261338566
Short name T932
Test name
Test status
Simulation time 2401280853 ps
CPU time 88.75 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:07:59 PM PDT 24
Peak memory 726828 kb
Host smart-2fab4bf1-b589-46cb-872b-46517ec73805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261338566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1261338566
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.3825459110
Short name T327
Test name
Test status
Simulation time 3761273160 ps
CPU time 63.64 seconds
Started Apr 04 03:06:38 PM PDT 24
Finished Apr 04 03:07:42 PM PDT 24
Peak memory 703912 kb
Host smart-3177d31b-f74e-4d29-9ac5-77cc8599e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825459110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3825459110
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1882406301
Short name T346
Test name
Test status
Simulation time 64814324 ps
CPU time 0.78 seconds
Started Apr 04 03:06:37 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 203592 kb
Host smart-8c2a160f-9371-413b-9d5f-f07285bb093b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882406301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1882406301
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1754289096
Short name T742
Test name
Test status
Simulation time 549777676 ps
CPU time 3.38 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:06:35 PM PDT 24
Peak memory 203640 kb
Host smart-50ca215b-5c53-4c5a-9b32-1d1f55d84ce9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754289096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1754289096
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.961605052
Short name T1147
Test name
Test status
Simulation time 12903481475 ps
CPU time 67.99 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:07:41 PM PDT 24
Peak memory 908108 kb
Host smart-64fed91a-b481-4e98-88d6-9ca294c4c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961605052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.961605052
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3507771985
Short name T781
Test name
Test status
Simulation time 231349720 ps
CPU time 3.09 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:36 PM PDT 24
Peak memory 203644 kb
Host smart-01eb16d5-6fd4-4e59-a974-16764b0a0f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507771985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3507771985
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.3096664264
Short name T98
Test name
Test status
Simulation time 3446772969 ps
CPU time 26.75 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:06:59 PM PDT 24
Peak memory 348220 kb
Host smart-8fdc654a-9e5b-4c8d-8065-e6d4630671ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096664264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.3096664264
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3131487221
Short name T1082
Test name
Test status
Simulation time 98426487 ps
CPU time 0.65 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:06:33 PM PDT 24
Peak memory 203512 kb
Host smart-615a5474-b736-44f8-8808-d003aa83d6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131487221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3131487221
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1907274855
Short name T42
Test name
Test status
Simulation time 25509279416 ps
CPU time 3493.81 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 04:04:48 PM PDT 24
Peak memory 5465220 kb
Host smart-a3d75417-ac4c-47a2-a587-dbf63ec9ab67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907274855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1907274855
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2446776980
Short name T747
Test name
Test status
Simulation time 6100990808 ps
CPU time 76.32 seconds
Started Apr 04 03:06:31 PM PDT 24
Finished Apr 04 03:07:47 PM PDT 24
Peak memory 354172 kb
Host smart-628ed8c0-cb1a-42f5-b4ca-b667bfd87080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446776980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2446776980
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.413916567
Short name T26
Test name
Test status
Simulation time 45811316126 ps
CPU time 524.51 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:15:16 PM PDT 24
Peak memory 2083156 kb
Host smart-a0be1eda-9d11-46e8-86ce-a127925dd8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413916567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.413916567
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2638018310
Short name T495
Test name
Test status
Simulation time 2796216430 ps
CPU time 3.41 seconds
Started Apr 04 03:06:36 PM PDT 24
Finished Apr 04 03:06:40 PM PDT 24
Peak memory 203864 kb
Host smart-1e8514fb-0df7-4f58-897d-17b100683b10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638018310 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2638018310
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.418956733
Short name T751
Test name
Test status
Simulation time 10974563083 ps
CPU time 5.33 seconds
Started Apr 04 03:06:37 PM PDT 24
Finished Apr 04 03:06:42 PM PDT 24
Peak memory 231972 kb
Host smart-44e48a18-f497-4cdd-ab7a-fb9408be5c98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418956733 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.418956733
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.4262240134
Short name T1070
Test name
Test status
Simulation time 10258844495 ps
CPU time 18.87 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:52 PM PDT 24
Peak memory 319236 kb
Host smart-d54e81e3-264c-4738-a601-fdf16c19e4db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262240134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.4262240134
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3125322211
Short name T203
Test name
Test status
Simulation time 478348652 ps
CPU time 2.83 seconds
Started Apr 04 03:06:38 PM PDT 24
Finished Apr 04 03:06:41 PM PDT 24
Peak memory 203636 kb
Host smart-35edf808-f8f2-46b0-98e6-4771c1a4ef5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125322211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3125322211
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.2227821431
Short name T270
Test name
Test status
Simulation time 5056367434 ps
CPU time 6.09 seconds
Started Apr 04 03:06:34 PM PDT 24
Finished Apr 04 03:06:40 PM PDT 24
Peak memory 209588 kb
Host smart-90ab1aa6-6524-4d0e-bb7e-a9e08c4cb9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227821431 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.2227821431
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3814137395
Short name T86
Test name
Test status
Simulation time 942959030 ps
CPU time 32.99 seconds
Started Apr 04 03:06:34 PM PDT 24
Finished Apr 04 03:07:07 PM PDT 24
Peak memory 203752 kb
Host smart-a755e2cd-9ecc-416c-adbc-c713e29a0892
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814137395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3814137395
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.1246716390
Short name T477
Test name
Test status
Simulation time 1585052468 ps
CPU time 30.15 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:07:04 PM PDT 24
Peak memory 224216 kb
Host smart-9d5775dc-7894-4674-8ef2-07f90670c0ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246716390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.1246716390
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.2800932713
Short name T1086
Test name
Test status
Simulation time 32678161929 ps
CPU time 349.3 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:12:22 PM PDT 24
Peak memory 1115360 kb
Host smart-3614a630-550d-416b-a90f-9cf6c9b83e2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800932713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.2800932713
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.519393379
Short name T869
Test name
Test status
Simulation time 5447321206 ps
CPU time 6.92 seconds
Started Apr 04 03:06:30 PM PDT 24
Finished Apr 04 03:06:38 PM PDT 24
Peak memory 214748 kb
Host smart-6933ac85-4a61-4ff1-ba5f-8c220bf8621a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519393379 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.519393379
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.265277044
Short name T923
Test name
Test status
Simulation time 71693373 ps
CPU time 0.62 seconds
Started Apr 04 03:06:44 PM PDT 24
Finished Apr 04 03:06:45 PM PDT 24
Peak memory 203584 kb
Host smart-bf8f1a37-fd0d-4aed-973e-09c144383c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265277044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.265277044
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1726245777
Short name T1189
Test name
Test status
Simulation time 242937874 ps
CPU time 1.21 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:35 PM PDT 24
Peak memory 211928 kb
Host smart-078a9643-1959-483c-8055-ffe5df6c96a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726245777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1726245777
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2436184434
Short name T332
Test name
Test status
Simulation time 599766764 ps
CPU time 3.25 seconds
Started Apr 04 03:06:39 PM PDT 24
Finished Apr 04 03:06:42 PM PDT 24
Peak memory 226468 kb
Host smart-00ed00a7-2f7c-49e0-81da-2db3f3ab3dd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436184434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2436184434
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3524372553
Short name T889
Test name
Test status
Simulation time 1401168120 ps
CPU time 102.43 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:08:16 PM PDT 24
Peak memory 544376 kb
Host smart-12644fcb-09a9-4d7b-aaa1-fc0d48ddccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524372553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3524372553
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1971714133
Short name T293
Test name
Test status
Simulation time 26697619957 ps
CPU time 89.2 seconds
Started Apr 04 03:06:36 PM PDT 24
Finished Apr 04 03:08:06 PM PDT 24
Peak memory 507616 kb
Host smart-fe1feb38-605c-403b-94fa-fdec83157d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971714133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1971714133
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1942597584
Short name T941
Test name
Test status
Simulation time 153743243 ps
CPU time 1.25 seconds
Started Apr 04 03:06:35 PM PDT 24
Finished Apr 04 03:06:37 PM PDT 24
Peak memory 203716 kb
Host smart-7680112c-df37-4784-a9a4-cc2434f0481b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942597584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1942597584
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2162229267
Short name T687
Test name
Test status
Simulation time 121979589 ps
CPU time 2.48 seconds
Started Apr 04 03:06:39 PM PDT 24
Finished Apr 04 03:06:42 PM PDT 24
Peak memory 203720 kb
Host smart-e305a7e9-77e6-4fc9-8320-f49aaead950e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162229267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2162229267
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1632068461
Short name T1172
Test name
Test status
Simulation time 3517741359 ps
CPU time 218.55 seconds
Started Apr 04 03:06:37 PM PDT 24
Finished Apr 04 03:10:15 PM PDT 24
Peak memory 973980 kb
Host smart-3906a16b-aaad-4502-8c49-52f07f0da878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632068461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1632068461
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1454117786
Short name T724
Test name
Test status
Simulation time 558061205 ps
CPU time 21.85 seconds
Started Apr 04 03:06:37 PM PDT 24
Finished Apr 04 03:06:59 PM PDT 24
Peak memory 203752 kb
Host smart-dc31829c-65c7-4f50-8262-9e30b1521c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454117786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1454117786
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2996766173
Short name T902
Test name
Test status
Simulation time 2554524050 ps
CPU time 35.08 seconds
Started Apr 04 03:06:39 PM PDT 24
Finished Apr 04 03:07:14 PM PDT 24
Peak memory 379228 kb
Host smart-b07b6bb8-00e1-4bb0-9771-faa8b88ea315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996766173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2996766173
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1810522953
Short name T12
Test name
Test status
Simulation time 106533975 ps
CPU time 0.65 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:06:33 PM PDT 24
Peak memory 203524 kb
Host smart-f4387acf-a6ae-4d41-ab72-b642656ad76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810522953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1810522953
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2648010463
Short name T1002
Test name
Test status
Simulation time 4209669854 ps
CPU time 19.21 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:52 PM PDT 24
Peak memory 203796 kb
Host smart-883c0a1a-04d6-4007-964a-99c6a288c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648010463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2648010463
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1839676639
Short name T533
Test name
Test status
Simulation time 2430303273 ps
CPU time 60.9 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:07:34 PM PDT 24
Peak memory 350796 kb
Host smart-f99b2e01-d2b6-4152-b448-b7c7f21c71f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839676639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1839676639
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.426852335
Short name T741
Test name
Test status
Simulation time 515282389 ps
CPU time 2.81 seconds
Started Apr 04 03:06:38 PM PDT 24
Finished Apr 04 03:06:41 PM PDT 24
Peak memory 203672 kb
Host smart-b2875fd7-1a2e-469e-ab9e-e1b590098561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426852335 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.426852335
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1611102069
Short name T562
Test name
Test status
Simulation time 11244902322 ps
CPU time 3.49 seconds
Started Apr 04 03:06:38 PM PDT 24
Finished Apr 04 03:06:42 PM PDT 24
Peak memory 210060 kb
Host smart-65156f11-95a0-481e-8de2-df23266b20ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611102069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1611102069
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.860686411
Short name T642
Test name
Test status
Simulation time 10126938877 ps
CPU time 84.65 seconds
Started Apr 04 03:06:37 PM PDT 24
Finished Apr 04 03:08:02 PM PDT 24
Peak memory 647984 kb
Host smart-8a3834fb-580a-4533-ba7f-85c1f79f7cb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860686411 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.860686411
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1596284587
Short name T688
Test name
Test status
Simulation time 426864934 ps
CPU time 2.83 seconds
Started Apr 04 03:06:36 PM PDT 24
Finished Apr 04 03:06:39 PM PDT 24
Peak memory 203696 kb
Host smart-6d825f55-1394-42ef-8bbd-f333342b3f11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596284587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1596284587
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1778924908
Short name T1186
Test name
Test status
Simulation time 8457688798 ps
CPU time 7.25 seconds
Started Apr 04 03:06:32 PM PDT 24
Finished Apr 04 03:06:39 PM PDT 24
Peak memory 203884 kb
Host smart-cc43c74e-a591-4ee5-b248-2c1fcf243a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778924908 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1778924908
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3864099719
Short name T1154
Test name
Test status
Simulation time 11765695690 ps
CPU time 16.97 seconds
Started Apr 04 03:06:36 PM PDT 24
Finished Apr 04 03:06:53 PM PDT 24
Peak memory 203884 kb
Host smart-dfa694aa-0914-461e-ba5a-55e416f5e383
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864099719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3864099719
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1185380129
Short name T753
Test name
Test status
Simulation time 470264164 ps
CPU time 19.56 seconds
Started Apr 04 03:06:36 PM PDT 24
Finished Apr 04 03:06:56 PM PDT 24
Peak memory 203708 kb
Host smart-eb24cc22-3f57-4c53-97e8-db586333b63f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185380129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1185380129
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1390527987
Short name T636
Test name
Test status
Simulation time 29704902618 ps
CPU time 2522 seconds
Started Apr 04 03:06:35 PM PDT 24
Finished Apr 04 03:48:38 PM PDT 24
Peak memory 7125980 kb
Host smart-c45e6acc-0d6d-401a-ab8f-11cb42360dfd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390527987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1390527987
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3769148720
Short name T935
Test name
Test status
Simulation time 5569659963 ps
CPU time 6.2 seconds
Started Apr 04 03:06:33 PM PDT 24
Finished Apr 04 03:06:40 PM PDT 24
Peak memory 203852 kb
Host smart-c4a450a5-7949-4b66-808c-6ccca1d5097f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769148720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3769148720
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3402424300
Short name T1011
Test name
Test status
Simulation time 15801646 ps
CPU time 0.61 seconds
Started Apr 04 03:03:01 PM PDT 24
Finished Apr 04 03:03:03 PM PDT 24
Peak memory 203580 kb
Host smart-4e6e80e3-5d92-4c35-aa1f-9e258698f0d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402424300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3402424300
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.4036178680
Short name T479
Test name
Test status
Simulation time 179249928 ps
CPU time 1.55 seconds
Started Apr 04 03:02:52 PM PDT 24
Finished Apr 04 03:02:55 PM PDT 24
Peak memory 214448 kb
Host smart-e048fa3e-884a-40cd-b61f-7a23a422a467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036178680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.4036178680
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2304697769
Short name T242
Test name
Test status
Simulation time 4830724226 ps
CPU time 4.41 seconds
Started Apr 04 03:02:56 PM PDT 24
Finished Apr 04 03:03:00 PM PDT 24
Peak memory 247644 kb
Host smart-7c2f0818-1781-42b6-8a4d-cbd180d81413
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304697769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2304697769
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.464639478
Short name T621
Test name
Test status
Simulation time 3541880367 ps
CPU time 101.15 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:04:35 PM PDT 24
Peak memory 566800 kb
Host smart-91c12dcc-9ac1-4d57-92ae-466591d6ee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464639478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.464639478
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.3572482622
Short name T887
Test name
Test status
Simulation time 1403692643 ps
CPU time 38.11 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:03:32 PM PDT 24
Peak memory 535176 kb
Host smart-f2eb96ef-934d-4a4e-9141-a4c200b03b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572482622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3572482622
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.485268505
Short name T1047
Test name
Test status
Simulation time 507140785 ps
CPU time 1.01 seconds
Started Apr 04 03:02:48 PM PDT 24
Finished Apr 04 03:02:49 PM PDT 24
Peak memory 203612 kb
Host smart-5d345b35-637c-4d06-8599-a632e110b901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485268505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.485268505
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1669837014
Short name T299
Test name
Test status
Simulation time 675536227 ps
CPU time 8.09 seconds
Started Apr 04 03:02:49 PM PDT 24
Finished Apr 04 03:02:58 PM PDT 24
Peak memory 203780 kb
Host smart-83f3fdde-6389-4a23-aff9-75532716394b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669837014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1669837014
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1780884862
Short name T974
Test name
Test status
Simulation time 12094498374 ps
CPU time 180.51 seconds
Started Apr 04 03:02:52 PM PDT 24
Finished Apr 04 03:05:54 PM PDT 24
Peak memory 840016 kb
Host smart-bc4c00ae-3dcd-46a5-a7ae-4d294f80e3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780884862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1780884862
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.512564203
Short name T994
Test name
Test status
Simulation time 483715966 ps
CPU time 7.44 seconds
Started Apr 04 03:03:01 PM PDT 24
Finished Apr 04 03:03:10 PM PDT 24
Peak memory 203748 kb
Host smart-0da32197-200c-47ac-953a-fbdf0ccad3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512564203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.512564203
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1536181187
Short name T341
Test name
Test status
Simulation time 1653898276 ps
CPU time 83.45 seconds
Started Apr 04 03:03:05 PM PDT 24
Finished Apr 04 03:04:29 PM PDT 24
Peak memory 448964 kb
Host smart-ac8e6150-7088-44a6-9201-131448c36738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536181187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1536181187
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3228350655
Short name T11
Test name
Test status
Simulation time 26739802 ps
CPU time 0.66 seconds
Started Apr 04 03:02:51 PM PDT 24
Finished Apr 04 03:02:54 PM PDT 24
Peak memory 203512 kb
Host smart-5fdb84dc-2551-4c10-b733-5b2bf76124a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228350655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3228350655
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.425952978
Short name T1165
Test name
Test status
Simulation time 17580112419 ps
CPU time 181.04 seconds
Started Apr 04 03:02:50 PM PDT 24
Finished Apr 04 03:05:52 PM PDT 24
Peak memory 220264 kb
Host smart-cc590a2b-3b49-465c-ad85-16a7be72b2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425952978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.425952978
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3015713241
Short name T275
Test name
Test status
Simulation time 976503715 ps
CPU time 20.31 seconds
Started Apr 04 03:02:52 PM PDT 24
Finished Apr 04 03:03:14 PM PDT 24
Peak memory 343208 kb
Host smart-2d17c433-a575-4c7a-b4c8-9b16845c4880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015713241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3015713241
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2921239047
Short name T94
Test name
Test status
Simulation time 67234072 ps
CPU time 0.95 seconds
Started Apr 04 03:02:57 PM PDT 24
Finished Apr 04 03:02:58 PM PDT 24
Peak memory 222324 kb
Host smart-2f0a81e0-a17b-4f31-a654-3ea957bce3c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921239047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2921239047
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.766098082
Short name T403
Test name
Test status
Simulation time 1134672817 ps
CPU time 3.6 seconds
Started Apr 04 03:02:53 PM PDT 24
Finished Apr 04 03:02:57 PM PDT 24
Peak memory 203740 kb
Host smart-35e1af7c-36c5-4bb9-a185-0643c4cac643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766098082 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.766098082
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2602394573
Short name T1044
Test name
Test status
Simulation time 10222143077 ps
CPU time 18.39 seconds
Started Apr 04 03:02:57 PM PDT 24
Finished Apr 04 03:03:16 PM PDT 24
Peak memory 304912 kb
Host smart-090041e1-e493-4dc5-b7b0-f4f5503a5fe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602394573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2602394573
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1282162883
Short name T700
Test name
Test status
Simulation time 10363388057 ps
CPU time 14.55 seconds
Started Apr 04 03:02:56 PM PDT 24
Finished Apr 04 03:03:11 PM PDT 24
Peak memory 335304 kb
Host smart-6313af79-2b01-4ad4-a2d5-88db845fa0da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282162883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1282162883
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2426828168
Short name T939
Test name
Test status
Simulation time 390503259 ps
CPU time 2.49 seconds
Started Apr 04 03:03:01 PM PDT 24
Finished Apr 04 03:03:05 PM PDT 24
Peak memory 203792 kb
Host smart-9a04465f-4a8c-4358-9574-398e133d2433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426828168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2426828168
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2384361173
Short name T875
Test name
Test status
Simulation time 1450894663 ps
CPU time 7.08 seconds
Started Apr 04 03:02:55 PM PDT 24
Finished Apr 04 03:03:02 PM PDT 24
Peak memory 219920 kb
Host smart-169ca4ea-9aca-4217-8265-cf6d227541a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384361173 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2384361173
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.281528908
Short name T1200
Test name
Test status
Simulation time 814692272 ps
CPU time 10.85 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:03:05 PM PDT 24
Peak memory 203732 kb
Host smart-798f18cd-5633-47ec-b235-b411f8855df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281528908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.281528908
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3038697817
Short name T693
Test name
Test status
Simulation time 771436874 ps
CPU time 10.9 seconds
Started Apr 04 03:02:53 PM PDT 24
Finished Apr 04 03:03:05 PM PDT 24
Peak memory 204576 kb
Host smart-eecd9af6-0ae3-4651-9872-69300e6b47d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038697817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3038697817
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.141256229
Short name T380
Test name
Test status
Simulation time 12502475082 ps
CPU time 14.05 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:03:08 PM PDT 24
Peak memory 203844 kb
Host smart-273359a8-0d07-471e-8c8d-841e03251dad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141256229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_wr.141256229
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.798343664
Short name T950
Test name
Test status
Simulation time 25217352989 ps
CPU time 179.53 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:05:54 PM PDT 24
Peak memory 1562864 kb
Host smart-081fa73a-291a-480a-a172-78a1cc44a9eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798343664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.798343664
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1820427468
Short name T417
Test name
Test status
Simulation time 1323487514 ps
CPU time 6.54 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:03:01 PM PDT 24
Peak memory 211404 kb
Host smart-ac69b008-4d60-418e-8844-67db5b48db3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820427468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1820427468
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1103394998
Short name T611
Test name
Test status
Simulation time 25286729 ps
CPU time 0.62 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:06:46 PM PDT 24
Peak memory 203556 kb
Host smart-b3a5abbf-39dc-4c58-bd4c-25db78bc37fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103394998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1103394998
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1797296084
Short name T52
Test name
Test status
Simulation time 68331702 ps
CPU time 1.35 seconds
Started Apr 04 03:06:46 PM PDT 24
Finished Apr 04 03:06:48 PM PDT 24
Peak memory 211980 kb
Host smart-2aa209f3-5c06-4186-a2ca-be474dda38e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797296084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1797296084
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1643485761
Short name T557
Test name
Test status
Simulation time 283450427 ps
CPU time 3.65 seconds
Started Apr 04 03:06:43 PM PDT 24
Finished Apr 04 03:06:48 PM PDT 24
Peak memory 221384 kb
Host smart-561628bb-e3af-4fc2-919b-2ef9b9ba4678
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643485761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1643485761
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2482101631
Short name T447
Test name
Test status
Simulation time 4790318420 ps
CPU time 77.4 seconds
Started Apr 04 03:06:44 PM PDT 24
Finished Apr 04 03:08:02 PM PDT 24
Peak memory 786840 kb
Host smart-fac469fe-ce66-4bd5-a56b-211d73ef1f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482101631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2482101631
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2524897801
Short name T1131
Test name
Test status
Simulation time 1894876716 ps
CPU time 51.85 seconds
Started Apr 04 03:06:48 PM PDT 24
Finished Apr 04 03:07:40 PM PDT 24
Peak memory 577160 kb
Host smart-f39deeeb-b655-4a73-aa99-507f166213b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524897801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2524897801
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3019648355
Short name T737
Test name
Test status
Simulation time 93299842 ps
CPU time 0.87 seconds
Started Apr 04 03:06:44 PM PDT 24
Finished Apr 04 03:06:45 PM PDT 24
Peak memory 203520 kb
Host smart-f42bf8f3-327a-46a6-a9e5-dd071c976c08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019648355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3019648355
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1780849641
Short name T508
Test name
Test status
Simulation time 121113925 ps
CPU time 2.65 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:06:54 PM PDT 24
Peak memory 203660 kb
Host smart-7814b1ae-e917-4165-921e-c19dd0799afb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780849641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1780849641
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2808161591
Short name T476
Test name
Test status
Simulation time 1171796107 ps
CPU time 11.64 seconds
Started Apr 04 03:06:49 PM PDT 24
Finished Apr 04 03:07:01 PM PDT 24
Peak memory 203792 kb
Host smart-b9a616e9-8587-4ca3-a339-fc95136d4471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808161591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2808161591
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.216213885
Short name T779
Test name
Test status
Simulation time 3020059889 ps
CPU time 26.53 seconds
Started Apr 04 03:06:42 PM PDT 24
Finished Apr 04 03:07:09 PM PDT 24
Peak memory 367156 kb
Host smart-b878c228-02ea-49a8-bbd9-1881694b752d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216213885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.216213885
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1615938994
Short name T1111
Test name
Test status
Simulation time 28719562 ps
CPU time 0.68 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:06:48 PM PDT 24
Peak memory 203524 kb
Host smart-a89360ac-1ae4-47f0-bf39-7e8be7c444a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615938994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1615938994
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3844380486
Short name T179
Test name
Test status
Simulation time 367796255 ps
CPU time 3.48 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:06:51 PM PDT 24
Peak memory 228172 kb
Host smart-10d96873-be06-4e10-870f-a239148c4e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844380486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3844380486
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2920874767
Short name T1023
Test name
Test status
Simulation time 2879036507 ps
CPU time 17.92 seconds
Started Apr 04 03:06:46 PM PDT 24
Finished Apr 04 03:07:05 PM PDT 24
Peak memory 311296 kb
Host smart-69867b41-b1a5-46cb-bb2b-d2e73c9e8694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920874767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2920874767
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.3430595414
Short name T237
Test name
Test status
Simulation time 16239433036 ps
CPU time 293.25 seconds
Started Apr 04 03:06:52 PM PDT 24
Finished Apr 04 03:11:45 PM PDT 24
Peak memory 669236 kb
Host smart-0e83a3bd-bb3c-42f0-9910-92d7c88a6840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430595414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.3430595414
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3867150870
Short name T523
Test name
Test status
Simulation time 2407871779 ps
CPU time 3.19 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:06:50 PM PDT 24
Peak memory 203844 kb
Host smart-ccd1aeb8-b80c-49d7-b896-dd258de7bde1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867150870 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3867150870
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.797225650
Short name T905
Test name
Test status
Simulation time 10115725275 ps
CPU time 74.64 seconds
Started Apr 04 03:06:43 PM PDT 24
Finished Apr 04 03:07:57 PM PDT 24
Peak memory 562772 kb
Host smart-52b2b3a9-8c93-4edf-9989-e4012e459284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797225650 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.797225650
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2573940602
Short name T744
Test name
Test status
Simulation time 10073760956 ps
CPU time 94.14 seconds
Started Apr 04 03:06:51 PM PDT 24
Finished Apr 04 03:08:25 PM PDT 24
Peak memory 772792 kb
Host smart-37f313d4-68e8-4520-9c2d-920d6badb729
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573940602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2573940602
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1497586655
Short name T906
Test name
Test status
Simulation time 847696360 ps
CPU time 2.7 seconds
Started Apr 04 03:06:43 PM PDT 24
Finished Apr 04 03:06:45 PM PDT 24
Peak memory 203716 kb
Host smart-d58fdc14-b7b2-4387-a3d4-5cdafd4b01f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497586655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1497586655
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.993177083
Short name T267
Test name
Test status
Simulation time 6436255416 ps
CPU time 6.02 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:06:56 PM PDT 24
Peak memory 217892 kb
Host smart-2306cf35-a9f2-40e5-ac4b-62a699338d2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993177083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.993177083
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.875847957
Short name T755
Test name
Test status
Simulation time 4814654184 ps
CPU time 17.06 seconds
Started Apr 04 03:06:43 PM PDT 24
Finished Apr 04 03:07:01 PM PDT 24
Peak memory 203760 kb
Host smart-6a3eb33b-f24a-493e-b144-011107ae9512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875847957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.875847957
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2534927113
Short name T607
Test name
Test status
Simulation time 6532259667 ps
CPU time 71.5 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:07:56 PM PDT 24
Peak memory 206064 kb
Host smart-2725e603-6fc1-4b8d-be3d-b5cbd44ddf85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534927113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2534927113
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.2697039692
Short name T1206
Test name
Test status
Simulation time 8574574994 ps
CPU time 30.83 seconds
Started Apr 04 03:06:43 PM PDT 24
Finished Apr 04 03:07:14 PM PDT 24
Peak memory 628996 kb
Host smart-f7c35e1d-60b5-4d51-bf02-c1e7eae9f7d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697039692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.2697039692
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1777621222
Short name T1027
Test name
Test status
Simulation time 1642874343 ps
CPU time 7.88 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:06:55 PM PDT 24
Peak memory 211192 kb
Host smart-ca8fed44-9e61-4ee0-b020-05662f68b3fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777621222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1777621222
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3003770083
Short name T401
Test name
Test status
Simulation time 65589661 ps
CPU time 0.62 seconds
Started Apr 04 03:06:48 PM PDT 24
Finished Apr 04 03:06:49 PM PDT 24
Peak memory 203624 kb
Host smart-8bc5c725-5496-48a3-bf5a-4370b09ce9b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003770083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3003770083
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3116613008
Short name T836
Test name
Test status
Simulation time 116258280 ps
CPU time 1.5 seconds
Started Apr 04 03:06:49 PM PDT 24
Finished Apr 04 03:06:51 PM PDT 24
Peak memory 211872 kb
Host smart-005bad8b-0987-4644-9daf-5fe41c517d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116613008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3116613008
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2602533036
Short name T1019
Test name
Test status
Simulation time 1393783657 ps
CPU time 6.47 seconds
Started Apr 04 03:06:48 PM PDT 24
Finished Apr 04 03:06:55 PM PDT 24
Peak memory 274352 kb
Host smart-6a54b029-cbff-46ea-8223-1130d41bb32b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602533036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.2602533036
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3679550637
Short name T516
Test name
Test status
Simulation time 7516247621 ps
CPU time 54.27 seconds
Started Apr 04 03:06:51 PM PDT 24
Finished Apr 04 03:07:46 PM PDT 24
Peak memory 617064 kb
Host smart-01cf3eda-6c4b-41dc-b77a-2afec03260c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679550637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3679550637
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.352745364
Short name T978
Test name
Test status
Simulation time 7603177687 ps
CPU time 55.76 seconds
Started Apr 04 03:06:46 PM PDT 24
Finished Apr 04 03:07:43 PM PDT 24
Peak memory 657456 kb
Host smart-cef014bb-9ddd-453a-bb1e-6a8d715c2c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352745364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.352745364
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3442364478
Short name T1036
Test name
Test status
Simulation time 204172450 ps
CPU time 0.92 seconds
Started Apr 04 03:06:49 PM PDT 24
Finished Apr 04 03:06:50 PM PDT 24
Peak memory 203600 kb
Host smart-1bfa3b09-03da-4c52-9e1a-037cdeb5efb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442364478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3442364478
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3478106278
Short name T788
Test name
Test status
Simulation time 216014045 ps
CPU time 6.55 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:06:54 PM PDT 24
Peak memory 220468 kb
Host smart-c7fc199d-72c4-4202-af3b-f50ae5f352c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478106278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3478106278
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2484491401
Short name T854
Test name
Test status
Simulation time 7701591355 ps
CPU time 88.68 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:08:20 PM PDT 24
Peak memory 1086436 kb
Host smart-138cb4f7-5f91-49be-b5c3-d7e2d1c83a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484491401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2484491401
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2623995879
Short name T1064
Test name
Test status
Simulation time 1658448453 ps
CPU time 20.13 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:07:05 PM PDT 24
Peak memory 203688 kb
Host smart-a05dc5d6-f160-4fcd-aada-c3708e23c816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623995879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2623995879
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2761235630
Short name T587
Test name
Test status
Simulation time 3405643128 ps
CPU time 17.11 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:07:07 PM PDT 24
Peak memory 344620 kb
Host smart-d5f445bd-de7b-4ca4-ad3d-dc7ae69ee616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761235630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2761235630
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2192288606
Short name T626
Test name
Test status
Simulation time 21215426 ps
CPU time 0.66 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:06:48 PM PDT 24
Peak memory 203532 kb
Host smart-ba3dc867-9217-4395-8531-1851232dffdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192288606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2192288606
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.440550954
Short name T667
Test name
Test status
Simulation time 438182921 ps
CPU time 3.72 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:06:55 PM PDT 24
Peak memory 220456 kb
Host smart-a24518f6-2ad1-445b-a860-0015973d73cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440550954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.440550954
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.841109803
Short name T1039
Test name
Test status
Simulation time 1107021257 ps
CPU time 20.58 seconds
Started Apr 04 03:06:51 PM PDT 24
Finished Apr 04 03:07:12 PM PDT 24
Peak memory 346548 kb
Host smart-3f663eca-128e-4abb-8407-f9648018c4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841109803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.841109803
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2136779621
Short name T1040
Test name
Test status
Simulation time 2389207385 ps
CPU time 3.03 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:06:50 PM PDT 24
Peak memory 203756 kb
Host smart-0e4e40da-be38-4880-aa8f-bce55724b339
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136779621 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2136779621
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.4002130388
Short name T1066
Test name
Test status
Simulation time 10041132222 ps
CPU time 91.53 seconds
Started Apr 04 03:06:48 PM PDT 24
Finished Apr 04 03:08:20 PM PDT 24
Peak memory 616608 kb
Host smart-1e653fda-c8bf-4249-b206-0d8cd9c51ffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002130388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.4002130388
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.273307021
Short name T874
Test name
Test status
Simulation time 10087078439 ps
CPU time 33.03 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 438804 kb
Host smart-5eaa6030-601e-4089-aa76-2906fcfef55b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273307021 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.273307021
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.3332841011
Short name T817
Test name
Test status
Simulation time 903968034 ps
CPU time 1.74 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:06:49 PM PDT 24
Peak memory 203724 kb
Host smart-4d0c347c-738d-4f95-91f0-d05847481914
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332841011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.3332841011
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2117813977
Short name T720
Test name
Test status
Simulation time 2494753484 ps
CPU time 5.9 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:06:57 PM PDT 24
Peak memory 207428 kb
Host smart-745efd7d-0f4e-4a5e-9557-ee4596989eeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117813977 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2117813977
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3151940333
Short name T338
Test name
Test status
Simulation time 2639045263 ps
CPU time 49.15 seconds
Started Apr 04 03:06:49 PM PDT 24
Finished Apr 04 03:07:38 PM PDT 24
Peak memory 203832 kb
Host smart-6b352652-05d5-4dc0-86cf-cc8df44c513d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151940333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3151940333
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.1808459033
Short name T927
Test name
Test status
Simulation time 3604314535 ps
CPU time 7.01 seconds
Started Apr 04 03:06:49 PM PDT 24
Finished Apr 04 03:06:56 PM PDT 24
Peak memory 203832 kb
Host smart-59ba7ef0-330e-4f1b-9e95-f77720c38bc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808459033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.1808459033
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1327689467
Short name T1149
Test name
Test status
Simulation time 9195916895 ps
CPU time 168.38 seconds
Started Apr 04 03:06:44 PM PDT 24
Finished Apr 04 03:09:33 PM PDT 24
Peak memory 1648756 kb
Host smart-08e01a90-56c4-4702-9169-06141d0263db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327689467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1327689467
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2184883001
Short name T550
Test name
Test status
Simulation time 2169546471 ps
CPU time 6.73 seconds
Started Apr 04 03:06:43 PM PDT 24
Finished Apr 04 03:06:50 PM PDT 24
Peak memory 219932 kb
Host smart-e7834d47-4127-490a-be50-da4f3ac42272
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184883001 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2184883001
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.109163797
Short name T1045
Test name
Test status
Simulation time 112027131 ps
CPU time 0.62 seconds
Started Apr 04 03:07:01 PM PDT 24
Finished Apr 04 03:07:02 PM PDT 24
Peak memory 203548 kb
Host smart-68bbd668-416d-46b2-b1f1-73502ae50929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109163797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.109163797
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.265273937
Short name T1084
Test name
Test status
Simulation time 131728249 ps
CPU time 1.61 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:06:49 PM PDT 24
Peak memory 211880 kb
Host smart-ae9eb7d7-8432-463a-8be9-6b94f874c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265273937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.265273937
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1988379043
Short name T437
Test name
Test status
Simulation time 918798978 ps
CPU time 8.63 seconds
Started Apr 04 03:06:44 PM PDT 24
Finished Apr 04 03:06:53 PM PDT 24
Peak memory 280372 kb
Host smart-b6f12df7-4723-442a-88fb-d484d78fee60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988379043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1988379043
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2584470695
Short name T1074
Test name
Test status
Simulation time 1371754554 ps
CPU time 91.05 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:08:18 PM PDT 24
Peak memory 534756 kb
Host smart-3df7e764-0efa-4844-a67d-7680b9b4e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584470695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2584470695
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3738537317
Short name T654
Test name
Test status
Simulation time 9084947901 ps
CPU time 66.96 seconds
Started Apr 04 03:06:48 PM PDT 24
Finished Apr 04 03:07:55 PM PDT 24
Peak memory 715188 kb
Host smart-2a2a3870-7ac2-41e9-8df7-8d568a2468d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738537317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3738537317
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3135677002
Short name T386
Test name
Test status
Simulation time 88962753 ps
CPU time 0.89 seconds
Started Apr 04 03:06:51 PM PDT 24
Finished Apr 04 03:06:52 PM PDT 24
Peak memory 203600 kb
Host smart-3ea9740b-ba8d-495d-8bb0-fc29f722ef8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135677002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3135677002
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.806597808
Short name T500
Test name
Test status
Simulation time 325666000 ps
CPU time 8.36 seconds
Started Apr 04 03:06:49 PM PDT 24
Finished Apr 04 03:06:57 PM PDT 24
Peak memory 203716 kb
Host smart-a5dbbee2-f7c4-4757-bc99-d3dea3e3c500
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806597808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
806597808
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1832111309
Short name T220
Test name
Test status
Simulation time 2417596400 ps
CPU time 46.22 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 717000 kb
Host smart-836d9b5b-6dab-472a-9143-5175422077d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832111309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1832111309
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2170413430
Short name T24
Test name
Test status
Simulation time 588294553 ps
CPU time 4.39 seconds
Started Apr 04 03:07:04 PM PDT 24
Finished Apr 04 03:07:08 PM PDT 24
Peak memory 203732 kb
Host smart-7d20ab82-96a9-4c19-9f50-0fc2a8660b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170413430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2170413430
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3399205688
Short name T253
Test name
Test status
Simulation time 1321062423 ps
CPU time 27.93 seconds
Started Apr 04 03:07:04 PM PDT 24
Finished Apr 04 03:07:32 PM PDT 24
Peak memory 359604 kb
Host smart-3cd6a155-ba35-4fa5-bfcf-1869fc111fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399205688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3399205688
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1107616057
Short name T297
Test name
Test status
Simulation time 27153867 ps
CPU time 0.69 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:06:52 PM PDT 24
Peak memory 203516 kb
Host smart-29d4f302-6fe1-4240-9634-113557630d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107616057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1107616057
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3759158159
Short name T1022
Test name
Test status
Simulation time 7525484644 ps
CPU time 79.48 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:08:04 PM PDT 24
Peak memory 259232 kb
Host smart-ee5b4d51-bd4e-4d6b-93b0-7315b387f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759158159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3759158159
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.961579187
Short name T208
Test name
Test status
Simulation time 1823362537 ps
CPU time 90.99 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:08:21 PM PDT 24
Peak memory 421924 kb
Host smart-59de3b40-8c01-4cba-a3e6-3b1028c95b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961579187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.961579187
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1722077057
Short name T461
Test name
Test status
Simulation time 6090815624 ps
CPU time 5.35 seconds
Started Apr 04 03:07:01 PM PDT 24
Finished Apr 04 03:07:07 PM PDT 24
Peak memory 212212 kb
Host smart-db241d15-439b-4354-bb60-30c22c4410b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722077057 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1722077057
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1913850583
Short name T61
Test name
Test status
Simulation time 10039525074 ps
CPU time 73.74 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:08:19 PM PDT 24
Peak memory 596664 kb
Host smart-bcba1f14-fc25-4dca-b569-a9cf4e167e79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913850583 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1913850583
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1476575998
Short name T1089
Test name
Test status
Simulation time 10082166161 ps
CPU time 96.01 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:08:38 PM PDT 24
Peak memory 738804 kb
Host smart-673976fa-22a9-4a29-891c-a57e7ec0f911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476575998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1476575998
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3456895365
Short name T1000
Test name
Test status
Simulation time 1204373703 ps
CPU time 5.9 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:06:53 PM PDT 24
Peak memory 203712 kb
Host smart-1a548bdc-1534-49b5-81cf-72b53247d33c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456895365 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3456895365
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1813960422
Short name T798
Test name
Test status
Simulation time 5445246847 ps
CPU time 6.74 seconds
Started Apr 04 03:06:45 PM PDT 24
Finished Apr 04 03:06:54 PM PDT 24
Peak memory 203752 kb
Host smart-529f0e58-e6e2-41e3-bab4-2f7b133a2ca1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813960422 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1813960422
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2391835379
Short name T85
Test name
Test status
Simulation time 600921164 ps
CPU time 9.49 seconds
Started Apr 04 03:06:49 PM PDT 24
Finished Apr 04 03:06:59 PM PDT 24
Peak memory 203728 kb
Host smart-3a0d9ec6-162d-446c-9b2b-c24ec1e2da6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391835379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2391835379
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2763758495
Short name T1090
Test name
Test status
Simulation time 1699876580 ps
CPU time 25.63 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:07:16 PM PDT 24
Peak memory 236400 kb
Host smart-74104610-5dda-4981-a311-19cd39070e13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763758495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2763758495
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3825686883
Short name T552
Test name
Test status
Simulation time 21675152429 ps
CPU time 12.2 seconds
Started Apr 04 03:06:47 PM PDT 24
Finished Apr 04 03:07:00 PM PDT 24
Peak memory 203856 kb
Host smart-314d5ee8-9cf6-4f5c-a0dc-bc2cfea3b23d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825686883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3825686883
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3537046835
Short name T279
Test name
Test status
Simulation time 41495811938 ps
CPU time 2894.73 seconds
Started Apr 04 03:06:50 PM PDT 24
Finished Apr 04 03:55:06 PM PDT 24
Peak memory 9386280 kb
Host smart-355c4cd8-570e-4e16-aeea-d1965644bd25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537046835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3537046835
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1588108834
Short name T559
Test name
Test status
Simulation time 8907531162 ps
CPU time 7.14 seconds
Started Apr 04 03:06:48 PM PDT 24
Finished Apr 04 03:06:55 PM PDT 24
Peak memory 215340 kb
Host smart-9d77156f-464d-4b8e-864b-8ef3619cb5a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588108834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1588108834
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1619206885
Short name T942
Test name
Test status
Simulation time 134995845 ps
CPU time 0.63 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:06 PM PDT 24
Peak memory 203612 kb
Host smart-1fda20ee-ee58-48bc-9b9e-cbf43a2e57c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619206885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1619206885
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.3852349896
Short name T674
Test name
Test status
Simulation time 93075878 ps
CPU time 1.36 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:05 PM PDT 24
Peak memory 211868 kb
Host smart-dbf62c3b-d76b-41aa-b5d9-1683be5a7d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852349896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.3852349896
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1016170416
Short name T867
Test name
Test status
Simulation time 2219023063 ps
CPU time 18.33 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:07:21 PM PDT 24
Peak memory 276732 kb
Host smart-497351f6-2e0a-414f-823e-d2b2dee262cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016170416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1016170416
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3505750079
Short name T87
Test name
Test status
Simulation time 1132288261 ps
CPU time 75.86 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:08:21 PM PDT 24
Peak memory 484136 kb
Host smart-3e799b06-efff-45be-b08a-70fb84fa65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505750079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3505750079
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3234755304
Short name T681
Test name
Test status
Simulation time 3076231292 ps
CPU time 37.46 seconds
Started Apr 04 03:07:01 PM PDT 24
Finished Apr 04 03:07:38 PM PDT 24
Peak memory 463008 kb
Host smart-f4ac252a-fbc9-4425-a1c8-ed041bf69e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234755304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3234755304
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.1598006799
Short name T101
Test name
Test status
Simulation time 516527776 ps
CPU time 1.05 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:06 PM PDT 24
Peak memory 203296 kb
Host smart-ba94941e-4216-4567-b62f-b67556bd54b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598006799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.1598006799
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1594288572
Short name T877
Test name
Test status
Simulation time 284302491 ps
CPU time 3.63 seconds
Started Apr 04 03:07:04 PM PDT 24
Finished Apr 04 03:07:08 PM PDT 24
Peak memory 203752 kb
Host smart-da0b6077-d89d-44b4-bf8b-f74c196df2c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594288572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1594288572
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.825594151
Short name T570
Test name
Test status
Simulation time 4125204431 ps
CPU time 312.45 seconds
Started Apr 04 03:07:01 PM PDT 24
Finished Apr 04 03:12:14 PM PDT 24
Peak memory 1217456 kb
Host smart-a885444b-ac8c-4aea-9fd2-d7a116718085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825594151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.825594151
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3090804238
Short name T775
Test name
Test status
Simulation time 661899701 ps
CPU time 4.1 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:09 PM PDT 24
Peak memory 203712 kb
Host smart-321d4165-e916-4116-95e4-69a81db0d1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090804238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3090804238
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.721056747
Short name T195
Test name
Test status
Simulation time 1197740995 ps
CPU time 57.34 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:08:04 PM PDT 24
Peak memory 329112 kb
Host smart-0a537c87-0224-4ace-ad58-5710a18f6ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721056747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.721056747
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1528485358
Short name T172
Test name
Test status
Simulation time 25855774 ps
CPU time 0.69 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:04 PM PDT 24
Peak memory 203528 kb
Host smart-ba20a99d-76cb-4f26-a7d5-ecd9a74b0622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528485358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1528485358
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2294415407
Short name T548
Test name
Test status
Simulation time 6540563887 ps
CPU time 17.78 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:21 PM PDT 24
Peak memory 312920 kb
Host smart-a1f3a160-106d-4be1-90f6-5a97994a3693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294415407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2294415407
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.4165706641
Short name T977
Test name
Test status
Simulation time 2197936680 ps
CPU time 5.02 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:10 PM PDT 24
Peak memory 211980 kb
Host smart-d30afcf9-e813-4321-8ba7-10c841dd8743
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165706641 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.4165706641
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.2108644958
Short name T1042
Test name
Test status
Simulation time 10311481515 ps
CPU time 4.2 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:07:07 PM PDT 24
Peak memory 229904 kb
Host smart-bc3a3f79-4620-45c8-b611-3b823adecfbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108644958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.2108644958
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.1772525148
Short name T343
Test name
Test status
Simulation time 10447573018 ps
CPU time 14.79 seconds
Started Apr 04 03:07:04 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 319312 kb
Host smart-d0ea4785-faa7-4412-bb06-f2fda041679b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772525148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.1772525148
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3710169773
Short name T949
Test name
Test status
Simulation time 210270951 ps
CPU time 1.84 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:05 PM PDT 24
Peak memory 203644 kb
Host smart-2d9aae0b-4644-4e71-9482-f8cda07d59d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710169773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3710169773
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1360350579
Short name T662
Test name
Test status
Simulation time 2249971338 ps
CPU time 5.59 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:07:08 PM PDT 24
Peak memory 213872 kb
Host smart-8228d658-1dca-4f33-9297-d61fd3aef3e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360350579 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1360350579
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3274441249
Short name T513
Test name
Test status
Simulation time 2631936542 ps
CPU time 15.65 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:21 PM PDT 24
Peak memory 203716 kb
Host smart-ffbdbe28-18b4-49ac-82de-dd6d01660ea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274441249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3274441249
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.4186674937
Short name T623
Test name
Test status
Simulation time 6168172503 ps
CPU time 37.92 seconds
Started Apr 04 03:07:04 PM PDT 24
Finished Apr 04 03:07:42 PM PDT 24
Peak memory 203828 kb
Host smart-4993dc9d-a07f-475a-ba29-22d1d52126a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186674937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.4186674937
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.3022969366
Short name T428
Test name
Test status
Simulation time 27821102266 ps
CPU time 145.02 seconds
Started Apr 04 03:07:00 PM PDT 24
Finished Apr 04 03:09:25 PM PDT 24
Peak memory 1449672 kb
Host smart-5855c3e8-008e-488e-8d19-4d251473ef66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022969366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.3022969366
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.399929190
Short name T19
Test name
Test status
Simulation time 1244448072 ps
CPU time 6.47 seconds
Started Apr 04 03:07:06 PM PDT 24
Finished Apr 04 03:07:13 PM PDT 24
Peak memory 211948 kb
Host smart-80f68be0-662f-4b34-8f2f-2c4553e377cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399929190 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.399929190
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1588931769
Short name T519
Test name
Test status
Simulation time 40604237 ps
CPU time 0.64 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 203556 kb
Host smart-a653dfa7-675d-4d30-acb2-cb5c5bae621d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588931769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1588931769
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3852853191
Short name T1034
Test name
Test status
Simulation time 48372860 ps
CPU time 1.21 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:04 PM PDT 24
Peak memory 220108 kb
Host smart-f1c0f97f-5eb8-40bd-957a-6d2b4abcd6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852853191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3852853191
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3261132693
Short name T1099
Test name
Test status
Simulation time 352714339 ps
CPU time 18.59 seconds
Started Apr 04 03:07:07 PM PDT 24
Finished Apr 04 03:07:27 PM PDT 24
Peak memory 265700 kb
Host smart-59628ed7-5ab5-4adc-aa2b-1f3dd5351d99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261132693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3261132693
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.452023263
Short name T888
Test name
Test status
Simulation time 11162220103 ps
CPU time 87.8 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:08:31 PM PDT 24
Peak memory 761552 kb
Host smart-5dbdad58-0f8e-4d1d-b616-eecce31fd835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452023263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.452023263
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2562892313
Short name T618
Test name
Test status
Simulation time 2813889015 ps
CPU time 37.79 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:07:40 PM PDT 24
Peak memory 491140 kb
Host smart-29b3b63a-8822-4e53-973c-683f19dbeb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562892313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2562892313
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.954649994
Short name T719
Test name
Test status
Simulation time 84589188 ps
CPU time 0.89 seconds
Started Apr 04 03:07:07 PM PDT 24
Finished Apr 04 03:07:09 PM PDT 24
Peak memory 203616 kb
Host smart-d8ebe489-a58f-49c1-b6ab-232f1d5bf500
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954649994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fm
t.954649994
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.4148974397
Short name T520
Test name
Test status
Simulation time 378051450 ps
CPU time 4.67 seconds
Started Apr 04 03:07:07 PM PDT 24
Finished Apr 04 03:07:13 PM PDT 24
Peak memory 236696 kb
Host smart-f6d625ba-06d2-4f16-bcc2-d76791a03758
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148974397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.4148974397
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.4163950908
Short name T311
Test name
Test status
Simulation time 3254329060 ps
CPU time 91.43 seconds
Started Apr 04 03:07:01 PM PDT 24
Finished Apr 04 03:08:33 PM PDT 24
Peak memory 994660 kb
Host smart-b9b78787-537c-4604-9a23-d4a11c78f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163950908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.4163950908
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2373275715
Short name T691
Test name
Test status
Simulation time 388326960 ps
CPU time 6.27 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:12 PM PDT 24
Peak memory 203760 kb
Host smart-002f839d-99a3-4e2a-afd7-3b3c7a46db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373275715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2373275715
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.403843156
Short name T464
Test name
Test status
Simulation time 17719254567 ps
CPU time 36.4 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:42 PM PDT 24
Peak memory 430684 kb
Host smart-1ea56880-675a-4d48-8377-b1d3fe3dacd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403843156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.403843156
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2016361113
Short name T797
Test name
Test status
Simulation time 26671837 ps
CPU time 0.62 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:04 PM PDT 24
Peak memory 203512 kb
Host smart-c72564c4-c862-4484-b925-a8d2a785933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016361113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2016361113
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1990539394
Short name T323
Test name
Test status
Simulation time 6668202828 ps
CPU time 320.88 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:12:23 PM PDT 24
Peak memory 403188 kb
Host smart-74d521ba-9b1e-4da1-a34d-46c79d74fd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990539394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1990539394
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3045843121
Short name T896
Test name
Test status
Simulation time 7714693677 ps
CPU time 50.38 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:07:56 PM PDT 24
Peak memory 294684 kb
Host smart-8effdd9e-99c5-4e56-8037-a3721f341741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045843121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3045843121
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.94409784
Short name T148
Test name
Test status
Simulation time 72582866587 ps
CPU time 1999.1 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:40:23 PM PDT 24
Peak memory 4123724 kb
Host smart-c1c184a5-eca3-41b4-92ae-cbc7b254777f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94409784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.94409784
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3710877145
Short name T1173
Test name
Test status
Simulation time 536628759 ps
CPU time 2.62 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:06 PM PDT 24
Peak memory 203792 kb
Host smart-1517403d-cc68-4b0c-a56e-b3cdbf1889bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710877145 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3710877145
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2522676860
Short name T375
Test name
Test status
Simulation time 10188449384 ps
CPU time 18.78 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:07:21 PM PDT 24
Peak memory 317224 kb
Host smart-42dbbdac-f405-4735-8339-dcb7513eea2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522676860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2522676860
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.828047536
Short name T1109
Test name
Test status
Simulation time 10063021599 ps
CPU time 120.15 seconds
Started Apr 04 03:07:05 PM PDT 24
Finished Apr 04 03:09:05 PM PDT 24
Peak memory 766808 kb
Host smart-7a78ef68-1ab8-4aea-addc-6b98c85614e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828047536 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.828047536
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1012396866
Short name T861
Test name
Test status
Simulation time 395216627 ps
CPU time 2.41 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:06 PM PDT 24
Peak memory 203680 kb
Host smart-98097f3a-b3dc-4514-93eb-d67dc67e6025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012396866 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1012396866
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.4243040942
Short name T886
Test name
Test status
Simulation time 1045992538 ps
CPU time 5.78 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:09 PM PDT 24
Peak memory 212300 kb
Host smart-596b72da-daa3-4520-93fb-eab9a5e1aec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243040942 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.4243040942
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3653803157
Short name T371
Test name
Test status
Simulation time 6369408588 ps
CPU time 8.87 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:12 PM PDT 24
Peak memory 203904 kb
Host smart-945a5135-7df3-4831-b62f-e31894f9c039
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653803157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3653803157
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.318572808
Short name T465
Test name
Test status
Simulation time 2597823570 ps
CPU time 22.3 seconds
Started Apr 04 03:07:03 PM PDT 24
Finished Apr 04 03:07:26 PM PDT 24
Peak memory 218608 kb
Host smart-af3b41b3-05fc-453f-8c9f-f3dd19d2fcf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318572808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.318572808
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1593500557
Short name T897
Test name
Test status
Simulation time 18823734951 ps
CPU time 117.81 seconds
Started Apr 04 03:07:04 PM PDT 24
Finished Apr 04 03:09:02 PM PDT 24
Peak memory 1024696 kb
Host smart-50dd70bb-35bc-470b-b229-428d83736e25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593500557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1593500557
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.599477206
Short name T1146
Test name
Test status
Simulation time 11684988747 ps
CPU time 6.7 seconds
Started Apr 04 03:07:02 PM PDT 24
Finished Apr 04 03:07:09 PM PDT 24
Peak memory 219548 kb
Host smart-5f496c66-3af6-4c50-a025-52bde01de18a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599477206 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.599477206
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2728217962
Short name T1207
Test name
Test status
Simulation time 42083469 ps
CPU time 0.64 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 203628 kb
Host smart-ef7d5f3e-45c5-4baa-85d5-fb01615e1167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728217962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2728217962
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.180736343
Short name T1188
Test name
Test status
Simulation time 97418669 ps
CPU time 1.94 seconds
Started Apr 04 03:07:15 PM PDT 24
Finished Apr 04 03:07:17 PM PDT 24
Peak memory 211952 kb
Host smart-0d61781f-00a0-4961-8a44-6debcd4940d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180736343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.180736343
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1461639600
Short name T473
Test name
Test status
Simulation time 369196043 ps
CPU time 4.51 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 212892 kb
Host smart-8f60971e-bbf9-4951-8d6a-5e61a0189fad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461639600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1461639600
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3815103164
Short name T731
Test name
Test status
Simulation time 3096894864 ps
CPU time 77.44 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:08:37 PM PDT 24
Peak memory 214000 kb
Host smart-b85db0b5-d870-4eb5-9afe-cc7593315482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815103164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3815103164
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.4169259890
Short name T281
Test name
Test status
Simulation time 2852366627 ps
CPU time 92.57 seconds
Started Apr 04 03:07:15 PM PDT 24
Finished Apr 04 03:08:48 PM PDT 24
Peak memory 517864 kb
Host smart-4b54e6ec-54c5-4d46-850c-d2b3bec666f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169259890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.4169259890
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1766333352
Short name T656
Test name
Test status
Simulation time 128011097 ps
CPU time 0.96 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 203564 kb
Host smart-02019c5d-c8e6-4049-a79c-67c58e9f1ada
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766333352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1766333352
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3790924117
Short name T998
Test name
Test status
Simulation time 771913883 ps
CPU time 4.6 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:25 PM PDT 24
Peak memory 203572 kb
Host smart-4e4ca667-e84d-4c4a-aa0d-cfebc8c9d78a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790924117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3790924117
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1700714385
Short name T153
Test name
Test status
Simulation time 14223727450 ps
CPU time 83.56 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:08:43 PM PDT 24
Peak memory 1054732 kb
Host smart-c12c6e16-76cd-4e75-b634-b89753e46ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700714385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1700714385
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.55755605
Short name T355
Test name
Test status
Simulation time 1286197991 ps
CPU time 4.41 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:26 PM PDT 24
Peak memory 203720 kb
Host smart-09f69835-4a15-4edc-ad3c-3200291684df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55755605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.55755605
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2812440795
Short name T555
Test name
Test status
Simulation time 1047544545 ps
CPU time 52.53 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:08:10 PM PDT 24
Peak memory 358888 kb
Host smart-063709eb-d4c2-4492-8686-85d4c031079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812440795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2812440795
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3581124443
Short name T168
Test name
Test status
Simulation time 62005475 ps
CPU time 0.65 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 203488 kb
Host smart-c23a31ed-9438-4a6c-a0cc-763fbf864098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581124443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3581124443
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3587954407
Short name T590
Test name
Test status
Simulation time 1685868016 ps
CPU time 30.13 seconds
Started Apr 04 03:07:14 PM PDT 24
Finished Apr 04 03:07:45 PM PDT 24
Peak memory 350400 kb
Host smart-90903387-7e37-4a76-8be3-1c9ef9f70bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587954407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3587954407
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1752574730
Short name T257
Test name
Test status
Simulation time 849901451 ps
CPU time 16.41 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:37 PM PDT 24
Peak memory 281300 kb
Host smart-5883d4ce-e651-43c0-a126-58b48889087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752574730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1752574730
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.660707559
Short name T1104
Test name
Test status
Simulation time 2950199112 ps
CPU time 3.95 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:24 PM PDT 24
Peak memory 203792 kb
Host smart-a164a92f-633e-49f4-89a6-08d59d5c555c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660707559 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.660707559
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1408957503
Short name T75
Test name
Test status
Simulation time 10210927388 ps
CPU time 12.84 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:34 PM PDT 24
Peak memory 293944 kb
Host smart-fcbe6038-520b-49d4-892b-aa058c48ea18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408957503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1408957503
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1491498784
Short name T655
Test name
Test status
Simulation time 10181234075 ps
CPU time 11.68 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:33 PM PDT 24
Peak memory 308324 kb
Host smart-f41763b0-c54e-4cb0-9821-6cee15af7b9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491498784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1491498784
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1802389317
Short name T49
Test name
Test status
Simulation time 1352882584 ps
CPU time 2.2 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:07:20 PM PDT 24
Peak memory 203748 kb
Host smart-dc6681c4-41fe-4132-8d1a-58a5dd1a4ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802389317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1802389317
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1018298577
Short name T685
Test name
Test status
Simulation time 3984109847 ps
CPU time 3.8 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:25 PM PDT 24
Peak memory 205032 kb
Host smart-48e43a4b-3ccc-4585-81c6-1347930468ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018298577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1018298577
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1680106036
Short name T577
Test name
Test status
Simulation time 8067758539 ps
CPU time 5.88 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 203840 kb
Host smart-add45816-0dac-40c0-a710-45f5757e963d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680106036 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1680106036
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.630994797
Short name T1101
Test name
Test status
Simulation time 1205384718 ps
CPU time 20.27 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:42 PM PDT 24
Peak memory 203668 kb
Host smart-86ef6f1e-e43a-47b3-9256-5672fac713ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630994797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.630994797
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2099123521
Short name T469
Test name
Test status
Simulation time 3335097498 ps
CPU time 29.18 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:51 PM PDT 24
Peak memory 225736 kb
Host smart-4377fd7c-3047-4eef-b3d8-c49ea9d699d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099123521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2099123521
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1664440958
Short name T310
Test name
Test status
Simulation time 41110773186 ps
CPU time 2965.76 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:56:46 PM PDT 24
Peak memory 9801824 kb
Host smart-845ae350-0bc6-4afc-93bf-6ec3431aa02f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664440958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1664440958
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_alert_test.585609229
Short name T582
Test name
Test status
Simulation time 16928102 ps
CPU time 0.6 seconds
Started Apr 04 03:07:21 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 203404 kb
Host smart-03e32dd7-0006-454b-8c79-8acf06eaa660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585609229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.585609229
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.831887165
Short name T699
Test name
Test status
Simulation time 80513447 ps
CPU time 1.44 seconds
Started Apr 04 03:07:15 PM PDT 24
Finished Apr 04 03:07:16 PM PDT 24
Peak memory 211876 kb
Host smart-a56b23b3-cfc2-4c93-b96f-d83620c1dacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831887165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.831887165
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2447286585
Short name T255
Test name
Test status
Simulation time 716985088 ps
CPU time 2.8 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:24 PM PDT 24
Peak memory 226444 kb
Host smart-d4e9cece-a9fa-47af-a8e9-4866446ec266
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447286585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2447286585
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.4186177898
Short name T58
Test name
Test status
Simulation time 2858354693 ps
CPU time 96.81 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:08:59 PM PDT 24
Peak memory 549988 kb
Host smart-9c650c98-58c3-49ac-81dd-8e0f4383e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186177898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.4186177898
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2785645703
Short name T1073
Test name
Test status
Simulation time 5461515336 ps
CPU time 36.85 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:07:54 PM PDT 24
Peak memory 433340 kb
Host smart-738a0a33-3af1-4340-9a19-2834e6ffcf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785645703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2785645703
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2798470052
Short name T894
Test name
Test status
Simulation time 461884568 ps
CPU time 1 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 203576 kb
Host smart-843d1a9f-67d8-47b7-b411-1f9d0c094323
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798470052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2798470052
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2312936083
Short name T672
Test name
Test status
Simulation time 652595571 ps
CPU time 8.73 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:30 PM PDT 24
Peak memory 231388 kb
Host smart-9a6d9041-915f-4bc5-a1c9-2204a73a0375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312936083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2312936083
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3795443429
Short name T630
Test name
Test status
Simulation time 14425933490 ps
CPU time 265.3 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:11:47 PM PDT 24
Peak memory 1066640 kb
Host smart-77c98ae4-0821-4637-a4d6-2fbec12a8369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795443429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3795443429
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3662656075
Short name T606
Test name
Test status
Simulation time 1281121160 ps
CPU time 9.8 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:32 PM PDT 24
Peak memory 203764 kb
Host smart-3d4a9b2c-5634-417e-95f1-e111f346566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662656075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3662656075
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3100824427
Short name T814
Test name
Test status
Simulation time 5009005596 ps
CPU time 32.26 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:54 PM PDT 24
Peak memory 446056 kb
Host smart-043cf2e9-2dde-496f-b8c8-5d32fec1fd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100824427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3100824427
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.91049465
Short name T578
Test name
Test status
Simulation time 70028619 ps
CPU time 0.66 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:21 PM PDT 24
Peak memory 203504 kb
Host smart-3c5b2cf3-41ac-462e-b8ea-43ba14ae775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91049465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.91049465
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3500817361
Short name T356
Test name
Test status
Simulation time 4926270797 ps
CPU time 193.34 seconds
Started Apr 04 03:07:15 PM PDT 24
Finished Apr 04 03:10:28 PM PDT 24
Peak memory 221284 kb
Host smart-0bd336c1-5173-443b-9399-b6af8f3caf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500817361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3500817361
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3454147860
Short name T271
Test name
Test status
Simulation time 4515449432 ps
CPU time 53.81 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:08:14 PM PDT 24
Peak memory 350068 kb
Host smart-71219812-6470-4c3c-adce-9a45783a0178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454147860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3454147860
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1809553323
Short name T506
Test name
Test status
Simulation time 756020588 ps
CPU time 4.1 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:24 PM PDT 24
Peak memory 204748 kb
Host smart-96ae678b-b48b-4fd5-8b38-81243c3b5e62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809553323 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1809553323
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3517654809
Short name T1016
Test name
Test status
Simulation time 10102853783 ps
CPU time 32.63 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:52 PM PDT 24
Peak memory 400788 kb
Host smart-8772f016-b261-4ed0-8011-91f256c8bb36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517654809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3517654809
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3367445775
Short name T66
Test name
Test status
Simulation time 10646505681 ps
CPU time 16.86 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:37 PM PDT 24
Peak memory 363492 kb
Host smart-cf8ab145-e3ed-4c19-b3db-b034ed60eca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367445775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3367445775
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.78325152
Short name T384
Test name
Test status
Simulation time 3212821261 ps
CPU time 2.33 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:24 PM PDT 24
Peak memory 203832 kb
Host smart-b2da306c-4b6d-4628-9c11-24aed8c9cd82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78325152 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.i2c_target_hrst.78325152
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1128688947
Short name T1035
Test name
Test status
Simulation time 1941273798 ps
CPU time 4.77 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:27 PM PDT 24
Peak memory 208184 kb
Host smart-81ec290f-9867-44ca-bca0-abd6567dbd3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128688947 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1128688947
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.2740964463
Short name T564
Test name
Test status
Simulation time 4948098701 ps
CPU time 46.64 seconds
Started Apr 04 03:07:21 PM PDT 24
Finished Apr 04 03:08:09 PM PDT 24
Peak memory 203880 kb
Host smart-4aaa2aa1-371f-4ed9-95ec-af18b5d5fdf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740964463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.2740964463
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3560432733
Short name T493
Test name
Test status
Simulation time 1746741495 ps
CPU time 17.98 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:40 PM PDT 24
Peak memory 223232 kb
Host smart-4986b318-c9b6-4a6b-8932-1d4079833fc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560432733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3560432733
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1029646834
Short name T722
Test name
Test status
Simulation time 9550458688 ps
CPU time 5.97 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:07:26 PM PDT 24
Peak memory 203812 kb
Host smart-9355eeb9-8d81-41c8-a0c2-7ce8da44a774
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029646834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1029646834
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.2458659155
Short name T427
Test name
Test status
Simulation time 17949989744 ps
CPU time 175.09 seconds
Started Apr 04 03:07:16 PM PDT 24
Finished Apr 04 03:10:11 PM PDT 24
Peak memory 751952 kb
Host smart-97474ee4-1959-41dd-bb70-1098f88784fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458659155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.2458659155
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.356598457
Short name T940
Test name
Test status
Simulation time 2816763738 ps
CPU time 7.69 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:29 PM PDT 24
Peak memory 219984 kb
Host smart-5a6fad83-2b09-4c68-b7a7-1c2b25b118e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356598457 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_timeout.356598457
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.401956846
Short name T534
Test name
Test status
Simulation time 4966109110 ps
CPU time 7.94 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:30 PM PDT 24
Peak memory 203720 kb
Host smart-0b248bbf-1550-44bb-a6b4-72cbf026e798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401956846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_unexp_stop.401956846
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/47.i2c_alert_test.4206767378
Short name T328
Test name
Test status
Simulation time 17810431 ps
CPU time 0.61 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:34 PM PDT 24
Peak memory 203496 kb
Host smart-2b5699f7-5af8-4320-b0ee-581400adc69c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206767378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.4206767378
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1050592288
Short name T952
Test name
Test status
Simulation time 200681190 ps
CPU time 2.01 seconds
Started Apr 04 03:07:21 PM PDT 24
Finished Apr 04 03:07:24 PM PDT 24
Peak memory 211928 kb
Host smart-58a36da9-6e01-454e-978b-bb36613b4f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050592288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1050592288
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3549208627
Short name T925
Test name
Test status
Simulation time 340770068 ps
CPU time 7.46 seconds
Started Apr 04 03:07:22 PM PDT 24
Finished Apr 04 03:07:30 PM PDT 24
Peak memory 274188 kb
Host smart-9b7cf26e-aa52-40c6-ad4b-ef9f7c4518e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549208627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3549208627
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.335139668
Short name T354
Test name
Test status
Simulation time 2198832146 ps
CPU time 85.8 seconds
Started Apr 04 03:07:22 PM PDT 24
Finished Apr 04 03:08:48 PM PDT 24
Peak memory 745452 kb
Host smart-73d71c85-ef4e-44ae-ba6e-f401fb844514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335139668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.335139668
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3031083875
Short name T1051
Test name
Test status
Simulation time 7320503523 ps
CPU time 52.77 seconds
Started Apr 04 03:07:17 PM PDT 24
Finished Apr 04 03:08:13 PM PDT 24
Peak memory 660792 kb
Host smart-7ef358ca-e148-4e9d-a900-0b2f7a4c191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031083875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3031083875
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1201242591
Short name T1017
Test name
Test status
Simulation time 298970904 ps
CPU time 0.92 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 203616 kb
Host smart-ec64ab34-931f-49f2-a884-8747b0d8ee94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201242591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1201242591
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1760876088
Short name T964
Test name
Test status
Simulation time 734315997 ps
CPU time 4.38 seconds
Started Apr 04 03:07:19 PM PDT 24
Finished Apr 04 03:07:26 PM PDT 24
Peak memory 235880 kb
Host smart-7d6f9542-76b3-487a-9ff4-7e5ad4f47015
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760876088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1760876088
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1571053512
Short name T1050
Test name
Test status
Simulation time 6912841371 ps
CPU time 203.65 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:10:44 PM PDT 24
Peak memory 926908 kb
Host smart-8d316238-f83f-4a5d-8e44-3ad5e817aaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571053512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1571053512
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.59099340
Short name T647
Test name
Test status
Simulation time 392137176 ps
CPU time 5.31 seconds
Started Apr 04 03:07:30 PM PDT 24
Finished Apr 04 03:07:39 PM PDT 24
Peak memory 203640 kb
Host smart-aa074859-6ec6-4362-a0c3-c0ff0a5bbd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59099340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.59099340
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.264595661
Short name T1126
Test name
Test status
Simulation time 1178237802 ps
CPU time 25.17 seconds
Started Apr 04 03:07:29 PM PDT 24
Finished Apr 04 03:07:59 PM PDT 24
Peak memory 356836 kb
Host smart-5a9e4f22-9bbb-4605-b1fd-fa7fe84e73cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264595661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.264595661
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2491664815
Short name T1170
Test name
Test status
Simulation time 58623160 ps
CPU time 0.67 seconds
Started Apr 04 03:07:21 PM PDT 24
Finished Apr 04 03:07:23 PM PDT 24
Peak memory 203524 kb
Host smart-b3b093ca-3e5a-480c-8041-aaee7bdedfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491664815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2491664815
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2512038893
Short name T507
Test name
Test status
Simulation time 7377419599 ps
CPU time 124.32 seconds
Started Apr 04 03:07:21 PM PDT 24
Finished Apr 04 03:09:26 PM PDT 24
Peak memory 713992 kb
Host smart-98e7d035-9fd2-40eb-80b8-68c279f372c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512038893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2512038893
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3947162021
Short name T717
Test name
Test status
Simulation time 6960109886 ps
CPU time 19.71 seconds
Started Apr 04 03:07:18 PM PDT 24
Finished Apr 04 03:07:41 PM PDT 24
Peak memory 342304 kb
Host smart-e3ec3de2-d11b-4b1c-9334-c8f45be655bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947162021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3947162021
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1385810904
Short name T1063
Test name
Test status
Simulation time 1490796211 ps
CPU time 4.06 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:38 PM PDT 24
Peak memory 203724 kb
Host smart-612aa99c-a2fc-401c-8eac-c8278d478259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385810904 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1385810904
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.649581099
Short name T63
Test name
Test status
Simulation time 10058995336 ps
CPU time 33.56 seconds
Started Apr 04 03:07:23 PM PDT 24
Finished Apr 04 03:07:57 PM PDT 24
Peak memory 404436 kb
Host smart-032e791b-97e6-4eb3-b1df-d5c07f4dc361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649581099 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.649581099
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2277408795
Short name T686
Test name
Test status
Simulation time 10483113972 ps
CPU time 16.37 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:38 PM PDT 24
Peak memory 333440 kb
Host smart-208890c9-d7be-4624-8b95-c6d1ec61717d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277408795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2277408795
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.2782029295
Short name T326
Test name
Test status
Simulation time 389921906 ps
CPU time 2.55 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 203716 kb
Host smart-571be758-0c21-40a0-852a-8d5357ce32f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782029295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.2782029295
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2654157523
Short name T398
Test name
Test status
Simulation time 3739524349 ps
CPU time 5.8 seconds
Started Apr 04 03:07:21 PM PDT 24
Finished Apr 04 03:07:28 PM PDT 24
Peak memory 203840 kb
Host smart-aaf0c627-d751-486a-87b2-71b692c2d83a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654157523 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2654157523
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.3183934329
Short name T529
Test name
Test status
Simulation time 2851159278 ps
CPU time 8.88 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:31 PM PDT 24
Peak memory 203700 kb
Host smart-d8c8043b-9ad7-4cc5-8880-1eed7828c978
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183934329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.3183934329
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.94072349
Short name T786
Test name
Test status
Simulation time 299554392 ps
CPU time 11.1 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:33 PM PDT 24
Peak memory 203688 kb
Host smart-15f405ec-8df4-4478-b424-31cff65eb74d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94072349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stress_rd.94072349
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1516805011
Short name T895
Test name
Test status
Simulation time 9320124572 ps
CPU time 11.38 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:33 PM PDT 24
Peak memory 203780 kb
Host smart-07f6131a-f9f5-48bf-adba-702be4b4c1ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516805011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1516805011
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2650821798
Short name T431
Test name
Test status
Simulation time 14275281181 ps
CPU time 982.25 seconds
Started Apr 04 03:07:22 PM PDT 24
Finished Apr 04 03:23:45 PM PDT 24
Peak memory 2325104 kb
Host smart-73da2f56-2d36-47af-a7e1-11606cf04e90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650821798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2650821798
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2257747331
Short name T342
Test name
Test status
Simulation time 1533077982 ps
CPU time 7.16 seconds
Started Apr 04 03:07:20 PM PDT 24
Finished Apr 04 03:07:29 PM PDT 24
Peak memory 219812 kb
Host smart-c869ea15-572b-4ef9-9016-5337447deb1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257747331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2257747331
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2117135070
Short name T859
Test name
Test status
Simulation time 26801625 ps
CPU time 0.59 seconds
Started Apr 04 03:07:29 PM PDT 24
Finished Apr 04 03:07:34 PM PDT 24
Peak memory 203592 kb
Host smart-6ddc475d-81f2-4c4d-88b0-8f51194767b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117135070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2117135070
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.4172703138
Short name T992
Test name
Test status
Simulation time 111663385 ps
CPU time 1.15 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:35 PM PDT 24
Peak memory 203680 kb
Host smart-57b93c91-6d5e-45bd-a230-fcdbb9800074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172703138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.4172703138
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3649125372
Short name T601
Test name
Test status
Simulation time 638741468 ps
CPU time 5.67 seconds
Started Apr 04 03:07:36 PM PDT 24
Finished Apr 04 03:07:41 PM PDT 24
Peak memory 266492 kb
Host smart-00a88cf1-8e3c-4065-b731-7fa26244a8b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649125372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3649125372
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1171966826
Short name T591
Test name
Test status
Simulation time 1952241573 ps
CPU time 70.18 seconds
Started Apr 04 03:07:29 PM PDT 24
Finished Apr 04 03:08:44 PM PDT 24
Peak memory 670132 kb
Host smart-db470bf7-9a78-45f6-a3d6-e4e5b587757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171966826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1171966826
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3082163568
Short name T1118
Test name
Test status
Simulation time 4671518013 ps
CPU time 68.11 seconds
Started Apr 04 03:07:30 PM PDT 24
Finished Apr 04 03:08:42 PM PDT 24
Peak memory 755396 kb
Host smart-67c3c1af-e054-43b1-b8e1-730e0b89269a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082163568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3082163568
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.27019586
Short name T958
Test name
Test status
Simulation time 331741496 ps
CPU time 0.96 seconds
Started Apr 04 03:07:31 PM PDT 24
Finished Apr 04 03:07:34 PM PDT 24
Peak memory 203628 kb
Host smart-e7a4c1a8-1976-46a4-a180-46723de5e931
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt
.27019586
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3786232581
Short name T10
Test name
Test status
Simulation time 420510498 ps
CPU time 5.52 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:39 PM PDT 24
Peak memory 217408 kb
Host smart-49bfd48e-87fa-4cbc-82a4-591702241633
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786232581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3786232581
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.3977676027
Short name T226
Test name
Test status
Simulation time 4106786749 ps
CPU time 125.87 seconds
Started Apr 04 03:07:31 PM PDT 24
Finished Apr 04 03:09:40 PM PDT 24
Peak memory 1223352 kb
Host smart-ea2d5baf-6c5b-46bb-9b0b-7b1be9eea571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977676027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3977676027
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3582157920
Short name T547
Test name
Test status
Simulation time 2372364853 ps
CPU time 8.08 seconds
Started Apr 04 03:07:31 PM PDT 24
Finished Apr 04 03:07:42 PM PDT 24
Peak memory 203856 kb
Host smart-f873d2d9-b072-4b53-8e91-ff6fca5a451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582157920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3582157920
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.4032066220
Short name T1098
Test name
Test status
Simulation time 2068804916 ps
CPU time 99.26 seconds
Started Apr 04 03:07:29 PM PDT 24
Finished Apr 04 03:09:13 PM PDT 24
Peak memory 415764 kb
Host smart-a9ec2ec0-5798-4526-850e-72b93c9feb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032066220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.4032066220
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.4133274248
Short name T169
Test name
Test status
Simulation time 30839757 ps
CPU time 0.68 seconds
Started Apr 04 03:07:27 PM PDT 24
Finished Apr 04 03:07:28 PM PDT 24
Peak memory 203472 kb
Host smart-434184ca-c8bf-41f3-9902-fa237af43ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133274248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.4133274248
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1391601099
Short name T183
Test name
Test status
Simulation time 8358999490 ps
CPU time 37.78 seconds
Started Apr 04 03:07:29 PM PDT 24
Finished Apr 04 03:08:11 PM PDT 24
Peak memory 372492 kb
Host smart-9638e219-42f2-4893-b896-0d4bc1bf3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391601099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1391601099
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1044032766
Short name T873
Test name
Test status
Simulation time 6064243350 ps
CPU time 47.87 seconds
Started Apr 04 03:07:30 PM PDT 24
Finished Apr 04 03:08:21 PM PDT 24
Peak memory 533456 kb
Host smart-abeb5663-dd3f-47e9-abf0-aea531bb55b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044032766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1044032766
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.800173691
Short name T239
Test name
Test status
Simulation time 35764871950 ps
CPU time 935.59 seconds
Started Apr 04 03:07:30 PM PDT 24
Finished Apr 04 03:23:09 PM PDT 24
Peak memory 2703996 kb
Host smart-17828c34-ef19-4e9f-9209-963d780c4b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800173691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.800173691
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2651089688
Short name T282
Test name
Test status
Simulation time 842045052 ps
CPU time 3.31 seconds
Started Apr 04 03:07:34 PM PDT 24
Finished Apr 04 03:07:38 PM PDT 24
Peak memory 203728 kb
Host smart-f81f7eb8-1660-4118-828b-9e134721169f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651089688 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2651089688
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3658021927
Short name T1161
Test name
Test status
Simulation time 10125160517 ps
CPU time 82.85 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 612524 kb
Host smart-9bcc2595-534a-44fc-ad5f-d272c0faca2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658021927 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3658021927
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1260140796
Short name T632
Test name
Test status
Simulation time 11306799148 ps
CPU time 5.6 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:39 PM PDT 24
Peak memory 255780 kb
Host smart-f3f60d18-29d6-4346-8e52-1fcb45f6f36f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260140796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1260140796
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1306636759
Short name T205
Test name
Test status
Simulation time 599801063 ps
CPU time 2.26 seconds
Started Apr 04 03:07:30 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 203684 kb
Host smart-0d0d28b0-8a5e-4a06-99ee-97fb48a4e467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306636759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1306636759
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2256790862
Short name T843
Test name
Test status
Simulation time 1336774839 ps
CPU time 3.61 seconds
Started Apr 04 03:07:36 PM PDT 24
Finished Apr 04 03:07:39 PM PDT 24
Peak memory 205888 kb
Host smart-45bd94f5-8d6e-4a4c-81bf-56d27c3bf655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256790862 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2256790862
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1835601975
Short name T249
Test name
Test status
Simulation time 12178847563 ps
CPU time 29.3 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:08:03 PM PDT 24
Peak memory 203744 kb
Host smart-035030c1-7052-4137-91c4-e54885891e00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835601975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1835601975
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_all.491525434
Short name T1179
Test name
Test status
Simulation time 34770176630 ps
CPU time 39.95 seconds
Started Apr 04 03:07:31 PM PDT 24
Finished Apr 04 03:08:14 PM PDT 24
Peak memory 300156 kb
Host smart-dfbc7c2d-809d-435d-8ab1-efb3c2f7cc03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491525434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.i2c_target_stress_all.491525434
Directory /workspace/48.i2c_target_stress_all/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2416822504
Short name T425
Test name
Test status
Simulation time 1719053752 ps
CPU time 13.41 seconds
Started Apr 04 03:07:35 PM PDT 24
Finished Apr 04 03:07:49 PM PDT 24
Peak memory 214372 kb
Host smart-fda4756f-e08e-4774-8487-4d4963850899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416822504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2416822504
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3004552286
Short name T388
Test name
Test status
Simulation time 20413755319 ps
CPU time 23.55 seconds
Started Apr 04 03:07:30 PM PDT 24
Finished Apr 04 03:07:57 PM PDT 24
Peak memory 203824 kb
Host smart-d095155e-5bb6-429b-b077-f2a491d8ed01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004552286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3004552286
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.299264291
Short name T174
Test name
Test status
Simulation time 15606138296 ps
CPU time 2489.33 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:49:04 PM PDT 24
Peak memory 3852952 kb
Host smart-5b487948-1ed2-4b59-8640-a3352a38b578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299264291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.299264291
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2111107684
Short name T710
Test name
Test status
Simulation time 8990587119 ps
CPU time 7.86 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:07:42 PM PDT 24
Peak memory 203884 kb
Host smart-43d201ee-45e7-4ee5-a11a-8cca208106c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111107684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2111107684
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.267302083
Short name T436
Test name
Test status
Simulation time 940933787 ps
CPU time 5.5 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:39 PM PDT 24
Peak memory 205960 kb
Host smart-259024e6-a0f6-45cb-a90a-341d94f7ce6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267302083 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_unexp_stop.267302083
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.475889436
Short name T1136
Test name
Test status
Simulation time 40800904 ps
CPU time 0.62 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:07:35 PM PDT 24
Peak memory 203552 kb
Host smart-213659d9-9bdd-4077-a92b-7d45de146c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475889436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.475889436
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1201050020
Short name T934
Test name
Test status
Simulation time 224363061 ps
CPU time 1.4 seconds
Started Apr 04 03:07:36 PM PDT 24
Finished Apr 04 03:07:37 PM PDT 24
Peak memory 203684 kb
Host smart-45b348dc-f130-4873-a2b5-2e1ebcd97ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201050020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1201050020
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2481674802
Short name T387
Test name
Test status
Simulation time 1653953766 ps
CPU time 20.95 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:55 PM PDT 24
Peak memory 289272 kb
Host smart-f137bcf7-4f23-4959-b6df-eb18c3e2e2fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481674802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2481674802
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2578358440
Short name T966
Test name
Test status
Simulation time 1662152923 ps
CPU time 102.64 seconds
Started Apr 04 03:07:34 PM PDT 24
Finished Apr 04 03:09:17 PM PDT 24
Peak memory 534628 kb
Host smart-b817b85b-4b61-42e6-8d80-b59abcbb91bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578358440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2578358440
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2130567305
Short name T820
Test name
Test status
Simulation time 4873978828 ps
CPU time 146.35 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:10:00 PM PDT 24
Peak memory 677200 kb
Host smart-8d306786-bd6e-4766-adfd-49110a827afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130567305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2130567305
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1247342549
Short name T429
Test name
Test status
Simulation time 118832066 ps
CPU time 1.05 seconds
Started Apr 04 03:07:29 PM PDT 24
Finished Apr 04 03:07:35 PM PDT 24
Peak memory 203704 kb
Host smart-23e16685-4392-466a-89db-a94e8d20fea5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247342549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1247342549
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.227699042
Short name T1005
Test name
Test status
Simulation time 118913069 ps
CPU time 6.15 seconds
Started Apr 04 03:07:30 PM PDT 24
Finished Apr 04 03:07:40 PM PDT 24
Peak memory 203764 kb
Host smart-1af5ff4d-25ae-4617-9c6a-2aa0e2c671c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227699042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
227699042
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2308739397
Short name T1075
Test name
Test status
Simulation time 6190016704 ps
CPU time 74.65 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:08:48 PM PDT 24
Peak memory 864312 kb
Host smart-c14159e3-3d79-4aac-9f1c-1cd64ad9ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308739397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2308739397
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.160287854
Short name T840
Test name
Test status
Simulation time 1666878126 ps
CPU time 16.67 seconds
Started Apr 04 03:07:31 PM PDT 24
Finished Apr 04 03:07:50 PM PDT 24
Peak memory 203300 kb
Host smart-0a0e592e-fd01-462b-b6bb-cb94057a6b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160287854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.160287854
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1903982768
Short name T793
Test name
Test status
Simulation time 1252648998 ps
CPU time 56.21 seconds
Started Apr 04 03:07:40 PM PDT 24
Finished Apr 04 03:08:36 PM PDT 24
Peak memory 316044 kb
Host smart-c364000e-e735-427b-a56c-f5465416c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903982768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1903982768
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.269152610
Short name T96
Test name
Test status
Simulation time 87636252 ps
CPU time 0.69 seconds
Started Apr 04 03:07:36 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 203428 kb
Host smart-03b19c17-f3c5-43a0-8ce3-d0d84fb31e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269152610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.269152610
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1192919935
Short name T1196
Test name
Test status
Simulation time 11785470849 ps
CPU time 64.05 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:08:38 PM PDT 24
Peak memory 213144 kb
Host smart-d4a87ac9-3332-4ebd-b2fe-b03a5cac53eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192919935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1192919935
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1269083276
Short name T413
Test name
Test status
Simulation time 1208738351 ps
CPU time 59.12 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:08:33 PM PDT 24
Peak memory 329852 kb
Host smart-530bcc3b-1aa5-43a7-b69f-7fc4ee1af156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269083276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1269083276
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3436563780
Short name T449
Test name
Test status
Simulation time 3846441406 ps
CPU time 4.39 seconds
Started Apr 04 03:07:31 PM PDT 24
Finished Apr 04 03:07:38 PM PDT 24
Peak memory 212048 kb
Host smart-c5c97a4f-5608-4137-8f41-29c44ee3f0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436563780 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3436563780
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2922551118
Short name T358
Test name
Test status
Simulation time 10051663336 ps
CPU time 83.19 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:08:57 PM PDT 24
Peak memory 601284 kb
Host smart-6d07c815-ecad-4ef3-8f3a-0b10a45718a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922551118 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2922551118
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.200582783
Short name T653
Test name
Test status
Simulation time 10133523215 ps
CPU time 35.63 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:08:09 PM PDT 24
Peak memory 443976 kb
Host smart-34647d49-0ad5-44df-abe0-1d7d8dfbbb87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200582783 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.200582783
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.3520918429
Short name T178
Test name
Test status
Simulation time 4522747561 ps
CPU time 2.47 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:36 PM PDT 24
Peak memory 203848 kb
Host smart-4d75557e-3a8f-4cf6-9f4f-05cfcb9d92fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520918429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.3520918429
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.898227857
Short name T1076
Test name
Test status
Simulation time 9564126734 ps
CPU time 7.78 seconds
Started Apr 04 03:07:37 PM PDT 24
Finished Apr 04 03:07:45 PM PDT 24
Peak memory 217056 kb
Host smart-22516c93-8d87-4d9c-a640-470243f37a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898227857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.898227857
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.1390145494
Short name T900
Test name
Test status
Simulation time 2420062889 ps
CPU time 25.62 seconds
Started Apr 04 03:07:33 PM PDT 24
Finished Apr 04 03:08:00 PM PDT 24
Peak memory 203768 kb
Host smart-ce1f7afa-0055-4868-8ff4-6b0e998f40c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390145494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.1390145494
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2649736544
Short name T409
Test name
Test status
Simulation time 3233245383 ps
CPU time 14.57 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:07:48 PM PDT 24
Peak memory 212336 kb
Host smart-856dcd5b-864c-41c8-8e0c-2186032db076
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649736544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2649736544
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.4134452448
Short name T910
Test name
Test status
Simulation time 6543629995 ps
CPU time 159.09 seconds
Started Apr 04 03:07:32 PM PDT 24
Finished Apr 04 03:10:13 PM PDT 24
Peak memory 1394688 kb
Host smart-1efdfe65-1ac6-4487-84a0-8eddfb5cacd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134452448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.4134452448
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.641833113
Short name T430
Test name
Test status
Simulation time 2440748272 ps
CPU time 6.69 seconds
Started Apr 04 03:07:31 PM PDT 24
Finished Apr 04 03:07:40 PM PDT 24
Peak memory 218344 kb
Host smart-84966cec-77c9-4c02-ae48-f534f1f934be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641833113 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.641833113
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_unexp_stop.189165099
Short name T34
Test name
Test status
Simulation time 1097425533 ps
CPU time 6.14 seconds
Started Apr 04 03:07:37 PM PDT 24
Finished Apr 04 03:07:44 PM PDT 24
Peak memory 204252 kb
Host smart-2815db56-5403-4866-b841-574c20488b0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189165099 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_unexp_stop.189165099
Directory /workspace/49.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2369939500
Short name T815
Test name
Test status
Simulation time 23052583 ps
CPU time 0.68 seconds
Started Apr 04 03:03:14 PM PDT 24
Finished Apr 04 03:03:16 PM PDT 24
Peak memory 203412 kb
Host smart-087870d3-5b92-4d1d-8ab7-7fc3aafa9430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369939500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2369939500
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2434231378
Short name T1209
Test name
Test status
Simulation time 241684712 ps
CPU time 1.24 seconds
Started Apr 04 03:02:56 PM PDT 24
Finished Apr 04 03:02:58 PM PDT 24
Peak memory 211996 kb
Host smart-baf37724-bb13-4adb-a888-d4a6d8054871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434231378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2434231378
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2400589199
Short name T1176
Test name
Test status
Simulation time 505887898 ps
CPU time 12.74 seconds
Started Apr 04 03:02:54 PM PDT 24
Finished Apr 04 03:03:07 PM PDT 24
Peak memory 255360 kb
Host smart-efd5e2e5-237d-4c13-9e7d-4c51407fb798
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400589199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2400589199
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1755534977
Short name T320
Test name
Test status
Simulation time 1410101812 ps
CPU time 47.91 seconds
Started Apr 04 03:02:56 PM PDT 24
Finished Apr 04 03:03:44 PM PDT 24
Peak memory 540924 kb
Host smart-33a189ab-ffd8-4a9d-accd-26889c471ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755534977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1755534977
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.2062630240
Short name T1095
Test name
Test status
Simulation time 3731839004 ps
CPU time 63.34 seconds
Started Apr 04 03:02:57 PM PDT 24
Finished Apr 04 03:04:00 PM PDT 24
Peak memory 650844 kb
Host smart-a0cb73e4-fece-4834-ac15-ca70795ff09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062630240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2062630240
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3807312160
Short name T770
Test name
Test status
Simulation time 386601564 ps
CPU time 0.91 seconds
Started Apr 04 03:02:57 PM PDT 24
Finished Apr 04 03:02:58 PM PDT 24
Peak memory 203584 kb
Host smart-317ca3c3-aa07-4017-963e-c5db3cc891a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807312160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3807312160
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3383312328
Short name T973
Test name
Test status
Simulation time 128352562 ps
CPU time 2.82 seconds
Started Apr 04 03:02:59 PM PDT 24
Finished Apr 04 03:03:02 PM PDT 24
Peak memory 203700 kb
Host smart-9d28db1e-5e39-4cc5-ab06-e4b8d61b301f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383312328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3383312328
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.1009137824
Short name T1138
Test name
Test status
Simulation time 4197677813 ps
CPU time 112.42 seconds
Started Apr 04 03:03:01 PM PDT 24
Finished Apr 04 03:04:55 PM PDT 24
Peak memory 1133328 kb
Host smart-b65319e6-e268-4e44-8da0-44704b6c7199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009137824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1009137824
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.1657427167
Short name T891
Test name
Test status
Simulation time 1267173820 ps
CPU time 3.81 seconds
Started Apr 04 03:03:06 PM PDT 24
Finished Apr 04 03:03:10 PM PDT 24
Peak memory 203704 kb
Host smart-209e22df-3d36-44ff-be94-d2543f39318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657427167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1657427167
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.976817595
Short name T568
Test name
Test status
Simulation time 933613596 ps
CPU time 39.71 seconds
Started Apr 04 03:03:10 PM PDT 24
Finished Apr 04 03:03:51 PM PDT 24
Peak memory 260508 kb
Host smart-58ccfea8-93ee-4771-8a01-91493688eb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976817595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.976817595
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.532012146
Short name T521
Test name
Test status
Simulation time 31606736 ps
CPU time 0.67 seconds
Started Apr 04 03:03:00 PM PDT 24
Finished Apr 04 03:03:03 PM PDT 24
Peak memory 203508 kb
Host smart-88970cbf-9cd9-4fac-83f7-21b2ec50ddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532012146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.532012146
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.170833618
Short name T463
Test name
Test status
Simulation time 1212223925 ps
CPU time 24.55 seconds
Started Apr 04 03:02:56 PM PDT 24
Finished Apr 04 03:03:20 PM PDT 24
Peak memory 331864 kb
Host smart-8b2cbf1d-147e-407e-aef7-d1aa83a12a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170833618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.170833618
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3644676344
Short name T1
Test name
Test status
Simulation time 955693209 ps
CPU time 2.99 seconds
Started Apr 04 03:03:04 PM PDT 24
Finished Apr 04 03:03:08 PM PDT 24
Peak memory 203740 kb
Host smart-42587bde-08e0-4b16-9f4f-c2c99163e46a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644676344 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3644676344
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1427925135
Short name T835
Test name
Test status
Simulation time 10106888641 ps
CPU time 64.87 seconds
Started Apr 04 03:03:06 PM PDT 24
Finished Apr 04 03:04:11 PM PDT 24
Peak memory 524380 kb
Host smart-a50533eb-3b3f-4bb4-b01e-2ded7f25a81f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427925135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1427925135
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3505272235
Short name T959
Test name
Test status
Simulation time 10353236710 ps
CPU time 18.11 seconds
Started Apr 04 03:03:06 PM PDT 24
Finished Apr 04 03:03:25 PM PDT 24
Peak memory 339280 kb
Host smart-b9e077ab-0342-49c3-9812-5dcc283c56e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505272235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3505272235
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.299701694
Short name T1162
Test name
Test status
Simulation time 404136037 ps
CPU time 2.11 seconds
Started Apr 04 03:03:12 PM PDT 24
Finished Apr 04 03:03:14 PM PDT 24
Peak memory 203612 kb
Host smart-ec93cfe1-a8cc-4200-b4a9-9d4044358974
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299701694 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.299701694
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.4062978319
Short name T518
Test name
Test status
Simulation time 841380232 ps
CPU time 4.55 seconds
Started Apr 04 03:03:15 PM PDT 24
Finished Apr 04 03:03:20 PM PDT 24
Peak memory 207424 kb
Host smart-17d3352c-b5ba-4af7-b1d0-395d7c8881ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062978319 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.4062978319
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2855560743
Short name T701
Test name
Test status
Simulation time 4186920088 ps
CPU time 15.72 seconds
Started Apr 04 03:03:00 PM PDT 24
Finished Apr 04 03:03:18 PM PDT 24
Peak memory 203884 kb
Host smart-0393d68f-eef5-425d-83e9-86ef58ee02ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855560743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2855560743
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2579938089
Short name T1175
Test name
Test status
Simulation time 5718886421 ps
CPU time 40.73 seconds
Started Apr 04 03:03:00 PM PDT 24
Finished Apr 04 03:03:43 PM PDT 24
Peak memory 203868 kb
Host smart-75474b4e-0ddd-4e93-a847-c940cdf0b40d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579938089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2579938089
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.2124491173
Short name T407
Test name
Test status
Simulation time 35843758800 ps
CPU time 853.24 seconds
Started Apr 04 03:03:05 PM PDT 24
Finished Apr 04 03:17:19 PM PDT 24
Peak memory 4371768 kb
Host smart-e3b917ee-7ae5-4a05-8b41-35e566dfe0de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124491173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.2124491173
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.979633205
Short name T740
Test name
Test status
Simulation time 1528481104 ps
CPU time 7.6 seconds
Started Apr 04 03:03:05 PM PDT 24
Finished Apr 04 03:03:13 PM PDT 24
Peak memory 219964 kb
Host smart-c8254c23-449d-492f-b97d-2198ebd6d218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979633205 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_timeout.979633205
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3790546670
Short name T1184
Test name
Test status
Simulation time 18678704 ps
CPU time 0.65 seconds
Started Apr 04 03:03:19 PM PDT 24
Finished Apr 04 03:03:20 PM PDT 24
Peak memory 203528 kb
Host smart-32eb0192-8c93-4f95-99b2-20ef41e32f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790546670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3790546670
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1101999999
Short name T373
Test name
Test status
Simulation time 297881047 ps
CPU time 1.42 seconds
Started Apr 04 03:03:12 PM PDT 24
Finished Apr 04 03:03:14 PM PDT 24
Peak memory 211840 kb
Host smart-9fe4fd75-05c8-4d39-94d1-ec38b60fbab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101999999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1101999999
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2316929064
Short name T531
Test name
Test status
Simulation time 2041681550 ps
CPU time 8.86 seconds
Started Apr 04 03:03:13 PM PDT 24
Finished Apr 04 03:03:25 PM PDT 24
Peak memory 281884 kb
Host smart-be6ff633-b49d-4396-98aa-063121185862
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316929064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2316929064
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3085644529
Short name T383
Test name
Test status
Simulation time 1262177144 ps
CPU time 39.9 seconds
Started Apr 04 03:03:15 PM PDT 24
Finished Apr 04 03:03:56 PM PDT 24
Peak memory 502084 kb
Host smart-1ff18d05-1cb3-4e5a-903e-a2130d7db02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085644529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3085644529
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1045945199
Short name T748
Test name
Test status
Simulation time 2695279494 ps
CPU time 39.33 seconds
Started Apr 04 03:03:14 PM PDT 24
Finished Apr 04 03:03:55 PM PDT 24
Peak memory 497332 kb
Host smart-5f5f13c2-8ed9-423b-9b0d-2e08aa0ce0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045945199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1045945199
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3619800867
Short name T1156
Test name
Test status
Simulation time 184617797 ps
CPU time 0.89 seconds
Started Apr 04 03:03:06 PM PDT 24
Finished Apr 04 03:03:07 PM PDT 24
Peak memory 203580 kb
Host smart-55f99bc8-4ecf-4fd4-a16d-d93bc7ca5701
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619800867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3619800867
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1234703147
Short name T363
Test name
Test status
Simulation time 179695333 ps
CPU time 9.9 seconds
Started Apr 04 03:03:02 PM PDT 24
Finished Apr 04 03:03:14 PM PDT 24
Peak memory 235508 kb
Host smart-b6431549-b490-47ba-b7f9-6fcbc4515838
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234703147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1234703147
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2565768102
Short name T154
Test name
Test status
Simulation time 9620054450 ps
CPU time 126.29 seconds
Started Apr 04 03:03:03 PM PDT 24
Finished Apr 04 03:05:11 PM PDT 24
Peak memory 1354028 kb
Host smart-46c865ce-8e5a-4d53-9548-4e4efb27eac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565768102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2565768102
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3637580944
Short name T381
Test name
Test status
Simulation time 1675629713 ps
CPU time 5.78 seconds
Started Apr 04 03:03:21 PM PDT 24
Finished Apr 04 03:03:29 PM PDT 24
Peak memory 203748 kb
Host smart-c018317c-73b9-4a11-b027-9d2573b24d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637580944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3637580944
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3662868548
Short name T996
Test name
Test status
Simulation time 4996949023 ps
CPU time 54.79 seconds
Started Apr 04 03:03:20 PM PDT 24
Finished Apr 04 03:04:15 PM PDT 24
Peak memory 321108 kb
Host smart-cd8f2c28-aa3c-4f3d-9390-c13bc95d505c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662868548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3662868548
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2269027122
Short name T527
Test name
Test status
Simulation time 30357123 ps
CPU time 0.67 seconds
Started Apr 04 03:03:05 PM PDT 24
Finished Apr 04 03:03:06 PM PDT 24
Peak memory 203432 kb
Host smart-73b0db27-43cc-4e13-aa51-cb74cb196133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269027122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2269027122
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3054092683
Short name T794
Test name
Test status
Simulation time 6926284545 ps
CPU time 129.15 seconds
Started Apr 04 03:03:13 PM PDT 24
Finished Apr 04 03:05:25 PM PDT 24
Peak memory 1015812 kb
Host smart-77d9d36e-a800-4949-9ad9-c5727f318367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054092683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3054092683
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2016047638
Short name T485
Test name
Test status
Simulation time 2415160825 ps
CPU time 27.11 seconds
Started Apr 04 03:03:15 PM PDT 24
Finished Apr 04 03:03:43 PM PDT 24
Peak memory 379736 kb
Host smart-8cbd66bf-cb50-4915-ace4-87fa31704162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016047638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2016047638
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.436424780
Short name T194
Test name
Test status
Simulation time 66923936005 ps
CPU time 2735.34 seconds
Started Apr 04 03:03:14 PM PDT 24
Finished Apr 04 03:48:51 PM PDT 24
Peak memory 3628300 kb
Host smart-bda92821-b15b-4ac7-bf31-20420d1f16e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436424780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.436424780
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3158677467
Short name T32
Test name
Test status
Simulation time 10181341404 ps
CPU time 2.87 seconds
Started Apr 04 03:03:21 PM PDT 24
Finished Apr 04 03:03:26 PM PDT 24
Peak memory 203856 kb
Host smart-b31ebaf2-9caf-47f6-913c-d6d4516d0786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158677467 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3158677467
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.4248719910
Short name T728
Test name
Test status
Simulation time 10089605183 ps
CPU time 103.09 seconds
Started Apr 04 03:03:22 PM PDT 24
Finished Apr 04 03:05:06 PM PDT 24
Peak memory 648496 kb
Host smart-e1ade86e-5e5e-4eb9-a739-56a7e25fd93f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248719910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.4248719910
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.291542119
Short name T65
Test name
Test status
Simulation time 10081710949 ps
CPU time 89.74 seconds
Started Apr 04 03:03:19 PM PDT 24
Finished Apr 04 03:04:49 PM PDT 24
Peak memory 654884 kb
Host smart-b8b4eb33-78fc-42fe-9711-92ccee3b889f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291542119 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.291542119
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.3164092832
Short name T406
Test name
Test status
Simulation time 503465552 ps
CPU time 3 seconds
Started Apr 04 03:03:19 PM PDT 24
Finished Apr 04 03:03:23 PM PDT 24
Peak memory 203708 kb
Host smart-14c83a2a-6cc6-471a-8dc2-61db4d0f2205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164092832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.3164092832
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.136193258
Short name T390
Test name
Test status
Simulation time 13497142104 ps
CPU time 4.79 seconds
Started Apr 04 03:03:10 PM PDT 24
Finished Apr 04 03:03:17 PM PDT 24
Peak memory 204784 kb
Host smart-e3c01ba8-0185-4c88-8949-42bf879b463b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136193258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.136193258
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2081037561
Short name T56
Test name
Test status
Simulation time 3899832104 ps
CPU time 12.41 seconds
Started Apr 04 03:03:07 PM PDT 24
Finished Apr 04 03:03:19 PM PDT 24
Peak memory 203848 kb
Host smart-cf2b1a07-4252-4df7-bfb0-1c0baedf0638
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081037561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2081037561
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1042560448
Short name T517
Test name
Test status
Simulation time 2915766018 ps
CPU time 10.05 seconds
Started Apr 04 03:03:04 PM PDT 24
Finished Apr 04 03:03:15 PM PDT 24
Peak memory 204576 kb
Host smart-4d188142-aa9f-4079-b64f-0ede988d9322
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042560448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1042560448
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3533772510
Short name T361
Test name
Test status
Simulation time 9091428662 ps
CPU time 17.63 seconds
Started Apr 04 03:03:08 PM PDT 24
Finished Apr 04 03:03:25 PM PDT 24
Peak memory 203788 kb
Host smart-e0371295-c84c-4690-a139-b38a0427015a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533772510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3533772510
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.140731728
Short name T280
Test name
Test status
Simulation time 2714866116 ps
CPU time 6.19 seconds
Started Apr 04 03:03:19 PM PDT 24
Finished Apr 04 03:03:25 PM PDT 24
Peak memory 215716 kb
Host smart-d33c3195-f0c9-4f37-8614-e3eecf889423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140731728 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.140731728
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3940735092
Short name T595
Test name
Test status
Simulation time 21616770 ps
CPU time 0.6 seconds
Started Apr 04 03:03:38 PM PDT 24
Finished Apr 04 03:03:38 PM PDT 24
Peak memory 203588 kb
Host smart-9b8465df-e820-433e-adea-da0cadf1c346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940735092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3940735092
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3504648880
Short name T1004
Test name
Test status
Simulation time 176580144 ps
CPU time 1.45 seconds
Started Apr 04 03:03:34 PM PDT 24
Finished Apr 04 03:03:36 PM PDT 24
Peak memory 211848 kb
Host smart-9102f501-f29e-4ef2-b882-5bb40df8a5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504648880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3504648880
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.4041347226
Short name T499
Test name
Test status
Simulation time 1015904376 ps
CPU time 5.24 seconds
Started Apr 04 03:03:33 PM PDT 24
Finished Apr 04 03:03:39 PM PDT 24
Peak memory 235624 kb
Host smart-b4c08397-2fbb-4848-a3e6-8afc0f4c4a2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041347226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.4041347226
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3149384573
Short name T1054
Test name
Test status
Simulation time 1593973650 ps
CPU time 53.02 seconds
Started Apr 04 03:03:33 PM PDT 24
Finished Apr 04 03:04:27 PM PDT 24
Peak memory 581768 kb
Host smart-3ac7fb6f-b8b1-4e54-9c3c-1348eb73e699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149384573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3149384573
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1780999294
Short name T575
Test name
Test status
Simulation time 4616918814 ps
CPU time 71.69 seconds
Started Apr 04 03:03:34 PM PDT 24
Finished Apr 04 03:04:46 PM PDT 24
Peak memory 754428 kb
Host smart-53305e4f-29eb-4e2c-a308-c8595b0725bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780999294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1780999294
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.433157058
Short name T576
Test name
Test status
Simulation time 107690807 ps
CPU time 0.9 seconds
Started Apr 04 03:03:32 PM PDT 24
Finished Apr 04 03:03:34 PM PDT 24
Peak memory 203572 kb
Host smart-a02de29b-a2b5-44ef-82a7-414b0396f2d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433157058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.433157058
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2774543766
Short name T264
Test name
Test status
Simulation time 355601699 ps
CPU time 7.99 seconds
Started Apr 04 03:03:33 PM PDT 24
Finished Apr 04 03:03:41 PM PDT 24
Peak memory 226668 kb
Host smart-91015075-4379-40e2-9178-8771d9684c30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774543766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2774543766
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3276292431
Short name T224
Test name
Test status
Simulation time 4383159070 ps
CPU time 142.29 seconds
Started Apr 04 03:03:19 PM PDT 24
Finished Apr 04 03:05:41 PM PDT 24
Peak memory 1284040 kb
Host smart-1577f1be-1ad0-4001-a1be-c25adc5c9b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276292431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3276292431
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.4154943106
Short name T211
Test name
Test status
Simulation time 2009454735 ps
CPU time 8.07 seconds
Started Apr 04 03:03:35 PM PDT 24
Finished Apr 04 03:03:44 PM PDT 24
Peak memory 203632 kb
Host smart-b3044b7c-8cea-417d-b8f3-fef1c2a3c6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154943106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.4154943106
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3916523750
Short name T614
Test name
Test status
Simulation time 14976013861 ps
CPU time 38.26 seconds
Started Apr 04 03:03:38 PM PDT 24
Finished Apr 04 03:04:17 PM PDT 24
Peak memory 407116 kb
Host smart-45f22486-654d-456f-bc97-12e9d14bd1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916523750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3916523750
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.2316411908
Short name T165
Test name
Test status
Simulation time 28222657 ps
CPU time 0.64 seconds
Started Apr 04 03:03:20 PM PDT 24
Finished Apr 04 03:03:21 PM PDT 24
Peak memory 203476 kb
Host smart-13ffbfcd-5c58-4463-b6b2-f5a3f6a49786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316411908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2316411908
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3622313546
Short name T44
Test name
Test status
Simulation time 6409894331 ps
CPU time 24.62 seconds
Started Apr 04 03:03:34 PM PDT 24
Finished Apr 04 03:03:59 PM PDT 24
Peak memory 228408 kb
Host smart-549fa698-b5a1-4df1-a21d-8686a8245e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622313546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3622313546
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2984391528
Short name T567
Test name
Test status
Simulation time 3193476977 ps
CPU time 35.05 seconds
Started Apr 04 03:03:20 PM PDT 24
Finished Apr 04 03:03:55 PM PDT 24
Peak memory 366488 kb
Host smart-aad76b9a-03e7-4ea6-a3eb-2447646779dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984391528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2984391528
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1745077180
Short name T631
Test name
Test status
Simulation time 51879500859 ps
CPU time 1711.69 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:32:08 PM PDT 24
Peak memory 2999872 kb
Host smart-7f6820ce-2563-4b45-b183-7d7d4c8f8378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745077180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1745077180
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2014399506
Short name T931
Test name
Test status
Simulation time 3483381732 ps
CPU time 2.86 seconds
Started Apr 04 03:03:34 PM PDT 24
Finished Apr 04 03:03:37 PM PDT 24
Peak memory 203788 kb
Host smart-068a5626-cac7-4921-bb34-da38739cd9ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014399506 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2014399506
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.44595005
Short name T423
Test name
Test status
Simulation time 10069601805 ps
CPU time 82.7 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:04:59 PM PDT 24
Peak memory 599760 kb
Host smart-538ce301-8481-4860-98ce-e601754b4fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44595005 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_acq.44595005
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2599274406
Short name T1133
Test name
Test status
Simulation time 10515476946 ps
CPU time 17.98 seconds
Started Apr 04 03:03:37 PM PDT 24
Finished Apr 04 03:03:55 PM PDT 24
Peak memory 343836 kb
Host smart-8c671f7b-a699-4a69-a593-eaee6041430b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599274406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2599274406
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2452613252
Short name T871
Test name
Test status
Simulation time 1899000288 ps
CPU time 2.89 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:03:39 PM PDT 24
Peak memory 203636 kb
Host smart-41786120-3951-40d8-b768-cb7152eb8c6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452613252 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2452613252
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1598299749
Short name T396
Test name
Test status
Simulation time 2363370512 ps
CPU time 4.99 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:03:41 PM PDT 24
Peak memory 212076 kb
Host smart-651c9950-4d52-4ea8-8621-761a1188d21e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598299749 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1598299749
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3070323420
Short name T584
Test name
Test status
Simulation time 4786558195 ps
CPU time 10.35 seconds
Started Apr 04 03:03:37 PM PDT 24
Finished Apr 04 03:03:47 PM PDT 24
Peak memory 203872 kb
Host smart-ae5990d5-dd15-4fc5-b3f8-0b411fe843c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070323420 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3070323420
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2055093377
Short name T1150
Test name
Test status
Simulation time 4801430806 ps
CPU time 20.44 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:03:56 PM PDT 24
Peak memory 203768 kb
Host smart-423cd5bb-b3ee-4bf0-92dd-2a1f01fca260
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055093377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2055093377
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.790432139
Short name T604
Test name
Test status
Simulation time 1719800457 ps
CPU time 68.18 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:04:44 PM PDT 24
Peak memory 205460 kb
Host smart-b01e8125-961b-43d8-b5d3-5e687a380554
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790432139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.790432139
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.4030765501
Short name T173
Test name
Test status
Simulation time 6203282347 ps
CPU time 202.98 seconds
Started Apr 04 03:03:34 PM PDT 24
Finished Apr 04 03:06:57 PM PDT 24
Peak memory 1652616 kb
Host smart-e8ee630c-b3bc-49a7-b591-949c4e6681af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030765501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.4030765501
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.83892522
Short name T159
Test name
Test status
Simulation time 2774579499 ps
CPU time 6.9 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:03:43 PM PDT 24
Peak memory 212096 kb
Host smart-d85cdf6b-87cd-4e05-ba51-7372a78d1198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83892522 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_timeout.83892522
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3972405056
Short name T1006
Test name
Test status
Simulation time 16091569 ps
CPU time 0.63 seconds
Started Apr 04 03:03:51 PM PDT 24
Finished Apr 04 03:03:51 PM PDT 24
Peak memory 203600 kb
Host smart-cba87b2b-ee23-4dae-9967-05ea07eedcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972405056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3972405056
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2078731148
Short name T252
Test name
Test status
Simulation time 247522682 ps
CPU time 1.55 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:03:38 PM PDT 24
Peak memory 211852 kb
Host smart-137d270a-ec89-46e4-a8a0-f6e640e357ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078731148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2078731148
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.4222944000
Short name T1158
Test name
Test status
Simulation time 1055522269 ps
CPU time 6.57 seconds
Started Apr 04 03:03:38 PM PDT 24
Finished Apr 04 03:03:45 PM PDT 24
Peak memory 272964 kb
Host smart-7224b844-5ae5-4857-adab-754635045d97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222944000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.4222944000
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.670488760
Short name T538
Test name
Test status
Simulation time 7518690967 ps
CPU time 58.57 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:04:35 PM PDT 24
Peak memory 655208 kb
Host smart-a7b0367c-fd02-45b9-9c97-d0418286a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670488760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.670488760
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.568401377
Short name T714
Test name
Test status
Simulation time 2194295996 ps
CPU time 29.7 seconds
Started Apr 04 03:03:34 PM PDT 24
Finished Apr 04 03:04:04 PM PDT 24
Peak memory 476636 kb
Host smart-4fcd6a64-cf81-49b5-9c7a-4c194f2b26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568401377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.568401377
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3758612478
Short name T497
Test name
Test status
Simulation time 263268697 ps
CPU time 0.81 seconds
Started Apr 04 03:03:35 PM PDT 24
Finished Apr 04 03:03:36 PM PDT 24
Peak memory 203608 kb
Host smart-e06e4ece-fb71-4fb4-a6df-473559b2a8a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758612478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3758612478
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.4098011908
Short name T188
Test name
Test status
Simulation time 118572077 ps
CPU time 5.98 seconds
Started Apr 04 03:03:38 PM PDT 24
Finished Apr 04 03:03:44 PM PDT 24
Peak memory 203600 kb
Host smart-e31ece08-25ae-4605-b991-190083abb508
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098011908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
4098011908
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2736469129
Short name T302
Test name
Test status
Simulation time 2449576480 ps
CPU time 154.66 seconds
Started Apr 04 03:03:37 PM PDT 24
Finished Apr 04 03:06:12 PM PDT 24
Peak memory 744124 kb
Host smart-2da79d72-0e5e-43ba-92ba-0db0400a6dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736469129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2736469129
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2123760343
Short name T197
Test name
Test status
Simulation time 279279821 ps
CPU time 3.74 seconds
Started Apr 04 03:03:48 PM PDT 24
Finished Apr 04 03:03:52 PM PDT 24
Peak memory 203736 kb
Host smart-66e38a30-83bf-469a-88d3-80876dfb9860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123760343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2123760343
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3261828618
Short name T1205
Test name
Test status
Simulation time 2164262942 ps
CPU time 18.92 seconds
Started Apr 04 03:03:49 PM PDT 24
Finished Apr 04 03:04:08 PM PDT 24
Peak memory 334224 kb
Host smart-8cd385b4-85a8-4841-8bee-2c78494fdf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261828618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3261828618
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2696457100
Short name T961
Test name
Test status
Simulation time 135686987 ps
CPU time 0.62 seconds
Started Apr 04 03:03:37 PM PDT 24
Finished Apr 04 03:03:38 PM PDT 24
Peak memory 203508 kb
Host smart-0fb9bb14-50c4-4183-9c6d-d843651d062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696457100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2696457100
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2391801993
Short name T420
Test name
Test status
Simulation time 2582600952 ps
CPU time 84.73 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:05:01 PM PDT 24
Peak memory 220232 kb
Host smart-35c9bfcc-ff7b-432d-88b4-478da7dfeda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391801993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2391801993
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.632701118
Short name T795
Test name
Test status
Simulation time 5255979836 ps
CPU time 24.02 seconds
Started Apr 04 03:03:36 PM PDT 24
Finished Apr 04 03:04:00 PM PDT 24
Peak memory 340164 kb
Host smart-90c7cbfd-5335-41c6-9049-fd5ff125a10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632701118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.632701118
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3106420399
Short name T938
Test name
Test status
Simulation time 513395505 ps
CPU time 2.77 seconds
Started Apr 04 03:03:49 PM PDT 24
Finished Apr 04 03:03:52 PM PDT 24
Peak memory 203716 kb
Host smart-fd57edc5-ed6a-44e1-ab82-716e0efb0a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106420399 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3106420399
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1562529098
Short name T676
Test name
Test status
Simulation time 10165060623 ps
CPU time 33.6 seconds
Started Apr 04 03:03:47 PM PDT 24
Finished Apr 04 03:04:21 PM PDT 24
Peak memory 375720 kb
Host smart-6be8bf84-6c79-44c6-8415-4d2ce3a7352b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562529098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1562529098
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3219588322
Short name T470
Test name
Test status
Simulation time 10163941183 ps
CPU time 23.01 seconds
Started Apr 04 03:03:49 PM PDT 24
Finished Apr 04 03:04:13 PM PDT 24
Peak memory 371204 kb
Host smart-f0a44b8f-28d0-44af-8632-0f68c5d7db34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219588322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3219588322
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1553897186
Short name T613
Test name
Test status
Simulation time 1718857203 ps
CPU time 2.37 seconds
Started Apr 04 03:03:48 PM PDT 24
Finished Apr 04 03:03:50 PM PDT 24
Peak memory 203632 kb
Host smart-45fc4053-90a9-488e-ab19-7784d52e6b10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553897186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1553897186
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2441786538
Short name T771
Test name
Test status
Simulation time 2320516498 ps
CPU time 5.48 seconds
Started Apr 04 03:03:47 PM PDT 24
Finished Apr 04 03:03:53 PM PDT 24
Peak memory 203840 kb
Host smart-c26cd04e-fe12-457b-b466-0632ca6d9517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441786538 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2441786538
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.582759743
Short name T763
Test name
Test status
Simulation time 6001739635 ps
CPU time 9.46 seconds
Started Apr 04 03:03:46 PM PDT 24
Finished Apr 04 03:03:56 PM PDT 24
Peak memory 203744 kb
Host smart-3e6b75b9-f647-423f-bb96-3f959bb5931d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582759743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.582759743
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3683468935
Short name T782
Test name
Test status
Simulation time 1029983798 ps
CPU time 10 seconds
Started Apr 04 03:03:47 PM PDT 24
Finished Apr 04 03:03:57 PM PDT 24
Peak memory 203764 kb
Host smart-69ad94a3-7336-4364-9285-128581c8e04f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683468935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3683468935
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.1536632566
Short name T730
Test name
Test status
Simulation time 42288932462 ps
CPU time 66.8 seconds
Started Apr 04 03:03:49 PM PDT 24
Finished Apr 04 03:04:56 PM PDT 24
Peak memory 783664 kb
Host smart-3e2b02ba-c872-45c5-9225-753890bbba0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536632566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.1536632566
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.13993012
Short name T603
Test name
Test status
Simulation time 3974605113 ps
CPU time 7.08 seconds
Started Apr 04 03:03:51 PM PDT 24
Finished Apr 04 03:03:58 PM PDT 24
Peak memory 213348 kb
Host smart-dc8bd2a7-b626-4271-963a-06197f1fcbb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13993012 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_timeout.13993012
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1476429211
Short name T561
Test name
Test status
Simulation time 17274976 ps
CPU time 0.61 seconds
Started Apr 04 03:03:56 PM PDT 24
Finished Apr 04 03:03:57 PM PDT 24
Peak memory 203548 kb
Host smart-b11bcd9a-0ef6-4a05-a33c-a4668acc6194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476429211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1476429211
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1638411608
Short name T287
Test name
Test status
Simulation time 202627072 ps
CPU time 1.62 seconds
Started Apr 04 03:03:52 PM PDT 24
Finished Apr 04 03:03:54 PM PDT 24
Peak memory 220072 kb
Host smart-116c3021-3257-4d93-90e9-5fee660800aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638411608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1638411608
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2237822489
Short name T414
Test name
Test status
Simulation time 277102641 ps
CPU time 13.14 seconds
Started Apr 04 03:03:48 PM PDT 24
Finished Apr 04 03:04:02 PM PDT 24
Peak memory 256720 kb
Host smart-34a20993-4c4f-484b-8c2b-0a714aaa377c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237822489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2237822489
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.80235765
Short name T369
Test name
Test status
Simulation time 2654903036 ps
CPU time 57.56 seconds
Started Apr 04 03:03:52 PM PDT 24
Finished Apr 04 03:04:50 PM PDT 24
Peak memory 507528 kb
Host smart-b86f7e36-8aae-4203-9cc6-0ee568df3754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80235765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.80235765
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2376602418
Short name T274
Test name
Test status
Simulation time 1575845050 ps
CPU time 114.04 seconds
Started Apr 04 03:03:52 PM PDT 24
Finished Apr 04 03:05:46 PM PDT 24
Peak memory 595016 kb
Host smart-4072b705-4bd6-46d3-8ef3-47534b4df06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376602418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2376602418
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.2070236234
Short name T758
Test name
Test status
Simulation time 66570187 ps
CPU time 0.84 seconds
Started Apr 04 03:03:49 PM PDT 24
Finished Apr 04 03:03:50 PM PDT 24
Peak memory 203636 kb
Host smart-fca14ee5-2af9-47ba-a193-faf88281e28d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070236234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.2070236234
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3340996425
Short name T982
Test name
Test status
Simulation time 265694272 ps
CPU time 2.52 seconds
Started Apr 04 03:03:53 PM PDT 24
Finished Apr 04 03:03:56 PM PDT 24
Peak memory 203600 kb
Host smart-a9e4840d-04e4-45c6-a3d9-80ecf361c843
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340996425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3340996425
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1410740997
Short name T225
Test name
Test status
Simulation time 9586236010 ps
CPU time 143.96 seconds
Started Apr 04 03:03:53 PM PDT 24
Finished Apr 04 03:06:17 PM PDT 24
Peak memory 1312688 kb
Host smart-f6d2f704-85a1-462c-b1e8-d863a455280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410740997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1410740997
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3525101913
Short name T734
Test name
Test status
Simulation time 234914176 ps
CPU time 3.04 seconds
Started Apr 04 03:03:55 PM PDT 24
Finished Apr 04 03:03:58 PM PDT 24
Peak memory 203728 kb
Host smart-eb58f3bd-3635-4d94-ab56-50e99d31f087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525101913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3525101913
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.314617404
Short name T546
Test name
Test status
Simulation time 3835072518 ps
CPU time 46.37 seconds
Started Apr 04 03:03:56 PM PDT 24
Finished Apr 04 03:04:42 PM PDT 24
Peak memory 477652 kb
Host smart-ea848ea8-9b3e-4aaf-a245-592264089935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314617404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.314617404
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.1717014461
Short name T13
Test name
Test status
Simulation time 66318308 ps
CPU time 0.75 seconds
Started Apr 04 03:03:50 PM PDT 24
Finished Apr 04 03:03:50 PM PDT 24
Peak memory 203520 kb
Host smart-9204bd13-e75d-45d9-96b7-ef8165cb77f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717014461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1717014461
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1445893632
Short name T800
Test name
Test status
Simulation time 74275115992 ps
CPU time 2241.84 seconds
Started Apr 04 03:03:51 PM PDT 24
Finished Apr 04 03:41:13 PM PDT 24
Peak memory 4666048 kb
Host smart-b1c8ae9b-ad82-4a95-9029-a1c36f9ae227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445893632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1445893632
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3469789577
Short name T1001
Test name
Test status
Simulation time 8998740151 ps
CPU time 37.66 seconds
Started Apr 04 03:03:52 PM PDT 24
Finished Apr 04 03:04:30 PM PDT 24
Peak memory 309308 kb
Host smart-b03ff4a9-55e1-4409-828c-6a56a364e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469789577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3469789577
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.3688790988
Short name T1062
Test name
Test status
Simulation time 16090496167 ps
CPU time 329.96 seconds
Started Apr 04 03:03:51 PM PDT 24
Finished Apr 04 03:09:21 PM PDT 24
Peak memory 1705412 kb
Host smart-1b8eafbf-e801-4185-af3a-c6177cb6cb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688790988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.3688790988
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2126269707
Short name T883
Test name
Test status
Simulation time 3698285149 ps
CPU time 3.36 seconds
Started Apr 04 03:03:52 PM PDT 24
Finished Apr 04 03:03:56 PM PDT 24
Peak memory 203776 kb
Host smart-d8333561-6cc4-4107-bb58-8aa68e02bba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126269707 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2126269707
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.565140024
Short name T675
Test name
Test status
Simulation time 10228894665 ps
CPU time 30.08 seconds
Started Apr 04 03:03:50 PM PDT 24
Finished Apr 04 03:04:21 PM PDT 24
Peak memory 356296 kb
Host smart-566c9981-834f-4836-bbb0-0be7c3c393b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565140024 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.565140024
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1917572070
Short name T1151
Test name
Test status
Simulation time 10127562094 ps
CPU time 40.26 seconds
Started Apr 04 03:03:53 PM PDT 24
Finished Apr 04 03:04:34 PM PDT 24
Peak memory 476384 kb
Host smart-80c58017-1096-4b84-b5a5-0a361f037be5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917572070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1917572070
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.884798512
Short name T201
Test name
Test status
Simulation time 385242463 ps
CPU time 2.32 seconds
Started Apr 04 03:03:55 PM PDT 24
Finished Apr 04 03:03:57 PM PDT 24
Peak memory 203740 kb
Host smart-dff54e3d-fda8-46f6-bf8b-80145ceb246f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884798512 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_hrst.884798512
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.802612670
Short name T1018
Test name
Test status
Simulation time 1750116484 ps
CPU time 3.54 seconds
Started Apr 04 03:03:57 PM PDT 24
Finished Apr 04 03:04:00 PM PDT 24
Peak memory 203760 kb
Host smart-c6a7f839-1c71-4edf-99a0-204b27d0e851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802612670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.802612670
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.943959323
Short name T313
Test name
Test status
Simulation time 5849637490 ps
CPU time 4.49 seconds
Started Apr 04 03:03:55 PM PDT 24
Finished Apr 04 03:03:59 PM PDT 24
Peak memory 203812 kb
Host smart-76a5700e-8d8b-493a-a3c4-e3101107bca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943959323 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.943959323
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.577207604
Short name T16
Test name
Test status
Simulation time 2751830525 ps
CPU time 8.75 seconds
Started Apr 04 03:03:56 PM PDT 24
Finished Apr 04 03:04:05 PM PDT 24
Peak memory 203836 kb
Host smart-3f4621f8-b1bf-4e36-96c6-1ece29b26bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577207604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ
et_smoke.577207604
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2756989237
Short name T802
Test name
Test status
Simulation time 294079418 ps
CPU time 4.47 seconds
Started Apr 04 03:03:50 PM PDT 24
Finished Apr 04 03:03:55 PM PDT 24
Peak memory 203760 kb
Host smart-d2cbb25e-d96a-47d1-8712-d7c57624cf87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756989237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2756989237
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2863929204
Short name T1003
Test name
Test status
Simulation time 26710428609 ps
CPU time 177.27 seconds
Started Apr 04 03:03:51 PM PDT 24
Finished Apr 04 03:06:49 PM PDT 24
Peak memory 1559932 kb
Host smart-4e08a9f0-89f9-461b-ad37-efd6c200247a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863929204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2863929204
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.18777091
Short name T21
Test name
Test status
Simulation time 1470851297 ps
CPU time 7.81 seconds
Started Apr 04 03:03:55 PM PDT 24
Finished Apr 04 03:04:03 PM PDT 24
Peak memory 219944 kb
Host smart-32fe6844-0e99-48b6-9332-49793ee7770d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18777091 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_timeout.18777091
Directory /workspace/9.i2c_target_timeout/latest
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