Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	762873	1			T1	9		T2	3		T3	3
all_values[1]	762873	1			T1	9		T2	3		T3	3
all_values[2]	762873	1			T1	9		T2	3		T3	3
all_values[3]	762873	1			T1	9		T2	3		T3	3
all_values[4]	762873	1			T1	9		T2	3		T3	3
all_values[5]	762873	1			T1	9		T2	3		T3	3
all_values[6]	762873	1			T1	9		T2	3		T3	3
all_values[7]	762873	1			T1	9		T2	3		T3	3
all_values[8]	762873	1			T1	9		T2	3		T3	3
all_values[9]	762873	1			T1	9		T2	3		T3	3
all_values[10]	762873	1			T1	9		T2	3		T3	3
all_values[11]	762873	1			T1	9		T2	3		T3	3
all_values[12]	762873	1			T1	9		T2	3		T3	3
all_values[13]	762873	1			T1	9		T2	3		T3	3
all_values[14]	762873	1			T1	9		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8251006

1

T1

135

T2

38

T3

38

auto[1]

3192089

1

T2

7

T3

7

T4

22615

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9763530

1

T1

135

T2

45

T3

45

auto[1]

1679565

1

T65

6500

T66

56167

T136

134636

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80667	1			T1	9		T4	528		T5	2
all_values[0]	auto[0]	auto[1]	8300	1			T65	23		T66	47		T136	183
all_values[0]	auto[1]	auto[0]	563703	1			T2	3		T3	3		T4	4111
all_values[0]	auto[1]	auto[1]	110203	1			T65	466		T66	4272		T136	8793
all_values[1]	auto[0]	auto[0]	644238	1			T1	9		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	117973	1			T65	202		T66	4319		T136	8970
all_values[1]	auto[1]	auto[0]	403	1			T4	20		T234	2		T76	7
all_values[1]	auto[1]	auto[1]	259	1			T65	11		T66	2		T136	6
all_values[2]	auto[0]	auto[0]	644367	1			T1	9		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	118300	1			T65	478		T66	4318		T136	8970
all_values[2]	auto[1]	auto[0]	2	1			T235	2		-	-		-	-
all_values[2]	auto[1]	auto[1]	204	1			T65	11		T66	3		T136	5
all_values[3]	auto[0]	auto[0]	644372	1			T1	9		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	118224	1			T65	472		T66	4317		T136	8974
all_values[3]	auto[1]	auto[1]	277	1			T65	15		T66	4		T136	3
all_values[4]	auto[0]	auto[0]	663313	1			T1	9		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	99344	1			T65	480		T136	8972		T174	18
all_values[4]	auto[1]	auto[0]	17	1			T69	3		T236	2		T237	2
all_values[4]	auto[1]	auto[1]	199	1			T65	9		T136	5		T174	2
all_values[5]	auto[0]	auto[0]	648395	1			T1	9		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	114223	1			T65	473		T66	4317		T136	8970
all_values[5]	auto[1]	auto[1]	255	1			T65	15		T66	4		T136	4
all_values[6]	auto[0]	auto[0]	175797	1			T1	9		T2	3		T3	3
all_values[6]	auto[0]	auto[1]	25855	1			T65	454		T66	1227		T136	8950
all_values[6]	auto[1]	auto[0]	471568	1			T4	4626		T5	2		T6	1
all_values[6]	auto[1]	auto[1]	89653	1			T65	35		T66	3094		T136	24
all_values[7]	auto[0]	auto[0]	620749	1			T1	9		T2	3		T3	3
all_values[7]	auto[0]	auto[1]	111210	1			T65	183		T66	3928		T136	7992
all_values[7]	auto[1]	auto[0]	26549	1			T4	315		T5	13		T6	1
all_values[7]	auto[1]	auto[1]	4365	1			T65	30		T66	393		T136	981
all_values[8]	auto[0]	auto[0]	144518	1			T1	9		T2	3		T3	3
all_values[8]	auto[0]	auto[1]	26335	1			T65	414		T66	1167		T136	8919
all_values[8]	auto[1]	auto[0]	510730	1			T4	4616		T5	9		T6	1
all_values[8]	auto[1]	auto[1]	81290	1			T65	75		T66	3153		T136	58
all_values[9]	auto[0]	auto[0]	163898	1			T1	9		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	26991	1			T65	442		T66	1210		T136	8948
all_values[9]	auto[1]	auto[0]	481857	1			T2	1		T3	1		T4	4297
all_values[9]	auto[1]	auto[1]	90127	1			T65	47		T66	3110		T136	29
all_values[10]	auto[0]	auto[0]	653809	1			T1	9		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	108854	1			T65	476		T66	4319		T136	8970
all_values[10]	auto[1]	auto[1]	210	1			T65	12		T66	2		T136	5
all_values[11]	auto[0]	auto[0]	2829	1			T1	9		T4	9		T5	2
all_values[11]	auto[0]	auto[1]	529	1			T65	25		T66	36		T136	14
all_values[11]	auto[1]	auto[0]	654106	1			T2	3		T3	3		T4	4630
all_values[11]	auto[1]	auto[1]	105409	1			T65	464		T66	4284		T136	8963
all_values[12]	auto[0]	auto[0]	663332	1			T1	9		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	99335	1			T65	476		T136	8971		T174	17
all_values[12]	auto[1]	auto[1]	206	1			T65	11		T136	4		T174	3
all_values[13]	auto[0]	auto[0]	659006	1			T1	9		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	103620	1			T65	472		T66	4317		T136	8972
all_values[13]	auto[1]	auto[1]	247	1			T65	17		T66	4		T136	5
all_values[14]	auto[0]	auto[0]	645305	1			T1	9		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	117318	1			T65	193		T66	4317		T136	8971
all_values[14]	auto[1]	auto[1]	250	1			T65	19		T66	3		T136	5