Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	762873	1			T1	9		T2	3		T3	3
all_pins[1]	762873	1			T1	9		T2	3		T3	3
all_pins[2]	762873	1			T1	9		T2	3		T3	3
all_pins[3]	762873	1			T1	9		T2	3		T3	3
all_pins[4]	762873	1			T1	9		T2	3		T3	3
all_pins[5]	762873	1			T1	9		T2	3		T3	3
all_pins[6]	762873	1			T1	9		T2	3		T3	3
all_pins[7]	762873	1			T1	9		T2	3		T3	3
all_pins[8]	762873	1			T1	9		T2	3		T3	3
all_pins[9]	762873	1			T1	9		T2	3		T3	3
all_pins[10]	762873	1			T1	9		T2	3		T3	3
all_pins[11]	762873	1			T1	9		T2	3		T3	3
all_pins[12]	762873	1			T1	9		T2	3		T3	3
all_pins[13]	762873	1			T1	9		T2	3		T3	3
all_pins[14]	762873	1			T1	9		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8256047	1			T1	135		T2	38		T3	38
values[0x1]	3187048	1			T2	7		T3	7		T4	22721
transitions[0x0=>0x1]	2580371	1			T2	7		T3	7		T4	17569
transitions[0x1=>0x0]	2579336	1			T2	6		T3	6		T4	17568

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	91995	1			T1	9		T4	527		T5	70
all_pins[0]	values[0x1]	670878	1			T2	3		T3	3		T4	4112
all_pins[0]	transitions[0x0=>0x1]	670328	1			T2	3		T3	3		T4	4089
all_pins[0]	transitions[0x1=>0x0]	85	1			T234	1		T65	8		T66	2
all_pins[1]	values[0x0]	762238	1			T1	9		T2	3		T3	3
all_pins[1]	values[0x1]	635	1			T4	23		T234	2		T76	8
all_pins[1]	transitions[0x0=>0x1]	603	1			T4	23		T234	2		T76	8
all_pins[1]	transitions[0x1=>0x0]	80	1			T65	3		T136	2		T174	1
all_pins[2]	values[0x0]	762761	1			T1	9		T2	3		T3	3
all_pins[2]	values[0x1]	112	1			T65	3		T66	2		T136	2
all_pins[2]	transitions[0x0=>0x1]	83	1			T65	3		T66	1		T136	1
all_pins[2]	transitions[0x1=>0x0]	135	1			T65	11		T66	2		T136	1
all_pins[3]	values[0x0]	762709	1			T1	9		T2	3		T3	3
all_pins[3]	values[0x1]	164	1			T65	11		T66	3		T136	2
all_pins[3]	transitions[0x0=>0x1]	141	1			T65	10		T66	3		T136	1
all_pins[3]	transitions[0x1=>0x0]	95	1			T69	4		T236	2		T65	3
all_pins[4]	values[0x0]	762755	1			T1	9		T2	3		T3	3
all_pins[4]	values[0x1]	118	1			T69	4		T236	2		T65	4
all_pins[4]	transitions[0x0=>0x1]	101	1			T69	4		T236	2		T65	4
all_pins[4]	transitions[0x1=>0x0]	112	1			T65	5		T66	4		T136	3
all_pins[5]	values[0x0]	762744	1			T1	9		T2	3		T3	3
all_pins[5]	values[0x1]	129	1			T65	5		T66	4		T136	4
all_pins[5]	transitions[0x0=>0x1]	102	1			T65	4		T66	4		T136	4
all_pins[5]	transitions[0x1=>0x0]	560890	1			T4	4626		T6	1		T9	1
all_pins[6]	values[0x0]	201956	1			T1	9		T2	3		T3	3
all_pins[6]	values[0x1]	560917	1			T4	4626		T6	1		T9	1
all_pins[6]	transitions[0x0=>0x1]	543940	1			T4	4210		T9	1		T35	1
all_pins[6]	transitions[0x1=>0x0]	16823	1			T71	255		T41	40		T80	3
all_pins[7]	values[0x0]	729073	1			T1	9		T2	3		T3	3
all_pins[7]	values[0x1]	33800	1			T4	416		T6	1		T39	1
all_pins[7]	transitions[0x0=>0x1]	14724	1			T71	217		T41	35		T80	3
all_pins[7]	transitions[0x1=>0x0]	572637	1			T4	4201		T9	1		T71	32
all_pins[8]	values[0x0]	171160	1			T1	9		T2	3		T3	3
all_pins[8]	values[0x1]	591713	1			T4	4617		T6	1		T9	1
all_pins[8]	transitions[0x0=>0x1]	21952	1			T4	320		T9	1		T71	70
all_pins[8]	transitions[0x1=>0x0]	2135	1			T2	1		T3	1		T5	5
all_pins[9]	values[0x0]	190977	1			T1	9		T2	2		T3	2
all_pins[9]	values[0x1]	571896	1			T2	1		T3	1		T4	4297
all_pins[9]	transitions[0x0=>0x1]	571865	1			T2	1		T3	1		T4	4297
all_pins[9]	transitions[0x1=>0x0]	72	1			T65	7		T66	1		T136	2
all_pins[10]	values[0x0]	762770	1			T1	9		T2	3		T3	3
all_pins[10]	values[0x1]	103	1			T65	9		T66	2		T136	2
all_pins[10]	transitions[0x0=>0x1]	68	1			T65	6		T66	1		T136	2
all_pins[10]	transitions[0x1=>0x0]	756212	1			T2	3		T3	3		T4	4630
all_pins[11]	values[0x0]	6626	1			T1	9		T4	9		T5	70
all_pins[11]	values[0x1]	756247	1			T2	3		T3	3		T4	4630
all_pins[11]	transitions[0x0=>0x1]	756215	1			T2	3		T3	3		T4	4630
all_pins[11]	transitions[0x1=>0x0]	73	1			T65	7		T174	1		T178	5
all_pins[12]	values[0x0]	762768	1			T1	9		T2	3		T3	3
all_pins[12]	values[0x1]	105	1			T65	9		T174	1		T178	5
all_pins[12]	transitions[0x0=>0x1]	82	1			T65	6		T174	1		T178	3
all_pins[12]	transitions[0x1=>0x0]	86	1			T65	4		T66	1		T136	1
all_pins[13]	values[0x0]	762764	1			T1	9		T2	3		T3	3
all_pins[13]	values[0x1]	109	1			T65	7		T66	1		T136	1
all_pins[13]	transitions[0x0=>0x1]	83	1			T65	6		T66	1		T136	1
all_pins[13]	transitions[0x1=>0x0]	96	1			T65	9		T66	2		T136	2
all_pins[14]	values[0x0]	762751	1			T1	9		T2	3		T3	3
all_pins[14]	values[0x1]	122	1			T65	10		T66	2		T136	2
all_pins[14]	transitions[0x0=>0x1]	84	1			T65	6		T66	2		T136	2
all_pins[14]	transitions[0x1=>0x0]	669805	1			T2	2		T3	2		T4	4111