Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	513	1			T65	30		T66	4		T136	11
all_values[1]	513	1			T65	30		T66	4		T136	11
all_values[2]	513	1			T65	30		T66	4		T136	11
all_values[3]	513	1			T65	30		T66	4		T136	11
all_values[4]	513	1			T65	30		T66	4		T136	11
all_values[5]	513	1			T65	30		T66	4		T136	11
all_values[6]	513	1			T65	30		T66	4		T136	11
all_values[7]	513	1			T65	30		T66	4		T136	11
all_values[8]	513	1			T65	30		T66	4		T136	11
all_values[9]	513	1			T65	30		T66	4		T136	11
all_values[10]	513	1			T65	30		T66	4		T136	11
all_values[11]	513	1			T65	30		T66	4		T136	11
all_values[12]	513	1			T65	30		T66	4		T136	11
all_values[13]	513	1			T65	30		T66	4		T136	11
all_values[14]	513	1			T65	30		T66	4		T136	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4038

1

T65

253

T66

37

T136

70

auto[1]

3657

1

T65

197

T66

23

T136

95

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T65

22

T66

14

T136

19

auto[1]

6587

1

T65

428

T66

46

T136

146

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4514

1

T65

273

T66

34

T136

104

auto[1]

3181

1

T65

177

T66

26

T136

61

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	37	1			T66	2		T194	2		T262	1
all_values[0]	auto[0]	auto[0]	auto[1]	121	1			T65	11		T66	1		T136	1
all_values[0]	auto[0]	auto[1]	auto[0]	31	1			T136	1		T254	1		T194	2
all_values[0]	auto[0]	auto[1]	auto[1]	121	1			T65	7		T136	5		T174	1
all_values[0]	auto[1]	auto[0]	auto[1]	114	1			T65	7		T66	1		T174	1
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T65	5		T136	4		T174	1
all_values[1]	auto[0]	auto[0]	auto[0]	44	1			T65	2		T193	2		T194	1
all_values[1]	auto[0]	auto[0]	auto[1]	122	1			T65	7		T136	2		T174	3
all_values[1]	auto[0]	auto[1]	auto[0]	25	1			T65	3		T136	1		T254	1
all_values[1]	auto[0]	auto[1]	auto[1]	99	1			T65	7		T66	2		T136	4
all_values[1]	auto[1]	auto[0]	auto[1]	118	1			T65	7		T66	1		T136	1
all_values[1]	auto[1]	auto[1]	auto[1]	105	1			T65	4		T66	1		T136	3
all_values[2]	auto[0]	auto[0]	auto[0]	32	1			T178	1		T254	2		T197	1
all_values[2]	auto[0]	auto[0]	auto[1]	125	1			T65	13		T136	2		T174	6
all_values[2]	auto[0]	auto[1]	auto[0]	33	1			T136	2		T178	1		T83	1
all_values[2]	auto[0]	auto[1]	auto[1]	119	1			T65	6		T66	1		T136	2
all_values[2]	auto[1]	auto[0]	auto[1]	94	1			T65	10		T66	1		T136	2
all_values[2]	auto[1]	auto[1]	auto[1]	110	1			T65	1		T66	2		T136	3
all_values[3]	auto[0]	auto[0]	auto[0]	32	1			T65	2		T178	1		T254	2
all_values[3]	auto[0]	auto[0]	auto[1]	101	1			T65	6		T136	4		T174	1
all_values[3]	auto[0]	auto[1]	auto[0]	38	1			T178	1		T89	2		T194	1
all_values[3]	auto[0]	auto[1]	auto[1]	127	1			T65	9		T66	1		T136	3
all_values[3]	auto[1]	auto[0]	auto[1]	100	1			T65	5		T66	2		T174	2
all_values[3]	auto[1]	auto[1]	auto[1]	115	1			T65	8		T66	1		T136	4
all_values[4]	auto[0]	auto[0]	auto[0]	44	1			T66	2		T193	1		T262	1
all_values[4]	auto[0]	auto[0]	auto[1]	119	1			T65	15		T136	4		T178	4
all_values[4]	auto[0]	auto[1]	auto[0]	35	1			T66	2		T178	1		T254	1
all_values[4]	auto[0]	auto[1]	auto[1]	116	1			T65	6		T136	2		T174	6
all_values[4]	auto[1]	auto[0]	auto[1]	109	1			T65	4		T136	3		T174	2
all_values[4]	auto[1]	auto[1]	auto[1]	90	1			T65	5		T136	2		T178	1
all_values[5]	auto[0]	auto[0]	auto[0]	43	1			T65	1		T136	3		T178	3
all_values[5]	auto[0]	auto[0]	auto[1]	112	1			T65	8		T136	1		T174	2
all_values[5]	auto[0]	auto[1]	auto[0]	32	1			T174	2		T178	3		T263	4
all_values[5]	auto[0]	auto[1]	auto[1]	112	1			T65	11		T66	1		T136	5
all_values[5]	auto[1]	auto[0]	auto[1]	110	1			T65	3		T66	1		T136	1
all_values[5]	auto[1]	auto[1]	auto[1]	104	1			T65	7		T66	2		T136	1
all_values[6]	auto[0]	auto[0]	auto[0]	35	1			T178	1		T264	1		T194	3
all_values[6]	auto[0]	auto[0]	auto[1]	136	1			T65	10		T66	1		T136	4
all_values[6]	auto[0]	auto[1]	auto[0]	43	1			T136	3		T178	1		T185	3
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T65	7		T66	2		T136	2
all_values[6]	auto[1]	auto[0]	auto[1]	113	1			T65	8		T66	1		T136	1
all_values[6]	auto[1]	auto[1]	auto[1]	96	1			T65	5		T136	1		T174	1
all_values[7]	auto[0]	auto[0]	auto[0]	45	1			T65	2		T136	4		T174	3
all_values[7]	auto[0]	auto[0]	auto[1]	102	1			T65	10		T136	3		T178	6
all_values[7]	auto[0]	auto[1]	auto[0]	34	1			T65	3		T174	2		T178	1
all_values[7]	auto[0]	auto[1]	auto[1]	120	1			T65	7		T66	1		T136	1
all_values[7]	auto[1]	auto[0]	auto[1]	110	1			T65	6		T66	2		T136	1
all_values[7]	auto[1]	auto[1]	auto[1]	102	1			T65	2		T66	1		T136	2
all_values[8]	auto[0]	auto[0]	auto[0]	46	1			T66	1		T178	1		T193	1
all_values[8]	auto[0]	auto[0]	auto[1]	110	1			T65	10		T66	1		T136	3
all_values[8]	auto[0]	auto[1]	auto[0]	16	1			T178	1		T193	1		T264	1
all_values[8]	auto[0]	auto[1]	auto[1]	124	1			T65	7		T136	6		T174	3
all_values[8]	auto[1]	auto[0]	auto[1]	120	1			T65	7		T66	2		T136	1
all_values[8]	auto[1]	auto[1]	auto[1]	97	1			T65	6		T136	1		T174	1
all_values[9]	auto[0]	auto[0]	auto[0]	42	1			T66	1		T264	1		T254	2
all_values[9]	auto[0]	auto[0]	auto[1]	106	1			T65	9		T66	2		T136	1
all_values[9]	auto[0]	auto[1]	auto[0]	36	1			T174	1		T193	2		T254	1
all_values[9]	auto[0]	auto[1]	auto[1]	104	1			T65	6		T136	5		T174	2
all_values[9]	auto[1]	auto[0]	auto[1]	116	1			T65	10		T66	1		T136	4
all_values[9]	auto[1]	auto[1]	auto[1]	109	1			T65	5		T136	1		T174	2
all_values[10]	auto[0]	auto[0]	auto[0]	53	1			T65	1		T264	2		T254	3
all_values[10]	auto[0]	auto[0]	auto[1]	118	1			T65	8		T66	2		T136	1
all_values[10]	auto[0]	auto[1]	auto[0]	25	1			T136	2		T193	1		T264	3
all_values[10]	auto[0]	auto[1]	auto[1]	107	1			T65	9		T136	3		T174	6
all_values[10]	auto[1]	auto[0]	auto[1]	111	1			T65	4		T66	1		T136	3
all_values[10]	auto[1]	auto[1]	auto[1]	99	1			T65	8		T66	1		T136	2
all_values[11]	auto[0]	auto[0]	auto[0]	36	1			T66	1		T174	1		T185	2
all_values[11]	auto[0]	auto[0]	auto[1]	126	1			T65	12		T66	2		T136	3
all_values[11]	auto[0]	auto[1]	auto[0]	33	1			T264	4		T233	5		T89	1
all_values[11]	auto[0]	auto[1]	auto[1]	115	1			T65	8		T136	1		T178	2
all_values[11]	auto[1]	auto[0]	auto[1]	104	1			T65	5		T66	1		T136	3
all_values[11]	auto[1]	auto[1]	auto[1]	99	1			T65	5		T136	4		T178	1
all_values[12]	auto[0]	auto[0]	auto[0]	43	1			T65	2		T66	3		T89	3
all_values[12]	auto[0]	auto[0]	auto[1]	134	1			T65	8		T136	2		T174	4
all_values[12]	auto[0]	auto[1]	auto[0]	36	1			T66	1		T136	2		T254	1
all_values[12]	auto[0]	auto[1]	auto[1]	94	1			T65	9		T136	3		T174	1
all_values[12]	auto[1]	auto[0]	auto[1]	100	1			T65	4		T136	3		T174	2
all_values[12]	auto[1]	auto[1]	auto[1]	106	1			T65	7		T136	1		T174	1
all_values[13]	auto[0]	auto[0]	auto[0]	37	1			T174	1		T89	4		T262	1
all_values[13]	auto[0]	auto[0]	auto[1]	131	1			T65	11		T66	1		T136	4
all_values[13]	auto[0]	auto[1]	auto[0]	33	1			T233	1		T89	4		T265	1
all_values[13]	auto[0]	auto[1]	auto[1]	87	1			T65	3		T136	3		T178	4
all_values[13]	auto[1]	auto[0]	auto[1]	125	1			T65	10		T66	2		T136	1
all_values[13]	auto[1]	auto[1]	auto[1]	100	1			T65	6		T66	1		T136	3
all_values[14]	auto[0]	auto[0]	auto[0]	45	1			T65	3		T66	1		T264	4
all_values[14]	auto[0]	auto[0]	auto[1]	99	1			T65	5		T136	2		T178	6
all_values[14]	auto[0]	auto[1]	auto[0]	44	1			T65	3		T136	1		T193	1
all_values[14]	auto[0]	auto[1]	auto[1]	109	1			T65	6		T66	2		T136	3
all_values[14]	auto[1]	auto[0]	auto[1]	118	1			T65	7		T136	2		T178	3
all_values[14]	auto[1]	auto[1]	auto[1]	98	1			T65	6		T66	1		T136	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal